From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id C8FA0740053 for ; Wed, 20 Sep 2023 10:04:25 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=faHQxdI4Sdlzzvq3cpwMEcg8akTWor4CJXPY3zgdP24=; c=relaxed/simple; d=groups.io; h=Date:From:To:CC:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20140610; t=1695204264; v=1; b=HLcPZtn9e0qjU3mQU/5vX+K8AMqPInxSz+KPZPV5wFbFCD7tpAX7/a5g6sIfWG/oa8trndHY 7OjrJSdYuSmS3MQ2Ws92inwmcZtuRXmymfpkzud8Fl26JJquOHUEAnMS6/9slRM8bDy+dBJIUtn qsKbrShDkKaKK5HQSDqdQobo= X-Received: by 127.0.0.2 with SMTP id kmw6YY7687511xYHX0LjWa9O; Wed, 20 Sep 2023 03:04:24 -0700 X-Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by mx.groups.io with SMTP id smtpd.web10.34136.1695204263582995591 for ; Wed, 20 Sep 2023 03:04:23 -0700 X-Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38K9oGvM016906; Wed, 20 Sep 2023 10:04:22 GMT X-Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3t7r8w0qsy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Sep 2023 10:04:22 +0000 X-Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 38KA4LfW019202 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Sep 2023 10:04:21 GMT X-Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.36; Wed, 20 Sep 2023 03:04:19 -0700 Date: Wed, 20 Sep 2023 11:04:16 +0100 From: "Leif Lindholm" To: Marcin Juszkiewicz CC: , Graeme Gregory , Ard Biesheuvel Subject: Re: [edk2-devel] [PATCH edk2-platforms 1/1] Platform/QemuSbsa: define NS EL2 virtual timer in GTDT Message-ID: References: <20230920082509.383643-1-marcin.juszkiewicz@linaro.org> <20230920082509.383643-2-marcin.juszkiewicz@linaro.org> MIME-Version: 1.0 In-Reply-To: <20230920082509.383643-2-marcin.juszkiewicz@linaro.org> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-GUID: G19W_S-KIgzoUFJfg3oAjw4dqejSlCPS X-Proofpoint-ORIG-GUID: G19W_S-KIgzoUFJfg3oAjw4dqejSlCPS Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,quic_llindhol@quicinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: c3zkdeu7TYeeb6vVzar7pm2tx7686176AA= Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=HLcPZtn9; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=quicinc.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On Wed, Sep 20, 2023 at 10:25:09 +0200, Marcin Juszkiewicz wrote: > Armv8.1+ cpus have Virtual Host Extension (VHE) which added non-secure > EL2 virtual timer. > > This change adds it into GTDT to fullfil Arm BSA (Base System > Architecture) requirements. > > Signed-off-by: Marcin Juszkiewicz > --- > Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 2 ++ > Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 + > Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc | 4 ++-- > 3 files changed, 5 insertions(+), 2 deletions(-) > > diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > index be406144c242..8bea9793451a 100644 > --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > @@ -447,6 +447,8 @@ [PcdsFixedAtBuild.common] > gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27 > # PPI #10 > gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26 > + # PPI #12 > + gArmTokenSpaceGuid.PcdArmArchTimerHypVirtIntrNum|28 > > ## PL031 RealTimeClock > gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x60010000 > diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf > index 97021f7971c7..343c75f0b4ec 100644 > --- a/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf > +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf > @@ -36,6 +36,7 @@ [FixedPcd] > gArmTokenSpaceGuid.PcdArmArchTimerIntrNum > gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum > gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum > + gArmTokenSpaceGuid.PcdArmArchTimerHypVirtIntrNum > > gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId > gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision > diff --git a/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc b/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc > index ba145aff6413..b5e8f8405d61 100644 > --- a/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc > +++ b/Silicon/Qemu/SbsaQemu/AcpiTables/Gtdt.aslc > @@ -91,8 +91,8 @@ > SBSA_PLATFORM_TIMER_COUNT, // UINT32 PlatformTimerCount > sizeof(EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE), > // UINT32 PlatformTimerOffset > - 0, // UINT32 VirtualPL2TimerGSIV > - 0 // UINT32 VirtualPL2TimerFlags > + FixedPcdGet32 (PcdArmArchTimerHypVirtIntrNum),// UINT32 VirtualPL2TimerGSIV > + GTDT_GTIMER_FLAGS // UINT32 VirtualPL2TimerFlags It's still valid to use other CPUs than "max" with this platform. Don't we need to conditionalise this based on the contents of the VH bits in ID_AA64MFR1_EL1? Ideally, we'd add a helper function in edk2 ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c, like ArmHasCcidx(), and conditionalise on that. Hmm, but we'd probably also need to move from .aslc to manually construction GTDT in SbsaQemuAcpiDxe... If you're up for doing the GTDT rework, I could create the ArmLib helper function. / Leif > }, > EFI_ACPI_6_3_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT( > SBSAQEMU_WDT_REFRESH_FRAME_BASE, > -- > 2.41.0 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#108905): https://edk2.groups.io/g/devel/message/108905 Mute This Topic: https://groups.io/mt/101474460/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/12367111/7686176/1913456212/xyzzy [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-