From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id B452DD8021D for ; Wed, 4 Oct 2023 11:36:30 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=WmxSARBhInaGywHOOpF2abKleo5M9hGxp0E1EuiJ5iE=; c=relaxed/simple; d=groups.io; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20140610; t=1696419389; v=1; b=Z26OdSbD4Ib/ibFYg9U9t1IzO9XD45rbVeMos3hnCyY3QNMFpibzPNxL4MbenFIeGMQPTtln gEvwjH3uaEve4Vt80l/zI0e5MghwhFbTXB/BUWrLjaguUVuv7wvgFVNI7A0TH9PK2cyB3P5SsUa i7Ge/WZovKE5YuXP9lnlSrtg= X-Received: by 127.0.0.2 with SMTP id 44XYYY7687511xtiUeaUgTfP; Wed, 04 Oct 2023 04:36:29 -0700 X-Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) by mx.groups.io with SMTP id smtpd.web11.16021.1696419388761774399 for ; Wed, 04 Oct 2023 04:36:28 -0700 X-Received: by mail-pf1-f180.google.com with SMTP id d2e1a72fcca58-692c02adeefso1498220b3a.3 for ; Wed, 04 Oct 2023 04:36:28 -0700 (PDT) X-Gm-Message-State: NpQZj2CB6mEVIWZjtuskgWnEx7686176AA= X-Google-Smtp-Source: AGHT+IGGE7AKXSdN1118emn6EroJ7NHocnQfWYkjSx1emJH+1xEEsiYQmZfwQqO7ExbxI5WFwJSTBg== X-Received: by 2002:a05:6a20:6a28:b0:14c:a53c:498e with SMTP id p40-20020a056a206a2800b0014ca53c498emr2289239pzk.42.1696419388130; Wed, 04 Oct 2023 04:36:28 -0700 (PDT) X-Received: from sunil-laptop ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id a20-20020a170903101400b001c60a548331sm3460621plb.304.2023.10.04.04.36.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 04:36:27 -0700 (PDT) Date: Wed, 4 Oct 2023 17:06:12 +0530 From: "Sunil V L" To: Tuan Phan Cc: devel@edk2.groups.io, michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, git@danielschaefer.me, andrei.warkentin@intel.com, ardb+tianocore@kernel.org, Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode Message-ID: References: <20231003210021.26834-1-tphan@ventanamicro.com> MIME-Version: 1.0 In-Reply-To: <20231003210021.26834-1-tphan@ventanamicro.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=Z26OdSbD; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=none Hi Tuan, Thanks for the patch!. Adding UefiCpuPkg maintainers. On Tue, Oct 03, 2023 at 02:00:21PM -0700, Tuan Phan wrote: > Introduce a PCD to control the maximum SATP mode that MMU allowed > to use. This PCD helps RISC-V platform set bare or minimum SATA mode SATA -> SATP > during bring up to debug memory map issue. > > Signed-off-by: Tuan Phan > --- > UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 +++++- > UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++ > UefiCpuPkg/UefiCpuPkg.dec | 8 ++++++++ > 3 files changed, 16 insertions(+), 1 deletion(-) > > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > index 9cca5fc128af..826a1d32a1d4 100644 > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > @@ -36,7 +36,7 @@ > #define PTE_PPN_SHIFT 10 > #define RISCV_MMU_PAGE_SHIFT 12 > > -STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39 }; > +STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF }; > STATIC UINTN mMaxRootTableLevel; > STATIC UINTN mBitPerLevel; > STATIC UINTN mTableEntryCount; > @@ -590,6 +590,10 @@ RiscVMmuSetSatpMode ( > UINTN Index; > EFI_STATUS Status; > > + if (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) { > + return EFI_DEVICE_ERROR; > + } > + > switch (SatpMode) { > case SATP_MODE_OFF: > return EFI_SUCCESS; > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > index 9b28a98cb346..51ebe1750e97 100644 > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > @@ -25,3 +25,6 @@ > > [LibraryClasses] > BaseLib > + > +[Pcd] > + gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ## CONSUMES > diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec > index 68473fc640e6..79191af18a05 100644 > --- a/UefiCpuPkg/UefiCpuPkg.dec > +++ b/UefiCpuPkg/UefiCpuPkg.dec > @@ -396,6 +396,14 @@ > # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock. > gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F > > +[PcdsFixedAtBuild.RISCV64] > + ## Indicate the maximum SATP mode allowed. > + # 0 - Bare mode. > + # 8 - 39bit mode. > + # 9 - 48bit mode. > + # 10 - 57bit mode. > + gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0|UINT32|0x60000021 > + Shouldn't the default value be 10? Thanks, Sunil > [PcdsDynamic, PcdsDynamicEx] > ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA. > # @Prompt The pointer to a CPU S3 data buffer. > -- > 2.25.1 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109314): https://edk2.groups.io/g/devel/message/109314 Mute This Topic: https://groups.io/mt/101742937/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-