From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 2E7659410C2 for ; Thu, 5 Oct 2023 04:14:24 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=+AUMocPfnM07MNf2gWd8Jy37Bq2SycqOjBly3Hwl+wM=; c=relaxed/simple; d=groups.io; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20140610; t=1696479263; v=1; b=m1jOcLIG0zvqTcMiZNL5D/EBJyIGx8AzPc0jP9Gum3NryqLosvFxP0IUjXqz0qoDmD38ZUiP N6uc4XxIaFHqhdChnoaL+LY+Z3+7g8VyzT5dmmgVl0uMcHP3RV/Kkc0RBS3MBUT73AW/PkMTD8z shmUbsFNDWUY9OFmiZJ3sIw0= X-Received: by 127.0.0.2 with SMTP id 2kfzYY7687511xh9AtUn5QJz; Wed, 04 Oct 2023 21:14:23 -0700 X-Received: from mail-io1-f44.google.com (mail-io1-f44.google.com [209.85.166.44]) by mx.groups.io with SMTP id smtpd.web10.8296.1696479262899760597 for ; Wed, 04 Oct 2023 21:14:23 -0700 X-Received: by mail-io1-f44.google.com with SMTP id ca18e2360f4ac-79f909071c3so26219739f.0 for ; Wed, 04 Oct 2023 21:14:22 -0700 (PDT) X-Gm-Message-State: 4UsJsdwIZ4jzbwViXb2iC4Vyx7686176AA= X-Google-Smtp-Source: AGHT+IER78hkEJ2HCWnUSmlXn4D6ZIMYfzjWGKvorYLOl2YDplVDRmgYLF/XrBjxU8l/dJSuqQ90Tw== X-Received: by 2002:a05:6e02:b2b:b0:351:4f0c:b966 with SMTP id e11-20020a056e020b2b00b003514f0cb966mr4781933ilu.20.1696479261983; Wed, 04 Oct 2023 21:14:21 -0700 (PDT) X-Received: from sunil-laptop ([106.51.83.242]) by smtp.gmail.com with ESMTPSA id x7-20020a92de07000000b0035129b9c61bsm185434ilm.45.2023.10.04.21.14.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 21:14:21 -0700 (PDT) Date: Thu, 5 Oct 2023 09:44:13 +0530 From: "Sunil V L" To: Tuan Phan Cc: devel@edk2.groups.io, michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, git@danielschaefer.me, andrei.warkentin@intel.com, ardb+tianocore@kernel.org, eric.dong@intel.com, kraxel@redhat.com, rahul1.kumar@intel.com, ray.ni@intel.com, Dhaval Sharma Subject: Re: [edk2-devel] [PATCH v2] UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode Message-ID: References: <20231004183426.5803-1-tphan@ventanamicro.com> MIME-Version: 1.0 In-Reply-To: <20231004183426.5803-1-tphan@ventanamicro.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=m1jOcLIG; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On Wed, Oct 04, 2023 at 11:34:26AM -0700, Tuan Phan wrote: > Introduce a PCD to control the maximum SATP mode that MMU allowed > to use. This PCD helps RISC-V platform set bare or minimum SATP mode > during bring up to debug memory map issue. > > Signed-off-by: Tuan Phan > Reviewed-by: Dhaval Sharma > --- > Changes: > V2 > - Changed default mode to SV57 > > UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 6 +++++- > UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 3 +++ > UefiCpuPkg/UefiCpuPkg.dec | 8 ++++++++ > 3 files changed, 16 insertions(+), 1 deletion(-) > > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > index 9cca5fc128af..826a1d32a1d4 100644 > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > @@ -36,7 +36,7 @@ > #define PTE_PPN_SHIFT 10 > #define RISCV_MMU_PAGE_SHIFT 12 > > -STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39 }; > +STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF }; > STATIC UINTN mMaxRootTableLevel; > STATIC UINTN mBitPerLevel; > STATIC UINTN mTableEntryCount; > @@ -590,6 +590,10 @@ RiscVMmuSetSatpMode ( > UINTN Index; > EFI_STATUS Status; > > + if (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) { > + return EFI_DEVICE_ERROR; > + } > + > switch (SatpMode) { > case SATP_MODE_OFF: > return EFI_SUCCESS; > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > index 9b28a98cb346..51ebe1750e97 100644 > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > @@ -25,3 +25,6 @@ > > [LibraryClasses] > BaseLib > + > +[Pcd] > + gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ## CONSUMES > diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec > index 68473fc640e6..0b5431dbf70a 100644 > --- a/UefiCpuPkg/UefiCpuPkg.dec > +++ b/UefiCpuPkg/UefiCpuPkg.dec > @@ -396,6 +396,14 @@ > # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock. > gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F > > +[PcdsFixedAtBuild.RISCV64] > + ## Indicate the maximum SATP mode allowed. > + # 0 - Bare mode. > + # 8 - 39bit mode. > + # 9 - 48bit mode. > + # 10 - 57bit mode. > + gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|10|UINT32|0x60000021 > + LGTM. Thanks! Reviewed-by: Sunil V L > [PcdsDynamic, PcdsDynamicEx] > ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA. > # @Prompt The pointer to a CPU S3 data buffer. > -- > 2.25.1 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109340): https://edk2.groups.io/g/devel/message/109340 Mute This Topic: https://groups.io/mt/101761642/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-