From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 11DC9AC0EB7 for ; Mon, 30 Oct 2023 10:56:08 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=um4m3ELo9nMmjHKgHocgT5nloi1jjsJXMwZ4oMnQkiA=; c=relaxed/simple; d=groups.io; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20140610; t=1698663367; v=1; b=LgCfTjPSxNaKRy0dbNqyvIrzbT7rrqs1oJMXXOUmKaEdQPphsXL4JHoeVDlvKr6DucMIbjuT FA1TBqExpIAke2H1oq8g1k6s3Tjxfz3BcWbFas+j0c0WazzzH2x2+zpCnEOjewk+hVtr7ZyyT2F +3u1yI39N9MTyjZk6+I6U8j8= X-Received: by 127.0.0.2 with SMTP id Ug7TYY7687511xVl6EK93B3e; Mon, 30 Oct 2023 03:56:07 -0700 X-Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) by mx.groups.io with SMTP id smtpd.web10.145834.1698663366812329030 for ; Mon, 30 Oct 2023 03:56:06 -0700 X-Received: by mail-pf1-f176.google.com with SMTP id d2e1a72fcca58-6b20577ef7bso3583274b3a.3 for ; Mon, 30 Oct 2023 03:56:06 -0700 (PDT) X-Gm-Message-State: Vprox9xiagsODXmrmnGXRsF5x7686176AA= X-Google-Smtp-Source: AGHT+IEPTETuIXoZe9wfiTrs99hPg+t00dl+tP3A2LCgMPNxQl1TdkAFNpgKf8I9XkYdRAqdrVc4LA== X-Received: by 2002:a05:6a00:10c6:b0:6b5:92d9:ef44 with SMTP id d6-20020a056a0010c600b006b592d9ef44mr8288950pfu.7.1698663365890; Mon, 30 Oct 2023 03:56:05 -0700 (PDT) X-Received: from sunil-laptop ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id t19-20020a056a0021d300b006934e7ceb79sm5675396pfj.32.2023.10.30.03.56.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 03:56:05 -0700 (PDT) Date: Mon, 30 Oct 2023 16:25:58 +0530 From: "Sunil V L" To: Dhaval Cc: devel@edk2.groups.io, Michael D Kinney , Liming Gao , Zhiguang Liu , Daniel Schaefer , Laszlo Ersek Subject: Re: [edk2-devel] [PATCH v7 3/5] MdePkg: Implement RISC-V Cache Management Operations Message-ID: References: <20231029144613.150580-1-dhaval@rivosinc.com> <20231029144613.150580-4-dhaval@rivosinc.com> MIME-Version: 1.0 In-Reply-To: <20231029144613.150580-4-dhaval@rivosinc.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=LgCfTjPS; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On Sun, Oct 29, 2023 at 08:16:11PM +0530, Dhaval wrote: > Implement Cache Management Operations (CMO) defined by > RISC-V spec https://github.com/riscv/riscv-CMOs. > > Notes: > 1. CMO only supports block based Operations. Meaning cache > flush/invd/clean Operations are not available for the entire > range. In that case we fallback on fence.i instructions. > 2. Operations are implemented using Opcodes to make them compiler > independent. binutils 2.39+ compilers support CMO instructions. > > Test: > 1. Ensured correct instructions are refelecting in asm > 2. Not able to verify actual instruction in HW as Qemu ignores > any actual cache operations. > > Cc: Michael D Kinney > Cc: Liming Gao > Cc: Zhiguang Liu > Cc: Sunil V L > Cc: Daniel Schaefer > Cc: Laszlo Ersek > > Signed-off-by: Dhaval Sharma > Reviewed-by: Laszlo Ersek > --- > > Notes: > V7: > - Modify instruction names as per feedback from V6 > - Added RB > V6: > - Implement Cache management instructions in Baselib > > MdePkg/Library/BaseLib/BaseLib.inf | 2 +- > MdePkg/Include/Library/BaseLib.h | 33 ++++++++++++++++++++ > MdePkg/Include/RiscV64/RiscVasm.inc | 19 +++++++++++ > MdePkg/Library/BaseLib/RiscV64/{FlushCache.S => RiscVCacheMgmt.S} | 17 ++++++++++ > 4 files changed, 70 insertions(+), 1 deletion(-) > > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf > index 03c7b02e828b..53389389448c 100644 > --- a/MdePkg/Library/BaseLib/BaseLib.inf > +++ b/MdePkg/Library/BaseLib/BaseLib.inf > @@ -400,7 +400,7 @@ [Sources.RISCV64] > RiscV64/RiscVCpuBreakpoint.S | GCC > RiscV64/RiscVCpuPause.S | GCC > RiscV64/RiscVInterrupt.S | GCC > - RiscV64/FlushCache.S | GCC > + RiscV64/RiscVCacheMgmt.S | GCC > RiscV64/CpuScratch.S | GCC > RiscV64/ReadTimer.S | GCC > RiscV64/RiscVMmu.S | GCC > diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h > index d4b56a9601da..c42cc165dc82 100644 > --- a/MdePkg/Include/Library/BaseLib.h > +++ b/MdePkg/Include/Library/BaseLib.h > @@ -226,6 +226,39 @@ RiscVInvalidateDataCacheAsmFence ( > VOID > ); > > +/** > + RISC-V flush cache block. Atomically perform a clean operation > + followed by an invalidate operation > + > +**/ > +VOID > +EFIAPI > +RiscVCpuCacheFlushAsmCmo ( NIT: I would keep Asm at the end for these interface names. Otherwise, Reviewed-by: Sunil V L Thanks, Sunil -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110307): https://edk2.groups.io/g/devel/message/110307 Mute This Topic: https://groups.io/mt/102256466/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-