From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 157B2941435 for ; Mon, 30 Oct 2023 11:18:20 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=0j6ht/gUoTUAPg4sr02OESMpyOnXQe8SHkjfC9hAyEs=; c=relaxed/simple; d=groups.io; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20140610; t=1698664699; v=1; b=wuV2VByzBfItUaU1GoJR93WkwDlmiiIAAUEGj6IUDtyD6A+TG4R5HgWYE5vsuuEWzYve1Fea KnuDhTQmLXf3j74UA3jrk9cOS99QHgADgUHBkVZCGRiuWVqo1xE3Xld5cuXRnHLfQX4DARjOaOC 2Sd7/zM6GIQW8OzyH2PlLsaY= X-Received: by 127.0.0.2 with SMTP id wvtAYY7687511xx1OEs2hSk4; Mon, 30 Oct 2023 04:18:19 -0700 X-Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) by mx.groups.io with SMTP id smtpd.web11.146322.1698664698986030828 for ; Mon, 30 Oct 2023 04:18:19 -0700 X-Received: by mail-pf1-f180.google.com with SMTP id d2e1a72fcca58-6c0f14d6875so801401b3a.1 for ; Mon, 30 Oct 2023 04:18:18 -0700 (PDT) X-Gm-Message-State: YYwfHd7NDP2b4F4KIFQrwvC5x7686176AA= X-Google-Smtp-Source: AGHT+IFTGD+CEqwL/hl7ag18lA20vaatMPqkA5VQru7MdH8edHG4O74vBnRxvRh8IzMaWSDPBfgGrw== X-Received: by 2002:a05:6a00:2284:b0:6be:5367:2131 with SMTP id f4-20020a056a00228400b006be53672131mr8190397pfe.24.1698664697961; Mon, 30 Oct 2023 04:18:17 -0700 (PDT) X-Received: from sunil-laptop ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id b5-20020aa78705000000b0068fb8e18971sm5674992pfo.130.2023.10.30.04.18.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 04:18:17 -0700 (PDT) Date: Mon, 30 Oct 2023 16:48:11 +0530 From: "Sunil V L" To: devel@edk2.groups.io, dhaval@rivosinc.com Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Laszlo Ersek Subject: Re: [edk2-devel] [PATCH v7 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V Message-ID: References: <20231029144613.150580-1-dhaval@rivosinc.com> <20231029144613.150580-5-dhaval@rivosinc.com> MIME-Version: 1.0 In-Reply-To: <20231029144613.150580-5-dhaval@rivosinc.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=wuV2VByz; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On Sun, Oct 29, 2023 at 08:16:12PM +0530, Dhaval Sharma wrote: > Use newly defined cache management operations for RISC-V where possible > It builds up on the support added for RISC-V cache management > instructions in BaseLib. > Cc: Michael D Kinney > Cc: Liming Gao > Cc: Zhiguang Liu > Cc: Laszlo Ersek > > Signed-off-by: Dhaval Sharma > Acked-by: Laszlo Ersek > --- > > Notes: > V7: > - Added PcdLib > - Restructure DEBUG message based on feedback on V6 > - Make naming consistent to CMO, remove all CBO references > - Add ASSERT for not supported functions instead of plain debug message > - Added RB tag > V6: > - Utilize cache management instructions if HW supports it > This patch is part of restructuring on top of v5 > > MdePkg/MdePkg.dec | 8 + > MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf | 5 + > MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 168 +++++++++++++++++--- > MdePkg/MdePkg.uni | 4 + > 4 files changed, 165 insertions(+), 20 deletions(-) > > diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec > index ac54338089e8..fa92673ff633 100644 > --- a/MdePkg/MdePkg.dec > +++ b/MdePkg/MdePkg.dec > @@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AARCH64] > # @Prompt CPU Rng algorithm's GUID. > gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x00000037 > > +[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64] > + # > + # Configurability to override RISC-V CPU Features > + # BIT 0 = Cache Management Operations. This bit is relevant only if > + # previous stage has feature enabled and user wants to disable it. NIT: I am wondering whether PcdRiscVCpuFeatureDisable is better so that it is explicit. > + # > + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT64|0x69 > + Instead of this, can default value match only those features which are enabled by default for qemu virt machine? That way, I think we can avoid having this PCD defined again in RiscVVirt. > [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] > ## This value is used to set the base address of PCI express hierarchy. > # @Prompt PCI Express Base Address. > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf > index 6fd9cbe5f6c9..601a38d6c109 100644 > --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf > @@ -56,3 +56,8 @@ [LibraryClasses] > BaseLib > DebugLib > > +[LibraryClasses.RISCV64] > + PcdLib > + > +[Pcd.RISCV64] > + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c > index 4eb18edb9aa7..5b3104afb67e 100644 > --- a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c > @@ -2,6 +2,7 @@ > RISC-V specific functionality for cache. > > Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
> + Copyright (c) 2023, Rivos Inc. All rights reserved.
> > SPDX-License-Identifier: BSD-2-Clause-Patent > **/ > @@ -9,10 +10,115 @@ > #include > #include > #include > +#include > + > +// > +// TODO: Grab cache block size and make Cache Management Operation > +// enabling decision based on RISC-V CPU HOB in > +// future when it is available. > +// > +#define RISCV_CACHE_BLOCK_SIZE 64 > +#define RISCV_CPU_FEATURE_CMO_BITMASK 0x1 > + Can we define these bits in the header file so that the definitions can be used by multiple modules? Thanks, Sunil -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110308): https://edk2.groups.io/g/devel/message/110308 Mute This Topic: https://groups.io/mt/102256468/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-