From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id B6D33941435 for ; Mon, 30 Oct 2023 11:22:17 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=KHlp7Ld9WEeViTCUEvC8eiZpqMueJD4hvT4r1P2hexw=; c=relaxed/simple; d=groups.io; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20140610; t=1698664936; v=1; b=BJQzRAu+HycmM+MB2gkpd1nGg69Hu+g9qjOr145JmaZNs+l4zaulqBB/lDI7PDTiNYiYxAde I7jbGyY1kcsbOM3eTL0MSBU0Yhd01PEmCUZVeXauxBHPdk1zcpLo3kYCmnV6xZkoRs14+o9ujmS GyJ4HhPoBfDNm13sR6Veb1Qk= X-Received: by 127.0.0.2 with SMTP id mN1NYY7687511xvPu61sRTCq; Mon, 30 Oct 2023 04:22:16 -0700 X-Received: from mail-pf1-f181.google.com (mail-pf1-f181.google.com [209.85.210.181]) by mx.groups.io with SMTP id smtpd.web10.146256.1698664935764773006 for ; Mon, 30 Oct 2023 04:22:15 -0700 X-Received: by mail-pf1-f181.google.com with SMTP id d2e1a72fcca58-6b20a48522fso3822094b3a.1 for ; Mon, 30 Oct 2023 04:22:15 -0700 (PDT) X-Gm-Message-State: WXJFIsFcaOOCxUTwHIpm8uUmx7686176AA= X-Google-Smtp-Source: AGHT+IEfB08BLt5qttchqDxfA1Lhwm18Ojz12RitFj3esKmK7aAWPuOQs8r/WGsAjlSMMktGNMElLA== X-Received: by 2002:a05:6a00:23d4:b0:6be:22db:7a13 with SMTP id g20-20020a056a0023d400b006be22db7a13mr8789709pfc.25.1698664934855; Mon, 30 Oct 2023 04:22:14 -0700 (PDT) X-Received: from sunil-laptop ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id g4-20020aa78744000000b0068e49cb1692sm5714030pfo.1.2023.10.30.04.22.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 04:22:14 -0700 (PDT) Date: Mon, 30 Oct 2023 16:52:08 +0530 From: "Sunil V L" To: devel@edk2.groups.io, dhaval@rivosinc.com Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Laszlo Ersek Subject: Re: [edk2-devel] [PATCH v7 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V Message-ID: References: <20231029144613.150580-1-dhaval@rivosinc.com> <20231029144613.150580-5-dhaval@rivosinc.com> MIME-Version: 1.0 In-Reply-To: Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=BJQzRAu+; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On Mon, Oct 30, 2023 at 04:48:18PM +0530, Sunil V L wrote: > On Sun, Oct 29, 2023 at 08:16:12PM +0530, Dhaval Sharma wrote: > > Use newly defined cache management operations for RISC-V where possible > > It builds up on the support added for RISC-V cache management > > instructions in BaseLib. > > Cc: Michael D Kinney > > Cc: Liming Gao > > Cc: Zhiguang Liu > > Cc: Laszlo Ersek > > > > Signed-off-by: Dhaval Sharma > > Acked-by: Laszlo Ersek > > --- > > > > Notes: > > V7: > > - Added PcdLib > > - Restructure DEBUG message based on feedback on V6 > > - Make naming consistent to CMO, remove all CBO references > > - Add ASSERT for not supported functions instead of plain debug message > > - Added RB tag > > V6: > > - Utilize cache management instructions if HW supports it > > This patch is part of restructuring on top of v5 > > > > MdePkg/MdePkg.dec | 8 + > > MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf | 5 + > > MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c | 168 +++++++++++++++++--- > > MdePkg/MdePkg.uni | 4 + > > 4 files changed, 165 insertions(+), 20 deletions(-) > > > > diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec > > index ac54338089e8..fa92673ff633 100644 > > --- a/MdePkg/MdePkg.dec > > +++ b/MdePkg/MdePkg.dec > > @@ -2399,6 +2399,14 @@ [PcdsFixedAtBuild.AARCH64, PcdsPatchableInModule.AARCH64] > > # @Prompt CPU Rng algorithm's GUID. > > gEfiMdePkgTokenSpaceGuid.PcdCpuRngSupportedAlgorithm|{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}|VOID*|0x00000037 > > > > +[PcdsFixedAtBuild.RISCV64, PcdsPatchableInModule.RISCV64] > > + # > > + # Configurability to override RISC-V CPU Features > > + # BIT 0 = Cache Management Operations. This bit is relevant only if > > + # previous stage has feature enabled and user wants to disable it. > NIT: I am wondering whether PcdRiscVCpuFeatureDisable is better so that > it is explicit. > > > + # > > + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT64|0x69 > > + > Instead of this, can default value match only those features which are > enabled by default for qemu virt machine? That way, I think we can avoid > having this PCD defined again in RiscVVirt. > Sorry, I take back. This is common for all platforms. So, we can't take qemu as reference. Thanks, Sunil -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110309): https://edk2.groups.io/g/devel/message/110309 Mute This Topic: https://groups.io/mt/102256468/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-