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From: "Sunil V L" <sunilvl@ventanamicro.com>
To: Dhaval <dhaval@rivosinc.com>
Cc: devel@edk2.groups.io, Ard Biesheuvel <ardb+tianocore@kernel.org>,
	Jiewen Yao <jiewen.yao@intel.com>,
	Jordan Justen <jordan.l.justen@intel.com>,
	Gerd Hoffmann <kraxel@redhat.com>,
	Andrei Warkentin <andrei.warkentin@intel.com>,
	Laszlo Ersek <lersek@redhat.com>,
	Michael D Kinney <michael.d.kinney@intel.com>,
	Liming Gao <gaoliming@byosoft.com.cn>,
	Zhiguang Liu <zhiguang.liu@intel.com>,
	Daniel Schaefer <git@danielschaefer.me>
Subject: Re: [edk2-devel] [PATCH v8 0/5] Cache Management Operations Support For RISC-V
Date: Tue, 7 Nov 2023 12:45:19 +0530	[thread overview]
Message-ID: <ZUnkB6SHQlJU8MJk@sunil-laptop> (raw)
In-Reply-To: <20231106025356.167717-1-dhaval@rivosinc.com>

On Mon, Nov 06, 2023 at 08:23:51AM +0530, Dhaval wrote:
> Implementing code to support Cache Management Operations (CMO) defined by
> RISC-V CMO instructions.https://github.com/riscv/riscv-CMOs
> This is a re-write of original series v5.
> The patchset contains 5 patches- created based on V5 feedback.
> 1. Restructuring of existing code and move instruction declarations into BaseLib
> 2. Renaming existing functions to denote type of instruction used to maanage cache.
>    This is useful for further patches where more cache management instructions are added.
> 3. Add the new cache maintenance operations to BaseLib, including the
> 	 new assembly instruction encodings.
> 4. Update BaseCacheMaintenanceLib (utilizing the new BaseLib primitives)
> 5. Add platform level PCD to allow overriding of RISC-V features.
> 
> Code Link: https://github.com/tianocore/edk2/pull/5002
> 
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Sunil V L <sunilvl@ventanamicro.com>
> Cc: Andrei Warkentin <andrei.warkentin@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> Cc: Daniel Schaefer <git@danielschaefer.me>
> 
> Dhaval (5):
>   MdePkg: Move RISC-V Cache Management Declarations Into BaseLib
>   MdePkg: Rename Cache Management Function To Clarify Fence Based Op
>   MdePkg: Implement RISC-V Cache Management Operations
>   MdePkg: Utilize Cache Management Operations Implementation For RISC-V
>   OvmfPkg/RiscVVirt: Override for RV CPU Features

If nobody objects,  I will merge this tomorrow  with or without ack from
MdePkg maintainers. The changes are related to RISC-V only anyway.

Thanks,
Sunil


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  parent reply	other threads:[~2023-11-07  7:15 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-06  2:53 [edk2-devel] [PATCH v8 0/5] Cache Management Operations Support For RISC-V Dhaval Sharma
2023-11-06  2:53 ` [edk2-devel] [PATCH v8 1/5] MdePkg: Move RISC-V Cache Management Declarations Into BaseLib Dhaval Sharma
2023-11-06  2:53 ` [edk2-devel] [PATCH v8 2/5] MdePkg: Rename Cache Management Function To Clarify Fence Based Op Dhaval Sharma
2023-11-06  2:53 ` [edk2-devel] [PATCH v8 3/5] MdePkg: Implement RISC-V Cache Management Operations Dhaval Sharma
2023-11-06  2:53 ` [edk2-devel] [PATCH v8 4/5] MdePkg: Utilize Cache Management Operations Implementation For RISC-V Dhaval Sharma
2023-11-06  2:53 ` [edk2-devel] [PATCH v8 5/5] OvmfPkg/RiscVVirt: Override for RV CPU Features Dhaval Sharma
2023-11-07  7:15 ` Sunil V L [this message]
2023-11-07 18:04   ` [edk2-devel] [PATCH v8 0/5] Cache Management Operations Support For RISC-V Laszlo Ersek
2023-11-08  3:48     ` Sunil V L

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