From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 4B37C78043B for ; Thu, 9 Nov 2023 14:12:15 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=Qu8t0OaUvDxZKzfg0TNjOAJ4V2JIkq/dd+nxftwdRFA=; c=relaxed/simple; d=groups.io; h=Date:From:To:CC:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20140610; t=1699539133; v=1; b=l98zKhn/sBmL/mQeh/VfCIYQriWLPZh11eiYB+XIjvt4w8aVN2n7eEbKDG5QBX3dcm4nUed3 KBdImpC8RM2aGQ6dQEv7qY/ZAqOY4jBpRU9dU3qFYTJ9QltBKHbhLgTbfx3c+9Nv2Q2xU8BfpFS t2uXs3xqv475zh1WSQBARMus= X-Received: by 127.0.0.2 with SMTP id POndYY7687511xNzxx4mMjFN; Thu, 09 Nov 2023 06:12:13 -0800 X-Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by mx.groups.io with SMTP id smtpd.web10.122014.1699539132889488323 for ; Thu, 09 Nov 2023 06:12:13 -0800 X-Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3A9Bi4jC021191; Thu, 9 Nov 2023 14:12:01 GMT X-Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u8sud99c0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Nov 2023 14:12:01 +0000 X-Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3A9EC04G026011 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 9 Nov 2023 14:12:00 GMT X-Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Thu, 9 Nov 2023 06:11:57 -0800 Date: Thu, 9 Nov 2023 14:11:53 +0000 From: "Leif Lindholm" To: Pierre Gondois CC: , Jiewen Yao , Yi Li , Xiaoyu Lu , Guomin Jiang , Ard Biesheuvel , Sami Mujawar , Gerd Hoffmann , Michael D Kinney , Liming Gao Subject: Re: [edk2-devel] [PATCH v2 1/7] MdePkg/BaseLib: AARCH64: Add ArmReadCntPctReg() Message-ID: References: <20231109092307.1770332-1-pierre.gondois@arm.com> <20231109092307.1770332-2-pierre.gondois@arm.com> MIME-Version: 1.0 In-Reply-To: <20231109092307.1770332-2-pierre.gondois@arm.com> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-GUID: gn8x1i30ye2xSRzKh1_OxC4mbWPS8xEf X-Proofpoint-ORIG-GUID: gn8x1i30ye2xSRzKh1_OxC4mbWPS8xEf Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,quic_llindhol@quicinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 2Ql6deWmYhsJ0jXuq9O7a1nmx7686176AA= Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="l98zKhn/"; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=quicinc.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On Thu, Nov 09, 2023 at 10:23:01 +0100, Pierre Gondois wrote: > To enable AARCH64 native instruction support for Openssl, > some interfaces must be implemented. OPENSSL_rdtsc() requests > an access to a counter to get some non-trusted entropy. > > Add ArmReadCntPctReg() to read system count. > A similar ArmReadCntPct() function is available in the ArmPkg, > but the CryptoPkg where OPENSSL_rdtsc will reside cannot rely > on the ArmPkg. This is patently untrue, as can be discovered by grepping for ArmPkg under CryptoPkg already. Yes, we have a problematic history around how architectures that weren't already in tree when edk2 was first published got introduced at a later date. But this bit of contortionism helps no one. Please move this to ArmPkg, which is effectively an exclave of MdePkg anyway. (Yes, there is an argument for moving ArmLib into MdePkg, but that quickly escalates through dependencies to moving all of ArmPkg into MdePkg, and that's a fairly big task.) / Leif > Signed-off-by: Pierre Gondois > --- > MdePkg/Include/Library/BaseLib.h | 14 +++++++++ > .../BaseLib/AArch64/ArmReadCntPctReg.S | 30 +++++++++++++++++++ > .../BaseLib/AArch64/ArmReadCntPctReg.asm | 30 +++++++++++++++++++ > MdePkg/Library/BaseLib/BaseLib.inf | 4 ++- > 4 files changed, 77 insertions(+), 1 deletion(-) > create mode 100644 MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.S > create mode 100644 MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.asm > > diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h > index 5d7067ee854e..b81c9dd83508 100644 > --- a/MdePkg/Include/Library/BaseLib.h > +++ b/MdePkg/Include/Library/BaseLib.h > @@ -126,6 +126,20 @@ typedef struct { > > #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 > > +/** > + Reads the current value of CNTPCT_EL0 register. > + > + Reads and returns the current value of CNTPCT_EL0. > + This function is only available on AARCH64. > + > + @return The current value of CNTPCT_EL0 > +**/ > +UINT64 > +EFIAPI > +ArmReadCntPctReg ( > + VOID > + ); > + > #endif // defined (MDE_CPU_AARCH64) > > #if defined (MDE_CPU_RISCV64) > diff --git a/MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.S b/MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.S > new file mode 100644 > index 000000000000..d5f3a0082a99 > --- /dev/null > +++ b/MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.S > @@ -0,0 +1,30 @@ > +#------------------------------------------------------------------------------ > +# > +# ArmReadCntPctReg() for AArch64 > +# > +# Copyright (c) 2023, Arm Limited. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +#------------------------------------------------------------------------------ > + > +.text > +.p2align 2 > +GCC_ASM_EXPORT(ArmReadCntPctReg) > + > +#/** > +# Reads the CNTPCT_EL0 Register. > +# > +# @return The contents of the CNTPCT_EL0 register. > +# > +#**/ > +#UINT64 > +#EFIAPI > +#ArmReadCntPctReg ( > +# VOID > +# ); > +# > +ASM_PFX(ArmReadCntPctReg): > + AARCH64_BTI(c) > + mrs x0, cntpct_el0 > + ret > diff --git a/MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.asm b/MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.asm > new file mode 100644 > index 000000000000..cfdfe4cea4eb > --- /dev/null > +++ b/MdePkg/Library/BaseLib/AArch64/ArmReadCntPctReg.asm > @@ -0,0 +1,30 @@ > +;------------------------------------------------------------------------------ > +; > +; ArmReadCntPctReg() for AArch64 > +; > +; Copyright (c) 2023, Arm Limited. All rights reserved.
> +; > +; SPDX-License-Identifier: BSD-2-Clause-Patent > +; > +;------------------------------------------------------------------------------ > + > + EXPORT ArmReadCntPctReg > + AREA BaseLib_LowLevel, CODE, READONLY > + > +;/** > +; Reads the CNTPCT_EL0 Register. > +; > +; @return The contents of the CNTPCT_EL0 register. > +; > +;**/ > +;UINT64 > +;EFIAPI > +;ArmReadCntPctReg ( > +; VOID > +; ); > +; > +ArmReadCntPctReg > + mrs x0, cntpct_el0 > + ret > + > + END > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf > index 03c7b02e828b..24e5e6c3ecb5 100644 > --- a/MdePkg/Library/BaseLib/BaseLib.inf > +++ b/MdePkg/Library/BaseLib/BaseLib.inf > @@ -3,7 +3,7 @@ > # > # Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
> -# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
> +# Portions copyright (c) 2011 - 2023, Arm Limited. All rights reserved.
> # Copyright (c) 2020 - 2021, Hewlett Packard Enterprise Development LP. All rights reserved.
> # > # SPDX-License-Identifier: BSD-2-Clause-Patent > @@ -376,6 +376,7 @@ [Sources.AARCH64] > AArch64/SetJumpLongJump.S | GCC > AArch64/CpuBreakpoint.S | GCC > AArch64/SpeculationBarrier.S | GCC > + AArch64/ArmReadCntPctReg.S | GCC > > AArch64/MemoryFence.asm | MSFT > AArch64/SwitchStack.asm | MSFT > @@ -385,6 +386,7 @@ [Sources.AARCH64] > AArch64/SetJumpLongJump.asm | MSFT > AArch64/CpuBreakpoint.asm | MSFT > AArch64/SpeculationBarrier.asm | MSFT > + AArch64/ArmReadCntPctReg.asm | MSFT > > [Sources.RISCV64] > Math64.c > -- > 2.25.1 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110983): https://edk2.groups.io/g/devel/message/110983 Mute This Topic: https://groups.io/mt/102482399/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/12367111/7686176/1913456212/xyzzy [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-