From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id EE2B37803D8 for ; Thu, 9 Nov 2023 14:14:41 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=osMmvJsauxi80ImuXlsFvGU7Uc7RjLCnb4nUp+7Nqh0=; c=relaxed/simple; d=groups.io; h=Date:From:To:CC:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20140610; t=1699539280; v=1; b=frXZeFfcTgpDH+WyYtjqgw6MLXw8JjwLJNA9my2mGFegXpCUFXIGPwv67hs5GCkT9253CbN7 mPGXIIa90Qp2bLaQbyiUrxf73swdqq7U3FqfCsENB/6vBKHIgueWOgnI/RONKEkGeyNbzo87YLW bC3+fkPSVB1Gj4VjQA90LOck= X-Received: by 127.0.0.2 with SMTP id gETMYY7687511xYuCOVE4iOB; Thu, 09 Nov 2023 06:14:40 -0800 X-Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by mx.groups.io with SMTP id smtpd.web10.122076.1699539280014299427 for ; Thu, 09 Nov 2023 06:14:40 -0800 X-Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3A9DjLP9007751; Thu, 9 Nov 2023 14:14:29 GMT X-Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u8nhd1w8s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Nov 2023 14:14:29 +0000 X-Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3A9EES80032750 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 9 Nov 2023 14:14:28 GMT X-Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Thu, 9 Nov 2023 06:14:25 -0800 Date: Thu, 9 Nov 2023 14:14:21 +0000 From: "Leif Lindholm" To: Pierre Gondois CC: , Jiewen Yao , Yi Li , Xiaoyu Lu , Guomin Jiang , Ard Biesheuvel , Sami Mujawar , Gerd Hoffmann , Michael D Kinney , Liming Gao Subject: Re: [edk2-devel] [PATCH v2 2/7] MdePkg/BaseLib: AARCH64: Add ArmReadIdAA64Isar0Reg() Message-ID: References: <20231109092307.1770332-1-pierre.gondois@arm.com> <20231109092307.1770332-3-pierre.gondois@arm.com> MIME-Version: 1.0 In-Reply-To: <20231109092307.1770332-3-pierre.gondois@arm.com> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-GUID: 3oYqyB_VuGW9TrK7OnJo3WXP1JD5tD68 X-Proofpoint-ORIG-GUID: 3oYqyB_VuGW9TrK7OnJo3WXP1JD5tD68 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,quic_llindhol@quicinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 3S97VMVpoldsAKSZRSVRXZAOx7686176AA= Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=frXZeFfc; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=quicinc.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On Thu, Nov 09, 2023 at 10:23:02 +0100, Pierre Gondois wrote: > To enable AARCH64 native instruction support for Openssl, > some interfaces must be implemented. OPENSSL_cpuid_setup() > allows to probe the supported features of the platform. > > Add ArmReadIdAA64Isar0Reg() to read the AA64Isar0, containing > Arm64 instruction capabilities. > A similar ArmReadIdAA64Isar0() function is available in the ArmPkg, > but the CryptoPkg where OPENSSL_cpuid_setup will reside cannot rely > on the ArmPkg. The word "similar" here does an exemplary job of explaining why this is problematic. / Leif > Signed-off-by: Pierre Gondois > --- > MdePkg/Include/Library/BaseLib.h | 72 +++++++++++++++++++ > .../BaseLib/AArch64/ArmReadIdAA64Isar0Reg.S | 30 ++++++++ > .../BaseLib/AArch64/ArmReadIdAA64Isar0Reg.asm | 30 ++++++++ > MdePkg/Library/BaseLib/BaseLib.inf | 2 + > 4 files changed, 134 insertions(+) > create mode 100644 MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.S > create mode 100644 MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.asm > > diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h > index b81c9dd83508..365d50cfb1b8 100644 > --- a/MdePkg/Include/Library/BaseLib.h > +++ b/MdePkg/Include/Library/BaseLib.h > @@ -140,6 +140,78 @@ ArmReadCntPctReg ( > VOID > ); > > +// > +// Bit shifts for the ID_AA64ISAR0_EL1 register. > +// > +#define ARM_ID_AA64ISAR0_EL1_AES_SHIFT (4U) > +#define ARM_ID_AA64ISAR0_EL1_SHA1_SHIFT (8U) > +#define ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT (12U) > +#define ARM_ID_AA64ISAR0_EL1_CRC32_SHIFT (16U) > +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_SHIFT (20U) > +#define ARM_ID_AA64ISAR0_EL1_RDM_SHIFT (28U) > +#define ARM_ID_AA64ISAR0_EL1_SHA3_SHIFT (32U) > +#define ARM_ID_AA64ISAR0_EL1_SM3_SHIFT (36U) > +#define ARM_ID_AA64ISAR0_EL1_SM4_SHIFT (40U) > +#define ARM_ID_AA64ISAR0_EL1_DP_SHIFT (44U) > +#define ARM_ID_AA64ISAR0_EL1_FHM_SHIFT (48U) > +#define ARM_ID_AA64ISAR0_EL1_TS_SHIFT (52U) > +#define ARM_ID_AA64ISAR0_EL1_TLB_SHIFT (56U) > +#define ARM_ID_AA64ISAR0_EL1_RNDR_SHIFT (60U) > + > +// > +// Bit masks for the ID_AA64ISAR0_EL1 fields. > +// > +#define ARM_ID_AA64ISAR0_EL1_AES_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_SHA1_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_SHA2_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_CRC32_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_RDM_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_SHA3_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_SM3_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_SM4_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_DP_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_FHM_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_TS_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_TLB_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_RNDR_MASK (0xFU) > + > +// > +// Bit masks for the ID_AA64ISAR0_EL1 field values. > +// > +#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_AES_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_PMULL_MASK (0x2U) > +#define ARM_ID_AA64ISAR0_EL1_SHA1_FEAT_SHA1_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA256_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA512_MASK (0x2U) > +#define ARM_ID_AA64ISAR0_EL1_CRC32_HAVE_CRC32_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_FEAT_LSE_MASK (0x2U) > +#define ARM_ID_AA64ISAR0_EL1_RDM_FEAT_RDM_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_SHA3_FEAT_SHA3_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_SM3_FEAT_SM3_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_SM4_FEAT_SM4_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_DP_FEAT_DOTPROD_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_FHM_FEAT_FHM_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM2_MASK (0x2U) > +#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIOS_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIRANGE_MASK (0x2U) > +#define ARM_ID_AA64ISAR0_EL1_RNDR_FEAT_RNG_MASK (0x1U) > + > +/** > + Reads the current value of ID_AA64ISAR0_EL1 register. > + > + Reads and returns the current value of ID_AA64ISAR0_EL1. > + This function is only available on AARCH64. > + > + @return The current value of ID_AA64ISAR0_EL1 > +**/ > +UINT64 > +EFIAPI > +ArmReadIdAA64Isar0Reg ( > + VOID > + ); > + > #endif // defined (MDE_CPU_AARCH64) > > #if defined (MDE_CPU_RISCV64) > diff --git a/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.S b/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.S > new file mode 100644 > index 000000000000..4e61b869a401 > --- /dev/null > +++ b/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.S > @@ -0,0 +1,30 @@ > +#------------------------------------------------------------------------------ > +# > +# ArmReadIdAA64Isar0Reg() for AArch64 > +# > +# Copyright (c) 2021, NUVIA Inc. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +#------------------------------------------------------------------------------ > + > +.text > +.p2align 2 > +GCC_ASM_EXPORT(ArmReadIdAA64Isar0Reg) > + > +#/** > +# Reads the ID_AA64ISAR0 Register. > +# > +# @return The contents of the ID_AA64ISAR0 register. > +# > +#**/ > +#UINT64 > +#EFIAPI > +#ArmReadIdAA64Isar0Reg ( > +# VOID > +# ); > +# > +ASM_PFX(ArmReadIdAA64Isar0Reg): > + AARCH64_BTI(c) > + mrs x0, id_aa64isar0_el1 > + ret > diff --git a/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.asm b/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.asm > new file mode 100644 > index 000000000000..790fb905d001 > --- /dev/null > +++ b/MdePkg/Library/BaseLib/AArch64/ArmReadIdAA64Isar0Reg.asm > @@ -0,0 +1,30 @@ > +;------------------------------------------------------------------------------ > +; > +; ArmReadIdAA64Isar0Reg() for AArch64 > +; > +; Copyright (c) 2021, NUVIA Inc. All rights reserved.
> +; > +; SPDX-License-Identifier: BSD-2-Clause-Patent > +; > +;------------------------------------------------------------------------------ > + > + EXPORT ArmReadIdAA64Isar0Reg > + AREA BaseLib_LowLevel, CODE, READONLY > + > +;/** > +; Reads the ID_AA64ISAR0 Register. > +; > +; @return The contents of the ID_AA64ISAR0 register. > +; > +;**/ > +;UINT64 > +;EFIAPI > +;ArmReadIdAA64Isar0Reg ( > +; VOID > +; ); > +; > +ArmReadIdAA64Isar0Reg > + mrs x0, id_aa64isar0_el1 > + ret > + > + END > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf > index 24e5e6c3ecb5..299bcaa56d39 100644 > --- a/MdePkg/Library/BaseLib/BaseLib.inf > +++ b/MdePkg/Library/BaseLib/BaseLib.inf > @@ -377,6 +377,7 @@ [Sources.AARCH64] > AArch64/CpuBreakpoint.S | GCC > AArch64/SpeculationBarrier.S | GCC > AArch64/ArmReadCntPctReg.S | GCC > + AArch64/ArmReadIdAA64Isar0Reg.S | GCC > > AArch64/MemoryFence.asm | MSFT > AArch64/SwitchStack.asm | MSFT > @@ -387,6 +388,7 @@ [Sources.AARCH64] > AArch64/CpuBreakpoint.asm | MSFT > AArch64/SpeculationBarrier.asm | MSFT > AArch64/ArmReadCntPctReg.asm | MSFT > + AArch64/ArmReadIdAA64Isar0Reg.asm | MSFT > > [Sources.RISCV64] > Math64.c > -- > 2.25.1 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110984): https://edk2.groups.io/g/devel/message/110984 Mute This Topic: https://groups.io/mt/102482400/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/12367111/7686176/1913456212/xyzzy [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-