From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 3B9C2780091 for ; Wed, 15 Nov 2023 18:39:39 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=dzkc0EnqB5eU8TD0xMQZu8O/VYkT/JmMCK0jSQBetBU=; c=relaxed/simple; d=groups.io; h=Date:From:To:CC:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20140610; t=1700073577; v=1; b=OQYyWUIRxJct4fHuEqXjgVhXzMzp960sOJnBvon+TBt7VZSvBDCDIXeEpaf3ZkoxaCNj9xZ4 WRMq2g7OWGvVeFcpKgC6ZTXuyEkt1TUmG8V4T8ZBEWC2vLOD3TSS7knzSRWTv9l+OMGWOZEYJtP VooGQcrp0wg4DJ6S5LHLGIhU= X-Received: by 127.0.0.2 with SMTP id 8nxDYY7687511xjc11im1iwo; Wed, 15 Nov 2023 10:39:37 -0800 X-Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by mx.groups.io with SMTP id smtpd.web10.21285.1700073577373268488 for ; Wed, 15 Nov 2023 10:39:37 -0800 X-Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AFFK1n4004070; Wed, 15 Nov 2023 18:39:34 GMT X-Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ucg2uantf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Nov 2023 18:39:33 +0000 X-Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AFIdPEB019150 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Nov 2023 18:39:25 GMT X-Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Wed, 15 Nov 2023 10:39:22 -0800 Date: Wed, 15 Nov 2023 18:39:19 +0000 From: "Leif Lindholm" To: Pierre Gondois CC: , Jiewen Yao , Yi Li , Xiaoyu Lu , Guomin Jiang , Ard Biesheuvel , Sami Mujawar , Gerd Hoffmann Subject: Re: [edk2-devel] [PATCH v3 1/6] ArmPkg/ArmLib: Move ArmReadIdAA64Isar0() to ArmLib Message-ID: References: <20231110104810.2038376-1-pierre.gondois@arm.com> <20231110104810.2038376-2-pierre.gondois@arm.com> MIME-Version: 1.0 In-Reply-To: <20231110104810.2038376-2-pierre.gondois@arm.com> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-ORIG-GUID: csVhkkTz6peXIfN9eNrMI6b99HBGXnt5 X-Proofpoint-GUID: csVhkkTz6peXIfN9eNrMI6b99HBGXnt5 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,quic_llindhol@quicinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: ZwDYUUGshaHzyM61ztPtB7Y7x7686176AA= Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=OQYyWUIR; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=quicinc.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Hi Pierre, I apologise for asking this level of rework on a v3, but I would much prefer if we could add these definitions in ArmPkg/Include/Chipset/AArch64.h, add helper functions in AArch64Lib* and declare those in ArmLib.h - and then use those instead of doing the direct ID register accesses in AArch64Cap.c in 5/6. This follows the pattern that is used in that library already (and that we want to expand on). Regards, Leif On Fri, Nov 10, 2023 at 11:48:05 +0100, Pierre Gondois wrote: > Add ArmReadIdAA64Isar0() to ArmLib along with macros > to read specific register fields. > > Signed-off-by: Pierre Gondois > --- > ArmPkg/Include/Library/ArmLib.h | 68 ++++++++++++++++++++++ > ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h | 6 -- > 2 files changed, 68 insertions(+), 6 deletions(-) > > diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h > index 6aa8a48f07f3..1edaa8d45962 100644 > --- a/ArmPkg/Include/Library/ArmLib.h > +++ b/ArmPkg/Include/Library/ArmLib.h > @@ -805,6 +805,74 @@ ArmHasEte ( > VOID > ); > > +// > +// Bit shifts for the ID_AA64ISAR0_EL1 register. > +// > +#define ARM_ID_AA64ISAR0_EL1_AES_SHIFT (4U) > +#define ARM_ID_AA64ISAR0_EL1_SHA1_SHIFT (8U) > +#define ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT (12U) > +#define ARM_ID_AA64ISAR0_EL1_CRC32_SHIFT (16U) > +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_SHIFT (20U) > +#define ARM_ID_AA64ISAR0_EL1_RDM_SHIFT (28U) > +#define ARM_ID_AA64ISAR0_EL1_SHA3_SHIFT (32U) > +#define ARM_ID_AA64ISAR0_EL1_SM3_SHIFT (36U) > +#define ARM_ID_AA64ISAR0_EL1_SM4_SHIFT (40U) > +#define ARM_ID_AA64ISAR0_EL1_DP_SHIFT (44U) > +#define ARM_ID_AA64ISAR0_EL1_FHM_SHIFT (48U) > +#define ARM_ID_AA64ISAR0_EL1_TS_SHIFT (52U) > +#define ARM_ID_AA64ISAR0_EL1_TLB_SHIFT (56U) > +#define ARM_ID_AA64ISAR0_EL1_RNDR_SHIFT (60U) > + > +// > +// Bit masks for the ID_AA64ISAR0_EL1 fields. > +// > +#define ARM_ID_AA64ISAR0_EL1_AES_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_SHA1_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_SHA2_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_CRC32_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_RDM_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_SHA3_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_SM3_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_SM4_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_DP_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_FHM_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_TS_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_TLB_MASK (0xFU) > +#define ARM_ID_AA64ISAR0_EL1_RNDR_MASK (0xFU) > + > +// > +// Bit masks for the ID_AA64ISAR0_EL1 field values. > +// > +#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_AES_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_PMULL_MASK (0x2U) > +#define ARM_ID_AA64ISAR0_EL1_SHA1_FEAT_SHA1_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA256_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA512_MASK (0x2U) > +#define ARM_ID_AA64ISAR0_EL1_CRC32_HAVE_CRC32_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_FEAT_LSE_MASK (0x2U) > +#define ARM_ID_AA64ISAR0_EL1_RDM_FEAT_RDM_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_SHA3_FEAT_SHA3_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_SM3_FEAT_SM3_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_SM4_FEAT_SM4_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_DP_FEAT_DOTPROD_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_FHM_FEAT_FHM_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM2_MASK (0x2U) > +#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIOS_MASK (0x1U) > +#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIRANGE_MASK (0x2U) > +#define ARM_ID_AA64ISAR0_EL1_RNDR_FEAT_RNG_MASK (0x1U) > + > +/** Read AA64Isar0 register. > + > + @return AA64Isar0's register value. > +**/ > +UINTN > +EFIAPI > +ArmReadIdAA64Isar0 ( > + VOID > + ); > + > #endif // MDE_CPU_AARCH64 > > #ifdef MDE_CPU_ARM > diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h > index 6380a019ddc5..07181d940bdd 100644 > --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h > +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h > @@ -50,12 +50,6 @@ ArmReadIdAA64Dfr1 ( > VOID > ); > > -UINTN > -EFIAPI > -ArmReadIdAA64Isar0 ( > - VOID > - ); > - > UINTN > EFIAPI > ArmReadIdAA64Isar1 ( > -- > 2.25.1 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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