From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id B65C4941450 for ; Fri, 17 Nov 2023 11:35:27 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=5aVlwzAXkoc+0uzfZPeJzviOlqTl4toWQXLtEh48Jxw=; c=relaxed/simple; d=groups.io; h=Date:From:To:CC:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20140610; t=1700220926; v=1; b=wh9/RwYiHNPOPWut7au3hhMqCd+MnG9lHPlssLv7H07UWfmOSnC4JfJSeqvXkE5WkqRqSV9e DO9sdm2ggqzmvW8vGUZ0/koL0eW5cAK5q6l4zQSDu0sjewsIYQjcQmBWJW5aZVj2sMwB4kFwNU6 uc2kUzSeQ8UQbF7/bkYB1WdA= X-Received: by 127.0.0.2 with SMTP id cRDqYY7687511xEcPgMxZF9M; Fri, 17 Nov 2023 03:35:26 -0800 X-Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by mx.groups.io with SMTP id smtpd.web11.9666.1700220925828422296 for ; Fri, 17 Nov 2023 03:35:25 -0800 X-Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AHBZFc1031851; Fri, 17 Nov 2023 11:35:15 GMT X-Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3udw46s7wk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 11:35:15 +0000 X-Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AHBZE4P030821 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 17 Nov 2023 11:35:14 GMT X-Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Fri, 17 Nov 2023 03:35:12 -0800 Date: Fri, 17 Nov 2023 11:35:08 +0000 From: "Leif Lindholm" To: Chao Li CC: , Michael D Kinney , Liming Gao , Zhiguang Liu , Ard Biesheuvel , Sami Mujawar , Laszlo Ersek , Sunil V L Subject: Re: [edk2-devel] [PATCH v3 09/39] MdePkg: Add a new library named PeiServicesTablePointerLibReg Message-ID: References: <20231117095742.3605778-1-lichao@loongs> <20231117095949.3608941-1-lichao@loongson.cn> MIME-Version: 1.0 In-Reply-To: <20231117095949.3608941-1-lichao@loongson.cn> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-GUID: juqBneTEdGPglrBDzSx_co-8x13nxFzc X-Proofpoint-ORIG-GUID: juqBneTEdGPglrBDzSx_co-8x13nxFzc Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,quic_llindhol@quicinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 21rOLvJYd4L5Gkq9BUGy90C6x7686176AA= Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="wh9/RwYi"; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=quicinc.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Not my package, just spotted a typo below: On Fri, Nov 17, 2023 at 17:59:49 +0800, Chao Li wrote: > Since some ARCH or platform not require execute code on memory during > PEI phase, some values may transferred via CPU registers. > > Adding PeiServcieTablePointerLibReg to allow set and get the PEI service > table pointer depend by a CPU register, this library can accommodate lot > of platforms who not require execte code on memory during PEI phase. > > Adding PeiServiceTablePointerLibReg to allows setting and getting the > PEI service table pointer via CPU registers, and the library can > accommodate many platforms that do not need to execute code on memory > during the PEI phase. > > The idea of this library is derived from > ArmPkg/Library/PeiServicesTablePointerLib/ > > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=4584 > > Cc: Michael D Kinney > Cc: Liming Gao > Cc: Zhiguang Liu > Cc: Leif Lindholm > Cc: Ard Biesheuvel > Cc: Sami Mujawar > Cc: Laszlo Ersek > Cc: Sunil V L > Signed-off-by: Chao Li > --- > .../Library/PeiServicesTablePointerLib.h | 37 +++++++- > .../PeiServicesTablePointer.c | 86 +++++++++++++++++++ > .../PeiServicesTablePointerLib.uni | 20 +++++ > .../PeiServicesTablePointerLibReg.inf | 40 +++++++++ > MdePkg/MdePkg.dsc | 1 + > 5 files changed, 180 insertions(+), 4 deletions(-) > create mode 100644 MdePkg/Library/PeiServicesTablePointerLibReg/PeiServicesTablePointer.c > create mode 100644 MdePkg/Library/PeiServicesTablePointerLibReg/PeiServicesTablePointerLib.uni > create mode 100644 MdePkg/Library/PeiServicesTablePointerLibReg/PeiServicesTablePointerLibReg.inf > > diff --git a/MdePkg/Include/Library/PeiServicesTablePointerLib.h b/MdePkg/Include/Library/PeiServicesTablePointerLib.h > index 61635eff00..f5c764cb13 100644 > --- a/MdePkg/Include/Library/PeiServicesTablePointerLib.h > +++ b/MdePkg/Include/Library/PeiServicesTablePointerLib.h > @@ -52,10 +52,11 @@ SetPeiServicesTablePointer ( > immediately preceding the Interrupt Descriptor Table (IDT) in memory. > For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes > immediately preceding the Interrupt Descriptor Table (IDT) in memory. > - For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in > - a dedicated CPU register. This means that there is no memory storage > - associated with storing the PEI Services Table pointer, so no additional > - migration actions are required for Itanium or ARM CPUs. > + For Itanium, ARM and LoongArch CPUs, a the PEI Services Table Pointer > + is stored in a dedicated CPU register. This means that there is no > + memory storage associated with storing the PEI Services Table pointer, > + so no additional migration actions are required for Itanium, ARM and > + LoongArch CPUs. > > **/ > VOID > @@ -64,4 +65,32 @@ MigratePeiServicesTablePointer ( > VOID > ); > > +/** > + Retrieves the cached value of the PEI Services Table pointer from a CPU register. > + > + Returns the cached value of the PEI Services Table pointer in a CPU specific manner > + as specified in the CPU binding section of the Platform Initialization Pre-EFI > + Initialization Core Interface Specification. > + > + @return The pointer to PeiServices. > +**/ > +CONST EFI_PEI_SERVICES ** > +EFIAPI > +GetPeiServicesTablePointerFromRegister ( > + VOID > + ); > + > +/** > + Set the pointer PEI Service Table to a CPU register. > + > + Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer > + in a platform specific manner. > + > + @param PeiServicesTablePointer The address of PeiServices. > +**/ > +VOID > +EFIAPI > +SetPeiServicesTablePointerToRegester ( SetPeiServicesTablePointerToRegester -> SetPeiServicesTablePointerToRegister Regester -> Register. / Leif > + IN UINTN PeiServicesTablePointer > + ); > #endif > diff --git a/MdePkg/Library/PeiServicesTablePointerLibReg/PeiServicesTablePointer.c b/MdePkg/Library/PeiServicesTablePointerLibReg/PeiServicesTablePointer.c > new file mode 100644 > index 0000000000..0227f98871 > --- /dev/null > +++ b/MdePkg/Library/PeiServicesTablePointerLibReg/PeiServicesTablePointer.c > @@ -0,0 +1,86 @@ > +/** @file > + PEI Services Table Pointer Library For Reigseter Mechanism. > + > + This library is used for PEIM which does executed from flash device directly but > + executed in memory. > + > + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
> + Copyright (c) 2011 Hewlett-Packard Corporation. All rights reserved.
> + Copyright (c) 2023 Loongson Technology Corporation Limited. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > + > +/** > + Caches a pointer PEI Services Table. > + > + Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer > + in a platform specific manner. > + > + If PeiServicesTablePointer is NULL, then ASSERT(). > + > + @param PeiServicesTablePointer The address of PeiServices pointer. > +**/ > +VOID > +EFIAPI > +SetPeiServicesTablePointer ( > + IN CONST EFI_PEI_SERVICES **PeiServicesTablePointer > + ) > +{ > + ASSERT (PeiServicesTablePointer != NULL); > + SetPeiServicesTablePointerToRegester ((UINTN)PeiServicesTablePointer); > +} > + > +/** > + Retrieves the cached value of the PEI Services Table pointer. > + > + Returns the cached value of the PEI Services Table pointer in a CPU specific manner > + as specified in the CPU binding section of the Platform Initialization Pre-EFI > + Initialization Core Interface Specification. > + > + If the cached PEI Services Table pointer is NULL, then ASSERT(). > + > + @return The pointer to PeiServices. > + > +**/ > +CONST EFI_PEI_SERVICES ** > +EFIAPI > +GetPeiServicesTablePointer ( > + VOID > + ) > +{ > + CONST EFI_PEI_SERVICES **PeiServices; > + > + PeiServices = GetPeiServicesTablePointerFromRegister (); > + ASSERT (PeiServices != NULL); > + return PeiServices; > +} > + > +/** > + Perform CPU specific actions required to migrate the PEI Services Table > + pointer from temporary RAM to permanent RAM. > + > + For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes > + immediately preceding the Interrupt Descriptor Table (IDT) in memory. > + For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes > + immediately preceding the Interrupt Descriptor Table (IDT) in memory. > + For Itanium, ARM and LoongArch CPUs, a the PEI Services Table Pointer > + is stored in a dedicated CPU register. This means that there is no > + memory storage associated with storing the PEI Services Table pointer, > + so no additional migration actions are required for Itanium, ARM and > + LoongArch CPUs. > + > +**/ > +VOID > +EFIAPI > +MigratePeiServicesTablePointer ( > + VOID > + ) > +{ > + return; > +} > diff --git a/MdePkg/Library/PeiServicesTablePointerLibReg/PeiServicesTablePointerLib.uni b/MdePkg/Library/PeiServicesTablePointerLibReg/PeiServicesTablePointerLib.uni > new file mode 100644 > index 0000000000..937cf857d9 > --- /dev/null > +++ b/MdePkg/Library/PeiServicesTablePointerLibReg/PeiServicesTablePointerLib.uni > @@ -0,0 +1,20 @@ > +// /** @file > +// Instance of PEI Services Table Pointer Library using CPU register for the table pointer. > +// > +// PEI Services Table Pointer Library implementation that retrieves a pointer to the > +// PEI Services Table from a CPU register. Applies to modules that execute from > +// read-only memory. > +// > +// Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
> +// Copyright (c) 2011 Hewlett-Packard Corporation. All rights reserved.
> +// Copyright (c) 2023 Loongson Technology Corporation Limited. All rights reserved.
> +// > +// SPDX-License-Identifier: BSD-2-Clause-Patent > +// > +// **/ > + > + > +#string STR_MODULE_ABSTRACT #language en-US "Instance of PEI Services Table Pointer Library using CPU register for the table pointer" > + > +#string STR_MODULE_DESCRIPTION #language en-US "The PEI Services Table Pointer Library implementation that retrieves a pointer to the PEI Services Table from a CPU register. Applies to modules that execute from read-only memory." > + > diff --git a/MdePkg/Library/PeiServicesTablePointerLibReg/PeiServicesTablePointerLibReg.inf b/MdePkg/Library/PeiServicesTablePointerLibReg/PeiServicesTablePointerLibReg.inf > new file mode 100644 > index 0000000000..22499e22ad > --- /dev/null > +++ b/MdePkg/Library/PeiServicesTablePointerLibReg/PeiServicesTablePointerLibReg.inf > @@ -0,0 +1,40 @@ > +## @file > +# Instance of PEI Services Table Pointer Library using CPU register for the table pointer. > +# > +# PEI Services Table Pointer Library implementation that retrieves a pointer to the > +# PEI Services Table from a CPU register. Applies to modules that execute from > +# read-only memory. > +# > +# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
> +# Copyright (c) 2011 Hewlett-Packard Corporation. All rights reserved.
> +# Copyright (c) 2023 Loongson Technology Corporation Limited. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +# > +## > + > +[Defines] > + INF_VERSION = 0x00010005 > + BASE_NAME = PeiServicesTablePointerLib > + MODULE_UNI_FILE = PeiServicesTablePointerLib.uni > + FILE_GUID = 619950D1-7C5F-EA1B-D6DD-2FF7B0A4A2B7 > + MODULE_TYPE = PEIM > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = PeiServicesTablePointerLib|PEIM PEI_CORE SEC > + > +# > +# VALID_ARCHITECTURES = IA32 X64 AARCH64 RISCV64 LOONGARCH64 > +# > + > +[Sources] > + PeiServicesTablePointer.c > + > +[Packages] > + MdePkg/MdePkg.dec > + > +[LibraryClasses] > + DebugLib > + > +[Pcd] > + > diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc > index 3abd1a1e23..2e9a3d4b4c 100644 > --- a/MdePkg/MdePkg.dsc > +++ b/MdePkg/MdePkg.dsc > @@ -103,6 +103,7 @@ > MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf > MdePkg/Library/PeiServicesLib/PeiServicesLib.inf > MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf > + MdePkg/Library/PeiServicesTablePointerLibReg/PeiServicesTablePointerLibReg.inf > MdePkg/Library/PeiSmbusLibSmbus2Ppi/PeiSmbusLibSmbus2Ppi.inf > MdePkg/Library/PeiPciLibPciCfg2/PeiPciLibPciCfg2.inf > MdePkg/Library/PeiPciSegmentLibPciCfg2/PeiPciSegmentLibPciCfg2.inf > -- > 2.27.0 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#111393): https://edk2.groups.io/g/devel/message/111393 Mute This Topic: https://groups.io/mt/102644754/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/12367111/7686176/1913456212/xyzzy [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-