* [edk2-devel] [PATCH v4 0/6] CryptoPkg: Enable Openssl native instruction support for AARCH64
@ 2023-11-20 13:48 PierreGondois
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 1/6] ArmPkg/ArmLib: Add macros/helper functions around AA64Isar0 register PierreGondois
` (5 more replies)
0 siblings, 6 replies; 10+ messages in thread
From: PierreGondois @ 2023-11-20 13:48 UTC (permalink / raw)
To: devel
Cc: Jiewen Yao, Yi Li, Xiaoyu Lu, Guomin Jiang, Leif Lindholm,
Ard Biesheuvel, Sami Mujawar, Gerd Hoffmann
v4:
- Added Acked-by from Gerd
- Created bugzilla at:
https://bugzilla.tianocore.org/show_bug.cgi?id=4601
- Replaced:
- [PATCH v3 1/6] ArmPkg/ArmLib: Move ArmReadIdAA64Isar0() to ArmLib
by:
- [PATCH v4 1/6] ArmPkg/ArmLib: Add macros/helper functions around AA64Isar0 register
and:
- Moved ARM_ID_AA64ISAR0_EL1_* macros to ArmPkg/Include/Chipset/AArch64.h
- Added macros to get capabilities described in AA64ISAR0
v3:
- Use ArmPkg's function to access register:
- Dropped:
- [PATCH v2 1/7] MdePkg/BaseLib: AARCH64: Add ArmReadCntPctReg()
- [PATCH v2 2/7] MdePkg/BaseLib: AARCH64: Add ArmReadIdAA64Isar0Reg()
- [PATCH v2 3/7] MdePkg/BaseRngLib: Prefer ArmReadIdAA64Isar0Reg() over ArmReadIdIsar0()
- Added:
- [PATCH v3 1/6] ArmPkg/ArmLib: Move ArmReadIdAA64Isar0() to ArmLib
- Allow dependency of CryptoPkg over ArmPkg in CI:
- Added:
- [PATCH v3 2/6] CryptoPkg/CryptoPkg.ci.yaml: Allow dependency upon
v2:
- [PATCH v2 2/7] MdePkg/BaseLib: AARCH64: Add ArmReadIdAA64Isar0Reg()
- Correct bad mask values in MdePkg/Include/Library/BaseLib.h
- [PATCH v2 4/7] CryptoPkg/OpensslLib: Add native instruction support:
- Add armcap.c to configure.py:sources_filter_fn() instead of
manually commenting the file in .inf files
Various OpensslLib implementations are available in edk2. The
OpensslLibAccel.inf and OpensslLibFullAccel.inf ones use
architecture specific instructions, e.g. AESE, PMULL, SHA256H, ...,
allowing to improve speed.
Enable support for Aarch64's native instructions:
- Add ArmReadCntPctReg() and ArmReadIdAA64Isar0Reg() to
Aarch64's BaseLib.
- Generate Aarch64's specific Openssl functions.
- Add a OpensslStub/AArch64Cap.c file to allow Openssl
to probe Aarch64 native instruction support.
This patch-set only enable support for GCC for now (MSFT support
not added).
---- Testing ----
The tests run are based on the TestBaseCryptLibShell module.
Each test is run 100 times, then the first 5 values
(considered as warmup) are removed.
The NoAccel column relies on the OpensslLibFull implementation,
the Accel column relies on the OpensslLibFullAccel implementation.
The 'Improvement' column is computed as:
100 * ('Accel (ns)' - 'NoAccel (ns)') / 'NoAccel (ns)'
The std deviation of the TestVerifyDhGenerateKey is big.
It is due to [1] being called with the 'safe' parameter set, leading
to the prime number taking more time to generate. It requires ~10
iterations when safe=false, ~1000 iterations when safe=true.
The test was run on a Juno-r2. The native Openssl implementation makes
use of the following features (cf. [2]):
- ARMV7_NEON
- ARMV8_AES
- ARMV8_SHA1
- ARMV8_PMULL
- ARMV8_SHA256
and misses:
- ARMV8_SHA512
| TestName | NoAccel (ns) | NoAccel std | Accel (ns) | Accel std | Improvement |
|:---------------------------------|---------------:|--------------:|-------------:|------------:|--------------:|
| mPkcs7EkuTest | 14757511 | 14370 | 14947276 | 35677 | 1.28589 |
| mAeadAesGcmTest | 129667 | 2012 | 113897 | 1366 | -12.1619 |
| mBlockCipherTest | 7325 | 102 | 6487 | 81 | -11.4403 |
| mAuthenticodeTest | 72852444 | 3097832 | 67593102 | 3123627 | -7.21917 |
| mBnTest | 771921 | 57966 | 737656 | 61354 | -4.43893 |
| mDhTest | 4082083501 | 3340300622 | 3502629757 | 3444890110 | -14.195 |
| mEcTest | 24666075 | 191971 | 23250301 | 178985 | -5.73976 |
| mHkdfTest | 848440 | 4295 | 797966 | 4320 | -5.94904 |
| mHmacTest | 235527 | 36284 | 204823 | 37936 | -13.0363 |
| mImageTimestampTest | 12801070 | 18327 | 12190046 | 23138 | -4.77323 |
| mOaepTest | 20032245 | 46525 | 18671388 | 36399 | -6.79333 |
| mPkcs5Test | 178624 | 1962 | 114852 | 1376 | -35.7018 |
| mPkcs7Test | 28464572 | 70683 | 25282753 | 82616 | -11.1782 |
| mPrngTest | 727013 | 3637 | 460076 | 2668 | -36.717 |
| mRsaCertTest | 39109865 | 90380 | 36452412 | 220712 | -6.79484 |
| mRsaTest | 22451367 | 60643 | 16672060 | 53643 | -25.7414 |
| mRsaPssTest | 142051533 | 122172 | 98638975 | 99131 | -30.5611 |
| mHashTest | 22033 | 6308 | 17650 | 6622 | -19.8929 |
| mX509Test | 53796289 | 123676 | 51280121 | 187588 | -4.67721 |
Pierre Gondois (6):
ArmPkg/ArmLib: Add macros/helper functions around AA64Isar0 register
CryptoPkg/CryptoPkg.ci.yaml: Allow dependency upon ArmPkg
CryptoPkg/OpensslLib: Add native instruction support for AARCH64
CryptoPkg/OpensslLib: Generate files for AARCH64 native support
CryptoPkg/OpensslLib: Add AArch64Cap for arch specific hooks
CryptoPkg: Enable Openssl Accel builds for AARCH64
ArmPkg/Include/Chipset/AArch64.h | 60 +-
ArmPkg/Include/Library/ArmLib.h | 228 +-
ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c | 367 +
CryptoPkg/CryptoPkg.ci.yaml | 1 +
CryptoPkg/CryptoPkg.dsc | 23 +-
.../AARCH64-GCC/crypto/aes/aesv8-armx.S | 3180 ++++++++
.../AARCH64-GCC/crypto/aes/vpaes-armv8.S | 1196 +++
.../AARCH64-GCC/crypto/arm64cpuid.S | 129 +
.../AARCH64-GCC/crypto/bn/armv8-mont.S | 2124 ++++++
.../crypto/ec/ecp_nistz256-armv8.S | 4242 +++++++++++
.../crypto/modes/aes-gcm-armv8_64.S | 6389 +++++++++++++++++
.../AARCH64-GCC/crypto/modes/ghashv8-armx.S | 552 ++
.../AARCH64-GCC/crypto/sha/keccak1600-armv8.S | 1009 +++
.../AARCH64-GCC/crypto/sha/sha1-armv8.S | 1211 ++++
.../AARCH64-GCC/crypto/sha/sha256-armv8.S | 2051 ++++++
.../AARCH64-GCC/crypto/sha/sha512-armv8.S | 1606 +++++
.../Library/OpensslLib/OpensslLibAccel.inf | 647 +-
.../OpensslLib/OpensslLibFullAccel.inf | 696 +-
.../OpensslLib/OpensslStub/AArch64Cap.c | 79 +
CryptoPkg/Library/OpensslLib/UefiAsm.conf | 6 +
CryptoPkg/Library/OpensslLib/configure.py | 6 +-
CryptoPkg/Readme.md | 14 +-
22 files changed, 25793 insertions(+), 23 deletions(-)
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/aes/aesv8-armx.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/aes/vpaes-armv8.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/arm64cpuid.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/bn/armv8-mont.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/ec/ecp_nistz256-armv8.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/modes/aes-gcm-armv8_64.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/modes/ghashv8-armx.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/keccak1600-armv8.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/sha1-armv8.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/sha256-armv8.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/sha512-armv8.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c
--
2.25.1
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [edk2-devel] [PATCH v4 1/6] ArmPkg/ArmLib: Add macros/helper functions around AA64Isar0 register
2023-11-20 13:48 [edk2-devel] [PATCH v4 0/6] CryptoPkg: Enable Openssl native instruction support for AARCH64 PierreGondois
@ 2023-11-20 13:48 ` PierreGondois
2023-11-20 18:27 ` Leif Lindholm
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 2/6] CryptoPkg/CryptoPkg.ci.yaml: Allow dependency upon ArmPkg PierreGondois
` (4 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: PierreGondois @ 2023-11-20 13:48 UTC (permalink / raw)
To: devel
Cc: Jiewen Yao, Yi Li, Xiaoyu Lu, Guomin Jiang, Leif Lindholm,
Ard Biesheuvel, Sami Mujawar, Gerd Hoffmann
Add macro definitions and helper functions to access AArch64
capabilities described in the AA64Isar0 register.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
ArmPkg/Include/Chipset/AArch64.h | 60 +++-
ArmPkg/Include/Library/ArmLib.h | 228 ++++++++++++-
ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c | 367 +++++++++++++++++++++
3 files changed, 653 insertions(+), 2 deletions(-)
diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h
index 5390bf0a2774..97c20e71a811 100644
--- a/ArmPkg/Include/Chipset/AArch64.h
+++ b/ArmPkg/Include/Chipset/AArch64.h
@@ -1,7 +1,7 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
- Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
+ Copyright (c) 2011 - 2023, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -127,6 +127,64 @@
// build for ARMv8.0, we need to define the register here.
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
+//
+// Bit shifts for the ID_AA64ISAR0_EL1 register.
+//
+#define ARM_ID_AA64ISAR0_EL1_AES_SHIFT (4U)
+#define ARM_ID_AA64ISAR0_EL1_SHA1_SHIFT (8U)
+#define ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT (12U)
+#define ARM_ID_AA64ISAR0_EL1_CRC32_SHIFT (16U)
+#define ARM_ID_AA64ISAR0_EL1_ATOMIC_SHIFT (20U)
+#define ARM_ID_AA64ISAR0_EL1_RDM_SHIFT (28U)
+#define ARM_ID_AA64ISAR0_EL1_SHA3_SHIFT (32U)
+#define ARM_ID_AA64ISAR0_EL1_SM3_SHIFT (36U)
+#define ARM_ID_AA64ISAR0_EL1_SM4_SHIFT (40U)
+#define ARM_ID_AA64ISAR0_EL1_DP_SHIFT (44U)
+#define ARM_ID_AA64ISAR0_EL1_FHM_SHIFT (48U)
+#define ARM_ID_AA64ISAR0_EL1_TS_SHIFT (52U)
+#define ARM_ID_AA64ISAR0_EL1_TLB_SHIFT (56U)
+#define ARM_ID_AA64ISAR0_EL1_RNDR_SHIFT (60U)
+
+//
+// Bit masks for the ID_AA64ISAR0_EL1 fields.
+//
+#define ARM_ID_AA64ISAR0_EL1_AES_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_SHA1_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_SHA2_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_CRC32_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_ATOMIC_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_RDM_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_SHA3_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_SM3_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_SM4_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_DP_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_FHM_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_TS_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_TLB_MASK (0xFU)
+#define ARM_ID_AA64ISAR0_EL1_RNDR_MASK (0xFU)
+
+//
+// Bit masks for the ID_AA64ISAR0_EL1 field values.
+//
+#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_AES_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_PMULL_MASK (0x2U)
+#define ARM_ID_AA64ISAR0_EL1_SHA1_FEAT_SHA1_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA256_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA512_MASK (0x2U)
+#define ARM_ID_AA64ISAR0_EL1_CRC32_HAVE_CRC32_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_ATOMIC_FEAT_LSE_MASK (0x2U)
+#define ARM_ID_AA64ISAR0_EL1_RDM_FEAT_RDM_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_SHA3_FEAT_SHA3_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_SM3_FEAT_SM3_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_SM4_FEAT_SM4_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_DP_FEAT_DOTPROD_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_FHM_FEAT_FHM_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM2_MASK (0x2U)
+#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIOS_MASK (0x1U)
+#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIRANGE_MASK (0x2U)
+#define ARM_ID_AA64ISAR0_EL1_RNDR_FEAT_RNG_MASK (0x1U)
+
#define VECTOR_BASE(tbl) \
.section .text.##tbl##,"ax"; \
.align 11; \
diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 6aa8a48f07f3..a176fcd7bf0a 100644
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -1,7 +1,7 @@
/** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
- Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2011 - 2023, Arm Limited. All rights reserved.<BR>
Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -805,6 +805,232 @@ ArmHasEte (
VOID
);
+/** Read AA64Isar0 register.
+
+ @return AA64Isar0's register value.
+**/
+UINTN
+EFIAPI
+ArmReadIdAA64Isar0 (
+ VOID
+ );
+
+/**
+ Checks whether the CPU implements FEAT_AES.
+
+ @retval TRUE FEAT_AES is implemented.
+ @retval FALSE FEAT_AES is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasAes (
+ VOID
+ );
+
+/**
+ Checks whether the CPU implements FEAT_PMULL.
+
+ @retval TRUE FEAT_PMULL is implemented.
+ @retval FALSE FEAT_PMULL is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasPmull (
+ VOID
+ );
+
+/**
+ Checks whether the CPU implements FEAT_SHA1.
+
+ @retval TRUE FEAT_SHA1 is implemented.
+ @retval FALSE FEAT_SHA1 is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasSha1 (
+ VOID
+ );
+
+/**
+ Checks whether the CPU implements FEAT_SHA256.
+
+ @retval TRUE FEAT_SHA256 is implemented.
+ @retval FALSE FEAT_SHA256 is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasSha256 (
+ VOID
+ );
+
+/**
+ Checks whether the CPU implements FEAT_SHA512.
+
+ @retval TRUE FEAT_SHA512 is implemented.
+ @retval FALSE FEAT_SHA512 is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasSha512 (
+ VOID
+ );
+
+/**
+ Checks whether the CPU implements CRC32 instruction.
+
+ @retval TRUE CRC32 instruction is implemented.
+ @retval FALSE CRC32 instruction is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasCrc32 (
+ VOID
+ );
+
+/**
+ Checks whether the CPU implements FEAT_LSE.
+
+ @retval TRUE FEAT_LSE is implemented.
+ @retval FALSE FEAT_LSE is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasLse (
+ VOID
+ );
+
+/**
+ Checks whether the CPU implements FEAT_RDM.
+
+ @retval TRUE FEAT_RDM is implemented.
+ @retval FALSE FEAT_RDM is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasRdm (
+ VOID
+ );
+
+/**
+ Checks whether the CPU implements FEAT_SHA3.
+
+ @retval TRUE FEAT_SHA3 is implemented.
+ @retval FALSE FEAT_SHA3 is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasSha3 (
+ VOID
+ );
+
+/**
+ Checks whether the CPU implements FEAT_SM3.
+
+ @retval TRUE FEAT_SM3 is implemented.
+ @retval FALSE FEAT_SM3 is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasSm3 (
+ VOID
+ );
+
+/**
+ Checks whether the CPU implements FEAT_SM4.
+
+ @retval TRUE FEAT_SM4 is implemented.
+ @retval FALSE FEAT_SM4 is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasSm4 (
+ VOID
+ );
+
+/**
+ Checks whether the CPU implements FEAT_DotProd.
+
+ @retval TRUE FEAT_DotProd is implemented.
+ @retval FALSE FEAT_DotProd is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasDp (
+ VOID
+ );
+
+/**
+ Checks whether the CPU implements FEAT_FHM.
+
+ @retval TRUE FEAT_FHM is implemented.
+ @retval FALSE FEAT_FHM is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasFhm (
+ VOID
+ );
+
+/**
+ Checks whether the CPU implements FEAT_FlagM.
+
+ @retval TRUE FEAT_FlagM is implemented.
+ @retval FALSE FEAT_FlagM is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasFlagm (
+ VOID
+ );
+
+/**
+ Checks whether the CPU implements FEAT_FlagM2.
+
+ @retval TRUE FEAT_FlagM2 is implemented.
+ @retval FALSE FEAT_FlagM2 is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasFlagm2 (
+ VOID
+ );
+
+/**
+ Checks whether the CPU implements FEAT_TLBIOS.
+
+ @retval TRUE FEAT_TLBIOS is implemented.
+ @retval FALSE FEAT_TLBIOS is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasTlbios (
+ VOID
+ );
+
+/**
+ Checks whether the CPU implements FEAT_TLBIRANGE.
+
+ @retval TRUE FEAT_TLBIRANGE is implemented.
+ @retval FALSE FEAT_TLBIRANGE is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasTlbirange (
+ VOID
+ );
+
+/**
+ Checks whether the CPU implements FEAT_RNG.
+
+ @retval TRUE FEAT_RNG is implemented.
+ @retval FALSE FEAT_RNG is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasRndr (
+ VOID
+ );
+
#endif // MDE_CPU_AARCH64
#ifdef MDE_CPU_ARM
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
index 87285465871d..c64c015844a6 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
@@ -18,6 +18,19 @@
#include "AArch64Lib.h"
#include "ArmLibPrivate.h"
+/** Get bits from a value.
+
+ Shift the input value from 'shift' bits and apply 'mask'.
+
+ @param value The value to get the bits from.
+ @param shift Index of the bits to read.
+ @param mask Mask to apply to the value once shifted.
+
+ @return The desired bitfield from the value.
+**/
+#define GET_BITFIELD(value, shift, mask) \
+ ((value >> shift) & mask)
+
VOID
AArch64DataCacheOperation (
IN AARCH64_CACHE_OPERATION DataCacheOperation
@@ -150,3 +163,357 @@ ArmHasEte (
// The ID_AA64DFR0_EL1.TraceVer field identifies the presence of FEAT_ETE.
return ((ArmReadIdAA64Dfr0 () & AARCH64_DFR0_TRACEVER) != 0);
}
+
+/**
+ Checks whether the CPU implements FEAT_AES.
+
+ @retval TRUE FEAT_AES is implemented.
+ @retval FALSE FEAT_AES is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasAes (
+ VOID
+ )
+{
+ return GET_BITFIELD (
+ ArmReadIdAA64Isar0 (),
+ ARM_ID_AA64ISAR0_EL1_AES_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_AES_MASK
+ ) != 0;
+}
+
+/**
+ Checks whether the CPU implements FEAT_PMULL.
+
+ @retval TRUE FEAT_PMULL is implemented.
+ @retval FALSE FEAT_PMULL is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasPmull (
+ VOID
+ )
+{
+ //
+ // Only check BIT1 of AES field, bits [7:4]
+ //
+ return GET_BITFIELD (
+ ArmReadIdAA64Isar0 (),
+ ARM_ID_AA64ISAR0_EL1_AES_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_AES_FEAT_PMULL_MASK
+ ) != 0;
+}
+
+/**
+ Checks whether the CPU implements FEAT_SHA1.
+
+ @retval TRUE FEAT_SHA1 is implemented.
+ @retval FALSE FEAT_SHA1 is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasSha1 (
+ VOID
+ )
+{
+ return GET_BITFIELD (
+ ArmReadIdAA64Isar0 (),
+ ARM_ID_AA64ISAR0_EL1_SHA1_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_SHA1_MASK
+ ) != 0;
+}
+
+/**
+ Checks whether the CPU implements FEAT_SHA256.
+
+ @retval TRUE FEAT_SHA256 is implemented.
+ @retval FALSE FEAT_SHA256 is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasSha256 (
+ VOID
+ )
+{
+ return GET_BITFIELD (
+ ArmReadIdAA64Isar0 (),
+ ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_SHA2_MASK
+ ) != 0;
+}
+
+/**
+ Checks whether the CPU implements FEAT_SHA512.
+
+ @retval TRUE FEAT_SHA512 is implemented.
+ @retval FALSE FEAT_SHA512 is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasSha512 (
+ VOID
+ )
+{
+ //
+ // Only check BIT1 of SHA2 field, bits [15:12]
+ //
+ return GET_BITFIELD (
+ ArmReadIdAA64Isar0 (),
+ ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA512_MASK
+ ) != 0;
+}
+
+/**
+ Checks whether the CPU implements CRC32 instruction.
+
+ @retval TRUE CRC32 instruction is implemented.
+ @retval FALSE CRC32 instruction is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasCrc32 (
+ VOID
+ )
+{
+ return GET_BITFIELD (
+ ArmReadIdAA64Isar0 (),
+ ARM_ID_AA64ISAR0_EL1_CRC32_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_CRC32_MASK
+ ) != 0;
+}
+
+/**
+ Checks whether the CPU implements FEAT_LSE.
+
+ @retval TRUE FEAT_LSE is implemented.
+ @retval FALSE FEAT_LSE is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasLse (
+ VOID
+ )
+{
+ return GET_BITFIELD (
+ ArmReadIdAA64Isar0 (),
+ ARM_ID_AA64ISAR0_EL1_ATOMIC_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_ATOMIC_MASK
+ ) != 0;
+}
+
+/**
+ Checks whether the CPU implements FEAT_RDM.
+
+ @retval TRUE FEAT_RDM is implemented.
+ @retval FALSE FEAT_RDM is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasRdm (
+ VOID
+ )
+{
+ return GET_BITFIELD (
+ ArmReadIdAA64Isar0 (),
+ ARM_ID_AA64ISAR0_EL1_RDM_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_RDM_MASK
+ ) != 0;
+}
+
+/**
+ Checks whether the CPU implements FEAT_SHA3.
+
+ @retval TRUE FEAT_SHA3 is implemented.
+ @retval FALSE FEAT_SHA3 is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasSha3 (
+ VOID
+ )
+{
+ return GET_BITFIELD (
+ ArmReadIdAA64Isar0 (),
+ ARM_ID_AA64ISAR0_EL1_SHA3_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_SHA3_MASK
+ ) != 0;
+}
+
+/**
+ Checks whether the CPU implements FEAT_SM3.
+
+ @retval TRUE FEAT_SM3 is implemented.
+ @retval FALSE FEAT_SM3 is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasSm3 (
+ VOID
+ )
+{
+ return GET_BITFIELD (
+ ArmReadIdAA64Isar0 (),
+ ARM_ID_AA64ISAR0_EL1_SM3_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_SM3_MASK
+ ) != 0;
+}
+
+/**
+ Checks whether the CPU implements FEAT_SM4.
+
+ @retval TRUE FEAT_SM4 is implemented.
+ @retval FALSE FEAT_SM4 is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasSm4 (
+ VOID
+ )
+{
+ return GET_BITFIELD (
+ ArmReadIdAA64Isar0 (),
+ ARM_ID_AA64ISAR0_EL1_SM4_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_SM4_MASK
+ ) != 0;
+}
+
+/**
+ Checks whether the CPU implements FEAT_DotProd.
+
+ @retval TRUE FEAT_DotProd is implemented.
+ @retval FALSE FEAT_DotProd is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasDp (
+ VOID
+ )
+{
+ return GET_BITFIELD (
+ ArmReadIdAA64Isar0 (),
+ ARM_ID_AA64ISAR0_EL1_DP_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_DP_MASK
+ ) != 0;
+}
+
+/**
+ Checks whether the CPU implements FEAT_FHM.
+
+ @retval TRUE FEAT_FHM is implemented.
+ @retval FALSE FEAT_FHM is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasFhm (
+ VOID
+ )
+{
+ return GET_BITFIELD (
+ ArmReadIdAA64Isar0 (),
+ ARM_ID_AA64ISAR0_EL1_FHM_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_FHM_MASK
+ ) != 0;
+}
+
+/**
+ Checks whether the CPU implements FEAT_FlagM.
+
+ @retval TRUE FEAT_FlagM is implemented.
+ @retval FALSE FEAT_FlagM is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasFlagm (
+ VOID
+ )
+{
+ return GET_BITFIELD (
+ ArmReadIdAA64Isar0 (),
+ ARM_ID_AA64ISAR0_EL1_TS_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_TS_MASK
+ ) != 0;
+}
+
+/**
+ Checks whether the CPU implements FEAT_FlagM2.
+
+ @retval TRUE FEAT_FlagM2 is implemented.
+ @retval FALSE FEAT_FlagM2 is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasFlagm2 (
+ VOID
+ )
+{
+ //
+ // Only check BIT1 of TS field, bits [55:52]
+ //
+ return GET_BITFIELD (
+ ArmReadIdAA64Isar0 (),
+ ARM_ID_AA64ISAR0_EL1_TS_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM2_MASK
+ ) != 0;
+}
+
+/**
+ Checks whether the CPU implements FEAT_TLBIOS.
+
+ @retval TRUE FEAT_TLBIOS is implemented.
+ @retval FALSE FEAT_TLBIOS is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasTlbios (
+ VOID
+ )
+{
+ return GET_BITFIELD (
+ ArmReadIdAA64Isar0 (),
+ ARM_ID_AA64ISAR0_EL1_TLB_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_TLB_MASK
+ ) != 0;
+}
+
+/**
+ Checks whether the CPU implements FEAT_TLBIRANGE.
+
+ @retval TRUE FEAT_TLBIRANGE is implemented.
+ @retval FALSE FEAT_TLBIRANGE is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasTlbirange (
+ VOID
+ )
+{
+ //
+ // Only check BIT1 of TLB field, bits [59:56]
+ //
+ return GET_BITFIELD (
+ ArmReadIdAA64Isar0 (),
+ ARM_ID_AA64ISAR0_EL1_TLB_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIRANGE_MASK
+ ) != 0;
+}
+
+/**
+ Checks whether the CPU implements FEAT_RNG.
+
+ @retval TRUE FEAT_RNG is implemented.
+ @retval FALSE FEAT_RNG is not implemented.
+**/
+BOOLEAN
+EFIAPI
+ArmHasRndr (
+ VOID
+ )
+{
+ return GET_BITFIELD (
+ ArmReadIdAA64Isar0 (),
+ ARM_ID_AA64ISAR0_EL1_RNDR_SHIFT,
+ ARM_ID_AA64ISAR0_EL1_RNDR_MASK
+ ) != 0;
+}
--
2.25.1
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* [edk2-devel] [PATCH v4 2/6] CryptoPkg/CryptoPkg.ci.yaml: Allow dependency upon ArmPkg
2023-11-20 13:48 [edk2-devel] [PATCH v4 0/6] CryptoPkg: Enable Openssl native instruction support for AARCH64 PierreGondois
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 1/6] ArmPkg/ArmLib: Add macros/helper functions around AA64Isar0 register PierreGondois
@ 2023-11-20 13:48 ` PierreGondois
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 3/6] CryptoPkg/OpensslLib: Add native instruction support for AARCH64 PierreGondois
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: PierreGondois @ 2023-11-20 13:48 UTC (permalink / raw)
To: devel
Cc: Jiewen Yao, Yi Li, Xiaoyu Lu, Guomin Jiang, Leif Lindholm,
Ard Biesheuvel, Sami Mujawar, Gerd Hoffmann
Allow dependency upon ArmPkg to pass the dependency Check.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
CryptoPkg/CryptoPkg.ci.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/CryptoPkg/CryptoPkg.ci.yaml b/CryptoPkg/CryptoPkg.ci.yaml
index f961d85927c0..3bbb220d3224 100644
--- a/CryptoPkg/CryptoPkg.ci.yaml
+++ b/CryptoPkg/CryptoPkg.ci.yaml
@@ -69,6 +69,7 @@
},
"DependencyCheck": {
"AcceptableDependencies": [
+ "ArmPkg/ArmPkg.dec",
"MdePkg/MdePkg.dec",
"MdeModulePkg/MdeModulePkg.dec",
"CryptoPkg/CryptoPkg.dec",
--
2.25.1
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* [edk2-devel] [PATCH v4 3/6] CryptoPkg/OpensslLib: Add native instruction support for AARCH64
2023-11-20 13:48 [edk2-devel] [PATCH v4 0/6] CryptoPkg: Enable Openssl native instruction support for AARCH64 PierreGondois
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 1/6] ArmPkg/ArmLib: Add macros/helper functions around AA64Isar0 register PierreGondois
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 2/6] CryptoPkg/CryptoPkg.ci.yaml: Allow dependency upon ArmPkg PierreGondois
@ 2023-11-20 13:48 ` PierreGondois
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 4/6] CryptoPkg/OpensslLib: Generate files for AARCH64 native support PierreGondois
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: PierreGondois @ 2023-11-20 13:48 UTC (permalink / raw)
To: devel
Cc: Jiewen Yao, Yi Li, Xiaoyu Lu, Guomin Jiang, Leif Lindholm,
Ard Biesheuvel, Sami Mujawar, Gerd Hoffmann
Add native instruction support for AARCH64.
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
.../Library/OpensslLib/OpensslLibAccel.inf | 21 ++++++++++++++++++-
.../OpensslLib/OpensslLibFullAccel.inf | 21 ++++++++++++++++++-
CryptoPkg/Library/OpensslLib/UefiAsm.conf | 6 ++++++
CryptoPkg/Library/OpensslLib/configure.py | 6 +++++-
4 files changed, 51 insertions(+), 3 deletions(-)
diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf b/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf
index a37347fbbfd6..a47e9087133b 100644
--- a/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf
+++ b/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf
@@ -5,6 +5,7 @@
#
# Copyright (c) 2010 - 2020, Intel Corporation. All rights reserved.<BR>
# (C) Copyright 2020 Hewlett Packard Enterprise Development LP<BR>
+# Copyright (c) 2023, Arm Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -24,9 +25,10 @@ [Defines]
DEFINE OPENSSL_FLAGS = -DL_ENDIAN -DOPENSSL_SMALL_FOOTPRINT -D_CRT_SECURE_NO_DEPRECATE -D_CRT_NONSTDC_NO_DEPRECATE -DEDK2_OPENSSL_NOEC=1
DEFINE OPENSSL_FLAGS_IA32 = -DAES_ASM -DGHASH_ASM -DMD5_ASM -DOPENSSL_CPUID_OBJ -DSHA1_ASM -DSHA256_ASM -DSHA512_ASM -DVPAES_ASM
DEFINE OPENSSL_FLAGS_X64 = -DAES_ASM -DBSAES_ASM -DGHASH_ASM -DKECCAK1600_ASM -DMD5_ASM -DOPENSSL_CPUID_OBJ -DSHA1_ASM -DSHA256_ASM -DSHA512_ASM -DVPAES_ASM
+ DEFINE OPENSSL_FLAGS_AARCH64 =
#
-# VALID_ARCHITECTURES = IA32 X64
+# VALID_ARCHITECTURES = IA32 X64 AARCH64
#
[Sources]
@@ -1326,6 +1328,10 @@ [Sources.X64]
$(OPENSSL_GEN_PATH)/X64-GCC/crypto/sha/sha512-x86_64.s | GCC
# Autogenerated files list ends here
+[Sources.AARCH64]
+# Autogenerated files list starts here
+# Autogenerated files list ends here
+
[Packages]
MdePkg/MdePkg.dec
CryptoPkg/CryptoPkg.dec
@@ -1403,3 +1409,16 @@ [BuildOptions]
# commit d9b8b89bec4480de3a10bdaf9425db371c19145b, and can be dropped then.)
XCODE:*_*_IA32_CC_FLAGS = -mmmx -msse -U_WIN32 -U_WIN64 $(OPENSSL_FLAGS) $(OPENSSL_FLAGS_IA32) -w -std=c99 -Wno-error=uninitialized
XCODE:*_*_X64_CC_FLAGS = -mmmx -msse -U_WIN32 -U_WIN64 $(OPENSSL_FLAGS) $(OPENSSL_FLAGS_X64) -w -std=c99 -Wno-error=uninitialized
+
+ GCC:*_*_AARCH64_CC_FLAGS = $(OPENSSL_FLAGS) $(OPENSSL_FLAGS_AARCH64) -Wno-error=format -Wno-format -D_BITS_STDINT_UINTN_H -D_BITS_STDINT_INTN_H
+
+ #
+ # AARCH64 uses strict alignment and avoids SIMD registers for code that may execute
+ # with the MMU off. This involves SEC, PEI_CORE and PEIM modules as well as BASE
+ # libraries, given that they may be included into such modules.
+ # This library, even though of the BASE type, is never used in such cases, and
+ # avoiding the SIMD register file (which is shared with the FPU) prevents the
+ # compiler from successfully building some of the OpenSSL source files that
+ # use floating point types, so clear the flags here.
+ #
+ GCC:*_*_AARCH64_CC_XIPFLAGS ==
diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf b/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf
index 780d5febd72e..45a58c7d382e 100644
--- a/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf
+++ b/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf
@@ -10,6 +10,7 @@
#
# Copyright (c) 2010 - 2020, Intel Corporation. All rights reserved.<BR>
# (C) Copyright 2020 Hewlett Packard Enterprise Development LP<BR>
+# Copyright (c) 2023, Arm Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -29,9 +30,10 @@ [Defines]
DEFINE OPENSSL_FLAGS = -DL_ENDIAN -DOPENSSL_SMALL_FOOTPRINT -D_CRT_SECURE_NO_DEPRECATE -D_CRT_NONSTDC_NO_DEPRECATE
DEFINE OPENSSL_FLAGS_IA32 = -DAES_ASM -DGHASH_ASM -DMD5_ASM -DOPENSSL_CPUID_OBJ -DSHA1_ASM -DSHA256_ASM -DSHA512_ASM -DVPAES_ASM
DEFINE OPENSSL_FLAGS_X64 = -DAES_ASM -DBSAES_ASM -DGHASH_ASM -DKECCAK1600_ASM -DMD5_ASM -DOPENSSL_CPUID_OBJ -DSHA1_ASM -DSHA256_ASM -DSHA512_ASM -DVPAES_ASM
+ DEFINE OPENSSL_FLAGS_AARCH64 =
#
-# VALID_ARCHITECTURES = IA32 X64
+# VALID_ARCHITECTURES = IA32 X64 AARCH64
#
[Sources]
@@ -1429,6 +1431,10 @@ [Sources.X64]
$(OPENSSL_GEN_PATH)/X64-GCC/crypto/sha/sha512-x86_64.s | GCC
# Autogenerated files list ends here
+[Sources.AARCH64]
+# Autogenerated files list starts here
+# Autogenerated files list ends here
+
[Packages]
MdePkg/MdePkg.dec
CryptoPkg/CryptoPkg.dec
@@ -1506,3 +1512,16 @@ [BuildOptions]
# commit d9b8b89bec4480de3a10bdaf9425db371c19145b, and can be dropped then.)
XCODE:*_*_IA32_CC_FLAGS = -mmmx -msse -U_WIN32 -U_WIN64 $(OPENSSL_FLAGS) $(OPENSSL_FLAGS_IA32) -w -std=c99 -Wno-error=uninitialized
XCODE:*_*_X64_CC_FLAGS = -mmmx -msse -U_WIN32 -U_WIN64 $(OPENSSL_FLAGS) $(OPENSSL_FLAGS_X64) -w -std=c99 -Wno-error=uninitialized
+
+ GCC:*_*_AARCH64_CC_FLAGS = $(OPENSSL_FLAGS) $(OPENSSL_FLAGS_AARCH64) -Wno-error=format -Wno-format -D_BITS_STDINT_UINTN_H -D_BITS_STDINT_INTN_H
+
+ #
+ # AARCH64 uses strict alignment and avoids SIMD registers for code that may execute
+ # with the MMU off. This involves SEC, PEI_CORE and PEIM modules as well as BASE
+ # libraries, given that they may be included into such modules.
+ # This library, even though of the BASE type, is never used in such cases, and
+ # avoiding the SIMD register file (which is shared with the FPU) prevents the
+ # compiler from successfully building some of the OpenSSL source files that
+ # use floating point types, so clear the flags here.
+ #
+ GCC:*_*_AARCH64_CC_XIPFLAGS ==
diff --git a/CryptoPkg/Library/OpensslLib/UefiAsm.conf b/CryptoPkg/Library/OpensslLib/UefiAsm.conf
index 907582f93e2d..07273d6a1ab5 100644
--- a/CryptoPkg/Library/OpensslLib/UefiAsm.conf
+++ b/CryptoPkg/Library/OpensslLib/UefiAsm.conf
@@ -2,6 +2,7 @@
# UEFI assembly openssl configuration targets.
#
# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2023, Arm Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -28,4 +29,9 @@ my %targets = (
perlasm_scheme => "elf",
asm_arch => "x86_64",
},
+ "UEFI-AARCH64-GCC" => {
+ inherit_from => [ "UEFI" ],
+ asm_arch => "aarch64",
+ perlasm_scheme => "linux64-aarch64",
+ },
);
diff --git a/CryptoPkg/Library/OpensslLib/configure.py b/CryptoPkg/Library/OpensslLib/configure.py
index 4243ca4c2574..dc09124f44ce 100755
--- a/CryptoPkg/Library/OpensslLib/configure.py
+++ b/CryptoPkg/Library/OpensslLib/configure.py
@@ -262,6 +262,7 @@ def sources_filter_fn(filename):
'provider_predefined.c',
'ecp_nistz256.c',
'x86_64-gcc.c',
+ 'armcap.c',
]
for item in exclude:
if item in filename:
@@ -353,7 +354,8 @@ def main():
sources = {}
defines = {}
for asm in [ 'UEFI-IA32-MSFT', 'UEFI-IA32-GCC',
- 'UEFI-X64-MSFT', 'UEFI-X64-GCC']:
+ 'UEFI-X64-MSFT', 'UEFI-X64-GCC',
+ 'UEFI-AARCH64-GCC']:
(uefi, arch, cc) = asm.split('-')
archcc = f'{arch}-{cc}'
@@ -375,6 +377,8 @@ def main():
x64accel = sources['X64'] + sources['X64-MSFT'] + sources['X64-GCC']
update_inf(inf, ia32accel, 'IA32', defines['IA32'])
update_inf(inf, x64accel, 'X64', defines['X64'])
+ aarch64accel = sources['AARCH64'] + sources['AARCH64-GCC']
+ update_inf(inf, aarch64accel, 'AARCH64', defines['AARCH64'])
# noaccel - ec enabled
openssl_configure(openssldir, 'UEFI', ec = True);
--
2.25.1
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* [edk2-devel] [PATCH v4 4/6] CryptoPkg/OpensslLib: Generate files for AARCH64 native support
2023-11-20 13:48 [edk2-devel] [PATCH v4 0/6] CryptoPkg: Enable Openssl native instruction support for AARCH64 PierreGondois
` (2 preceding siblings ...)
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 3/6] CryptoPkg/OpensslLib: Add native instruction support for AARCH64 PierreGondois
@ 2023-11-20 13:48 ` PierreGondois
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 5/6] CryptoPkg/OpensslLib: Add AArch64Cap for arch specific hooks PierreGondois
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 6/6] CryptoPkg: Enable Openssl Accel builds for AARCH64 PierreGondois
5 siblings, 0 replies; 10+ messages in thread
From: PierreGondois @ 2023-11-20 13:48 UTC (permalink / raw)
To: devel
Cc: Jiewen Yao, Yi Li, Xiaoyu Lu, Guomin Jiang, Leif Lindholm,
Ard Biesheuvel, Sami Mujawar, Gerd Hoffmann
Generate AARCH64 related files and update .inf files,
running:
python CryptoPkg/Library/OpensslLib/configure.py
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
.../AARCH64-GCC/crypto/aes/aesv8-armx.S | 3180 ++++++++
.../AARCH64-GCC/crypto/aes/vpaes-armv8.S | 1196 +++
.../AARCH64-GCC/crypto/arm64cpuid.S | 129 +
.../AARCH64-GCC/crypto/bn/armv8-mont.S | 2124 ++++++
.../crypto/ec/ecp_nistz256-armv8.S | 4242 +++++++++++
.../crypto/modes/aes-gcm-armv8_64.S | 6389 +++++++++++++++++
.../AARCH64-GCC/crypto/modes/ghashv8-armx.S | 552 ++
.../AARCH64-GCC/crypto/sha/keccak1600-armv8.S | 1009 +++
.../AARCH64-GCC/crypto/sha/sha1-armv8.S | 1211 ++++
.../AARCH64-GCC/crypto/sha/sha256-armv8.S | 2051 ++++++
.../AARCH64-GCC/crypto/sha/sha512-armv8.S | 1606 +++++
.../Library/OpensslLib/OpensslLibAccel.inf | 621 +-
.../OpensslLib/OpensslLibFullAccel.inf | 670 +-
13 files changed, 24978 insertions(+), 2 deletions(-)
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/aes/aesv8-armx.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/aes/vpaes-armv8.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/arm64cpuid.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/bn/armv8-mont.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/ec/ecp_nistz256-armv8.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/modes/aes-gcm-armv8_64.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/modes/ghashv8-armx.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/keccak1600-armv8.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/sha1-armv8.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/sha256-armv8.S
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/sha512-armv8.S
diff --git a/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/aes/aesv8-armx.S b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/aes/aesv8-armx.S
new file mode 100644
index 000000000000..5c50b4a0180b
--- /dev/null
+++ b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/aes/aesv8-armx.S
@@ -0,0 +1,3180 @@
+#include "arm_arch.h"
+
+#if __ARM_MAX_ARCH__>=7
+.arch armv8-a+crypto
+.text
+.align 5
+.Lrcon:
+.long 0x01,0x01,0x01,0x01
+.long 0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d // rotate-n-splat
+.long 0x1b,0x1b,0x1b,0x1b
+
+.globl aes_v8_set_encrypt_key
+.type aes_v8_set_encrypt_key,%function
+.align 5
+aes_v8_set_encrypt_key:
+.Lenc_key:
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+ mov x3,#-1
+ cmp x0,#0
+ b.eq .Lenc_key_abort
+ cmp x2,#0
+ b.eq .Lenc_key_abort
+ mov x3,#-2
+ cmp w1,#128
+ b.lt .Lenc_key_abort
+ cmp w1,#256
+ b.gt .Lenc_key_abort
+ tst w1,#0x3f
+ b.ne .Lenc_key_abort
+
+ adr x3,.Lrcon
+ cmp w1,#192
+
+ eor v0.16b,v0.16b,v0.16b
+ ld1 {v3.16b},[x0],#16
+ mov w1,#8 // reuse w1
+ ld1 {v1.4s,v2.4s},[x3],#32
+
+ b.lt .Loop128
+ b.eq .L192
+ b .L256
+
+.align 4
+.Loop128:
+ tbl v6.16b,{v3.16b},v2.16b
+ ext v5.16b,v0.16b,v3.16b,#12
+ st1 {v3.4s},[x2],#16
+ aese v6.16b,v0.16b
+ subs w1,w1,#1
+
+ eor v3.16b,v3.16b,v5.16b
+ ext v5.16b,v0.16b,v5.16b,#12
+ eor v3.16b,v3.16b,v5.16b
+ ext v5.16b,v0.16b,v5.16b,#12
+ eor v6.16b,v6.16b,v1.16b
+ eor v3.16b,v3.16b,v5.16b
+ shl v1.16b,v1.16b,#1
+ eor v3.16b,v3.16b,v6.16b
+ b.ne .Loop128
+
+ ld1 {v1.4s},[x3]
+
+ tbl v6.16b,{v3.16b},v2.16b
+ ext v5.16b,v0.16b,v3.16b,#12
+ st1 {v3.4s},[x2],#16
+ aese v6.16b,v0.16b
+
+ eor v3.16b,v3.16b,v5.16b
+ ext v5.16b,v0.16b,v5.16b,#12
+ eor v3.16b,v3.16b,v5.16b
+ ext v5.16b,v0.16b,v5.16b,#12
+ eor v6.16b,v6.16b,v1.16b
+ eor v3.16b,v3.16b,v5.16b
+ shl v1.16b,v1.16b,#1
+ eor v3.16b,v3.16b,v6.16b
+
+ tbl v6.16b,{v3.16b},v2.16b
+ ext v5.16b,v0.16b,v3.16b,#12
+ st1 {v3.4s},[x2],#16
+ aese v6.16b,v0.16b
+
+ eor v3.16b,v3.16b,v5.16b
+ ext v5.16b,v0.16b,v5.16b,#12
+ eor v3.16b,v3.16b,v5.16b
+ ext v5.16b,v0.16b,v5.16b,#12
+ eor v6.16b,v6.16b,v1.16b
+ eor v3.16b,v3.16b,v5.16b
+ eor v3.16b,v3.16b,v6.16b
+ st1 {v3.4s},[x2]
+ add x2,x2,#0x50
+
+ mov w12,#10
+ b .Ldone
+
+.align 4
+.L192:
+ ld1 {v4.8b},[x0],#8
+ movi v6.16b,#8 // borrow v6.16b
+ st1 {v3.4s},[x2],#16
+ sub v2.16b,v2.16b,v6.16b // adjust the mask
+
+.Loop192:
+ tbl v6.16b,{v4.16b},v2.16b
+ ext v5.16b,v0.16b,v3.16b,#12
+#ifdef __ARMEB__
+ st1 {v4.4s},[x2],#16
+ sub x2,x2,#8
+#else
+ st1 {v4.8b},[x2],#8
+#endif
+ aese v6.16b,v0.16b
+ subs w1,w1,#1
+
+ eor v3.16b,v3.16b,v5.16b
+ ext v5.16b,v0.16b,v5.16b,#12
+ eor v3.16b,v3.16b,v5.16b
+ ext v5.16b,v0.16b,v5.16b,#12
+ eor v3.16b,v3.16b,v5.16b
+
+ dup v5.4s,v3.s[3]
+ eor v5.16b,v5.16b,v4.16b
+ eor v6.16b,v6.16b,v1.16b
+ ext v4.16b,v0.16b,v4.16b,#12
+ shl v1.16b,v1.16b,#1
+ eor v4.16b,v4.16b,v5.16b
+ eor v3.16b,v3.16b,v6.16b
+ eor v4.16b,v4.16b,v6.16b
+ st1 {v3.4s},[x2],#16
+ b.ne .Loop192
+
+ mov w12,#12
+ add x2,x2,#0x20
+ b .Ldone
+
+.align 4
+.L256:
+ ld1 {v4.16b},[x0]
+ mov w1,#7
+ mov w12,#14
+ st1 {v3.4s},[x2],#16
+
+.Loop256:
+ tbl v6.16b,{v4.16b},v2.16b
+ ext v5.16b,v0.16b,v3.16b,#12
+ st1 {v4.4s},[x2],#16
+ aese v6.16b,v0.16b
+ subs w1,w1,#1
+
+ eor v3.16b,v3.16b,v5.16b
+ ext v5.16b,v0.16b,v5.16b,#12
+ eor v3.16b,v3.16b,v5.16b
+ ext v5.16b,v0.16b,v5.16b,#12
+ eor v6.16b,v6.16b,v1.16b
+ eor v3.16b,v3.16b,v5.16b
+ shl v1.16b,v1.16b,#1
+ eor v3.16b,v3.16b,v6.16b
+ st1 {v3.4s},[x2],#16
+ b.eq .Ldone
+
+ dup v6.4s,v3.s[3] // just splat
+ ext v5.16b,v0.16b,v4.16b,#12
+ aese v6.16b,v0.16b
+
+ eor v4.16b,v4.16b,v5.16b
+ ext v5.16b,v0.16b,v5.16b,#12
+ eor v4.16b,v4.16b,v5.16b
+ ext v5.16b,v0.16b,v5.16b,#12
+ eor v4.16b,v4.16b,v5.16b
+
+ eor v4.16b,v4.16b,v6.16b
+ b .Loop256
+
+.Ldone:
+ str w12,[x2]
+ mov x3,#0
+
+.Lenc_key_abort:
+ mov x0,x3 // return value
+ ldr x29,[sp],#16
+ ret
+.size aes_v8_set_encrypt_key,.-aes_v8_set_encrypt_key
+
+.globl aes_v8_set_decrypt_key
+.type aes_v8_set_decrypt_key,%function
+.align 5
+aes_v8_set_decrypt_key:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+ bl .Lenc_key
+
+ cmp x0,#0
+ b.ne .Ldec_key_abort
+
+ sub x2,x2,#240 // restore original x2
+ mov x4,#-16
+ add x0,x2,x12,lsl#4 // end of key schedule
+
+ ld1 {v0.4s},[x2]
+ ld1 {v1.4s},[x0]
+ st1 {v0.4s},[x0],x4
+ st1 {v1.4s},[x2],#16
+
+.Loop_imc:
+ ld1 {v0.4s},[x2]
+ ld1 {v1.4s},[x0]
+ aesimc v0.16b,v0.16b
+ aesimc v1.16b,v1.16b
+ st1 {v0.4s},[x0],x4
+ st1 {v1.4s},[x2],#16
+ cmp x0,x2
+ b.hi .Loop_imc
+
+ ld1 {v0.4s},[x2]
+ aesimc v0.16b,v0.16b
+ st1 {v0.4s},[x0]
+
+ eor x0,x0,x0 // return value
+.Ldec_key_abort:
+ ldp x29,x30,[sp],#16
+.inst 0xd50323bf // autiasp
+ ret
+.size aes_v8_set_decrypt_key,.-aes_v8_set_decrypt_key
+.globl aes_v8_encrypt
+.type aes_v8_encrypt,%function
+.align 5
+aes_v8_encrypt:
+ ldr w3,[x2,#240]
+ ld1 {v0.4s},[x2],#16
+ ld1 {v2.16b},[x0]
+ sub w3,w3,#2
+ ld1 {v1.4s},[x2],#16
+
+.Loop_enc:
+ aese v2.16b,v0.16b
+ aesmc v2.16b,v2.16b
+ ld1 {v0.4s},[x2],#16
+ subs w3,w3,#2
+ aese v2.16b,v1.16b
+ aesmc v2.16b,v2.16b
+ ld1 {v1.4s},[x2],#16
+ b.gt .Loop_enc
+
+ aese v2.16b,v0.16b
+ aesmc v2.16b,v2.16b
+ ld1 {v0.4s},[x2]
+ aese v2.16b,v1.16b
+ eor v2.16b,v2.16b,v0.16b
+
+ st1 {v2.16b},[x1]
+ ret
+.size aes_v8_encrypt,.-aes_v8_encrypt
+.globl aes_v8_decrypt
+.type aes_v8_decrypt,%function
+.align 5
+aes_v8_decrypt:
+ ldr w3,[x2,#240]
+ ld1 {v0.4s},[x2],#16
+ ld1 {v2.16b},[x0]
+ sub w3,w3,#2
+ ld1 {v1.4s},[x2],#16
+
+.Loop_dec:
+ aesd v2.16b,v0.16b
+ aesimc v2.16b,v2.16b
+ ld1 {v0.4s},[x2],#16
+ subs w3,w3,#2
+ aesd v2.16b,v1.16b
+ aesimc v2.16b,v2.16b
+ ld1 {v1.4s},[x2],#16
+ b.gt .Loop_dec
+
+ aesd v2.16b,v0.16b
+ aesimc v2.16b,v2.16b
+ ld1 {v0.4s},[x2]
+ aesd v2.16b,v1.16b
+ eor v2.16b,v2.16b,v0.16b
+
+ st1 {v2.16b},[x1]
+ ret
+.size aes_v8_decrypt,.-aes_v8_decrypt
+.globl aes_v8_ecb_encrypt
+.type aes_v8_ecb_encrypt,%function
+.align 5
+aes_v8_ecb_encrypt:
+ subs x2,x2,#16
+ // Original input data size bigger than 16, jump to big size processing.
+ b.ne .Lecb_big_size
+ ld1 {v0.16b},[x0]
+ cmp w4,#0 // en- or decrypting?
+ ldr w5,[x3,#240]
+ ld1 {v5.4s,v6.4s},[x3],#32 // load key schedule...
+
+ b.eq .Lecb_small_dec
+ aese v0.16b,v5.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v16.4s,v17.4s},[x3],#32 // load key schedule...
+ aese v0.16b,v6.16b
+ aesmc v0.16b,v0.16b
+ subs w5,w5,#10 // if rounds==10, jump to aes-128-ecb processing
+ b.eq .Lecb_128_enc
+.Lecb_round_loop:
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v16.4s},[x3],#16 // load key schedule...
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v17.4s},[x3],#16 // load key schedule...
+ subs w5,w5,#2 // bias
+ b.gt .Lecb_round_loop
+.Lecb_128_enc:
+ ld1 {v18.4s,v19.4s},[x3],#32 // load key schedule...
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v20.4s,v21.4s},[x3],#32 // load key schedule...
+ aese v0.16b,v18.16b
+ aesmc v0.16b,v0.16b
+ aese v0.16b,v19.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v22.4s,v23.4s},[x3],#32 // load key schedule...
+ aese v0.16b,v20.16b
+ aesmc v0.16b,v0.16b
+ aese v0.16b,v21.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v7.4s},[x3]
+ aese v0.16b,v22.16b
+ aesmc v0.16b,v0.16b
+ aese v0.16b,v23.16b
+ eor v0.16b,v0.16b,v7.16b
+ st1 {v0.16b},[x1]
+ b .Lecb_Final_abort
+.Lecb_small_dec:
+ aesd v0.16b,v5.16b
+ aesimc v0.16b,v0.16b
+ ld1 {v16.4s,v17.4s},[x3],#32 // load key schedule...
+ aesd v0.16b,v6.16b
+ aesimc v0.16b,v0.16b
+ subs w5,w5,#10 // bias
+ b.eq .Lecb_128_dec
+.Lecb_dec_round_loop:
+ aesd v0.16b,v16.16b
+ aesimc v0.16b,v0.16b
+ ld1 {v16.4s},[x3],#16 // load key schedule...
+ aesd v0.16b,v17.16b
+ aesimc v0.16b,v0.16b
+ ld1 {v17.4s},[x3],#16 // load key schedule...
+ subs w5,w5,#2 // bias
+ b.gt .Lecb_dec_round_loop
+.Lecb_128_dec:
+ ld1 {v18.4s,v19.4s},[x3],#32 // load key schedule...
+ aesd v0.16b,v16.16b
+ aesimc v0.16b,v0.16b
+ aesd v0.16b,v17.16b
+ aesimc v0.16b,v0.16b
+ ld1 {v20.4s,v21.4s},[x3],#32 // load key schedule...
+ aesd v0.16b,v18.16b
+ aesimc v0.16b,v0.16b
+ aesd v0.16b,v19.16b
+ aesimc v0.16b,v0.16b
+ ld1 {v22.4s,v23.4s},[x3],#32 // load key schedule...
+ aesd v0.16b,v20.16b
+ aesimc v0.16b,v0.16b
+ aesd v0.16b,v21.16b
+ aesimc v0.16b,v0.16b
+ ld1 {v7.4s},[x3]
+ aesd v0.16b,v22.16b
+ aesimc v0.16b,v0.16b
+ aesd v0.16b,v23.16b
+ eor v0.16b,v0.16b,v7.16b
+ st1 {v0.16b},[x1]
+ b .Lecb_Final_abort
+.Lecb_big_size:
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+ mov x8,#16
+ b.lo .Lecb_done
+ csel x8,xzr,x8,eq
+
+ cmp w4,#0 // en- or decrypting?
+ ldr w5,[x3,#240]
+ and x2,x2,#-16
+ ld1 {v0.16b},[x0],x8
+
+ ld1 {v16.4s,v17.4s},[x3] // load key schedule...
+ sub w5,w5,#6
+ add x7,x3,x5,lsl#4 // pointer to last 7 round keys
+ sub w5,w5,#2
+ ld1 {v18.4s,v19.4s},[x7],#32
+ ld1 {v20.4s,v21.4s},[x7],#32
+ ld1 {v22.4s,v23.4s},[x7],#32
+ ld1 {v7.4s},[x7]
+
+ add x7,x3,#32
+ mov w6,w5
+ b.eq .Lecb_dec
+
+ ld1 {v1.16b},[x0],#16
+ subs x2,x2,#32 // bias
+ add w6,w5,#2
+ orr v3.16b,v1.16b,v1.16b
+ orr v24.16b,v1.16b,v1.16b
+ orr v1.16b,v0.16b,v0.16b
+ b.lo .Lecb_enc_tail
+
+ orr v1.16b,v3.16b,v3.16b
+ ld1 {v24.16b},[x0],#16
+ cmp x2,#32
+ b.lo .Loop3x_ecb_enc
+
+ ld1 {v25.16b},[x0],#16
+ ld1 {v26.16b},[x0],#16
+ sub x2,x2,#32 // bias
+ mov w6,w5
+
+.Loop5x_ecb_enc:
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v16.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v16.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v16.16b
+ aesmc v25.16b,v25.16b
+ aese v26.16b,v16.16b
+ aesmc v26.16b,v26.16b
+ ld1 {v16.4s},[x7],#16
+ subs w6,w6,#2
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v17.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v17.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v17.16b
+ aesmc v25.16b,v25.16b
+ aese v26.16b,v17.16b
+ aesmc v26.16b,v26.16b
+ ld1 {v17.4s},[x7],#16
+ b.gt .Loop5x_ecb_enc
+
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v16.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v16.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v16.16b
+ aesmc v25.16b,v25.16b
+ aese v26.16b,v16.16b
+ aesmc v26.16b,v26.16b
+ cmp x2,#0x40 // because .Lecb_enc_tail4x
+ sub x2,x2,#0x50
+
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v17.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v17.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v17.16b
+ aesmc v25.16b,v25.16b
+ aese v26.16b,v17.16b
+ aesmc v26.16b,v26.16b
+ csel x6,xzr,x2,gt // borrow x6, w6, "gt" is not typo
+ mov x7,x3
+
+ aese v0.16b,v18.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v18.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v18.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v18.16b
+ aesmc v25.16b,v25.16b
+ aese v26.16b,v18.16b
+ aesmc v26.16b,v26.16b
+ add x0,x0,x6 // x0 is adjusted in such way that
+ // at exit from the loop v1.16b-v26.16b
+ // are loaded with last "words"
+ add x6,x2,#0x60 // because .Lecb_enc_tail4x
+
+ aese v0.16b,v19.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v19.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v19.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v19.16b
+ aesmc v25.16b,v25.16b
+ aese v26.16b,v19.16b
+ aesmc v26.16b,v26.16b
+
+ aese v0.16b,v20.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v20.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v20.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v20.16b
+ aesmc v25.16b,v25.16b
+ aese v26.16b,v20.16b
+ aesmc v26.16b,v26.16b
+
+ aese v0.16b,v21.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v21.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v21.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v21.16b
+ aesmc v25.16b,v25.16b
+ aese v26.16b,v21.16b
+ aesmc v26.16b,v26.16b
+
+ aese v0.16b,v22.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v22.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v22.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v22.16b
+ aesmc v25.16b,v25.16b
+ aese v26.16b,v22.16b
+ aesmc v26.16b,v26.16b
+
+ aese v0.16b,v23.16b
+ ld1 {v2.16b},[x0],#16
+ aese v1.16b,v23.16b
+ ld1 {v3.16b},[x0],#16
+ aese v24.16b,v23.16b
+ ld1 {v27.16b},[x0],#16
+ aese v25.16b,v23.16b
+ ld1 {v28.16b},[x0],#16
+ aese v26.16b,v23.16b
+ ld1 {v29.16b},[x0],#16
+ cbz x6,.Lecb_enc_tail4x
+ ld1 {v16.4s},[x7],#16 // re-pre-load rndkey[0]
+ eor v4.16b,v7.16b,v0.16b
+ orr v0.16b,v2.16b,v2.16b
+ eor v5.16b,v7.16b,v1.16b
+ orr v1.16b,v3.16b,v3.16b
+ eor v17.16b,v7.16b,v24.16b
+ orr v24.16b,v27.16b,v27.16b
+ eor v30.16b,v7.16b,v25.16b
+ orr v25.16b,v28.16b,v28.16b
+ eor v31.16b,v7.16b,v26.16b
+ st1 {v4.16b},[x1],#16
+ orr v26.16b,v29.16b,v29.16b
+ st1 {v5.16b},[x1],#16
+ mov w6,w5
+ st1 {v17.16b},[x1],#16
+ ld1 {v17.4s},[x7],#16 // re-pre-load rndkey[1]
+ st1 {v30.16b},[x1],#16
+ st1 {v31.16b},[x1],#16
+ b.hs .Loop5x_ecb_enc
+
+ add x2,x2,#0x50
+ cbz x2,.Lecb_done
+
+ add w6,w5,#2
+ subs x2,x2,#0x30
+ orr v0.16b,v27.16b,v27.16b
+ orr v1.16b,v28.16b,v28.16b
+ orr v24.16b,v29.16b,v29.16b
+ b.lo .Lecb_enc_tail
+
+ b .Loop3x_ecb_enc
+
+.align 4
+.Lecb_enc_tail4x:
+ eor v5.16b,v7.16b,v1.16b
+ eor v17.16b,v7.16b,v24.16b
+ eor v30.16b,v7.16b,v25.16b
+ eor v31.16b,v7.16b,v26.16b
+ st1 {v5.16b},[x1],#16
+ st1 {v17.16b},[x1],#16
+ st1 {v30.16b},[x1],#16
+ st1 {v31.16b},[x1],#16
+
+ b .Lecb_done
+.align 4
+.Loop3x_ecb_enc:
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v16.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v16.16b
+ aesmc v24.16b,v24.16b
+ ld1 {v16.4s},[x7],#16
+ subs w6,w6,#2
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v17.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v17.16b
+ aesmc v24.16b,v24.16b
+ ld1 {v17.4s},[x7],#16
+ b.gt .Loop3x_ecb_enc
+
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v16.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v16.16b
+ aesmc v24.16b,v24.16b
+ subs x2,x2,#0x30
+ csel x6,x2,x6,lo // x6, w6, is zero at this point
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v17.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v17.16b
+ aesmc v24.16b,v24.16b
+ add x0,x0,x6 // x0 is adjusted in such way that
+ // at exit from the loop v1.16b-v24.16b
+ // are loaded with last "words"
+ mov x7,x3
+ aese v0.16b,v20.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v20.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v20.16b
+ aesmc v24.16b,v24.16b
+ ld1 {v2.16b},[x0],#16
+ aese v0.16b,v21.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v21.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v21.16b
+ aesmc v24.16b,v24.16b
+ ld1 {v3.16b},[x0],#16
+ aese v0.16b,v22.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v22.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v22.16b
+ aesmc v24.16b,v24.16b
+ ld1 {v27.16b},[x0],#16
+ aese v0.16b,v23.16b
+ aese v1.16b,v23.16b
+ aese v24.16b,v23.16b
+ ld1 {v16.4s},[x7],#16 // re-pre-load rndkey[0]
+ add w6,w5,#2
+ eor v4.16b,v7.16b,v0.16b
+ eor v5.16b,v7.16b,v1.16b
+ eor v24.16b,v24.16b,v7.16b
+ ld1 {v17.4s},[x7],#16 // re-pre-load rndkey[1]
+ st1 {v4.16b},[x1],#16
+ orr v0.16b,v2.16b,v2.16b
+ st1 {v5.16b},[x1],#16
+ orr v1.16b,v3.16b,v3.16b
+ st1 {v24.16b},[x1],#16
+ orr v24.16b,v27.16b,v27.16b
+ b.hs .Loop3x_ecb_enc
+
+ cmn x2,#0x30
+ b.eq .Lecb_done
+ nop
+
+.Lecb_enc_tail:
+ aese v1.16b,v16.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v16.16b
+ aesmc v24.16b,v24.16b
+ ld1 {v16.4s},[x7],#16
+ subs w6,w6,#2
+ aese v1.16b,v17.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v17.16b
+ aesmc v24.16b,v24.16b
+ ld1 {v17.4s},[x7],#16
+ b.gt .Lecb_enc_tail
+
+ aese v1.16b,v16.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v16.16b
+ aesmc v24.16b,v24.16b
+ aese v1.16b,v17.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v17.16b
+ aesmc v24.16b,v24.16b
+ aese v1.16b,v20.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v20.16b
+ aesmc v24.16b,v24.16b
+ cmn x2,#0x20
+ aese v1.16b,v21.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v21.16b
+ aesmc v24.16b,v24.16b
+ aese v1.16b,v22.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v22.16b
+ aesmc v24.16b,v24.16b
+ aese v1.16b,v23.16b
+ aese v24.16b,v23.16b
+ b.eq .Lecb_enc_one
+ eor v5.16b,v7.16b,v1.16b
+ eor v17.16b,v7.16b,v24.16b
+ st1 {v5.16b},[x1],#16
+ st1 {v17.16b},[x1],#16
+ b .Lecb_done
+
+.Lecb_enc_one:
+ eor v5.16b,v7.16b,v24.16b
+ st1 {v5.16b},[x1],#16
+ b .Lecb_done
+.align 5
+.Lecb_dec:
+ ld1 {v1.16b},[x0],#16
+ subs x2,x2,#32 // bias
+ add w6,w5,#2
+ orr v3.16b,v1.16b,v1.16b
+ orr v24.16b,v1.16b,v1.16b
+ orr v1.16b,v0.16b,v0.16b
+ b.lo .Lecb_dec_tail
+
+ orr v1.16b,v3.16b,v3.16b
+ ld1 {v24.16b},[x0],#16
+ cmp x2,#32
+ b.lo .Loop3x_ecb_dec
+
+ ld1 {v25.16b},[x0],#16
+ ld1 {v26.16b},[x0],#16
+ sub x2,x2,#32 // bias
+ mov w6,w5
+
+.Loop5x_ecb_dec:
+ aesd v0.16b,v16.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v16.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v16.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v16.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v16.16b
+ aesimc v26.16b,v26.16b
+ ld1 {v16.4s},[x7],#16
+ subs w6,w6,#2
+ aesd v0.16b,v17.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v17.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v17.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v17.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v17.16b
+ aesimc v26.16b,v26.16b
+ ld1 {v17.4s},[x7],#16
+ b.gt .Loop5x_ecb_dec
+
+ aesd v0.16b,v16.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v16.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v16.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v16.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v16.16b
+ aesimc v26.16b,v26.16b
+ cmp x2,#0x40 // because .Lecb_tail4x
+ sub x2,x2,#0x50
+
+ aesd v0.16b,v17.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v17.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v17.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v17.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v17.16b
+ aesimc v26.16b,v26.16b
+ csel x6,xzr,x2,gt // borrow x6, w6, "gt" is not typo
+ mov x7,x3
+
+ aesd v0.16b,v18.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v18.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v18.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v18.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v18.16b
+ aesimc v26.16b,v26.16b
+ add x0,x0,x6 // x0 is adjusted in such way that
+ // at exit from the loop v1.16b-v26.16b
+ // are loaded with last "words"
+ add x6,x2,#0x60 // because .Lecb_tail4x
+
+ aesd v0.16b,v19.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v19.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v19.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v19.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v19.16b
+ aesimc v26.16b,v26.16b
+
+ aesd v0.16b,v20.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v20.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v20.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v20.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v20.16b
+ aesimc v26.16b,v26.16b
+
+ aesd v0.16b,v21.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v21.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v21.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v21.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v21.16b
+ aesimc v26.16b,v26.16b
+
+ aesd v0.16b,v22.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v22.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v22.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v22.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v22.16b
+ aesimc v26.16b,v26.16b
+
+ aesd v0.16b,v23.16b
+ ld1 {v2.16b},[x0],#16
+ aesd v1.16b,v23.16b
+ ld1 {v3.16b},[x0],#16
+ aesd v24.16b,v23.16b
+ ld1 {v27.16b},[x0],#16
+ aesd v25.16b,v23.16b
+ ld1 {v28.16b},[x0],#16
+ aesd v26.16b,v23.16b
+ ld1 {v29.16b},[x0],#16
+ cbz x6,.Lecb_tail4x
+ ld1 {v16.4s},[x7],#16 // re-pre-load rndkey[0]
+ eor v4.16b,v7.16b,v0.16b
+ orr v0.16b,v2.16b,v2.16b
+ eor v5.16b,v7.16b,v1.16b
+ orr v1.16b,v3.16b,v3.16b
+ eor v17.16b,v7.16b,v24.16b
+ orr v24.16b,v27.16b,v27.16b
+ eor v30.16b,v7.16b,v25.16b
+ orr v25.16b,v28.16b,v28.16b
+ eor v31.16b,v7.16b,v26.16b
+ st1 {v4.16b},[x1],#16
+ orr v26.16b,v29.16b,v29.16b
+ st1 {v5.16b},[x1],#16
+ mov w6,w5
+ st1 {v17.16b},[x1],#16
+ ld1 {v17.4s},[x7],#16 // re-pre-load rndkey[1]
+ st1 {v30.16b},[x1],#16
+ st1 {v31.16b},[x1],#16
+ b.hs .Loop5x_ecb_dec
+
+ add x2,x2,#0x50
+ cbz x2,.Lecb_done
+
+ add w6,w5,#2
+ subs x2,x2,#0x30
+ orr v0.16b,v27.16b,v27.16b
+ orr v1.16b,v28.16b,v28.16b
+ orr v24.16b,v29.16b,v29.16b
+ b.lo .Lecb_dec_tail
+
+ b .Loop3x_ecb_dec
+
+.align 4
+.Lecb_tail4x:
+ eor v5.16b,v7.16b,v1.16b
+ eor v17.16b,v7.16b,v24.16b
+ eor v30.16b,v7.16b,v25.16b
+ eor v31.16b,v7.16b,v26.16b
+ st1 {v5.16b},[x1],#16
+ st1 {v17.16b},[x1],#16
+ st1 {v30.16b},[x1],#16
+ st1 {v31.16b},[x1],#16
+
+ b .Lecb_done
+.align 4
+.Loop3x_ecb_dec:
+ aesd v0.16b,v16.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v16.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v16.16b
+ aesimc v24.16b,v24.16b
+ ld1 {v16.4s},[x7],#16
+ subs w6,w6,#2
+ aesd v0.16b,v17.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v17.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v17.16b
+ aesimc v24.16b,v24.16b
+ ld1 {v17.4s},[x7],#16
+ b.gt .Loop3x_ecb_dec
+
+ aesd v0.16b,v16.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v16.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v16.16b
+ aesimc v24.16b,v24.16b
+ subs x2,x2,#0x30
+ csel x6,x2,x6,lo // x6, w6, is zero at this point
+ aesd v0.16b,v17.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v17.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v17.16b
+ aesimc v24.16b,v24.16b
+ add x0,x0,x6 // x0 is adjusted in such way that
+ // at exit from the loop v1.16b-v24.16b
+ // are loaded with last "words"
+ mov x7,x3
+ aesd v0.16b,v20.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v20.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v20.16b
+ aesimc v24.16b,v24.16b
+ ld1 {v2.16b},[x0],#16
+ aesd v0.16b,v21.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v21.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v21.16b
+ aesimc v24.16b,v24.16b
+ ld1 {v3.16b},[x0],#16
+ aesd v0.16b,v22.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v22.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v22.16b
+ aesimc v24.16b,v24.16b
+ ld1 {v27.16b},[x0],#16
+ aesd v0.16b,v23.16b
+ aesd v1.16b,v23.16b
+ aesd v24.16b,v23.16b
+ ld1 {v16.4s},[x7],#16 // re-pre-load rndkey[0]
+ add w6,w5,#2
+ eor v4.16b,v7.16b,v0.16b
+ eor v5.16b,v7.16b,v1.16b
+ eor v24.16b,v24.16b,v7.16b
+ ld1 {v17.4s},[x7],#16 // re-pre-load rndkey[1]
+ st1 {v4.16b},[x1],#16
+ orr v0.16b,v2.16b,v2.16b
+ st1 {v5.16b},[x1],#16
+ orr v1.16b,v3.16b,v3.16b
+ st1 {v24.16b},[x1],#16
+ orr v24.16b,v27.16b,v27.16b
+ b.hs .Loop3x_ecb_dec
+
+ cmn x2,#0x30
+ b.eq .Lecb_done
+ nop
+
+.Lecb_dec_tail:
+ aesd v1.16b,v16.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v16.16b
+ aesimc v24.16b,v24.16b
+ ld1 {v16.4s},[x7],#16
+ subs w6,w6,#2
+ aesd v1.16b,v17.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v17.16b
+ aesimc v24.16b,v24.16b
+ ld1 {v17.4s},[x7],#16
+ b.gt .Lecb_dec_tail
+
+ aesd v1.16b,v16.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v16.16b
+ aesimc v24.16b,v24.16b
+ aesd v1.16b,v17.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v17.16b
+ aesimc v24.16b,v24.16b
+ aesd v1.16b,v20.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v20.16b
+ aesimc v24.16b,v24.16b
+ cmn x2,#0x20
+ aesd v1.16b,v21.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v21.16b
+ aesimc v24.16b,v24.16b
+ aesd v1.16b,v22.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v22.16b
+ aesimc v24.16b,v24.16b
+ aesd v1.16b,v23.16b
+ aesd v24.16b,v23.16b
+ b.eq .Lecb_dec_one
+ eor v5.16b,v7.16b,v1.16b
+ eor v17.16b,v7.16b,v24.16b
+ st1 {v5.16b},[x1],#16
+ st1 {v17.16b},[x1],#16
+ b .Lecb_done
+
+.Lecb_dec_one:
+ eor v5.16b,v7.16b,v24.16b
+ st1 {v5.16b},[x1],#16
+
+.Lecb_done:
+ ldr x29,[sp],#16
+.Lecb_Final_abort:
+ ret
+.size aes_v8_ecb_encrypt,.-aes_v8_ecb_encrypt
+.globl aes_v8_cbc_encrypt
+.type aes_v8_cbc_encrypt,%function
+.align 5
+aes_v8_cbc_encrypt:
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+ subs x2,x2,#16
+ mov x8,#16
+ b.lo .Lcbc_abort
+ csel x8,xzr,x8,eq
+
+ cmp w5,#0 // en- or decrypting?
+ ldr w5,[x3,#240]
+ and x2,x2,#-16
+ ld1 {v6.16b},[x4]
+ ld1 {v0.16b},[x0],x8
+
+ ld1 {v16.4s,v17.4s},[x3] // load key schedule...
+ sub w5,w5,#6
+ add x7,x3,x5,lsl#4 // pointer to last 7 round keys
+ sub w5,w5,#2
+ ld1 {v18.4s,v19.4s},[x7],#32
+ ld1 {v20.4s,v21.4s},[x7],#32
+ ld1 {v22.4s,v23.4s},[x7],#32
+ ld1 {v7.4s},[x7]
+
+ add x7,x3,#32
+ mov w6,w5
+ b.eq .Lcbc_dec
+
+ cmp w5,#2
+ eor v0.16b,v0.16b,v6.16b
+ eor v5.16b,v16.16b,v7.16b
+ b.eq .Lcbc_enc128
+
+ ld1 {v2.4s,v3.4s},[x7]
+ add x7,x3,#16
+ add x6,x3,#16*4
+ add x12,x3,#16*5
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ add x14,x3,#16*6
+ add x3,x3,#16*7
+ b .Lenter_cbc_enc
+
+.align 4
+.Loop_cbc_enc:
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ st1 {v6.16b},[x1],#16
+.Lenter_cbc_enc:
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ aese v0.16b,v2.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v16.4s},[x6]
+ cmp w5,#4
+ aese v0.16b,v3.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v17.4s},[x12]
+ b.eq .Lcbc_enc192
+
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v16.4s},[x14]
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v17.4s},[x3]
+ nop
+
+.Lcbc_enc192:
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ subs x2,x2,#16
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ csel x8,xzr,x8,eq
+ aese v0.16b,v18.16b
+ aesmc v0.16b,v0.16b
+ aese v0.16b,v19.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v16.16b},[x0],x8
+ aese v0.16b,v20.16b
+ aesmc v0.16b,v0.16b
+ eor v16.16b,v16.16b,v5.16b
+ aese v0.16b,v21.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v17.4s},[x7] // re-pre-load rndkey[1]
+ aese v0.16b,v22.16b
+ aesmc v0.16b,v0.16b
+ aese v0.16b,v23.16b
+ eor v6.16b,v0.16b,v7.16b
+ b.hs .Loop_cbc_enc
+
+ st1 {v6.16b},[x1],#16
+ b .Lcbc_done
+
+.align 5
+.Lcbc_enc128:
+ ld1 {v2.4s,v3.4s},[x7]
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ b .Lenter_cbc_enc128
+.Loop_cbc_enc128:
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ st1 {v6.16b},[x1],#16
+.Lenter_cbc_enc128:
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ subs x2,x2,#16
+ aese v0.16b,v2.16b
+ aesmc v0.16b,v0.16b
+ csel x8,xzr,x8,eq
+ aese v0.16b,v3.16b
+ aesmc v0.16b,v0.16b
+ aese v0.16b,v18.16b
+ aesmc v0.16b,v0.16b
+ aese v0.16b,v19.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v16.16b},[x0],x8
+ aese v0.16b,v20.16b
+ aesmc v0.16b,v0.16b
+ aese v0.16b,v21.16b
+ aesmc v0.16b,v0.16b
+ aese v0.16b,v22.16b
+ aesmc v0.16b,v0.16b
+ eor v16.16b,v16.16b,v5.16b
+ aese v0.16b,v23.16b
+ eor v6.16b,v0.16b,v7.16b
+ b.hs .Loop_cbc_enc128
+
+ st1 {v6.16b},[x1],#16
+ b .Lcbc_done
+.align 5
+.Lcbc_dec:
+ ld1 {v24.16b},[x0],#16
+ subs x2,x2,#32 // bias
+ add w6,w5,#2
+ orr v3.16b,v0.16b,v0.16b
+ orr v1.16b,v0.16b,v0.16b
+ orr v27.16b,v24.16b,v24.16b
+ b.lo .Lcbc_dec_tail
+
+ orr v1.16b,v24.16b,v24.16b
+ ld1 {v24.16b},[x0],#16
+ orr v2.16b,v0.16b,v0.16b
+ orr v3.16b,v1.16b,v1.16b
+ orr v27.16b,v24.16b,v24.16b
+ cmp x2,#32
+ b.lo .Loop3x_cbc_dec
+
+ ld1 {v25.16b},[x0],#16
+ ld1 {v26.16b},[x0],#16
+ sub x2,x2,#32 // bias
+ mov w6,w5
+ orr v28.16b,v25.16b,v25.16b
+ orr v29.16b,v26.16b,v26.16b
+
+.Loop5x_cbc_dec:
+ aesd v0.16b,v16.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v16.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v16.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v16.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v16.16b
+ aesimc v26.16b,v26.16b
+ ld1 {v16.4s},[x7],#16
+ subs w6,w6,#2
+ aesd v0.16b,v17.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v17.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v17.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v17.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v17.16b
+ aesimc v26.16b,v26.16b
+ ld1 {v17.4s},[x7],#16
+ b.gt .Loop5x_cbc_dec
+
+ aesd v0.16b,v16.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v16.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v16.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v16.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v16.16b
+ aesimc v26.16b,v26.16b
+ cmp x2,#0x40 // because .Lcbc_tail4x
+ sub x2,x2,#0x50
+
+ aesd v0.16b,v17.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v17.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v17.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v17.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v17.16b
+ aesimc v26.16b,v26.16b
+ csel x6,xzr,x2,gt // borrow x6, w6, "gt" is not typo
+ mov x7,x3
+
+ aesd v0.16b,v18.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v18.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v18.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v18.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v18.16b
+ aesimc v26.16b,v26.16b
+ add x0,x0,x6 // x0 is adjusted in such way that
+ // at exit from the loop v1.16b-v26.16b
+ // are loaded with last "words"
+ add x6,x2,#0x60 // because .Lcbc_tail4x
+
+ aesd v0.16b,v19.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v19.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v19.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v19.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v19.16b
+ aesimc v26.16b,v26.16b
+
+ aesd v0.16b,v20.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v20.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v20.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v20.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v20.16b
+ aesimc v26.16b,v26.16b
+
+ aesd v0.16b,v21.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v21.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v21.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v21.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v21.16b
+ aesimc v26.16b,v26.16b
+
+ aesd v0.16b,v22.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v22.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v22.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v22.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v22.16b
+ aesimc v26.16b,v26.16b
+
+ eor v4.16b,v6.16b,v7.16b
+ aesd v0.16b,v23.16b
+ eor v5.16b,v2.16b,v7.16b
+ ld1 {v2.16b},[x0],#16
+ aesd v1.16b,v23.16b
+ eor v17.16b,v3.16b,v7.16b
+ ld1 {v3.16b},[x0],#16
+ aesd v24.16b,v23.16b
+ eor v30.16b,v27.16b,v7.16b
+ ld1 {v27.16b},[x0],#16
+ aesd v25.16b,v23.16b
+ eor v31.16b,v28.16b,v7.16b
+ ld1 {v28.16b},[x0],#16
+ aesd v26.16b,v23.16b
+ orr v6.16b,v29.16b,v29.16b
+ ld1 {v29.16b},[x0],#16
+ cbz x6,.Lcbc_tail4x
+ ld1 {v16.4s},[x7],#16 // re-pre-load rndkey[0]
+ eor v4.16b,v4.16b,v0.16b
+ orr v0.16b,v2.16b,v2.16b
+ eor v5.16b,v5.16b,v1.16b
+ orr v1.16b,v3.16b,v3.16b
+ eor v17.16b,v17.16b,v24.16b
+ orr v24.16b,v27.16b,v27.16b
+ eor v30.16b,v30.16b,v25.16b
+ orr v25.16b,v28.16b,v28.16b
+ eor v31.16b,v31.16b,v26.16b
+ st1 {v4.16b},[x1],#16
+ orr v26.16b,v29.16b,v29.16b
+ st1 {v5.16b},[x1],#16
+ mov w6,w5
+ st1 {v17.16b},[x1],#16
+ ld1 {v17.4s},[x7],#16 // re-pre-load rndkey[1]
+ st1 {v30.16b},[x1],#16
+ st1 {v31.16b},[x1],#16
+ b.hs .Loop5x_cbc_dec
+
+ add x2,x2,#0x50
+ cbz x2,.Lcbc_done
+
+ add w6,w5,#2
+ subs x2,x2,#0x30
+ orr v0.16b,v27.16b,v27.16b
+ orr v2.16b,v27.16b,v27.16b
+ orr v1.16b,v28.16b,v28.16b
+ orr v3.16b,v28.16b,v28.16b
+ orr v24.16b,v29.16b,v29.16b
+ orr v27.16b,v29.16b,v29.16b
+ b.lo .Lcbc_dec_tail
+
+ b .Loop3x_cbc_dec
+
+.align 4
+.Lcbc_tail4x:
+ eor v5.16b,v4.16b,v1.16b
+ eor v17.16b,v17.16b,v24.16b
+ eor v30.16b,v30.16b,v25.16b
+ eor v31.16b,v31.16b,v26.16b
+ st1 {v5.16b},[x1],#16
+ st1 {v17.16b},[x1],#16
+ st1 {v30.16b},[x1],#16
+ st1 {v31.16b},[x1],#16
+
+ b .Lcbc_done
+.align 4
+.Loop3x_cbc_dec:
+ aesd v0.16b,v16.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v16.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v16.16b
+ aesimc v24.16b,v24.16b
+ ld1 {v16.4s},[x7],#16
+ subs w6,w6,#2
+ aesd v0.16b,v17.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v17.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v17.16b
+ aesimc v24.16b,v24.16b
+ ld1 {v17.4s},[x7],#16
+ b.gt .Loop3x_cbc_dec
+
+ aesd v0.16b,v16.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v16.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v16.16b
+ aesimc v24.16b,v24.16b
+ eor v4.16b,v6.16b,v7.16b
+ subs x2,x2,#0x30
+ eor v5.16b,v2.16b,v7.16b
+ csel x6,x2,x6,lo // x6, w6, is zero at this point
+ aesd v0.16b,v17.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v17.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v17.16b
+ aesimc v24.16b,v24.16b
+ eor v17.16b,v3.16b,v7.16b
+ add x0,x0,x6 // x0 is adjusted in such way that
+ // at exit from the loop v1.16b-v24.16b
+ // are loaded with last "words"
+ orr v6.16b,v27.16b,v27.16b
+ mov x7,x3
+ aesd v0.16b,v20.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v20.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v20.16b
+ aesimc v24.16b,v24.16b
+ ld1 {v2.16b},[x0],#16
+ aesd v0.16b,v21.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v21.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v21.16b
+ aesimc v24.16b,v24.16b
+ ld1 {v3.16b},[x0],#16
+ aesd v0.16b,v22.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v22.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v22.16b
+ aesimc v24.16b,v24.16b
+ ld1 {v27.16b},[x0],#16
+ aesd v0.16b,v23.16b
+ aesd v1.16b,v23.16b
+ aesd v24.16b,v23.16b
+ ld1 {v16.4s},[x7],#16 // re-pre-load rndkey[0]
+ add w6,w5,#2
+ eor v4.16b,v4.16b,v0.16b
+ eor v5.16b,v5.16b,v1.16b
+ eor v24.16b,v24.16b,v17.16b
+ ld1 {v17.4s},[x7],#16 // re-pre-load rndkey[1]
+ st1 {v4.16b},[x1],#16
+ orr v0.16b,v2.16b,v2.16b
+ st1 {v5.16b},[x1],#16
+ orr v1.16b,v3.16b,v3.16b
+ st1 {v24.16b},[x1],#16
+ orr v24.16b,v27.16b,v27.16b
+ b.hs .Loop3x_cbc_dec
+
+ cmn x2,#0x30
+ b.eq .Lcbc_done
+ nop
+
+.Lcbc_dec_tail:
+ aesd v1.16b,v16.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v16.16b
+ aesimc v24.16b,v24.16b
+ ld1 {v16.4s},[x7],#16
+ subs w6,w6,#2
+ aesd v1.16b,v17.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v17.16b
+ aesimc v24.16b,v24.16b
+ ld1 {v17.4s},[x7],#16
+ b.gt .Lcbc_dec_tail
+
+ aesd v1.16b,v16.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v16.16b
+ aesimc v24.16b,v24.16b
+ aesd v1.16b,v17.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v17.16b
+ aesimc v24.16b,v24.16b
+ aesd v1.16b,v20.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v20.16b
+ aesimc v24.16b,v24.16b
+ cmn x2,#0x20
+ aesd v1.16b,v21.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v21.16b
+ aesimc v24.16b,v24.16b
+ eor v5.16b,v6.16b,v7.16b
+ aesd v1.16b,v22.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v22.16b
+ aesimc v24.16b,v24.16b
+ eor v17.16b,v3.16b,v7.16b
+ aesd v1.16b,v23.16b
+ aesd v24.16b,v23.16b
+ b.eq .Lcbc_dec_one
+ eor v5.16b,v5.16b,v1.16b
+ eor v17.16b,v17.16b,v24.16b
+ orr v6.16b,v27.16b,v27.16b
+ st1 {v5.16b},[x1],#16
+ st1 {v17.16b},[x1],#16
+ b .Lcbc_done
+
+.Lcbc_dec_one:
+ eor v5.16b,v5.16b,v24.16b
+ orr v6.16b,v27.16b,v27.16b
+ st1 {v5.16b},[x1],#16
+
+.Lcbc_done:
+ st1 {v6.16b},[x4]
+.Lcbc_abort:
+ ldr x29,[sp],#16
+ ret
+.size aes_v8_cbc_encrypt,.-aes_v8_cbc_encrypt
+.globl aes_v8_ctr32_encrypt_blocks
+.type aes_v8_ctr32_encrypt_blocks,%function
+.align 5
+aes_v8_ctr32_encrypt_blocks:
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+ ldr w5,[x3,#240]
+
+ ldr w8, [x4, #12]
+#ifdef __ARMEB__
+ ld1 {v0.16b},[x4]
+#else
+ ld1 {v0.4s},[x4]
+#endif
+ ld1 {v16.4s,v17.4s},[x3] // load key schedule...
+ sub w5,w5,#4
+ mov x12,#16
+ cmp x2,#2
+ add x7,x3,x5,lsl#4 // pointer to last 5 round keys
+ sub w5,w5,#2
+ ld1 {v20.4s,v21.4s},[x7],#32
+ ld1 {v22.4s,v23.4s},[x7],#32
+ ld1 {v7.4s},[x7]
+ add x7,x3,#32
+ mov w6,w5
+ csel x12,xzr,x12,lo
+#ifndef __ARMEB__
+ rev w8, w8
+#endif
+ orr v1.16b,v0.16b,v0.16b
+ add w10, w8, #1
+ orr v18.16b,v0.16b,v0.16b
+ add w8, w8, #2
+ orr v6.16b,v0.16b,v0.16b
+ rev w10, w10
+ mov v1.s[3],w10
+ b.ls .Lctr32_tail
+ rev w12, w8
+ sub x2,x2,#3 // bias
+ mov v18.s[3],w12
+ cmp x2,#32
+ b.lo .Loop3x_ctr32
+
+ add w13,w8,#1
+ add w14,w8,#2
+ orr v24.16b,v0.16b,v0.16b
+ rev w13,w13
+ orr v25.16b,v0.16b,v0.16b
+ rev w14,w14
+ mov v24.s[3],w13
+ sub x2,x2,#2 // bias
+ mov v25.s[3],w14
+ add w8,w8,#2
+ b .Loop5x_ctr32
+
+.align 4
+.Loop5x_ctr32:
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v16.16b
+ aesmc v1.16b,v1.16b
+ aese v18.16b,v16.16b
+ aesmc v18.16b,v18.16b
+ aese v24.16b,v16.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v16.16b
+ aesmc v25.16b,v25.16b
+ ld1 {v16.4s},[x7],#16
+ subs w6,w6,#2
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v17.16b
+ aesmc v1.16b,v1.16b
+ aese v18.16b,v17.16b
+ aesmc v18.16b,v18.16b
+ aese v24.16b,v17.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v17.16b
+ aesmc v25.16b,v25.16b
+ ld1 {v17.4s},[x7],#16
+ b.gt .Loop5x_ctr32
+
+ mov x7,x3
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v16.16b
+ aesmc v1.16b,v1.16b
+ aese v18.16b,v16.16b
+ aesmc v18.16b,v18.16b
+ aese v24.16b,v16.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v16.16b
+ aesmc v25.16b,v25.16b
+ ld1 {v16.4s},[x7],#16 // re-pre-load rndkey[0]
+
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v17.16b
+ aesmc v1.16b,v1.16b
+ aese v18.16b,v17.16b
+ aesmc v18.16b,v18.16b
+ aese v24.16b,v17.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v17.16b
+ aesmc v25.16b,v25.16b
+ ld1 {v17.4s},[x7],#16 // re-pre-load rndkey[1]
+
+ aese v0.16b,v20.16b
+ aesmc v0.16b,v0.16b
+ add w9,w8,#1
+ add w10,w8,#2
+ aese v1.16b,v20.16b
+ aesmc v1.16b,v1.16b
+ add w12,w8,#3
+ add w13,w8,#4
+ aese v18.16b,v20.16b
+ aesmc v18.16b,v18.16b
+ add w14,w8,#5
+ rev w9,w9
+ aese v24.16b,v20.16b
+ aesmc v24.16b,v24.16b
+ rev w10,w10
+ rev w12,w12
+ aese v25.16b,v20.16b
+ aesmc v25.16b,v25.16b
+ rev w13,w13
+ rev w14,w14
+
+ aese v0.16b,v21.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v21.16b
+ aesmc v1.16b,v1.16b
+ aese v18.16b,v21.16b
+ aesmc v18.16b,v18.16b
+ aese v24.16b,v21.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v21.16b
+ aesmc v25.16b,v25.16b
+
+ aese v0.16b,v22.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v2.16b},[x0],#16
+ aese v1.16b,v22.16b
+ aesmc v1.16b,v1.16b
+ ld1 {v3.16b},[x0],#16
+ aese v18.16b,v22.16b
+ aesmc v18.16b,v18.16b
+ ld1 {v19.16b},[x0],#16
+ aese v24.16b,v22.16b
+ aesmc v24.16b,v24.16b
+ ld1 {v26.16b},[x0],#16
+ aese v25.16b,v22.16b
+ aesmc v25.16b,v25.16b
+ ld1 {v27.16b},[x0],#16
+
+ aese v0.16b,v23.16b
+ eor v2.16b,v2.16b,v7.16b
+ aese v1.16b,v23.16b
+ eor v3.16b,v3.16b,v7.16b
+ aese v18.16b,v23.16b
+ eor v19.16b,v19.16b,v7.16b
+ aese v24.16b,v23.16b
+ eor v26.16b,v26.16b,v7.16b
+ aese v25.16b,v23.16b
+ eor v27.16b,v27.16b,v7.16b
+
+ eor v2.16b,v2.16b,v0.16b
+ orr v0.16b,v6.16b,v6.16b
+ eor v3.16b,v3.16b,v1.16b
+ orr v1.16b,v6.16b,v6.16b
+ eor v19.16b,v19.16b,v18.16b
+ orr v18.16b,v6.16b,v6.16b
+ eor v26.16b,v26.16b,v24.16b
+ orr v24.16b,v6.16b,v6.16b
+ eor v27.16b,v27.16b,v25.16b
+ orr v25.16b,v6.16b,v6.16b
+
+ st1 {v2.16b},[x1],#16
+ mov v0.s[3],w9
+ st1 {v3.16b},[x1],#16
+ mov v1.s[3],w10
+ st1 {v19.16b},[x1],#16
+ mov v18.s[3],w12
+ st1 {v26.16b},[x1],#16
+ mov v24.s[3],w13
+ st1 {v27.16b},[x1],#16
+ mov v25.s[3],w14
+
+ mov w6,w5
+ cbz x2,.Lctr32_done
+
+ add w8,w8,#5
+ subs x2,x2,#5
+ b.hs .Loop5x_ctr32
+
+ add x2,x2,#5
+ sub w8,w8,#5
+
+ cmp x2,#2
+ mov x12,#16
+ csel x12,xzr,x12,lo
+ b.ls .Lctr32_tail
+
+ sub x2,x2,#3 // bias
+ add w8,w8,#3
+ b .Loop3x_ctr32
+
+.align 4
+.Loop3x_ctr32:
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v16.16b
+ aesmc v1.16b,v1.16b
+ aese v18.16b,v16.16b
+ aesmc v18.16b,v18.16b
+ ld1 {v16.4s},[x7],#16
+ subs w6,w6,#2
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v17.16b
+ aesmc v1.16b,v1.16b
+ aese v18.16b,v17.16b
+ aesmc v18.16b,v18.16b
+ ld1 {v17.4s},[x7],#16
+ b.gt .Loop3x_ctr32
+
+ aese v0.16b,v16.16b
+ aesmc v4.16b,v0.16b
+ aese v1.16b,v16.16b
+ aesmc v5.16b,v1.16b
+ ld1 {v2.16b},[x0],#16
+ orr v0.16b,v6.16b,v6.16b
+ aese v18.16b,v16.16b
+ aesmc v18.16b,v18.16b
+ ld1 {v3.16b},[x0],#16
+ orr v1.16b,v6.16b,v6.16b
+ aese v4.16b,v17.16b
+ aesmc v4.16b,v4.16b
+ aese v5.16b,v17.16b
+ aesmc v5.16b,v5.16b
+ ld1 {v19.16b},[x0],#16
+ mov x7,x3
+ aese v18.16b,v17.16b
+ aesmc v17.16b,v18.16b
+ orr v18.16b,v6.16b,v6.16b
+ add w9,w8,#1
+ aese v4.16b,v20.16b
+ aesmc v4.16b,v4.16b
+ aese v5.16b,v20.16b
+ aesmc v5.16b,v5.16b
+ eor v2.16b,v2.16b,v7.16b
+ add w10,w8,#2
+ aese v17.16b,v20.16b
+ aesmc v17.16b,v17.16b
+ eor v3.16b,v3.16b,v7.16b
+ add w8,w8,#3
+ aese v4.16b,v21.16b
+ aesmc v4.16b,v4.16b
+ aese v5.16b,v21.16b
+ aesmc v5.16b,v5.16b
+ eor v19.16b,v19.16b,v7.16b
+ rev w9,w9
+ aese v17.16b,v21.16b
+ aesmc v17.16b,v17.16b
+ mov v0.s[3], w9
+ rev w10,w10
+ aese v4.16b,v22.16b
+ aesmc v4.16b,v4.16b
+ aese v5.16b,v22.16b
+ aesmc v5.16b,v5.16b
+ mov v1.s[3], w10
+ rev w12,w8
+ aese v17.16b,v22.16b
+ aesmc v17.16b,v17.16b
+ mov v18.s[3], w12
+ subs x2,x2,#3
+ aese v4.16b,v23.16b
+ aese v5.16b,v23.16b
+ aese v17.16b,v23.16b
+
+ eor v2.16b,v2.16b,v4.16b
+ ld1 {v16.4s},[x7],#16 // re-pre-load rndkey[0]
+ st1 {v2.16b},[x1],#16
+ eor v3.16b,v3.16b,v5.16b
+ mov w6,w5
+ st1 {v3.16b},[x1],#16
+ eor v19.16b,v19.16b,v17.16b
+ ld1 {v17.4s},[x7],#16 // re-pre-load rndkey[1]
+ st1 {v19.16b},[x1],#16
+ b.hs .Loop3x_ctr32
+
+ adds x2,x2,#3
+ b.eq .Lctr32_done
+ cmp x2,#1
+ mov x12,#16
+ csel x12,xzr,x12,eq
+
+.Lctr32_tail:
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v16.16b
+ aesmc v1.16b,v1.16b
+ ld1 {v16.4s},[x7],#16
+ subs w6,w6,#2
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v17.16b
+ aesmc v1.16b,v1.16b
+ ld1 {v17.4s},[x7],#16
+ b.gt .Lctr32_tail
+
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v16.16b
+ aesmc v1.16b,v1.16b
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v17.16b
+ aesmc v1.16b,v1.16b
+ ld1 {v2.16b},[x0],x12
+ aese v0.16b,v20.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v20.16b
+ aesmc v1.16b,v1.16b
+ ld1 {v3.16b},[x0]
+ aese v0.16b,v21.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v21.16b
+ aesmc v1.16b,v1.16b
+ eor v2.16b,v2.16b,v7.16b
+ aese v0.16b,v22.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v22.16b
+ aesmc v1.16b,v1.16b
+ eor v3.16b,v3.16b,v7.16b
+ aese v0.16b,v23.16b
+ aese v1.16b,v23.16b
+
+ cmp x2,#1
+ eor v2.16b,v2.16b,v0.16b
+ eor v3.16b,v3.16b,v1.16b
+ st1 {v2.16b},[x1],#16
+ b.eq .Lctr32_done
+ st1 {v3.16b},[x1]
+
+.Lctr32_done:
+ ldr x29,[sp],#16
+ ret
+.size aes_v8_ctr32_encrypt_blocks,.-aes_v8_ctr32_encrypt_blocks
+.globl aes_v8_xts_encrypt
+.type aes_v8_xts_encrypt,%function
+.align 5
+aes_v8_xts_encrypt:
+ cmp x2,#16
+ // Original input data size bigger than 16, jump to big size processing.
+ b.ne .Lxts_enc_big_size
+ // Encrypt the iv with key2, as the first XEX iv.
+ ldr w6,[x4,#240]
+ ld1 {v0.4s},[x4],#16
+ ld1 {v6.16b},[x5]
+ sub w6,w6,#2
+ ld1 {v1.4s},[x4],#16
+
+.Loop_enc_iv_enc:
+ aese v6.16b,v0.16b
+ aesmc v6.16b,v6.16b
+ ld1 {v0.4s},[x4],#16
+ subs w6,w6,#2
+ aese v6.16b,v1.16b
+ aesmc v6.16b,v6.16b
+ ld1 {v1.4s},[x4],#16
+ b.gt .Loop_enc_iv_enc
+
+ aese v6.16b,v0.16b
+ aesmc v6.16b,v6.16b
+ ld1 {v0.4s},[x4]
+ aese v6.16b,v1.16b
+ eor v6.16b,v6.16b,v0.16b
+
+ ld1 {v0.16b},[x0]
+ eor v0.16b,v6.16b,v0.16b
+
+ ldr w6,[x3,#240]
+ ld1 {v28.4s,v29.4s},[x3],#32 // load key schedule...
+
+ aese v0.16b,v28.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v16.4s,v17.4s},[x3],#32 // load key schedule...
+ aese v0.16b,v29.16b
+ aesmc v0.16b,v0.16b
+ subs w6,w6,#10 // if rounds==10, jump to aes-128-xts processing
+ b.eq .Lxts_128_enc
+.Lxts_enc_round_loop:
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v16.4s},[x3],#16 // load key schedule...
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v17.4s},[x3],#16 // load key schedule...
+ subs w6,w6,#2 // bias
+ b.gt .Lxts_enc_round_loop
+.Lxts_128_enc:
+ ld1 {v18.4s,v19.4s},[x3],#32 // load key schedule...
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v20.4s,v21.4s},[x3],#32 // load key schedule...
+ aese v0.16b,v18.16b
+ aesmc v0.16b,v0.16b
+ aese v0.16b,v19.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v22.4s,v23.4s},[x3],#32 // load key schedule...
+ aese v0.16b,v20.16b
+ aesmc v0.16b,v0.16b
+ aese v0.16b,v21.16b
+ aesmc v0.16b,v0.16b
+ ld1 {v7.4s},[x3]
+ aese v0.16b,v22.16b
+ aesmc v0.16b,v0.16b
+ aese v0.16b,v23.16b
+ eor v0.16b,v0.16b,v7.16b
+ eor v0.16b,v0.16b,v6.16b
+ st1 {v0.16b},[x1]
+ b .Lxts_enc_final_abort
+
+.align 4
+.Lxts_enc_big_size:
+ stp x19,x20,[sp,#-64]!
+ stp x21,x22,[sp,#48]
+ stp d8,d9,[sp,#32]
+ stp d10,d11,[sp,#16]
+
+ // tailcnt store the tail value of length%16.
+ and x21,x2,#0xf
+ and x2,x2,#-16
+ subs x2,x2,#16
+ mov x8,#16
+ b.lo .Lxts_abort
+ csel x8,xzr,x8,eq
+
+ // Firstly, encrypt the iv with key2, as the first iv of XEX.
+ ldr w6,[x4,#240]
+ ld1 {v0.4s},[x4],#16
+ ld1 {v6.16b},[x5]
+ sub w6,w6,#2
+ ld1 {v1.4s},[x4],#16
+
+.Loop_iv_enc:
+ aese v6.16b,v0.16b
+ aesmc v6.16b,v6.16b
+ ld1 {v0.4s},[x4],#16
+ subs w6,w6,#2
+ aese v6.16b,v1.16b
+ aesmc v6.16b,v6.16b
+ ld1 {v1.4s},[x4],#16
+ b.gt .Loop_iv_enc
+
+ aese v6.16b,v0.16b
+ aesmc v6.16b,v6.16b
+ ld1 {v0.4s},[x4]
+ aese v6.16b,v1.16b
+ eor v6.16b,v6.16b,v0.16b
+
+ // The iv for second block
+ // x9- iv(low), x10 - iv(high)
+ // the five ivs stored into, v6.16b,v8.16b,v9.16b,v10.16b,v11.16b
+ fmov x9,d6
+ fmov x10,v6.d[1]
+ mov w19,#0x87
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr#31
+ eor x9,x11,x9,lsl#1
+ fmov d8,x9
+ fmov v8.d[1],x10
+
+ ldr w5,[x3,#240] // next starting point
+ ld1 {v0.16b},[x0],x8
+
+ ld1 {v16.4s,v17.4s},[x3] // load key schedule...
+ sub w5,w5,#6
+ add x7,x3,x5,lsl#4 // pointer to last 7 round keys
+ sub w5,w5,#2
+ ld1 {v18.4s,v19.4s},[x7],#32
+ ld1 {v20.4s,v21.4s},[x7],#32
+ ld1 {v22.4s,v23.4s},[x7],#32
+ ld1 {v7.4s},[x7]
+
+ add x7,x3,#32
+ mov w6,w5
+
+ // Encryption
+.Lxts_enc:
+ ld1 {v24.16b},[x0],#16
+ subs x2,x2,#32 // bias
+ add w6,w5,#2
+ orr v3.16b,v0.16b,v0.16b
+ orr v1.16b,v0.16b,v0.16b
+ orr v28.16b,v0.16b,v0.16b
+ orr v27.16b,v24.16b,v24.16b
+ orr v29.16b,v24.16b,v24.16b
+ b.lo .Lxts_inner_enc_tail
+ eor v0.16b,v0.16b,v6.16b // before encryption, xor with iv
+ eor v24.16b,v24.16b,v8.16b
+
+ // The iv for third block
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr#31
+ eor x9,x11,x9,lsl#1
+ fmov d9,x9
+ fmov v9.d[1],x10
+
+
+ orr v1.16b,v24.16b,v24.16b
+ ld1 {v24.16b},[x0],#16
+ orr v2.16b,v0.16b,v0.16b
+ orr v3.16b,v1.16b,v1.16b
+ eor v27.16b,v24.16b,v9.16b // the third block
+ eor v24.16b,v24.16b,v9.16b
+ cmp x2,#32
+ b.lo .Lxts_outer_enc_tail
+
+ // The iv for fourth block
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr#31
+ eor x9,x11,x9,lsl#1
+ fmov d10,x9
+ fmov v10.d[1],x10
+
+ ld1 {v25.16b},[x0],#16
+ // The iv for fifth block
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr#31
+ eor x9,x11,x9,lsl#1
+ fmov d11,x9
+ fmov v11.d[1],x10
+
+ ld1 {v26.16b},[x0],#16
+ eor v25.16b,v25.16b,v10.16b // the fourth block
+ eor v26.16b,v26.16b,v11.16b
+ sub x2,x2,#32 // bias
+ mov w6,w5
+ b .Loop5x_xts_enc
+
+.align 4
+.Loop5x_xts_enc:
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v16.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v16.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v16.16b
+ aesmc v25.16b,v25.16b
+ aese v26.16b,v16.16b
+ aesmc v26.16b,v26.16b
+ ld1 {v16.4s},[x7],#16
+ subs w6,w6,#2
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v17.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v17.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v17.16b
+ aesmc v25.16b,v25.16b
+ aese v26.16b,v17.16b
+ aesmc v26.16b,v26.16b
+ ld1 {v17.4s},[x7],#16
+ b.gt .Loop5x_xts_enc
+
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v16.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v16.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v16.16b
+ aesmc v25.16b,v25.16b
+ aese v26.16b,v16.16b
+ aesmc v26.16b,v26.16b
+ subs x2,x2,#0x50 // because .Lxts_enc_tail4x
+
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v17.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v17.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v17.16b
+ aesmc v25.16b,v25.16b
+ aese v26.16b,v17.16b
+ aesmc v26.16b,v26.16b
+ csel x6,xzr,x2,gt // borrow x6, w6, "gt" is not typo
+ mov x7,x3
+
+ aese v0.16b,v18.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v18.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v18.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v18.16b
+ aesmc v25.16b,v25.16b
+ aese v26.16b,v18.16b
+ aesmc v26.16b,v26.16b
+ add x0,x0,x6 // x0 is adjusted in such way that
+ // at exit from the loop v1.16b-v26.16b
+ // are loaded with last "words"
+ add x6,x2,#0x60 // because .Lxts_enc_tail4x
+
+ aese v0.16b,v19.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v19.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v19.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v19.16b
+ aesmc v25.16b,v25.16b
+ aese v26.16b,v19.16b
+ aesmc v26.16b,v26.16b
+
+ aese v0.16b,v20.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v20.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v20.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v20.16b
+ aesmc v25.16b,v25.16b
+ aese v26.16b,v20.16b
+ aesmc v26.16b,v26.16b
+
+ aese v0.16b,v21.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v21.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v21.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v21.16b
+ aesmc v25.16b,v25.16b
+ aese v26.16b,v21.16b
+ aesmc v26.16b,v26.16b
+
+ aese v0.16b,v22.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v22.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v22.16b
+ aesmc v24.16b,v24.16b
+ aese v25.16b,v22.16b
+ aesmc v25.16b,v25.16b
+ aese v26.16b,v22.16b
+ aesmc v26.16b,v26.16b
+
+ eor v4.16b,v7.16b,v6.16b
+ aese v0.16b,v23.16b
+ // The iv for first block of one iteration
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr#31
+ eor x9,x11,x9,lsl#1
+ fmov d6,x9
+ fmov v6.d[1],x10
+ eor v5.16b,v7.16b,v8.16b
+ ld1 {v2.16b},[x0],#16
+ aese v1.16b,v23.16b
+ // The iv for second block
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr#31
+ eor x9,x11,x9,lsl#1
+ fmov d8,x9
+ fmov v8.d[1],x10
+ eor v17.16b,v7.16b,v9.16b
+ ld1 {v3.16b},[x0],#16
+ aese v24.16b,v23.16b
+ // The iv for third block
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr#31
+ eor x9,x11,x9,lsl#1
+ fmov d9,x9
+ fmov v9.d[1],x10
+ eor v30.16b,v7.16b,v10.16b
+ ld1 {v27.16b},[x0],#16
+ aese v25.16b,v23.16b
+ // The iv for fourth block
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr#31
+ eor x9,x11,x9,lsl#1
+ fmov d10,x9
+ fmov v10.d[1],x10
+ eor v31.16b,v7.16b,v11.16b
+ ld1 {v28.16b},[x0],#16
+ aese v26.16b,v23.16b
+
+ // The iv for fifth block
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr #31
+ eor x9,x11,x9,lsl #1
+ fmov d11,x9
+ fmov v11.d[1],x10
+
+ ld1 {v29.16b},[x0],#16
+ cbz x6,.Lxts_enc_tail4x
+ ld1 {v16.4s},[x7],#16 // re-pre-load rndkey[0]
+ eor v4.16b,v4.16b,v0.16b
+ eor v0.16b,v2.16b,v6.16b
+ eor v5.16b,v5.16b,v1.16b
+ eor v1.16b,v3.16b,v8.16b
+ eor v17.16b,v17.16b,v24.16b
+ eor v24.16b,v27.16b,v9.16b
+ eor v30.16b,v30.16b,v25.16b
+ eor v25.16b,v28.16b,v10.16b
+ eor v31.16b,v31.16b,v26.16b
+ st1 {v4.16b},[x1],#16
+ eor v26.16b,v29.16b,v11.16b
+ st1 {v5.16b},[x1],#16
+ mov w6,w5
+ st1 {v17.16b},[x1],#16
+ ld1 {v17.4s},[x7],#16 // re-pre-load rndkey[1]
+ st1 {v30.16b},[x1],#16
+ st1 {v31.16b},[x1],#16
+ b.hs .Loop5x_xts_enc
+
+
+ // If left 4 blocks, borrow the five block's processing.
+ cmn x2,#0x10
+ b.ne .Loop5x_enc_after
+ orr v11.16b,v10.16b,v10.16b
+ orr v10.16b,v9.16b,v9.16b
+ orr v9.16b,v8.16b,v8.16b
+ orr v8.16b,v6.16b,v6.16b
+ fmov x9,d11
+ fmov x10,v11.d[1]
+ eor v0.16b,v6.16b,v2.16b
+ eor v1.16b,v8.16b,v3.16b
+ eor v24.16b,v27.16b,v9.16b
+ eor v25.16b,v28.16b,v10.16b
+ eor v26.16b,v29.16b,v11.16b
+ b.eq .Loop5x_xts_enc
+
+.Loop5x_enc_after:
+ add x2,x2,#0x50
+ cbz x2,.Lxts_enc_done
+
+ add w6,w5,#2
+ subs x2,x2,#0x30
+ b.lo .Lxts_inner_enc_tail
+
+ eor v0.16b,v6.16b,v27.16b
+ eor v1.16b,v8.16b,v28.16b
+ eor v24.16b,v29.16b,v9.16b
+ b .Lxts_outer_enc_tail
+
+.align 4
+.Lxts_enc_tail4x:
+ add x0,x0,#16
+ eor v5.16b,v1.16b,v5.16b
+ st1 {v5.16b},[x1],#16
+ eor v17.16b,v24.16b,v17.16b
+ st1 {v17.16b},[x1],#16
+ eor v30.16b,v25.16b,v30.16b
+ eor v31.16b,v26.16b,v31.16b
+ st1 {v30.16b,v31.16b},[x1],#32
+
+ b .Lxts_enc_done
+.align 4
+.Lxts_outer_enc_tail:
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v16.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v16.16b
+ aesmc v24.16b,v24.16b
+ ld1 {v16.4s},[x7],#16
+ subs w6,w6,#2
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v17.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v17.16b
+ aesmc v24.16b,v24.16b
+ ld1 {v17.4s},[x7],#16
+ b.gt .Lxts_outer_enc_tail
+
+ aese v0.16b,v16.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v16.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v16.16b
+ aesmc v24.16b,v24.16b
+ eor v4.16b,v6.16b,v7.16b
+ subs x2,x2,#0x30
+ // The iv for first block
+ fmov x9,d9
+ fmov x10,v9.d[1]
+ //mov w19,#0x87
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr#31
+ eor x9,x11,x9,lsl#1
+ fmov d6,x9
+ fmov v6.d[1],x10
+ eor v5.16b,v8.16b,v7.16b
+ csel x6,x2,x6,lo // x6, w6, is zero at this point
+ aese v0.16b,v17.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v17.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v17.16b
+ aesmc v24.16b,v24.16b
+ eor v17.16b,v9.16b,v7.16b
+
+ add x6,x6,#0x20
+ add x0,x0,x6
+ mov x7,x3
+
+ aese v0.16b,v20.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v20.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v20.16b
+ aesmc v24.16b,v24.16b
+ aese v0.16b,v21.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v21.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v21.16b
+ aesmc v24.16b,v24.16b
+ aese v0.16b,v22.16b
+ aesmc v0.16b,v0.16b
+ aese v1.16b,v22.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v22.16b
+ aesmc v24.16b,v24.16b
+ aese v0.16b,v23.16b
+ aese v1.16b,v23.16b
+ aese v24.16b,v23.16b
+ ld1 {v27.16b},[x0],#16
+ add w6,w5,#2
+ ld1 {v16.4s},[x7],#16 // re-pre-load rndkey[0]
+ eor v4.16b,v4.16b,v0.16b
+ eor v5.16b,v5.16b,v1.16b
+ eor v24.16b,v24.16b,v17.16b
+ ld1 {v17.4s},[x7],#16 // re-pre-load rndkey[1]
+ st1 {v4.16b},[x1],#16
+ st1 {v5.16b},[x1],#16
+ st1 {v24.16b},[x1],#16
+ cmn x2,#0x30
+ b.eq .Lxts_enc_done
+.Lxts_encxor_one:
+ orr v28.16b,v3.16b,v3.16b
+ orr v29.16b,v27.16b,v27.16b
+ nop
+
+.Lxts_inner_enc_tail:
+ cmn x2,#0x10
+ eor v1.16b,v28.16b,v6.16b
+ eor v24.16b,v29.16b,v8.16b
+ b.eq .Lxts_enc_tail_loop
+ eor v24.16b,v29.16b,v6.16b
+.Lxts_enc_tail_loop:
+ aese v1.16b,v16.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v16.16b
+ aesmc v24.16b,v24.16b
+ ld1 {v16.4s},[x7],#16
+ subs w6,w6,#2
+ aese v1.16b,v17.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v17.16b
+ aesmc v24.16b,v24.16b
+ ld1 {v17.4s},[x7],#16
+ b.gt .Lxts_enc_tail_loop
+
+ aese v1.16b,v16.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v16.16b
+ aesmc v24.16b,v24.16b
+ aese v1.16b,v17.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v17.16b
+ aesmc v24.16b,v24.16b
+ aese v1.16b,v20.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v20.16b
+ aesmc v24.16b,v24.16b
+ cmn x2,#0x20
+ aese v1.16b,v21.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v21.16b
+ aesmc v24.16b,v24.16b
+ eor v5.16b,v6.16b,v7.16b
+ aese v1.16b,v22.16b
+ aesmc v1.16b,v1.16b
+ aese v24.16b,v22.16b
+ aesmc v24.16b,v24.16b
+ eor v17.16b,v8.16b,v7.16b
+ aese v1.16b,v23.16b
+ aese v24.16b,v23.16b
+ b.eq .Lxts_enc_one
+ eor v5.16b,v5.16b,v1.16b
+ st1 {v5.16b},[x1],#16
+ eor v17.16b,v17.16b,v24.16b
+ orr v6.16b,v8.16b,v8.16b
+ st1 {v17.16b},[x1],#16
+ fmov x9,d8
+ fmov x10,v8.d[1]
+ mov w19,#0x87
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr #31
+ eor x9,x11,x9,lsl #1
+ fmov d6,x9
+ fmov v6.d[1],x10
+ b .Lxts_enc_done
+
+.Lxts_enc_one:
+ eor v5.16b,v5.16b,v24.16b
+ orr v6.16b,v6.16b,v6.16b
+ st1 {v5.16b},[x1],#16
+ fmov x9,d6
+ fmov x10,v6.d[1]
+ mov w19,#0x87
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr #31
+ eor x9,x11,x9,lsl #1
+ fmov d6,x9
+ fmov v6.d[1],x10
+ b .Lxts_enc_done
+.align 5
+.Lxts_enc_done:
+ // Process the tail block with cipher stealing.
+ tst x21,#0xf
+ b.eq .Lxts_abort
+
+ mov x20,x0
+ mov x13,x1
+ sub x1,x1,#16
+.composite_enc_loop:
+ subs x21,x21,#1
+ ldrb w15,[x1,x21]
+ ldrb w14,[x20,x21]
+ strb w15,[x13,x21]
+ strb w14,[x1,x21]
+ b.gt .composite_enc_loop
+.Lxts_enc_load_done:
+ ld1 {v26.16b},[x1]
+ eor v26.16b,v26.16b,v6.16b
+
+ // Encrypt the composite block to get the last second encrypted text block
+ ldr w6,[x3,#240] // load key schedule...
+ ld1 {v0.4s},[x3],#16
+ sub w6,w6,#2
+ ld1 {v1.4s},[x3],#16 // load key schedule...
+.Loop_final_enc:
+ aese v26.16b,v0.16b
+ aesmc v26.16b,v26.16b
+ ld1 {v0.4s},[x3],#16
+ subs w6,w6,#2
+ aese v26.16b,v1.16b
+ aesmc v26.16b,v26.16b
+ ld1 {v1.4s},[x3],#16
+ b.gt .Loop_final_enc
+
+ aese v26.16b,v0.16b
+ aesmc v26.16b,v26.16b
+ ld1 {v0.4s},[x3]
+ aese v26.16b,v1.16b
+ eor v26.16b,v26.16b,v0.16b
+ eor v26.16b,v26.16b,v6.16b
+ st1 {v26.16b},[x1]
+
+.Lxts_abort:
+ ldp x21,x22,[sp,#48]
+ ldp d8,d9,[sp,#32]
+ ldp d10,d11,[sp,#16]
+ ldp x19,x20,[sp],#64
+.Lxts_enc_final_abort:
+ ret
+.size aes_v8_xts_encrypt,.-aes_v8_xts_encrypt
+.globl aes_v8_xts_decrypt
+.type aes_v8_xts_decrypt,%function
+.align 5
+aes_v8_xts_decrypt:
+ cmp x2,#16
+ // Original input data size bigger than 16, jump to big size processing.
+ b.ne .Lxts_dec_big_size
+ // Encrypt the iv with key2, as the first XEX iv.
+ ldr w6,[x4,#240]
+ ld1 {v0.4s},[x4],#16
+ ld1 {v6.16b},[x5]
+ sub w6,w6,#2
+ ld1 {v1.4s},[x4],#16
+
+.Loop_dec_small_iv_enc:
+ aese v6.16b,v0.16b
+ aesmc v6.16b,v6.16b
+ ld1 {v0.4s},[x4],#16
+ subs w6,w6,#2
+ aese v6.16b,v1.16b
+ aesmc v6.16b,v6.16b
+ ld1 {v1.4s},[x4],#16
+ b.gt .Loop_dec_small_iv_enc
+
+ aese v6.16b,v0.16b
+ aesmc v6.16b,v6.16b
+ ld1 {v0.4s},[x4]
+ aese v6.16b,v1.16b
+ eor v6.16b,v6.16b,v0.16b
+
+ ld1 {v0.16b},[x0]
+ eor v0.16b,v6.16b,v0.16b
+
+ ldr w6,[x3,#240]
+ ld1 {v28.4s,v29.4s},[x3],#32 // load key schedule...
+
+ aesd v0.16b,v28.16b
+ aesimc v0.16b,v0.16b
+ ld1 {v16.4s,v17.4s},[x3],#32 // load key schedule...
+ aesd v0.16b,v29.16b
+ aesimc v0.16b,v0.16b
+ subs w6,w6,#10 // bias
+ b.eq .Lxts_128_dec
+.Lxts_dec_round_loop:
+ aesd v0.16b,v16.16b
+ aesimc v0.16b,v0.16b
+ ld1 {v16.4s},[x3],#16 // load key schedule...
+ aesd v0.16b,v17.16b
+ aesimc v0.16b,v0.16b
+ ld1 {v17.4s},[x3],#16 // load key schedule...
+ subs w6,w6,#2 // bias
+ b.gt .Lxts_dec_round_loop
+.Lxts_128_dec:
+ ld1 {v18.4s,v19.4s},[x3],#32 // load key schedule...
+ aesd v0.16b,v16.16b
+ aesimc v0.16b,v0.16b
+ aesd v0.16b,v17.16b
+ aesimc v0.16b,v0.16b
+ ld1 {v20.4s,v21.4s},[x3],#32 // load key schedule...
+ aesd v0.16b,v18.16b
+ aesimc v0.16b,v0.16b
+ aesd v0.16b,v19.16b
+ aesimc v0.16b,v0.16b
+ ld1 {v22.4s,v23.4s},[x3],#32 // load key schedule...
+ aesd v0.16b,v20.16b
+ aesimc v0.16b,v0.16b
+ aesd v0.16b,v21.16b
+ aesimc v0.16b,v0.16b
+ ld1 {v7.4s},[x3]
+ aesd v0.16b,v22.16b
+ aesimc v0.16b,v0.16b
+ aesd v0.16b,v23.16b
+ eor v0.16b,v0.16b,v7.16b
+ eor v0.16b,v6.16b,v0.16b
+ st1 {v0.16b},[x1]
+ b .Lxts_dec_final_abort
+.Lxts_dec_big_size:
+ stp x19,x20,[sp,#-64]!
+ stp x21,x22,[sp,#48]
+ stp d8,d9,[sp,#32]
+ stp d10,d11,[sp,#16]
+
+ and x21,x2,#0xf
+ and x2,x2,#-16
+ subs x2,x2,#16
+ mov x8,#16
+ b.lo .Lxts_dec_abort
+
+ // Encrypt the iv with key2, as the first XEX iv
+ ldr w6,[x4,#240]
+ ld1 {v0.4s},[x4],#16
+ ld1 {v6.16b},[x5]
+ sub w6,w6,#2
+ ld1 {v1.4s},[x4],#16
+
+.Loop_dec_iv_enc:
+ aese v6.16b,v0.16b
+ aesmc v6.16b,v6.16b
+ ld1 {v0.4s},[x4],#16
+ subs w6,w6,#2
+ aese v6.16b,v1.16b
+ aesmc v6.16b,v6.16b
+ ld1 {v1.4s},[x4],#16
+ b.gt .Loop_dec_iv_enc
+
+ aese v6.16b,v0.16b
+ aesmc v6.16b,v6.16b
+ ld1 {v0.4s},[x4]
+ aese v6.16b,v1.16b
+ eor v6.16b,v6.16b,v0.16b
+
+ // The iv for second block
+ // x9- iv(low), x10 - iv(high)
+ // the five ivs stored into, v6.16b,v8.16b,v9.16b,v10.16b,v11.16b
+ fmov x9,d6
+ fmov x10,v6.d[1]
+ mov w19,#0x87
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr #31
+ eor x9,x11,x9,lsl #1
+ fmov d8,x9
+ fmov v8.d[1],x10
+
+ ldr w5,[x3,#240] // load rounds number
+
+ // The iv for third block
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr #31
+ eor x9,x11,x9,lsl #1
+ fmov d9,x9
+ fmov v9.d[1],x10
+
+ ld1 {v16.4s,v17.4s},[x3] // load key schedule...
+ sub w5,w5,#6
+ add x7,x3,x5,lsl#4 // pointer to last 7 round keys
+ sub w5,w5,#2
+ ld1 {v18.4s,v19.4s},[x7],#32 // load key schedule...
+ ld1 {v20.4s,v21.4s},[x7],#32
+ ld1 {v22.4s,v23.4s},[x7],#32
+ ld1 {v7.4s},[x7]
+
+ // The iv for fourth block
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr #31
+ eor x9,x11,x9,lsl #1
+ fmov d10,x9
+ fmov v10.d[1],x10
+
+ add x7,x3,#32
+ mov w6,w5
+ b .Lxts_dec
+
+ // Decryption
+.align 5
+.Lxts_dec:
+ tst x21,#0xf
+ b.eq .Lxts_dec_begin
+ subs x2,x2,#16
+ csel x8,xzr,x8,eq
+ ld1 {v0.16b},[x0],#16
+ b.lo .Lxts_done
+ sub x0,x0,#16
+.Lxts_dec_begin:
+ ld1 {v0.16b},[x0],x8
+ subs x2,x2,#32 // bias
+ add w6,w5,#2
+ orr v3.16b,v0.16b,v0.16b
+ orr v1.16b,v0.16b,v0.16b
+ orr v28.16b,v0.16b,v0.16b
+ ld1 {v24.16b},[x0],#16
+ orr v27.16b,v24.16b,v24.16b
+ orr v29.16b,v24.16b,v24.16b
+ b.lo .Lxts_inner_dec_tail
+ eor v0.16b,v0.16b,v6.16b // before decryt, xor with iv
+ eor v24.16b,v24.16b,v8.16b
+
+ orr v1.16b,v24.16b,v24.16b
+ ld1 {v24.16b},[x0],#16
+ orr v2.16b,v0.16b,v0.16b
+ orr v3.16b,v1.16b,v1.16b
+ eor v27.16b,v24.16b,v9.16b // third block xox with third iv
+ eor v24.16b,v24.16b,v9.16b
+ cmp x2,#32
+ b.lo .Lxts_outer_dec_tail
+
+ ld1 {v25.16b},[x0],#16
+
+ // The iv for fifth block
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr #31
+ eor x9,x11,x9,lsl #1
+ fmov d11,x9
+ fmov v11.d[1],x10
+
+ ld1 {v26.16b},[x0],#16
+ eor v25.16b,v25.16b,v10.16b // the fourth block
+ eor v26.16b,v26.16b,v11.16b
+ sub x2,x2,#32 // bias
+ mov w6,w5
+ b .Loop5x_xts_dec
+
+.align 4
+.Loop5x_xts_dec:
+ aesd v0.16b,v16.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v16.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v16.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v16.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v16.16b
+ aesimc v26.16b,v26.16b
+ ld1 {v16.4s},[x7],#16 // load key schedule...
+ subs w6,w6,#2
+ aesd v0.16b,v17.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v17.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v17.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v17.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v17.16b
+ aesimc v26.16b,v26.16b
+ ld1 {v17.4s},[x7],#16 // load key schedule...
+ b.gt .Loop5x_xts_dec
+
+ aesd v0.16b,v16.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v16.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v16.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v16.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v16.16b
+ aesimc v26.16b,v26.16b
+ subs x2,x2,#0x50 // because .Lxts_dec_tail4x
+
+ aesd v0.16b,v17.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v17.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v17.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v17.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v17.16b
+ aesimc v26.16b,v26.16b
+ csel x6,xzr,x2,gt // borrow x6, w6, "gt" is not typo
+ mov x7,x3
+
+ aesd v0.16b,v18.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v18.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v18.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v18.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v18.16b
+ aesimc v26.16b,v26.16b
+ add x0,x0,x6 // x0 is adjusted in such way that
+ // at exit from the loop v1.16b-v26.16b
+ // are loaded with last "words"
+ add x6,x2,#0x60 // because .Lxts_dec_tail4x
+
+ aesd v0.16b,v19.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v19.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v19.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v19.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v19.16b
+ aesimc v26.16b,v26.16b
+
+ aesd v0.16b,v20.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v20.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v20.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v20.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v20.16b
+ aesimc v26.16b,v26.16b
+
+ aesd v0.16b,v21.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v21.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v21.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v21.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v21.16b
+ aesimc v26.16b,v26.16b
+
+ aesd v0.16b,v22.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v22.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v22.16b
+ aesimc v24.16b,v24.16b
+ aesd v25.16b,v22.16b
+ aesimc v25.16b,v25.16b
+ aesd v26.16b,v22.16b
+ aesimc v26.16b,v26.16b
+
+ eor v4.16b,v7.16b,v6.16b
+ aesd v0.16b,v23.16b
+ // The iv for first block of next iteration.
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr #31
+ eor x9,x11,x9,lsl #1
+ fmov d6,x9
+ fmov v6.d[1],x10
+ eor v5.16b,v7.16b,v8.16b
+ ld1 {v2.16b},[x0],#16
+ aesd v1.16b,v23.16b
+ // The iv for second block
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr #31
+ eor x9,x11,x9,lsl #1
+ fmov d8,x9
+ fmov v8.d[1],x10
+ eor v17.16b,v7.16b,v9.16b
+ ld1 {v3.16b},[x0],#16
+ aesd v24.16b,v23.16b
+ // The iv for third block
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr #31
+ eor x9,x11,x9,lsl #1
+ fmov d9,x9
+ fmov v9.d[1],x10
+ eor v30.16b,v7.16b,v10.16b
+ ld1 {v27.16b},[x0],#16
+ aesd v25.16b,v23.16b
+ // The iv for fourth block
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr #31
+ eor x9,x11,x9,lsl #1
+ fmov d10,x9
+ fmov v10.d[1],x10
+ eor v31.16b,v7.16b,v11.16b
+ ld1 {v28.16b},[x0],#16
+ aesd v26.16b,v23.16b
+
+ // The iv for fifth block
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr #31
+ eor x9,x11,x9,lsl #1
+ fmov d11,x9
+ fmov v11.d[1],x10
+
+ ld1 {v29.16b},[x0],#16
+ cbz x6,.Lxts_dec_tail4x
+ ld1 {v16.4s},[x7],#16 // re-pre-load rndkey[0]
+ eor v4.16b,v4.16b,v0.16b
+ eor v0.16b,v2.16b,v6.16b
+ eor v5.16b,v5.16b,v1.16b
+ eor v1.16b,v3.16b,v8.16b
+ eor v17.16b,v17.16b,v24.16b
+ eor v24.16b,v27.16b,v9.16b
+ eor v30.16b,v30.16b,v25.16b
+ eor v25.16b,v28.16b,v10.16b
+ eor v31.16b,v31.16b,v26.16b
+ st1 {v4.16b},[x1],#16
+ eor v26.16b,v29.16b,v11.16b
+ st1 {v5.16b},[x1],#16
+ mov w6,w5
+ st1 {v17.16b},[x1],#16
+ ld1 {v17.4s},[x7],#16 // re-pre-load rndkey[1]
+ st1 {v30.16b},[x1],#16
+ st1 {v31.16b},[x1],#16
+ b.hs .Loop5x_xts_dec
+
+ cmn x2,#0x10
+ b.ne .Loop5x_dec_after
+ // If x2(x2) equal to -0x10, the left blocks is 4.
+ // After specially processing, utilize the five blocks processing again.
+ // It will use the following IVs: v6.16b,v6.16b,v8.16b,v9.16b,v10.16b.
+ orr v11.16b,v10.16b,v10.16b
+ orr v10.16b,v9.16b,v9.16b
+ orr v9.16b,v8.16b,v8.16b
+ orr v8.16b,v6.16b,v6.16b
+ fmov x9,d11
+ fmov x10,v11.d[1]
+ eor v0.16b,v6.16b,v2.16b
+ eor v1.16b,v8.16b,v3.16b
+ eor v24.16b,v27.16b,v9.16b
+ eor v25.16b,v28.16b,v10.16b
+ eor v26.16b,v29.16b,v11.16b
+ b.eq .Loop5x_xts_dec
+
+.Loop5x_dec_after:
+ add x2,x2,#0x50
+ cbz x2,.Lxts_done
+
+ add w6,w5,#2
+ subs x2,x2,#0x30
+ b.lo .Lxts_inner_dec_tail
+
+ eor v0.16b,v6.16b,v27.16b
+ eor v1.16b,v8.16b,v28.16b
+ eor v24.16b,v29.16b,v9.16b
+ b .Lxts_outer_dec_tail
+
+.align 4
+.Lxts_dec_tail4x:
+ add x0,x0,#16
+ tst x21,#0xf
+ eor v5.16b,v1.16b,v4.16b
+ st1 {v5.16b},[x1],#16
+ eor v17.16b,v24.16b,v17.16b
+ st1 {v17.16b},[x1],#16
+ eor v30.16b,v25.16b,v30.16b
+ eor v31.16b,v26.16b,v31.16b
+ st1 {v30.16b,v31.16b},[x1],#32
+
+ b.eq .Lxts_dec_abort
+ ld1 {v0.16b},[x0],#16
+ b .Lxts_done
+.align 4
+.Lxts_outer_dec_tail:
+ aesd v0.16b,v16.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v16.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v16.16b
+ aesimc v24.16b,v24.16b
+ ld1 {v16.4s},[x7],#16
+ subs w6,w6,#2
+ aesd v0.16b,v17.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v17.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v17.16b
+ aesimc v24.16b,v24.16b
+ ld1 {v17.4s},[x7],#16
+ b.gt .Lxts_outer_dec_tail
+
+ aesd v0.16b,v16.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v16.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v16.16b
+ aesimc v24.16b,v24.16b
+ eor v4.16b,v6.16b,v7.16b
+ subs x2,x2,#0x30
+ // The iv for first block
+ fmov x9,d9
+ fmov x10,v9.d[1]
+ mov w19,#0x87
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr #31
+ eor x9,x11,x9,lsl #1
+ fmov d6,x9
+ fmov v6.d[1],x10
+ eor v5.16b,v8.16b,v7.16b
+ csel x6,x2,x6,lo // x6, w6, is zero at this point
+ aesd v0.16b,v17.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v17.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v17.16b
+ aesimc v24.16b,v24.16b
+ eor v17.16b,v9.16b,v7.16b
+ // The iv for second block
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr #31
+ eor x9,x11,x9,lsl #1
+ fmov d8,x9
+ fmov v8.d[1],x10
+
+ add x6,x6,#0x20
+ add x0,x0,x6 // x0 is adjusted to the last data
+
+ mov x7,x3
+
+ // The iv for third block
+ extr x22,x10,x10,#32
+ extr x10,x10,x9,#63
+ and w11,w19,w22,asr #31
+ eor x9,x11,x9,lsl #1
+ fmov d9,x9
+ fmov v9.d[1],x10
+
+ aesd v0.16b,v20.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v20.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v20.16b
+ aesimc v24.16b,v24.16b
+ aesd v0.16b,v21.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v21.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v21.16b
+ aesimc v24.16b,v24.16b
+ aesd v0.16b,v22.16b
+ aesimc v0.16b,v0.16b
+ aesd v1.16b,v22.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v22.16b
+ aesimc v24.16b,v24.16b
+ ld1 {v27.16b},[x0],#16
+ aesd v0.16b,v23.16b
+ aesd v1.16b,v23.16b
+ aesd v24.16b,v23.16b
+ ld1 {v16.4s},[x7],#16 // re-pre-load rndkey[0]
+ add w6,w5,#2
+ eor v4.16b,v4.16b,v0.16b
+ eor v5.16b,v5.16b,v1.16b
+ eor v24.16b,v24.16b,v17.16b
+ ld1 {v17.4s},[x7],#16 // re-pre-load rndkey[1]
+ st1 {v4.16b},[x1],#16
+ st1 {v5.16b},[x1],#16
+ st1 {v24.16b},[x1],#16
+
+ cmn x2,#0x30
+ add x2,x2,#0x30
+ b.eq .Lxts_done
+ sub x2,x2,#0x30
+ orr v28.16b,v3.16b,v3.16b
+ orr v29.16b,v27.16b,v27.16b
+ nop
+
+.Lxts_inner_dec_tail:
+ // x2 == -0x10 means two blocks left.
+ cmn x2,#0x10
+ eor v1.16b,v28.16b,v6.16b
+ eor v24.16b,v29.16b,v8.16b
+ b.eq .Lxts_dec_tail_loop
+ eor v24.16b,v29.16b,v6.16b
+.Lxts_dec_tail_loop:
+ aesd v1.16b,v16.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v16.16b
+ aesimc v24.16b,v24.16b
+ ld1 {v16.4s},[x7],#16
+ subs w6,w6,#2
+ aesd v1.16b,v17.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v17.16b
+ aesimc v24.16b,v24.16b
+ ld1 {v17.4s},[x7],#16
+ b.gt .Lxts_dec_tail_loop
+
+ aesd v1.16b,v16.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v16.16b
+ aesimc v24.16b,v24.16b
+ aesd v1.16b,v17.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v17.16b
+ aesimc v24.16b,v24.16b
+ aesd v1.16b,v20.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v20.16b
+ aesimc v24.16b,v24.16b
+ cmn x2,#0x20
+ aesd v1.16b,v21.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v21.16b
+ aesimc v24.16b,v24.16b
+ eor v5.16b,v6.16b,v7.16b
+ aesd v1.16b,v22.16b
+ aesimc v1.16b,v1.16b
+ aesd v24.16b,v22.16b
+ aesimc v24.16b,v24.16b
+ eor v17.16b,v8.16b,v7.16b
+ aesd v1.16b,v23.16b
+ aesd v24.16b,v23.16b
+ b.eq .Lxts_dec_one
+ eor v5.16b,v5.16b,v1.16b
+ eor v17.16b,v17.16b,v24.16b
+ orr v6.16b,v9.16b,v9.16b
+ orr v8.16b,v10.16b,v10.16b
+ st1 {v5.16b},[x1],#16
+ st1 {v17.16b},[x1],#16
+ add x2,x2,#16
+ b .Lxts_done
+
+.Lxts_dec_one:
+ eor v5.16b,v5.16b,v24.16b
+ orr v6.16b,v8.16b,v8.16b
+ orr v8.16b,v9.16b,v9.16b
+ st1 {v5.16b},[x1],#16
+ add x2,x2,#32
+
+.Lxts_done:
+ tst x21,#0xf
+ b.eq .Lxts_dec_abort
+ // Processing the last two blocks with cipher stealing.
+ mov x7,x3
+ cbnz x2,.Lxts_dec_1st_done
+ ld1 {v0.16b},[x0],#16
+
+ // Decrypt the last secod block to get the last plain text block
+.Lxts_dec_1st_done:
+ eor v26.16b,v0.16b,v8.16b
+ ldr w6,[x3,#240]
+ ld1 {v0.4s},[x3],#16
+ sub w6,w6,#2
+ ld1 {v1.4s},[x3],#16
+.Loop_final_2nd_dec:
+ aesd v26.16b,v0.16b
+ aesimc v26.16b,v26.16b
+ ld1 {v0.4s},[x3],#16 // load key schedule...
+ subs w6,w6,#2
+ aesd v26.16b,v1.16b
+ aesimc v26.16b,v26.16b
+ ld1 {v1.4s},[x3],#16 // load key schedule...
+ b.gt .Loop_final_2nd_dec
+
+ aesd v26.16b,v0.16b
+ aesimc v26.16b,v26.16b
+ ld1 {v0.4s},[x3]
+ aesd v26.16b,v1.16b
+ eor v26.16b,v26.16b,v0.16b
+ eor v26.16b,v26.16b,v8.16b
+ st1 {v26.16b},[x1]
+
+ mov x20,x0
+ add x13,x1,#16
+
+ // Composite the tailcnt "16 byte not aligned block" into the last second plain blocks
+ // to get the last encrypted block.
+.composite_dec_loop:
+ subs x21,x21,#1
+ ldrb w15,[x1,x21]
+ ldrb w14,[x20,x21]
+ strb w15,[x13,x21]
+ strb w14,[x1,x21]
+ b.gt .composite_dec_loop
+.Lxts_dec_load_done:
+ ld1 {v26.16b},[x1]
+ eor v26.16b,v26.16b,v6.16b
+
+ // Decrypt the composite block to get the last second plain text block
+ ldr w6,[x7,#240]
+ ld1 {v0.4s},[x7],#16
+ sub w6,w6,#2
+ ld1 {v1.4s},[x7],#16
+.Loop_final_dec:
+ aesd v26.16b,v0.16b
+ aesimc v26.16b,v26.16b
+ ld1 {v0.4s},[x7],#16 // load key schedule...
+ subs w6,w6,#2
+ aesd v26.16b,v1.16b
+ aesimc v26.16b,v26.16b
+ ld1 {v1.4s},[x7],#16 // load key schedule...
+ b.gt .Loop_final_dec
+
+ aesd v26.16b,v0.16b
+ aesimc v26.16b,v26.16b
+ ld1 {v0.4s},[x7]
+ aesd v26.16b,v1.16b
+ eor v26.16b,v26.16b,v0.16b
+ eor v26.16b,v26.16b,v6.16b
+ st1 {v26.16b},[x1]
+
+.Lxts_dec_abort:
+ ldp x21,x22,[sp,#48]
+ ldp d8,d9,[sp,#32]
+ ldp d10,d11,[sp,#16]
+ ldp x19,x20,[sp],#64
+
+.Lxts_dec_final_abort:
+ ret
+.size aes_v8_xts_decrypt,.-aes_v8_xts_decrypt
+#endif
diff --git a/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/aes/vpaes-armv8.S b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/aes/vpaes-armv8.S
new file mode 100644
index 000000000000..229dad24d350
--- /dev/null
+++ b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/aes/vpaes-armv8.S
@@ -0,0 +1,1196 @@
+.text
+
+.type _vpaes_consts,%object
+.align 7 // totally strategic alignment
+_vpaes_consts:
+.Lk_mc_forward: // mc_forward
+.quad 0x0407060500030201, 0x0C0F0E0D080B0A09
+.quad 0x080B0A0904070605, 0x000302010C0F0E0D
+.quad 0x0C0F0E0D080B0A09, 0x0407060500030201
+.quad 0x000302010C0F0E0D, 0x080B0A0904070605
+.Lk_mc_backward: // mc_backward
+.quad 0x0605040702010003, 0x0E0D0C0F0A09080B
+.quad 0x020100030E0D0C0F, 0x0A09080B06050407
+.quad 0x0E0D0C0F0A09080B, 0x0605040702010003
+.quad 0x0A09080B06050407, 0x020100030E0D0C0F
+.Lk_sr: // sr
+.quad 0x0706050403020100, 0x0F0E0D0C0B0A0908
+.quad 0x030E09040F0A0500, 0x0B06010C07020D08
+.quad 0x0F060D040B020900, 0x070E050C030A0108
+.quad 0x0B0E0104070A0D00, 0x0306090C0F020508
+
+//
+// "Hot" constants
+//
+.Lk_inv: // inv, inva
+.quad 0x0E05060F0D080180, 0x040703090A0B0C02
+.quad 0x01040A060F0B0780, 0x030D0E0C02050809
+.Lk_ipt: // input transform (lo, hi)
+.quad 0xC2B2E8985A2A7000, 0xCABAE09052227808
+.quad 0x4C01307D317C4D00, 0xCD80B1FCB0FDCC81
+.Lk_sbo: // sbou, sbot
+.quad 0xD0D26D176FBDC700, 0x15AABF7AC502A878
+.quad 0xCFE474A55FBB6A00, 0x8E1E90D1412B35FA
+.Lk_sb1: // sb1u, sb1t
+.quad 0x3618D415FAE22300, 0x3BF7CCC10D2ED9EF
+.quad 0xB19BE18FCB503E00, 0xA5DF7A6E142AF544
+.Lk_sb2: // sb2u, sb2t
+.quad 0x69EB88400AE12900, 0xC2A163C8AB82234A
+.quad 0xE27A93C60B712400, 0x5EB7E955BC982FCD
+
+//
+// Decryption stuff
+//
+.Lk_dipt: // decryption input transform
+.quad 0x0F505B040B545F00, 0x154A411E114E451A
+.quad 0x86E383E660056500, 0x12771772F491F194
+.Lk_dsbo: // decryption sbox final output
+.quad 0x1387EA537EF94000, 0xC7AA6DB9D4943E2D
+.quad 0x12D7560F93441D00, 0xCA4B8159D8C58E9C
+.Lk_dsb9: // decryption sbox output *9*u, *9*t
+.quad 0x851C03539A86D600, 0xCAD51F504F994CC9
+.quad 0xC03B1789ECD74900, 0x725E2C9EB2FBA565
+.Lk_dsbd: // decryption sbox output *D*u, *D*t
+.quad 0x7D57CCDFE6B1A200, 0xF56E9B13882A4439
+.quad 0x3CE2FAF724C6CB00, 0x2931180D15DEEFD3
+.Lk_dsbb: // decryption sbox output *B*u, *B*t
+.quad 0xD022649296B44200, 0x602646F6B0F2D404
+.quad 0xC19498A6CD596700, 0xF3FF0C3E3255AA6B
+.Lk_dsbe: // decryption sbox output *E*u, *E*t
+.quad 0x46F2929626D4D000, 0x2242600464B4F6B0
+.quad 0x0C55A6CDFFAAC100, 0x9467F36B98593E32
+
+//
+// Key schedule constants
+//
+.Lk_dksd: // decryption key schedule: invskew x*D
+.quad 0xFEB91A5DA3E44700, 0x0740E3A45A1DBEF9
+.quad 0x41C277F4B5368300, 0x5FDC69EAAB289D1E
+.Lk_dksb: // decryption key schedule: invskew x*B
+.quad 0x9A4FCA1F8550D500, 0x03D653861CC94C99
+.quad 0x115BEDA7B6FC4A00, 0xD993256F7E3482C8
+.Lk_dkse: // decryption key schedule: invskew x*E + 0x63
+.quad 0xD5031CCA1FC9D600, 0x53859A4C994F5086
+.quad 0xA23196054FDC7BE8, 0xCD5EF96A20B31487
+.Lk_dks9: // decryption key schedule: invskew x*9
+.quad 0xB6116FC87ED9A700, 0x4AED933482255BFC
+.quad 0x4576516227143300, 0x8BB89FACE9DAFDCE
+
+.Lk_rcon: // rcon
+.quad 0x1F8391B9AF9DEEB6, 0x702A98084D7C7D81
+
+.Lk_opt: // output transform
+.quad 0xFF9F4929D6B66000, 0xF7974121DEBE6808
+.quad 0x01EDBD5150BCEC00, 0xE10D5DB1B05C0CE0
+.Lk_deskew: // deskew tables: inverts the sbox's "skew"
+.quad 0x07E4A34047A4E300, 0x1DFEB95A5DBEF91A
+.quad 0x5F36B5DC83EA6900, 0x2841C2ABF49D1E77
+
+.byte 86,101,99,116,111,114,32,80,101,114,109,117,116,97,116,105,111,110,32,65,69,83,32,102,111,114,32,65,82,77,118,56,44,32,77,105,107,101,32,72,97,109,98,117,114,103,32,40,83,116,97,110,102,111,114,100,32,85,110,105,118,101,114,115,105,116,121,41,0
+.align 2
+.size _vpaes_consts,.-_vpaes_consts
+.align 6
+//
+// _aes_preheat
+//
+// Fills register %r10 -> .aes_consts (so you can -fPIC)
+// and %xmm9-%xmm15 as specified below.
+//
+.type _vpaes_encrypt_preheat,%function
+.align 4
+_vpaes_encrypt_preheat:
+ adr x10, .Lk_inv
+ movi v17.16b, #0x0f
+ ld1 {v18.2d,v19.2d}, [x10],#32 // .Lk_inv
+ ld1 {v20.2d,v21.2d,v22.2d,v23.2d}, [x10],#64 // .Lk_ipt, .Lk_sbo
+ ld1 {v24.2d,v25.2d,v26.2d,v27.2d}, [x10] // .Lk_sb1, .Lk_sb2
+ ret
+.size _vpaes_encrypt_preheat,.-_vpaes_encrypt_preheat
+
+//
+// _aes_encrypt_core
+//
+// AES-encrypt %xmm0.
+//
+// Inputs:
+// %xmm0 = input
+// %xmm9-%xmm15 as in _vpaes_preheat
+// (%rdx) = scheduled keys
+//
+// Output in %xmm0
+// Clobbers %xmm1-%xmm5, %r9, %r10, %r11, %rax
+// Preserves %xmm6 - %xmm8 so you get some local vectors
+//
+//
+.type _vpaes_encrypt_core,%function
+.align 4
+_vpaes_encrypt_core:
+ mov x9, x2
+ ldr w8, [x2,#240] // pull rounds
+ adr x11, .Lk_mc_forward+16
+ // vmovdqa .Lk_ipt(%rip), %xmm2 # iptlo
+ ld1 {v16.2d}, [x9], #16 // vmovdqu (%r9), %xmm5 # round0 key
+ and v1.16b, v7.16b, v17.16b // vpand %xmm9, %xmm0, %xmm1
+ ushr v0.16b, v7.16b, #4 // vpsrlb $4, %xmm0, %xmm0
+ tbl v1.16b, {v20.16b}, v1.16b // vpshufb %xmm1, %xmm2, %xmm1
+ // vmovdqa .Lk_ipt+16(%rip), %xmm3 # ipthi
+ tbl v2.16b, {v21.16b}, v0.16b // vpshufb %xmm0, %xmm3, %xmm2
+ eor v0.16b, v1.16b, v16.16b // vpxor %xmm5, %xmm1, %xmm0
+ eor v0.16b, v0.16b, v2.16b // vpxor %xmm2, %xmm0, %xmm0
+ b .Lenc_entry
+
+.align 4
+.Lenc_loop:
+ // middle of middle round
+ add x10, x11, #0x40
+ tbl v4.16b, {v25.16b}, v2.16b // vpshufb %xmm2, %xmm13, %xmm4 # 4 = sb1u
+ ld1 {v1.2d}, [x11], #16 // vmovdqa -0x40(%r11,%r10), %xmm1 # .Lk_mc_forward[]
+ tbl v0.16b, {v24.16b}, v3.16b // vpshufb %xmm3, %xmm12, %xmm0 # 0 = sb1t
+ eor v4.16b, v4.16b, v16.16b // vpxor %xmm5, %xmm4, %xmm4 # 4 = sb1u + k
+ tbl v5.16b, {v27.16b}, v2.16b // vpshufb %xmm2, %xmm15, %xmm5 # 4 = sb2u
+ eor v0.16b, v0.16b, v4.16b // vpxor %xmm4, %xmm0, %xmm0 # 0 = A
+ tbl v2.16b, {v26.16b}, v3.16b // vpshufb %xmm3, %xmm14, %xmm2 # 2 = sb2t
+ ld1 {v4.2d}, [x10] // vmovdqa (%r11,%r10), %xmm4 # .Lk_mc_backward[]
+ tbl v3.16b, {v0.16b}, v1.16b // vpshufb %xmm1, %xmm0, %xmm3 # 0 = B
+ eor v2.16b, v2.16b, v5.16b // vpxor %xmm5, %xmm2, %xmm2 # 2 = 2A
+ tbl v0.16b, {v0.16b}, v4.16b // vpshufb %xmm4, %xmm0, %xmm0 # 3 = D
+ eor v3.16b, v3.16b, v2.16b // vpxor %xmm2, %xmm3, %xmm3 # 0 = 2A+B
+ tbl v4.16b, {v3.16b}, v1.16b // vpshufb %xmm1, %xmm3, %xmm4 # 0 = 2B+C
+ eor v0.16b, v0.16b, v3.16b // vpxor %xmm3, %xmm0, %xmm0 # 3 = 2A+B+D
+ and x11, x11, #~(1<<6) // and $0x30, %r11 # ... mod 4
+ eor v0.16b, v0.16b, v4.16b // vpxor %xmm4, %xmm0, %xmm0 # 0 = 2A+3B+C+D
+ sub w8, w8, #1 // nr--
+
+.Lenc_entry:
+ // top of round
+ and v1.16b, v0.16b, v17.16b // vpand %xmm0, %xmm9, %xmm1 # 0 = k
+ ushr v0.16b, v0.16b, #4 // vpsrlb $4, %xmm0, %xmm0 # 1 = i
+ tbl v5.16b, {v19.16b}, v1.16b // vpshufb %xmm1, %xmm11, %xmm5 # 2 = a/k
+ eor v1.16b, v1.16b, v0.16b // vpxor %xmm0, %xmm1, %xmm1 # 0 = j
+ tbl v3.16b, {v18.16b}, v0.16b // vpshufb %xmm0, %xmm10, %xmm3 # 3 = 1/i
+ tbl v4.16b, {v18.16b}, v1.16b // vpshufb %xmm1, %xmm10, %xmm4 # 4 = 1/j
+ eor v3.16b, v3.16b, v5.16b // vpxor %xmm5, %xmm3, %xmm3 # 3 = iak = 1/i + a/k
+ eor v4.16b, v4.16b, v5.16b // vpxor %xmm5, %xmm4, %xmm4 # 4 = jak = 1/j + a/k
+ tbl v2.16b, {v18.16b}, v3.16b // vpshufb %xmm3, %xmm10, %xmm2 # 2 = 1/iak
+ tbl v3.16b, {v18.16b}, v4.16b // vpshufb %xmm4, %xmm10, %xmm3 # 3 = 1/jak
+ eor v2.16b, v2.16b, v1.16b // vpxor %xmm1, %xmm2, %xmm2 # 2 = io
+ eor v3.16b, v3.16b, v0.16b // vpxor %xmm0, %xmm3, %xmm3 # 3 = jo
+ ld1 {v16.2d}, [x9],#16 // vmovdqu (%r9), %xmm5
+ cbnz w8, .Lenc_loop
+
+ // middle of last round
+ add x10, x11, #0x80
+ // vmovdqa -0x60(%r10), %xmm4 # 3 : sbou .Lk_sbo
+ // vmovdqa -0x50(%r10), %xmm0 # 0 : sbot .Lk_sbo+16
+ tbl v4.16b, {v22.16b}, v2.16b // vpshufb %xmm2, %xmm4, %xmm4 # 4 = sbou
+ ld1 {v1.2d}, [x10] // vmovdqa 0x40(%r11,%r10), %xmm1 # .Lk_sr[]
+ tbl v0.16b, {v23.16b}, v3.16b // vpshufb %xmm3, %xmm0, %xmm0 # 0 = sb1t
+ eor v4.16b, v4.16b, v16.16b // vpxor %xmm5, %xmm4, %xmm4 # 4 = sb1u + k
+ eor v0.16b, v0.16b, v4.16b // vpxor %xmm4, %xmm0, %xmm0 # 0 = A
+ tbl v0.16b, {v0.16b}, v1.16b // vpshufb %xmm1, %xmm0, %xmm0
+ ret
+.size _vpaes_encrypt_core,.-_vpaes_encrypt_core
+
+.globl vpaes_encrypt
+.type vpaes_encrypt,%function
+.align 4
+vpaes_encrypt:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+
+ ld1 {v7.16b}, [x0]
+ bl _vpaes_encrypt_preheat
+ bl _vpaes_encrypt_core
+ st1 {v0.16b}, [x1]
+
+ ldp x29,x30,[sp],#16
+.inst 0xd50323bf // autiasp
+ ret
+.size vpaes_encrypt,.-vpaes_encrypt
+
+.type _vpaes_encrypt_2x,%function
+.align 4
+_vpaes_encrypt_2x:
+ mov x9, x2
+ ldr w8, [x2,#240] // pull rounds
+ adr x11, .Lk_mc_forward+16
+ // vmovdqa .Lk_ipt(%rip), %xmm2 # iptlo
+ ld1 {v16.2d}, [x9], #16 // vmovdqu (%r9), %xmm5 # round0 key
+ and v1.16b, v14.16b, v17.16b // vpand %xmm9, %xmm0, %xmm1
+ ushr v0.16b, v14.16b, #4 // vpsrlb $4, %xmm0, %xmm0
+ and v9.16b, v15.16b, v17.16b
+ ushr v8.16b, v15.16b, #4
+ tbl v1.16b, {v20.16b}, v1.16b // vpshufb %xmm1, %xmm2, %xmm1
+ tbl v9.16b, {v20.16b}, v9.16b
+ // vmovdqa .Lk_ipt+16(%rip), %xmm3 # ipthi
+ tbl v2.16b, {v21.16b}, v0.16b // vpshufb %xmm0, %xmm3, %xmm2
+ tbl v10.16b, {v21.16b}, v8.16b
+ eor v0.16b, v1.16b, v16.16b // vpxor %xmm5, %xmm1, %xmm0
+ eor v8.16b, v9.16b, v16.16b
+ eor v0.16b, v0.16b, v2.16b // vpxor %xmm2, %xmm0, %xmm0
+ eor v8.16b, v8.16b, v10.16b
+ b .Lenc_2x_entry
+
+.align 4
+.Lenc_2x_loop:
+ // middle of middle round
+ add x10, x11, #0x40
+ tbl v4.16b, {v25.16b}, v2.16b // vpshufb %xmm2, %xmm13, %xmm4 # 4 = sb1u
+ tbl v12.16b, {v25.16b}, v10.16b
+ ld1 {v1.2d}, [x11], #16 // vmovdqa -0x40(%r11,%r10), %xmm1 # .Lk_mc_forward[]
+ tbl v0.16b, {v24.16b}, v3.16b // vpshufb %xmm3, %xmm12, %xmm0 # 0 = sb1t
+ tbl v8.16b, {v24.16b}, v11.16b
+ eor v4.16b, v4.16b, v16.16b // vpxor %xmm5, %xmm4, %xmm4 # 4 = sb1u + k
+ eor v12.16b, v12.16b, v16.16b
+ tbl v5.16b, {v27.16b}, v2.16b // vpshufb %xmm2, %xmm15, %xmm5 # 4 = sb2u
+ tbl v13.16b, {v27.16b}, v10.16b
+ eor v0.16b, v0.16b, v4.16b // vpxor %xmm4, %xmm0, %xmm0 # 0 = A
+ eor v8.16b, v8.16b, v12.16b
+ tbl v2.16b, {v26.16b}, v3.16b // vpshufb %xmm3, %xmm14, %xmm2 # 2 = sb2t
+ tbl v10.16b, {v26.16b}, v11.16b
+ ld1 {v4.2d}, [x10] // vmovdqa (%r11,%r10), %xmm4 # .Lk_mc_backward[]
+ tbl v3.16b, {v0.16b}, v1.16b // vpshufb %xmm1, %xmm0, %xmm3 # 0 = B
+ tbl v11.16b, {v8.16b}, v1.16b
+ eor v2.16b, v2.16b, v5.16b // vpxor %xmm5, %xmm2, %xmm2 # 2 = 2A
+ eor v10.16b, v10.16b, v13.16b
+ tbl v0.16b, {v0.16b}, v4.16b // vpshufb %xmm4, %xmm0, %xmm0 # 3 = D
+ tbl v8.16b, {v8.16b}, v4.16b
+ eor v3.16b, v3.16b, v2.16b // vpxor %xmm2, %xmm3, %xmm3 # 0 = 2A+B
+ eor v11.16b, v11.16b, v10.16b
+ tbl v4.16b, {v3.16b}, v1.16b // vpshufb %xmm1, %xmm3, %xmm4 # 0 = 2B+C
+ tbl v12.16b, {v11.16b},v1.16b
+ eor v0.16b, v0.16b, v3.16b // vpxor %xmm3, %xmm0, %xmm0 # 3 = 2A+B+D
+ eor v8.16b, v8.16b, v11.16b
+ and x11, x11, #~(1<<6) // and $0x30, %r11 # ... mod 4
+ eor v0.16b, v0.16b, v4.16b // vpxor %xmm4, %xmm0, %xmm0 # 0 = 2A+3B+C+D
+ eor v8.16b, v8.16b, v12.16b
+ sub w8, w8, #1 // nr--
+
+.Lenc_2x_entry:
+ // top of round
+ and v1.16b, v0.16b, v17.16b // vpand %xmm0, %xmm9, %xmm1 # 0 = k
+ ushr v0.16b, v0.16b, #4 // vpsrlb $4, %xmm0, %xmm0 # 1 = i
+ and v9.16b, v8.16b, v17.16b
+ ushr v8.16b, v8.16b, #4
+ tbl v5.16b, {v19.16b},v1.16b // vpshufb %xmm1, %xmm11, %xmm5 # 2 = a/k
+ tbl v13.16b, {v19.16b},v9.16b
+ eor v1.16b, v1.16b, v0.16b // vpxor %xmm0, %xmm1, %xmm1 # 0 = j
+ eor v9.16b, v9.16b, v8.16b
+ tbl v3.16b, {v18.16b},v0.16b // vpshufb %xmm0, %xmm10, %xmm3 # 3 = 1/i
+ tbl v11.16b, {v18.16b},v8.16b
+ tbl v4.16b, {v18.16b},v1.16b // vpshufb %xmm1, %xmm10, %xmm4 # 4 = 1/j
+ tbl v12.16b, {v18.16b},v9.16b
+ eor v3.16b, v3.16b, v5.16b // vpxor %xmm5, %xmm3, %xmm3 # 3 = iak = 1/i + a/k
+ eor v11.16b, v11.16b, v13.16b
+ eor v4.16b, v4.16b, v5.16b // vpxor %xmm5, %xmm4, %xmm4 # 4 = jak = 1/j + a/k
+ eor v12.16b, v12.16b, v13.16b
+ tbl v2.16b, {v18.16b},v3.16b // vpshufb %xmm3, %xmm10, %xmm2 # 2 = 1/iak
+ tbl v10.16b, {v18.16b},v11.16b
+ tbl v3.16b, {v18.16b},v4.16b // vpshufb %xmm4, %xmm10, %xmm3 # 3 = 1/jak
+ tbl v11.16b, {v18.16b},v12.16b
+ eor v2.16b, v2.16b, v1.16b // vpxor %xmm1, %xmm2, %xmm2 # 2 = io
+ eor v10.16b, v10.16b, v9.16b
+ eor v3.16b, v3.16b, v0.16b // vpxor %xmm0, %xmm3, %xmm3 # 3 = jo
+ eor v11.16b, v11.16b, v8.16b
+ ld1 {v16.2d}, [x9],#16 // vmovdqu (%r9), %xmm5
+ cbnz w8, .Lenc_2x_loop
+
+ // middle of last round
+ add x10, x11, #0x80
+ // vmovdqa -0x60(%r10), %xmm4 # 3 : sbou .Lk_sbo
+ // vmovdqa -0x50(%r10), %xmm0 # 0 : sbot .Lk_sbo+16
+ tbl v4.16b, {v22.16b}, v2.16b // vpshufb %xmm2, %xmm4, %xmm4 # 4 = sbou
+ tbl v12.16b, {v22.16b}, v10.16b
+ ld1 {v1.2d}, [x10] // vmovdqa 0x40(%r11,%r10), %xmm1 # .Lk_sr[]
+ tbl v0.16b, {v23.16b}, v3.16b // vpshufb %xmm3, %xmm0, %xmm0 # 0 = sb1t
+ tbl v8.16b, {v23.16b}, v11.16b
+ eor v4.16b, v4.16b, v16.16b // vpxor %xmm5, %xmm4, %xmm4 # 4 = sb1u + k
+ eor v12.16b, v12.16b, v16.16b
+ eor v0.16b, v0.16b, v4.16b // vpxor %xmm4, %xmm0, %xmm0 # 0 = A
+ eor v8.16b, v8.16b, v12.16b
+ tbl v0.16b, {v0.16b},v1.16b // vpshufb %xmm1, %xmm0, %xmm0
+ tbl v1.16b, {v8.16b},v1.16b
+ ret
+.size _vpaes_encrypt_2x,.-_vpaes_encrypt_2x
+
+.type _vpaes_decrypt_preheat,%function
+.align 4
+_vpaes_decrypt_preheat:
+ adr x10, .Lk_inv
+ movi v17.16b, #0x0f
+ adr x11, .Lk_dipt
+ ld1 {v18.2d,v19.2d}, [x10],#32 // .Lk_inv
+ ld1 {v20.2d,v21.2d,v22.2d,v23.2d}, [x11],#64 // .Lk_dipt, .Lk_dsbo
+ ld1 {v24.2d,v25.2d,v26.2d,v27.2d}, [x11],#64 // .Lk_dsb9, .Lk_dsbd
+ ld1 {v28.2d,v29.2d,v30.2d,v31.2d}, [x11] // .Lk_dsbb, .Lk_dsbe
+ ret
+.size _vpaes_decrypt_preheat,.-_vpaes_decrypt_preheat
+
+//
+// Decryption core
+//
+// Same API as encryption core.
+//
+.type _vpaes_decrypt_core,%function
+.align 4
+_vpaes_decrypt_core:
+ mov x9, x2
+ ldr w8, [x2,#240] // pull rounds
+
+ // vmovdqa .Lk_dipt(%rip), %xmm2 # iptlo
+ lsl x11, x8, #4 // mov %rax, %r11; shl $4, %r11
+ eor x11, x11, #0x30 // xor $0x30, %r11
+ adr x10, .Lk_sr
+ and x11, x11, #0x30 // and $0x30, %r11
+ add x11, x11, x10
+ adr x10, .Lk_mc_forward+48
+
+ ld1 {v16.2d}, [x9],#16 // vmovdqu (%r9), %xmm4 # round0 key
+ and v1.16b, v7.16b, v17.16b // vpand %xmm9, %xmm0, %xmm1
+ ushr v0.16b, v7.16b, #4 // vpsrlb $4, %xmm0, %xmm0
+ tbl v2.16b, {v20.16b}, v1.16b // vpshufb %xmm1, %xmm2, %xmm2
+ ld1 {v5.2d}, [x10] // vmovdqa .Lk_mc_forward+48(%rip), %xmm5
+ // vmovdqa .Lk_dipt+16(%rip), %xmm1 # ipthi
+ tbl v0.16b, {v21.16b}, v0.16b // vpshufb %xmm0, %xmm1, %xmm0
+ eor v2.16b, v2.16b, v16.16b // vpxor %xmm4, %xmm2, %xmm2
+ eor v0.16b, v0.16b, v2.16b // vpxor %xmm2, %xmm0, %xmm0
+ b .Ldec_entry
+
+.align 4
+.Ldec_loop:
+//
+// Inverse mix columns
+//
+ // vmovdqa -0x20(%r10),%xmm4 # 4 : sb9u
+ // vmovdqa -0x10(%r10),%xmm1 # 0 : sb9t
+ tbl v4.16b, {v24.16b}, v2.16b // vpshufb %xmm2, %xmm4, %xmm4 # 4 = sb9u
+ tbl v1.16b, {v25.16b}, v3.16b // vpshufb %xmm3, %xmm1, %xmm1 # 0 = sb9t
+ eor v0.16b, v4.16b, v16.16b // vpxor %xmm4, %xmm0, %xmm0
+ // vmovdqa 0x00(%r10),%xmm4 # 4 : sbdu
+ eor v0.16b, v0.16b, v1.16b // vpxor %xmm1, %xmm0, %xmm0 # 0 = ch
+ // vmovdqa 0x10(%r10),%xmm1 # 0 : sbdt
+
+ tbl v4.16b, {v26.16b}, v2.16b // vpshufb %xmm2, %xmm4, %xmm4 # 4 = sbdu
+ tbl v0.16b, {v0.16b}, v5.16b // vpshufb %xmm5, %xmm0, %xmm0 # MC ch
+ tbl v1.16b, {v27.16b}, v3.16b // vpshufb %xmm3, %xmm1, %xmm1 # 0 = sbdt
+ eor v0.16b, v0.16b, v4.16b // vpxor %xmm4, %xmm0, %xmm0 # 4 = ch
+ // vmovdqa 0x20(%r10), %xmm4 # 4 : sbbu
+ eor v0.16b, v0.16b, v1.16b // vpxor %xmm1, %xmm0, %xmm0 # 0 = ch
+ // vmovdqa 0x30(%r10), %xmm1 # 0 : sbbt
+
+ tbl v4.16b, {v28.16b}, v2.16b // vpshufb %xmm2, %xmm4, %xmm4 # 4 = sbbu
+ tbl v0.16b, {v0.16b}, v5.16b // vpshufb %xmm5, %xmm0, %xmm0 # MC ch
+ tbl v1.16b, {v29.16b}, v3.16b // vpshufb %xmm3, %xmm1, %xmm1 # 0 = sbbt
+ eor v0.16b, v0.16b, v4.16b // vpxor %xmm4, %xmm0, %xmm0 # 4 = ch
+ // vmovdqa 0x40(%r10), %xmm4 # 4 : sbeu
+ eor v0.16b, v0.16b, v1.16b // vpxor %xmm1, %xmm0, %xmm0 # 0 = ch
+ // vmovdqa 0x50(%r10), %xmm1 # 0 : sbet
+
+ tbl v4.16b, {v30.16b}, v2.16b // vpshufb %xmm2, %xmm4, %xmm4 # 4 = sbeu
+ tbl v0.16b, {v0.16b}, v5.16b // vpshufb %xmm5, %xmm0, %xmm0 # MC ch
+ tbl v1.16b, {v31.16b}, v3.16b // vpshufb %xmm3, %xmm1, %xmm1 # 0 = sbet
+ eor v0.16b, v0.16b, v4.16b // vpxor %xmm4, %xmm0, %xmm0 # 4 = ch
+ ext v5.16b, v5.16b, v5.16b, #12 // vpalignr $12, %xmm5, %xmm5, %xmm5
+ eor v0.16b, v0.16b, v1.16b // vpxor %xmm1, %xmm0, %xmm0 # 0 = ch
+ sub w8, w8, #1 // sub $1,%rax # nr--
+
+.Ldec_entry:
+ // top of round
+ and v1.16b, v0.16b, v17.16b // vpand %xmm9, %xmm0, %xmm1 # 0 = k
+ ushr v0.16b, v0.16b, #4 // vpsrlb $4, %xmm0, %xmm0 # 1 = i
+ tbl v2.16b, {v19.16b}, v1.16b // vpshufb %xmm1, %xmm11, %xmm2 # 2 = a/k
+ eor v1.16b, v1.16b, v0.16b // vpxor %xmm0, %xmm1, %xmm1 # 0 = j
+ tbl v3.16b, {v18.16b}, v0.16b // vpshufb %xmm0, %xmm10, %xmm3 # 3 = 1/i
+ tbl v4.16b, {v18.16b}, v1.16b // vpshufb %xmm1, %xmm10, %xmm4 # 4 = 1/j
+ eor v3.16b, v3.16b, v2.16b // vpxor %xmm2, %xmm3, %xmm3 # 3 = iak = 1/i + a/k
+ eor v4.16b, v4.16b, v2.16b // vpxor %xmm2, %xmm4, %xmm4 # 4 = jak = 1/j + a/k
+ tbl v2.16b, {v18.16b}, v3.16b // vpshufb %xmm3, %xmm10, %xmm2 # 2 = 1/iak
+ tbl v3.16b, {v18.16b}, v4.16b // vpshufb %xmm4, %xmm10, %xmm3 # 3 = 1/jak
+ eor v2.16b, v2.16b, v1.16b // vpxor %xmm1, %xmm2, %xmm2 # 2 = io
+ eor v3.16b, v3.16b, v0.16b // vpxor %xmm0, %xmm3, %xmm3 # 3 = jo
+ ld1 {v16.2d}, [x9],#16 // vmovdqu (%r9), %xmm0
+ cbnz w8, .Ldec_loop
+
+ // middle of last round
+ // vmovdqa 0x60(%r10), %xmm4 # 3 : sbou
+ tbl v4.16b, {v22.16b}, v2.16b // vpshufb %xmm2, %xmm4, %xmm4 # 4 = sbou
+ // vmovdqa 0x70(%r10), %xmm1 # 0 : sbot
+ ld1 {v2.2d}, [x11] // vmovdqa -0x160(%r11), %xmm2 # .Lk_sr-.Lk_dsbd=-0x160
+ tbl v1.16b, {v23.16b}, v3.16b // vpshufb %xmm3, %xmm1, %xmm1 # 0 = sb1t
+ eor v4.16b, v4.16b, v16.16b // vpxor %xmm0, %xmm4, %xmm4 # 4 = sb1u + k
+ eor v0.16b, v1.16b, v4.16b // vpxor %xmm4, %xmm1, %xmm0 # 0 = A
+ tbl v0.16b, {v0.16b}, v2.16b // vpshufb %xmm2, %xmm0, %xmm0
+ ret
+.size _vpaes_decrypt_core,.-_vpaes_decrypt_core
+
+.globl vpaes_decrypt
+.type vpaes_decrypt,%function
+.align 4
+vpaes_decrypt:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+
+ ld1 {v7.16b}, [x0]
+ bl _vpaes_decrypt_preheat
+ bl _vpaes_decrypt_core
+ st1 {v0.16b}, [x1]
+
+ ldp x29,x30,[sp],#16
+.inst 0xd50323bf // autiasp
+ ret
+.size vpaes_decrypt,.-vpaes_decrypt
+
+// v14-v15 input, v0-v1 output
+.type _vpaes_decrypt_2x,%function
+.align 4
+_vpaes_decrypt_2x:
+ mov x9, x2
+ ldr w8, [x2,#240] // pull rounds
+
+ // vmovdqa .Lk_dipt(%rip), %xmm2 # iptlo
+ lsl x11, x8, #4 // mov %rax, %r11; shl $4, %r11
+ eor x11, x11, #0x30 // xor $0x30, %r11
+ adr x10, .Lk_sr
+ and x11, x11, #0x30 // and $0x30, %r11
+ add x11, x11, x10
+ adr x10, .Lk_mc_forward+48
+
+ ld1 {v16.2d}, [x9],#16 // vmovdqu (%r9), %xmm4 # round0 key
+ and v1.16b, v14.16b, v17.16b // vpand %xmm9, %xmm0, %xmm1
+ ushr v0.16b, v14.16b, #4 // vpsrlb $4, %xmm0, %xmm0
+ and v9.16b, v15.16b, v17.16b
+ ushr v8.16b, v15.16b, #4
+ tbl v2.16b, {v20.16b},v1.16b // vpshufb %xmm1, %xmm2, %xmm2
+ tbl v10.16b, {v20.16b},v9.16b
+ ld1 {v5.2d}, [x10] // vmovdqa .Lk_mc_forward+48(%rip), %xmm5
+ // vmovdqa .Lk_dipt+16(%rip), %xmm1 # ipthi
+ tbl v0.16b, {v21.16b},v0.16b // vpshufb %xmm0, %xmm1, %xmm0
+ tbl v8.16b, {v21.16b},v8.16b
+ eor v2.16b, v2.16b, v16.16b // vpxor %xmm4, %xmm2, %xmm2
+ eor v10.16b, v10.16b, v16.16b
+ eor v0.16b, v0.16b, v2.16b // vpxor %xmm2, %xmm0, %xmm0
+ eor v8.16b, v8.16b, v10.16b
+ b .Ldec_2x_entry
+
+.align 4
+.Ldec_2x_loop:
+//
+// Inverse mix columns
+//
+ // vmovdqa -0x20(%r10),%xmm4 # 4 : sb9u
+ // vmovdqa -0x10(%r10),%xmm1 # 0 : sb9t
+ tbl v4.16b, {v24.16b}, v2.16b // vpshufb %xmm2, %xmm4, %xmm4 # 4 = sb9u
+ tbl v12.16b, {v24.16b}, v10.16b
+ tbl v1.16b, {v25.16b}, v3.16b // vpshufb %xmm3, %xmm1, %xmm1 # 0 = sb9t
+ tbl v9.16b, {v25.16b}, v11.16b
+ eor v0.16b, v4.16b, v16.16b // vpxor %xmm4, %xmm0, %xmm0
+ eor v8.16b, v12.16b, v16.16b
+ // vmovdqa 0x00(%r10),%xmm4 # 4 : sbdu
+ eor v0.16b, v0.16b, v1.16b // vpxor %xmm1, %xmm0, %xmm0 # 0 = ch
+ eor v8.16b, v8.16b, v9.16b // vpxor %xmm1, %xmm0, %xmm0 # 0 = ch
+ // vmovdqa 0x10(%r10),%xmm1 # 0 : sbdt
+
+ tbl v4.16b, {v26.16b}, v2.16b // vpshufb %xmm2, %xmm4, %xmm4 # 4 = sbdu
+ tbl v12.16b, {v26.16b}, v10.16b
+ tbl v0.16b, {v0.16b},v5.16b // vpshufb %xmm5, %xmm0, %xmm0 # MC ch
+ tbl v8.16b, {v8.16b},v5.16b
+ tbl v1.16b, {v27.16b}, v3.16b // vpshufb %xmm3, %xmm1, %xmm1 # 0 = sbdt
+ tbl v9.16b, {v27.16b}, v11.16b
+ eor v0.16b, v0.16b, v4.16b // vpxor %xmm4, %xmm0, %xmm0 # 4 = ch
+ eor v8.16b, v8.16b, v12.16b
+ // vmovdqa 0x20(%r10), %xmm4 # 4 : sbbu
+ eor v0.16b, v0.16b, v1.16b // vpxor %xmm1, %xmm0, %xmm0 # 0 = ch
+ eor v8.16b, v8.16b, v9.16b
+ // vmovdqa 0x30(%r10), %xmm1 # 0 : sbbt
+
+ tbl v4.16b, {v28.16b}, v2.16b // vpshufb %xmm2, %xmm4, %xmm4 # 4 = sbbu
+ tbl v12.16b, {v28.16b}, v10.16b
+ tbl v0.16b, {v0.16b},v5.16b // vpshufb %xmm5, %xmm0, %xmm0 # MC ch
+ tbl v8.16b, {v8.16b},v5.16b
+ tbl v1.16b, {v29.16b}, v3.16b // vpshufb %xmm3, %xmm1, %xmm1 # 0 = sbbt
+ tbl v9.16b, {v29.16b}, v11.16b
+ eor v0.16b, v0.16b, v4.16b // vpxor %xmm4, %xmm0, %xmm0 # 4 = ch
+ eor v8.16b, v8.16b, v12.16b
+ // vmovdqa 0x40(%r10), %xmm4 # 4 : sbeu
+ eor v0.16b, v0.16b, v1.16b // vpxor %xmm1, %xmm0, %xmm0 # 0 = ch
+ eor v8.16b, v8.16b, v9.16b
+ // vmovdqa 0x50(%r10), %xmm1 # 0 : sbet
+
+ tbl v4.16b, {v30.16b}, v2.16b // vpshufb %xmm2, %xmm4, %xmm4 # 4 = sbeu
+ tbl v12.16b, {v30.16b}, v10.16b
+ tbl v0.16b, {v0.16b},v5.16b // vpshufb %xmm5, %xmm0, %xmm0 # MC ch
+ tbl v8.16b, {v8.16b},v5.16b
+ tbl v1.16b, {v31.16b}, v3.16b // vpshufb %xmm3, %xmm1, %xmm1 # 0 = sbet
+ tbl v9.16b, {v31.16b}, v11.16b
+ eor v0.16b, v0.16b, v4.16b // vpxor %xmm4, %xmm0, %xmm0 # 4 = ch
+ eor v8.16b, v8.16b, v12.16b
+ ext v5.16b, v5.16b, v5.16b, #12 // vpalignr $12, %xmm5, %xmm5, %xmm5
+ eor v0.16b, v0.16b, v1.16b // vpxor %xmm1, %xmm0, %xmm0 # 0 = ch
+ eor v8.16b, v8.16b, v9.16b
+ sub w8, w8, #1 // sub $1,%rax # nr--
+
+.Ldec_2x_entry:
+ // top of round
+ and v1.16b, v0.16b, v17.16b // vpand %xmm9, %xmm0, %xmm1 # 0 = k
+ ushr v0.16b, v0.16b, #4 // vpsrlb $4, %xmm0, %xmm0 # 1 = i
+ and v9.16b, v8.16b, v17.16b
+ ushr v8.16b, v8.16b, #4
+ tbl v2.16b, {v19.16b},v1.16b // vpshufb %xmm1, %xmm11, %xmm2 # 2 = a/k
+ tbl v10.16b, {v19.16b},v9.16b
+ eor v1.16b, v1.16b, v0.16b // vpxor %xmm0, %xmm1, %xmm1 # 0 = j
+ eor v9.16b, v9.16b, v8.16b
+ tbl v3.16b, {v18.16b},v0.16b // vpshufb %xmm0, %xmm10, %xmm3 # 3 = 1/i
+ tbl v11.16b, {v18.16b},v8.16b
+ tbl v4.16b, {v18.16b},v1.16b // vpshufb %xmm1, %xmm10, %xmm4 # 4 = 1/j
+ tbl v12.16b, {v18.16b},v9.16b
+ eor v3.16b, v3.16b, v2.16b // vpxor %xmm2, %xmm3, %xmm3 # 3 = iak = 1/i + a/k
+ eor v11.16b, v11.16b, v10.16b
+ eor v4.16b, v4.16b, v2.16b // vpxor %xmm2, %xmm4, %xmm4 # 4 = jak = 1/j + a/k
+ eor v12.16b, v12.16b, v10.16b
+ tbl v2.16b, {v18.16b},v3.16b // vpshufb %xmm3, %xmm10, %xmm2 # 2 = 1/iak
+ tbl v10.16b, {v18.16b},v11.16b
+ tbl v3.16b, {v18.16b},v4.16b // vpshufb %xmm4, %xmm10, %xmm3 # 3 = 1/jak
+ tbl v11.16b, {v18.16b},v12.16b
+ eor v2.16b, v2.16b, v1.16b // vpxor %xmm1, %xmm2, %xmm2 # 2 = io
+ eor v10.16b, v10.16b, v9.16b
+ eor v3.16b, v3.16b, v0.16b // vpxor %xmm0, %xmm3, %xmm3 # 3 = jo
+ eor v11.16b, v11.16b, v8.16b
+ ld1 {v16.2d}, [x9],#16 // vmovdqu (%r9), %xmm0
+ cbnz w8, .Ldec_2x_loop
+
+ // middle of last round
+ // vmovdqa 0x60(%r10), %xmm4 # 3 : sbou
+ tbl v4.16b, {v22.16b}, v2.16b // vpshufb %xmm2, %xmm4, %xmm4 # 4 = sbou
+ tbl v12.16b, {v22.16b}, v10.16b
+ // vmovdqa 0x70(%r10), %xmm1 # 0 : sbot
+ tbl v1.16b, {v23.16b}, v3.16b // vpshufb %xmm3, %xmm1, %xmm1 # 0 = sb1t
+ tbl v9.16b, {v23.16b}, v11.16b
+ ld1 {v2.2d}, [x11] // vmovdqa -0x160(%r11), %xmm2 # .Lk_sr-.Lk_dsbd=-0x160
+ eor v4.16b, v4.16b, v16.16b // vpxor %xmm0, %xmm4, %xmm4 # 4 = sb1u + k
+ eor v12.16b, v12.16b, v16.16b
+ eor v0.16b, v1.16b, v4.16b // vpxor %xmm4, %xmm1, %xmm0 # 0 = A
+ eor v8.16b, v9.16b, v12.16b
+ tbl v0.16b, {v0.16b},v2.16b // vpshufb %xmm2, %xmm0, %xmm0
+ tbl v1.16b, {v8.16b},v2.16b
+ ret
+.size _vpaes_decrypt_2x,.-_vpaes_decrypt_2x
+////////////////////////////////////////////////////////
+// //
+// AES key schedule //
+// //
+////////////////////////////////////////////////////////
+.type _vpaes_key_preheat,%function
+.align 4
+_vpaes_key_preheat:
+ adr x10, .Lk_inv
+ movi v16.16b, #0x5b // .Lk_s63
+ adr x11, .Lk_sb1
+ movi v17.16b, #0x0f // .Lk_s0F
+ ld1 {v18.2d,v19.2d,v20.2d,v21.2d}, [x10] // .Lk_inv, .Lk_ipt
+ adr x10, .Lk_dksd
+ ld1 {v22.2d,v23.2d}, [x11] // .Lk_sb1
+ adr x11, .Lk_mc_forward
+ ld1 {v24.2d,v25.2d,v26.2d,v27.2d}, [x10],#64 // .Lk_dksd, .Lk_dksb
+ ld1 {v28.2d,v29.2d,v30.2d,v31.2d}, [x10],#64 // .Lk_dkse, .Lk_dks9
+ ld1 {v8.2d}, [x10] // .Lk_rcon
+ ld1 {v9.2d}, [x11] // .Lk_mc_forward[0]
+ ret
+.size _vpaes_key_preheat,.-_vpaes_key_preheat
+
+.type _vpaes_schedule_core,%function
+.align 4
+_vpaes_schedule_core:
+.inst 0xd503233f // paciasp
+ stp x29, x30, [sp,#-16]!
+ add x29,sp,#0
+
+ bl _vpaes_key_preheat // load the tables
+
+ ld1 {v0.16b}, [x0],#16 // vmovdqu (%rdi), %xmm0 # load key (unaligned)
+
+ // input transform
+ mov v3.16b, v0.16b // vmovdqa %xmm0, %xmm3
+ bl _vpaes_schedule_transform
+ mov v7.16b, v0.16b // vmovdqa %xmm0, %xmm7
+
+ adr x10, .Lk_sr // lea .Lk_sr(%rip),%r10
+ add x8, x8, x10
+ cbnz w3, .Lschedule_am_decrypting
+
+ // encrypting, output zeroth round key after transform
+ st1 {v0.2d}, [x2] // vmovdqu %xmm0, (%rdx)
+ b .Lschedule_go
+
+.Lschedule_am_decrypting:
+ // decrypting, output zeroth round key after shiftrows
+ ld1 {v1.2d}, [x8] // vmovdqa (%r8,%r10), %xmm1
+ tbl v3.16b, {v3.16b}, v1.16b // vpshufb %xmm1, %xmm3, %xmm3
+ st1 {v3.2d}, [x2] // vmovdqu %xmm3, (%rdx)
+ eor x8, x8, #0x30 // xor $0x30, %r8
+
+.Lschedule_go:
+ cmp w1, #192 // cmp $192, %esi
+ b.hi .Lschedule_256
+ b.eq .Lschedule_192
+ // 128: fall though
+
+//
+// .schedule_128
+//
+// 128-bit specific part of key schedule.
+//
+// This schedule is really simple, because all its parts
+// are accomplished by the subroutines.
+//
+.Lschedule_128:
+ mov x0, #10 // mov $10, %esi
+
+.Loop_schedule_128:
+ sub x0, x0, #1 // dec %esi
+ bl _vpaes_schedule_round
+ cbz x0, .Lschedule_mangle_last
+ bl _vpaes_schedule_mangle // write output
+ b .Loop_schedule_128
+
+//
+// .aes_schedule_192
+//
+// 192-bit specific part of key schedule.
+//
+// The main body of this schedule is the same as the 128-bit
+// schedule, but with more smearing. The long, high side is
+// stored in %xmm7 as before, and the short, low side is in
+// the high bits of %xmm6.
+//
+// This schedule is somewhat nastier, however, because each
+// round produces 192 bits of key material, or 1.5 round keys.
+// Therefore, on each cycle we do 2 rounds and produce 3 round
+// keys.
+//
+.align 4
+.Lschedule_192:
+ sub x0, x0, #8
+ ld1 {v0.16b}, [x0] // vmovdqu 8(%rdi),%xmm0 # load key part 2 (very unaligned)
+ bl _vpaes_schedule_transform // input transform
+ mov v6.16b, v0.16b // vmovdqa %xmm0, %xmm6 # save short part
+ eor v4.16b, v4.16b, v4.16b // vpxor %xmm4, %xmm4, %xmm4 # clear 4
+ ins v6.d[0], v4.d[0] // vmovhlps %xmm4, %xmm6, %xmm6 # clobber low side with zeros
+ mov x0, #4 // mov $4, %esi
+
+.Loop_schedule_192:
+ sub x0, x0, #1 // dec %esi
+ bl _vpaes_schedule_round
+ ext v0.16b, v6.16b, v0.16b, #8 // vpalignr $8,%xmm6,%xmm0,%xmm0
+ bl _vpaes_schedule_mangle // save key n
+ bl _vpaes_schedule_192_smear
+ bl _vpaes_schedule_mangle // save key n+1
+ bl _vpaes_schedule_round
+ cbz x0, .Lschedule_mangle_last
+ bl _vpaes_schedule_mangle // save key n+2
+ bl _vpaes_schedule_192_smear
+ b .Loop_schedule_192
+
+//
+// .aes_schedule_256
+//
+// 256-bit specific part of key schedule.
+//
+// The structure here is very similar to the 128-bit
+// schedule, but with an additional "low side" in
+// %xmm6. The low side's rounds are the same as the
+// high side's, except no rcon and no rotation.
+//
+.align 4
+.Lschedule_256:
+ ld1 {v0.16b}, [x0] // vmovdqu 16(%rdi),%xmm0 # load key part 2 (unaligned)
+ bl _vpaes_schedule_transform // input transform
+ mov x0, #7 // mov $7, %esi
+
+.Loop_schedule_256:
+ sub x0, x0, #1 // dec %esi
+ bl _vpaes_schedule_mangle // output low result
+ mov v6.16b, v0.16b // vmovdqa %xmm0, %xmm6 # save cur_lo in xmm6
+
+ // high round
+ bl _vpaes_schedule_round
+ cbz x0, .Lschedule_mangle_last
+ bl _vpaes_schedule_mangle
+
+ // low round. swap xmm7 and xmm6
+ dup v0.4s, v0.s[3] // vpshufd $0xFF, %xmm0, %xmm0
+ movi v4.16b, #0
+ mov v5.16b, v7.16b // vmovdqa %xmm7, %xmm5
+ mov v7.16b, v6.16b // vmovdqa %xmm6, %xmm7
+ bl _vpaes_schedule_low_round
+ mov v7.16b, v5.16b // vmovdqa %xmm5, %xmm7
+
+ b .Loop_schedule_256
+
+//
+// .aes_schedule_mangle_last
+//
+// Mangler for last round of key schedule
+// Mangles %xmm0
+// when encrypting, outputs out(%xmm0) ^ 63
+// when decrypting, outputs unskew(%xmm0)
+//
+// Always called right before return... jumps to cleanup and exits
+//
+.align 4
+.Lschedule_mangle_last:
+ // schedule last round key from xmm0
+ adr x11, .Lk_deskew // lea .Lk_deskew(%rip),%r11 # prepare to deskew
+ cbnz w3, .Lschedule_mangle_last_dec
+
+ // encrypting
+ ld1 {v1.2d}, [x8] // vmovdqa (%r8,%r10),%xmm1
+ adr x11, .Lk_opt // lea .Lk_opt(%rip), %r11 # prepare to output transform
+ add x2, x2, #32 // add $32, %rdx
+ tbl v0.16b, {v0.16b}, v1.16b // vpshufb %xmm1, %xmm0, %xmm0 # output permute
+
+.Lschedule_mangle_last_dec:
+ ld1 {v20.2d,v21.2d}, [x11] // reload constants
+ sub x2, x2, #16 // add $-16, %rdx
+ eor v0.16b, v0.16b, v16.16b // vpxor .Lk_s63(%rip), %xmm0, %xmm0
+ bl _vpaes_schedule_transform // output transform
+ st1 {v0.2d}, [x2] // vmovdqu %xmm0, (%rdx) # save last key
+
+ // cleanup
+ eor v0.16b, v0.16b, v0.16b // vpxor %xmm0, %xmm0, %xmm0
+ eor v1.16b, v1.16b, v1.16b // vpxor %xmm1, %xmm1, %xmm1
+ eor v2.16b, v2.16b, v2.16b // vpxor %xmm2, %xmm2, %xmm2
+ eor v3.16b, v3.16b, v3.16b // vpxor %xmm3, %xmm3, %xmm3
+ eor v4.16b, v4.16b, v4.16b // vpxor %xmm4, %xmm4, %xmm4
+ eor v5.16b, v5.16b, v5.16b // vpxor %xmm5, %xmm5, %xmm5
+ eor v6.16b, v6.16b, v6.16b // vpxor %xmm6, %xmm6, %xmm6
+ eor v7.16b, v7.16b, v7.16b // vpxor %xmm7, %xmm7, %xmm7
+ ldp x29, x30, [sp],#16
+.inst 0xd50323bf // autiasp
+ ret
+.size _vpaes_schedule_core,.-_vpaes_schedule_core
+
+//
+// .aes_schedule_192_smear
+//
+// Smear the short, low side in the 192-bit key schedule.
+//
+// Inputs:
+// %xmm7: high side, b a x y
+// %xmm6: low side, d c 0 0
+// %xmm13: 0
+//
+// Outputs:
+// %xmm6: b+c+d b+c 0 0
+// %xmm0: b+c+d b+c b a
+//
+.type _vpaes_schedule_192_smear,%function
+.align 4
+_vpaes_schedule_192_smear:
+ movi v1.16b, #0
+ dup v0.4s, v7.s[3]
+ ins v1.s[3], v6.s[2] // vpshufd $0x80, %xmm6, %xmm1 # d c 0 0 -> c 0 0 0
+ ins v0.s[0], v7.s[2] // vpshufd $0xFE, %xmm7, %xmm0 # b a _ _ -> b b b a
+ eor v6.16b, v6.16b, v1.16b // vpxor %xmm1, %xmm6, %xmm6 # -> c+d c 0 0
+ eor v1.16b, v1.16b, v1.16b // vpxor %xmm1, %xmm1, %xmm1
+ eor v6.16b, v6.16b, v0.16b // vpxor %xmm0, %xmm6, %xmm6 # -> b+c+d b+c b a
+ mov v0.16b, v6.16b // vmovdqa %xmm6, %xmm0
+ ins v6.d[0], v1.d[0] // vmovhlps %xmm1, %xmm6, %xmm6 # clobber low side with zeros
+ ret
+.size _vpaes_schedule_192_smear,.-_vpaes_schedule_192_smear
+
+//
+// .aes_schedule_round
+//
+// Runs one main round of the key schedule on %xmm0, %xmm7
+//
+// Specifically, runs subbytes on the high dword of %xmm0
+// then rotates it by one byte and xors into the low dword of
+// %xmm7.
+//
+// Adds rcon from low byte of %xmm8, then rotates %xmm8 for
+// next rcon.
+//
+// Smears the dwords of %xmm7 by xoring the low into the
+// second low, result into third, result into highest.
+//
+// Returns results in %xmm7 = %xmm0.
+// Clobbers %xmm1-%xmm4, %r11.
+//
+.type _vpaes_schedule_round,%function
+.align 4
+_vpaes_schedule_round:
+ // extract rcon from xmm8
+ movi v4.16b, #0 // vpxor %xmm4, %xmm4, %xmm4
+ ext v1.16b, v8.16b, v4.16b, #15 // vpalignr $15, %xmm8, %xmm4, %xmm1
+ ext v8.16b, v8.16b, v8.16b, #15 // vpalignr $15, %xmm8, %xmm8, %xmm8
+ eor v7.16b, v7.16b, v1.16b // vpxor %xmm1, %xmm7, %xmm7
+
+ // rotate
+ dup v0.4s, v0.s[3] // vpshufd $0xFF, %xmm0, %xmm0
+ ext v0.16b, v0.16b, v0.16b, #1 // vpalignr $1, %xmm0, %xmm0, %xmm0
+
+ // fall through...
+
+ // low round: same as high round, but no rotation and no rcon.
+_vpaes_schedule_low_round:
+ // smear xmm7
+ ext v1.16b, v4.16b, v7.16b, #12 // vpslldq $4, %xmm7, %xmm1
+ eor v7.16b, v7.16b, v1.16b // vpxor %xmm1, %xmm7, %xmm7
+ ext v4.16b, v4.16b, v7.16b, #8 // vpslldq $8, %xmm7, %xmm4
+
+ // subbytes
+ and v1.16b, v0.16b, v17.16b // vpand %xmm9, %xmm0, %xmm1 # 0 = k
+ ushr v0.16b, v0.16b, #4 // vpsrlb $4, %xmm0, %xmm0 # 1 = i
+ eor v7.16b, v7.16b, v4.16b // vpxor %xmm4, %xmm7, %xmm7
+ tbl v2.16b, {v19.16b}, v1.16b // vpshufb %xmm1, %xmm11, %xmm2 # 2 = a/k
+ eor v1.16b, v1.16b, v0.16b // vpxor %xmm0, %xmm1, %xmm1 # 0 = j
+ tbl v3.16b, {v18.16b}, v0.16b // vpshufb %xmm0, %xmm10, %xmm3 # 3 = 1/i
+ eor v3.16b, v3.16b, v2.16b // vpxor %xmm2, %xmm3, %xmm3 # 3 = iak = 1/i + a/k
+ tbl v4.16b, {v18.16b}, v1.16b // vpshufb %xmm1, %xmm10, %xmm4 # 4 = 1/j
+ eor v7.16b, v7.16b, v16.16b // vpxor .Lk_s63(%rip), %xmm7, %xmm7
+ tbl v3.16b, {v18.16b}, v3.16b // vpshufb %xmm3, %xmm10, %xmm3 # 2 = 1/iak
+ eor v4.16b, v4.16b, v2.16b // vpxor %xmm2, %xmm4, %xmm4 # 4 = jak = 1/j + a/k
+ tbl v2.16b, {v18.16b}, v4.16b // vpshufb %xmm4, %xmm10, %xmm2 # 3 = 1/jak
+ eor v3.16b, v3.16b, v1.16b // vpxor %xmm1, %xmm3, %xmm3 # 2 = io
+ eor v2.16b, v2.16b, v0.16b // vpxor %xmm0, %xmm2, %xmm2 # 3 = jo
+ tbl v4.16b, {v23.16b}, v3.16b // vpshufb %xmm3, %xmm13, %xmm4 # 4 = sbou
+ tbl v1.16b, {v22.16b}, v2.16b // vpshufb %xmm2, %xmm12, %xmm1 # 0 = sb1t
+ eor v1.16b, v1.16b, v4.16b // vpxor %xmm4, %xmm1, %xmm1 # 0 = sbox output
+
+ // add in smeared stuff
+ eor v0.16b, v1.16b, v7.16b // vpxor %xmm7, %xmm1, %xmm0
+ eor v7.16b, v1.16b, v7.16b // vmovdqa %xmm0, %xmm7
+ ret
+.size _vpaes_schedule_round,.-_vpaes_schedule_round
+
+//
+// .aes_schedule_transform
+//
+// Linear-transform %xmm0 according to tables at (%r11)
+//
+// Requires that %xmm9 = 0x0F0F... as in preheat
+// Output in %xmm0
+// Clobbers %xmm1, %xmm2
+//
+.type _vpaes_schedule_transform,%function
+.align 4
+_vpaes_schedule_transform:
+ and v1.16b, v0.16b, v17.16b // vpand %xmm9, %xmm0, %xmm1
+ ushr v0.16b, v0.16b, #4 // vpsrlb $4, %xmm0, %xmm0
+ // vmovdqa (%r11), %xmm2 # lo
+ tbl v2.16b, {v20.16b}, v1.16b // vpshufb %xmm1, %xmm2, %xmm2
+ // vmovdqa 16(%r11), %xmm1 # hi
+ tbl v0.16b, {v21.16b}, v0.16b // vpshufb %xmm0, %xmm1, %xmm0
+ eor v0.16b, v0.16b, v2.16b // vpxor %xmm2, %xmm0, %xmm0
+ ret
+.size _vpaes_schedule_transform,.-_vpaes_schedule_transform
+
+//
+// .aes_schedule_mangle
+//
+// Mangle xmm0 from (basis-transformed) standard version
+// to our version.
+//
+// On encrypt,
+// xor with 0x63
+// multiply by circulant 0,1,1,1
+// apply shiftrows transform
+//
+// On decrypt,
+// xor with 0x63
+// multiply by "inverse mixcolumns" circulant E,B,D,9
+// deskew
+// apply shiftrows transform
+//
+//
+// Writes out to (%rdx), and increments or decrements it
+// Keeps track of round number mod 4 in %r8
+// Preserves xmm0
+// Clobbers xmm1-xmm5
+//
+.type _vpaes_schedule_mangle,%function
+.align 4
+_vpaes_schedule_mangle:
+ mov v4.16b, v0.16b // vmovdqa %xmm0, %xmm4 # save xmm0 for later
+ // vmovdqa .Lk_mc_forward(%rip),%xmm5
+ cbnz w3, .Lschedule_mangle_dec
+
+ // encrypting
+ eor v4.16b, v0.16b, v16.16b // vpxor .Lk_s63(%rip), %xmm0, %xmm4
+ add x2, x2, #16 // add $16, %rdx
+ tbl v4.16b, {v4.16b}, v9.16b // vpshufb %xmm5, %xmm4, %xmm4
+ tbl v1.16b, {v4.16b}, v9.16b // vpshufb %xmm5, %xmm4, %xmm1
+ tbl v3.16b, {v1.16b}, v9.16b // vpshufb %xmm5, %xmm1, %xmm3
+ eor v4.16b, v4.16b, v1.16b // vpxor %xmm1, %xmm4, %xmm4
+ ld1 {v1.2d}, [x8] // vmovdqa (%r8,%r10), %xmm1
+ eor v3.16b, v3.16b, v4.16b // vpxor %xmm4, %xmm3, %xmm3
+
+ b .Lschedule_mangle_both
+.align 4
+.Lschedule_mangle_dec:
+ // inverse mix columns
+ // lea .Lk_dksd(%rip),%r11
+ ushr v1.16b, v4.16b, #4 // vpsrlb $4, %xmm4, %xmm1 # 1 = hi
+ and v4.16b, v4.16b, v17.16b // vpand %xmm9, %xmm4, %xmm4 # 4 = lo
+
+ // vmovdqa 0x00(%r11), %xmm2
+ tbl v2.16b, {v24.16b}, v4.16b // vpshufb %xmm4, %xmm2, %xmm2
+ // vmovdqa 0x10(%r11), %xmm3
+ tbl v3.16b, {v25.16b}, v1.16b // vpshufb %xmm1, %xmm3, %xmm3
+ eor v3.16b, v3.16b, v2.16b // vpxor %xmm2, %xmm3, %xmm3
+ tbl v3.16b, {v3.16b}, v9.16b // vpshufb %xmm5, %xmm3, %xmm3
+
+ // vmovdqa 0x20(%r11), %xmm2
+ tbl v2.16b, {v26.16b}, v4.16b // vpshufb %xmm4, %xmm2, %xmm2
+ eor v2.16b, v2.16b, v3.16b // vpxor %xmm3, %xmm2, %xmm2
+ // vmovdqa 0x30(%r11), %xmm3
+ tbl v3.16b, {v27.16b}, v1.16b // vpshufb %xmm1, %xmm3, %xmm3
+ eor v3.16b, v3.16b, v2.16b // vpxor %xmm2, %xmm3, %xmm3
+ tbl v3.16b, {v3.16b}, v9.16b // vpshufb %xmm5, %xmm3, %xmm3
+
+ // vmovdqa 0x40(%r11), %xmm2
+ tbl v2.16b, {v28.16b}, v4.16b // vpshufb %xmm4, %xmm2, %xmm2
+ eor v2.16b, v2.16b, v3.16b // vpxor %xmm3, %xmm2, %xmm2
+ // vmovdqa 0x50(%r11), %xmm3
+ tbl v3.16b, {v29.16b}, v1.16b // vpshufb %xmm1, %xmm3, %xmm3
+ eor v3.16b, v3.16b, v2.16b // vpxor %xmm2, %xmm3, %xmm3
+
+ // vmovdqa 0x60(%r11), %xmm2
+ tbl v2.16b, {v30.16b}, v4.16b // vpshufb %xmm4, %xmm2, %xmm2
+ tbl v3.16b, {v3.16b}, v9.16b // vpshufb %xmm5, %xmm3, %xmm3
+ // vmovdqa 0x70(%r11), %xmm4
+ tbl v4.16b, {v31.16b}, v1.16b // vpshufb %xmm1, %xmm4, %xmm4
+ ld1 {v1.2d}, [x8] // vmovdqa (%r8,%r10), %xmm1
+ eor v2.16b, v2.16b, v3.16b // vpxor %xmm3, %xmm2, %xmm2
+ eor v3.16b, v4.16b, v2.16b // vpxor %xmm2, %xmm4, %xmm3
+
+ sub x2, x2, #16 // add $-16, %rdx
+
+.Lschedule_mangle_both:
+ tbl v3.16b, {v3.16b}, v1.16b // vpshufb %xmm1, %xmm3, %xmm3
+ add x8, x8, #64-16 // add $-16, %r8
+ and x8, x8, #~(1<<6) // and $0x30, %r8
+ st1 {v3.2d}, [x2] // vmovdqu %xmm3, (%rdx)
+ ret
+.size _vpaes_schedule_mangle,.-_vpaes_schedule_mangle
+
+.globl vpaes_set_encrypt_key
+.type vpaes_set_encrypt_key,%function
+.align 4
+vpaes_set_encrypt_key:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+ stp d8,d9,[sp,#-16]! // ABI spec says so
+
+ lsr w9, w1, #5 // shr $5,%eax
+ add w9, w9, #5 // $5,%eax
+ str w9, [x2,#240] // mov %eax,240(%rdx) # AES_KEY->rounds = nbits/32+5;
+
+ mov w3, #0 // mov $0,%ecx
+ mov x8, #0x30 // mov $0x30,%r8d
+ bl _vpaes_schedule_core
+ eor x0, x0, x0
+
+ ldp d8,d9,[sp],#16
+ ldp x29,x30,[sp],#16
+.inst 0xd50323bf // autiasp
+ ret
+.size vpaes_set_encrypt_key,.-vpaes_set_encrypt_key
+
+.globl vpaes_set_decrypt_key
+.type vpaes_set_decrypt_key,%function
+.align 4
+vpaes_set_decrypt_key:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+ stp d8,d9,[sp,#-16]! // ABI spec says so
+
+ lsr w9, w1, #5 // shr $5,%eax
+ add w9, w9, #5 // $5,%eax
+ str w9, [x2,#240] // mov %eax,240(%rdx) # AES_KEY->rounds = nbits/32+5;
+ lsl w9, w9, #4 // shl $4,%eax
+ add x2, x2, #16 // lea 16(%rdx,%rax),%rdx
+ add x2, x2, x9
+
+ mov w3, #1 // mov $1,%ecx
+ lsr w8, w1, #1 // shr $1,%r8d
+ and x8, x8, #32 // and $32,%r8d
+ eor x8, x8, #32 // xor $32,%r8d # nbits==192?0:32
+ bl _vpaes_schedule_core
+
+ ldp d8,d9,[sp],#16
+ ldp x29,x30,[sp],#16
+.inst 0xd50323bf // autiasp
+ ret
+.size vpaes_set_decrypt_key,.-vpaes_set_decrypt_key
+.globl vpaes_cbc_encrypt
+.type vpaes_cbc_encrypt,%function
+.align 4
+vpaes_cbc_encrypt:
+ cbz x2, .Lcbc_abort
+ cmp w5, #0 // check direction
+ b.eq vpaes_cbc_decrypt
+
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+
+ mov x17, x2 // reassign
+ mov x2, x3 // reassign
+
+ ld1 {v0.16b}, [x4] // load ivec
+ bl _vpaes_encrypt_preheat
+ b .Lcbc_enc_loop
+
+.align 4
+.Lcbc_enc_loop:
+ ld1 {v7.16b}, [x0],#16 // load input
+ eor v7.16b, v7.16b, v0.16b // xor with ivec
+ bl _vpaes_encrypt_core
+ st1 {v0.16b}, [x1],#16 // save output
+ subs x17, x17, #16
+ b.hi .Lcbc_enc_loop
+
+ st1 {v0.16b}, [x4] // write ivec
+
+ ldp x29,x30,[sp],#16
+.inst 0xd50323bf // autiasp
+.Lcbc_abort:
+ ret
+.size vpaes_cbc_encrypt,.-vpaes_cbc_encrypt
+
+.type vpaes_cbc_decrypt,%function
+.align 4
+vpaes_cbc_decrypt:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+ stp d8,d9,[sp,#-16]! // ABI spec says so
+ stp d10,d11,[sp,#-16]!
+ stp d12,d13,[sp,#-16]!
+ stp d14,d15,[sp,#-16]!
+
+ mov x17, x2 // reassign
+ mov x2, x3 // reassign
+ ld1 {v6.16b}, [x4] // load ivec
+ bl _vpaes_decrypt_preheat
+ tst x17, #16
+ b.eq .Lcbc_dec_loop2x
+
+ ld1 {v7.16b}, [x0], #16 // load input
+ bl _vpaes_decrypt_core
+ eor v0.16b, v0.16b, v6.16b // xor with ivec
+ orr v6.16b, v7.16b, v7.16b // next ivec value
+ st1 {v0.16b}, [x1], #16
+ subs x17, x17, #16
+ b.ls .Lcbc_dec_done
+
+.align 4
+.Lcbc_dec_loop2x:
+ ld1 {v14.16b,v15.16b}, [x0], #32
+ bl _vpaes_decrypt_2x
+ eor v0.16b, v0.16b, v6.16b // xor with ivec
+ eor v1.16b, v1.16b, v14.16b
+ orr v6.16b, v15.16b, v15.16b
+ st1 {v0.16b,v1.16b}, [x1], #32
+ subs x17, x17, #32
+ b.hi .Lcbc_dec_loop2x
+
+.Lcbc_dec_done:
+ st1 {v6.16b}, [x4]
+
+ ldp d14,d15,[sp],#16
+ ldp d12,d13,[sp],#16
+ ldp d10,d11,[sp],#16
+ ldp d8,d9,[sp],#16
+ ldp x29,x30,[sp],#16
+.inst 0xd50323bf // autiasp
+ ret
+.size vpaes_cbc_decrypt,.-vpaes_cbc_decrypt
+.globl vpaes_ecb_encrypt
+.type vpaes_ecb_encrypt,%function
+.align 4
+vpaes_ecb_encrypt:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+ stp d8,d9,[sp,#-16]! // ABI spec says so
+ stp d10,d11,[sp,#-16]!
+ stp d12,d13,[sp,#-16]!
+ stp d14,d15,[sp,#-16]!
+
+ mov x17, x2
+ mov x2, x3
+ bl _vpaes_encrypt_preheat
+ tst x17, #16
+ b.eq .Lecb_enc_loop
+
+ ld1 {v7.16b}, [x0],#16
+ bl _vpaes_encrypt_core
+ st1 {v0.16b}, [x1],#16
+ subs x17, x17, #16
+ b.ls .Lecb_enc_done
+
+.align 4
+.Lecb_enc_loop:
+ ld1 {v14.16b,v15.16b}, [x0], #32
+ bl _vpaes_encrypt_2x
+ st1 {v0.16b,v1.16b}, [x1], #32
+ subs x17, x17, #32
+ b.hi .Lecb_enc_loop
+
+.Lecb_enc_done:
+ ldp d14,d15,[sp],#16
+ ldp d12,d13,[sp],#16
+ ldp d10,d11,[sp],#16
+ ldp d8,d9,[sp],#16
+ ldp x29,x30,[sp],#16
+.inst 0xd50323bf // autiasp
+ ret
+.size vpaes_ecb_encrypt,.-vpaes_ecb_encrypt
+
+.globl vpaes_ecb_decrypt
+.type vpaes_ecb_decrypt,%function
+.align 4
+vpaes_ecb_decrypt:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+ stp d8,d9,[sp,#-16]! // ABI spec says so
+ stp d10,d11,[sp,#-16]!
+ stp d12,d13,[sp,#-16]!
+ stp d14,d15,[sp,#-16]!
+
+ mov x17, x2
+ mov x2, x3
+ bl _vpaes_decrypt_preheat
+ tst x17, #16
+ b.eq .Lecb_dec_loop
+
+ ld1 {v7.16b}, [x0],#16
+ bl _vpaes_encrypt_core
+ st1 {v0.16b}, [x1],#16
+ subs x17, x17, #16
+ b.ls .Lecb_dec_done
+
+.align 4
+.Lecb_dec_loop:
+ ld1 {v14.16b,v15.16b}, [x0], #32
+ bl _vpaes_decrypt_2x
+ st1 {v0.16b,v1.16b}, [x1], #32
+ subs x17, x17, #32
+ b.hi .Lecb_dec_loop
+
+.Lecb_dec_done:
+ ldp d14,d15,[sp],#16
+ ldp d12,d13,[sp],#16
+ ldp d10,d11,[sp],#16
+ ldp d8,d9,[sp],#16
+ ldp x29,x30,[sp],#16
+.inst 0xd50323bf // autiasp
+ ret
+.size vpaes_ecb_decrypt,.-vpaes_ecb_decrypt
diff --git a/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/arm64cpuid.S b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/arm64cpuid.S
new file mode 100644
index 000000000000..297d5075f95d
--- /dev/null
+++ b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/arm64cpuid.S
@@ -0,0 +1,129 @@
+#include "arm_arch.h"
+
+.text
+.arch armv8-a+crypto
+
+.align 5
+.globl _armv7_neon_probe
+.type _armv7_neon_probe,%function
+_armv7_neon_probe:
+ orr v15.16b, v15.16b, v15.16b
+ ret
+.size _armv7_neon_probe,.-_armv7_neon_probe
+
+.globl _armv7_tick
+.type _armv7_tick,%function
+_armv7_tick:
+#ifdef __APPLE__
+ mrs x0, CNTPCT_EL0
+#else
+ mrs x0, CNTVCT_EL0
+#endif
+ ret
+.size _armv7_tick,.-_armv7_tick
+
+.globl _armv8_aes_probe
+.type _armv8_aes_probe,%function
+_armv8_aes_probe:
+ aese v0.16b, v0.16b
+ ret
+.size _armv8_aes_probe,.-_armv8_aes_probe
+
+.globl _armv8_sha1_probe
+.type _armv8_sha1_probe,%function
+_armv8_sha1_probe:
+ sha1h s0, s0
+ ret
+.size _armv8_sha1_probe,.-_armv8_sha1_probe
+
+.globl _armv8_sha256_probe
+.type _armv8_sha256_probe,%function
+_armv8_sha256_probe:
+ sha256su0 v0.4s, v0.4s
+ ret
+.size _armv8_sha256_probe,.-_armv8_sha256_probe
+
+.globl _armv8_pmull_probe
+.type _armv8_pmull_probe,%function
+_armv8_pmull_probe:
+ pmull v0.1q, v0.1d, v0.1d
+ ret
+.size _armv8_pmull_probe,.-_armv8_pmull_probe
+
+.globl _armv8_sha512_probe
+.type _armv8_sha512_probe,%function
+_armv8_sha512_probe:
+.long 0xcec08000 // sha512su0 v0.2d,v0.2d
+ ret
+.size _armv8_sha512_probe,.-_armv8_sha512_probe
+
+.globl _armv8_cpuid_probe
+.type _armv8_cpuid_probe,%function
+_armv8_cpuid_probe:
+ mrs x0, midr_el1
+ ret
+.size _armv8_cpuid_probe,.-_armv8_cpuid_probe
+
+.globl OPENSSL_cleanse
+.type OPENSSL_cleanse,%function
+.align 5
+OPENSSL_cleanse:
+ cbz x1,.Lret // len==0?
+ cmp x1,#15
+ b.hi .Lot // len>15
+ nop
+.Little:
+ strb wzr,[x0],#1 // store byte-by-byte
+ subs x1,x1,#1
+ b.ne .Little
+.Lret: ret
+
+.align 4
+.Lot: tst x0,#7
+ b.eq .Laligned // inp is aligned
+ strb wzr,[x0],#1 // store byte-by-byte
+ sub x1,x1,#1
+ b .Lot
+
+.align 4
+.Laligned:
+ str xzr,[x0],#8 // store word-by-word
+ sub x1,x1,#8
+ tst x1,#-8
+ b.ne .Laligned // len>=8
+ cbnz x1,.Little // len!=0?
+ ret
+.size OPENSSL_cleanse,.-OPENSSL_cleanse
+
+.globl CRYPTO_memcmp
+.type CRYPTO_memcmp,%function
+.align 4
+CRYPTO_memcmp:
+ eor w3,w3,w3
+ cbz x2,.Lno_data // len==0?
+ cmp x2,#16
+ b.ne .Loop_cmp
+ ldp x8,x9,[x0]
+ ldp x10,x11,[x1]
+ eor x8,x8,x10
+ eor x9,x9,x11
+ orr x8,x8,x9
+ mov x0,#1
+ cmp x8,#0
+ csel x0,xzr,x0,eq
+ ret
+
+.align 4
+.Loop_cmp:
+ ldrb w4,[x0],#1
+ ldrb w5,[x1],#1
+ eor w4,w4,w5
+ orr w3,w3,w4
+ subs x2,x2,#1
+ b.ne .Loop_cmp
+
+.Lno_data:
+ neg w0,w3
+ lsr w0,w0,#31
+ ret
+.size CRYPTO_memcmp,.-CRYPTO_memcmp
diff --git a/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/bn/armv8-mont.S b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/bn/armv8-mont.S
new file mode 100644
index 000000000000..7448af982c99
--- /dev/null
+++ b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/bn/armv8-mont.S
@@ -0,0 +1,2124 @@
+#ifndef __KERNEL__
+# include "arm_arch.h"
+
+.hidden OPENSSL_armv8_rsa_neonized
+#endif
+.text
+
+.globl bn_mul_mont
+.type bn_mul_mont,%function
+.align 5
+bn_mul_mont:
+.Lbn_mul_mont:
+ tst x5,#3
+ b.ne .Lmul_mont
+ cmp x5,#32
+ b.le .Lscalar_impl
+#ifndef __KERNEL__
+ adrp x17,OPENSSL_armv8_rsa_neonized
+ ldr w17,[x17,#:lo12:OPENSSL_armv8_rsa_neonized]
+ cbnz w17, bn_mul8x_mont_neon
+#endif
+
+.Lscalar_impl:
+ tst x5,#7
+ b.eq __bn_sqr8x_mont
+ tst x5,#3
+ b.eq __bn_mul4x_mont
+
+.Lmul_mont:
+ stp x29,x30,[sp,#-64]!
+ add x29,sp,#0
+ stp x19,x20,[sp,#16]
+ stp x21,x22,[sp,#32]
+ stp x23,x24,[sp,#48]
+
+ ldr x9,[x2],#8 // bp[0]
+ sub x22,sp,x5,lsl#3
+ ldp x7,x8,[x1],#16 // ap[0..1]
+ lsl x5,x5,#3
+ ldr x4,[x4] // *n0
+ and x22,x22,#-16 // ABI says so
+ ldp x13,x14,[x3],#16 // np[0..1]
+
+ mul x6,x7,x9 // ap[0]*bp[0]
+ sub x21,x5,#16 // j=num-2
+ umulh x7,x7,x9
+ mul x10,x8,x9 // ap[1]*bp[0]
+ umulh x11,x8,x9
+
+ mul x15,x6,x4 // "tp[0]"*n0
+ mov sp,x22 // alloca
+
+ // (*) mul x12,x13,x15 // np[0]*m1
+ umulh x13,x13,x15
+ mul x16,x14,x15 // np[1]*m1
+ // (*) adds x12,x12,x6 // discarded
+ // (*) As for removal of first multiplication and addition
+ // instructions. The outcome of first addition is
+ // guaranteed to be zero, which leaves two computationally
+ // significant outcomes: it either carries or not. Then
+ // question is when does it carry? Is there alternative
+ // way to deduce it? If you follow operations, you can
+ // observe that condition for carry is quite simple:
+ // x6 being non-zero. So that carry can be calculated
+ // by adding -1 to x6. That's what next instruction does.
+ subs xzr,x6,#1 // (*)
+ umulh x17,x14,x15
+ adc x13,x13,xzr
+ cbz x21,.L1st_skip
+
+.L1st:
+ ldr x8,[x1],#8
+ adds x6,x10,x7
+ sub x21,x21,#8 // j--
+ adc x7,x11,xzr
+
+ ldr x14,[x3],#8
+ adds x12,x16,x13
+ mul x10,x8,x9 // ap[j]*bp[0]
+ adc x13,x17,xzr
+ umulh x11,x8,x9
+
+ adds x12,x12,x6
+ mul x16,x14,x15 // np[j]*m1
+ adc x13,x13,xzr
+ umulh x17,x14,x15
+ str x12,[x22],#8 // tp[j-1]
+ cbnz x21,.L1st
+
+.L1st_skip:
+ adds x6,x10,x7
+ sub x1,x1,x5 // rewind x1
+ adc x7,x11,xzr
+
+ adds x12,x16,x13
+ sub x3,x3,x5 // rewind x3
+ adc x13,x17,xzr
+
+ adds x12,x12,x6
+ sub x20,x5,#8 // i=num-1
+ adcs x13,x13,x7
+
+ adc x19,xzr,xzr // upmost overflow bit
+ stp x12,x13,[x22]
+
+.Louter:
+ ldr x9,[x2],#8 // bp[i]
+ ldp x7,x8,[x1],#16
+ ldr x23,[sp] // tp[0]
+ add x22,sp,#8
+
+ mul x6,x7,x9 // ap[0]*bp[i]
+ sub x21,x5,#16 // j=num-2
+ umulh x7,x7,x9
+ ldp x13,x14,[x3],#16
+ mul x10,x8,x9 // ap[1]*bp[i]
+ adds x6,x6,x23
+ umulh x11,x8,x9
+ adc x7,x7,xzr
+
+ mul x15,x6,x4
+ sub x20,x20,#8 // i--
+
+ // (*) mul x12,x13,x15 // np[0]*m1
+ umulh x13,x13,x15
+ mul x16,x14,x15 // np[1]*m1
+ // (*) adds x12,x12,x6
+ subs xzr,x6,#1 // (*)
+ umulh x17,x14,x15
+ cbz x21,.Linner_skip
+
+.Linner:
+ ldr x8,[x1],#8
+ adc x13,x13,xzr
+ ldr x23,[x22],#8 // tp[j]
+ adds x6,x10,x7
+ sub x21,x21,#8 // j--
+ adc x7,x11,xzr
+
+ adds x12,x16,x13
+ ldr x14,[x3],#8
+ adc x13,x17,xzr
+
+ mul x10,x8,x9 // ap[j]*bp[i]
+ adds x6,x6,x23
+ umulh x11,x8,x9
+ adc x7,x7,xzr
+
+ mul x16,x14,x15 // np[j]*m1
+ adds x12,x12,x6
+ umulh x17,x14,x15
+ stur x12,[x22,#-16] // tp[j-1]
+ cbnz x21,.Linner
+
+.Linner_skip:
+ ldr x23,[x22],#8 // tp[j]
+ adc x13,x13,xzr
+ adds x6,x10,x7
+ sub x1,x1,x5 // rewind x1
+ adc x7,x11,xzr
+
+ adds x12,x16,x13
+ sub x3,x3,x5 // rewind x3
+ adcs x13,x17,x19
+ adc x19,xzr,xzr
+
+ adds x6,x6,x23
+ adc x7,x7,xzr
+
+ adds x12,x12,x6
+ adcs x13,x13,x7
+ adc x19,x19,xzr // upmost overflow bit
+ stp x12,x13,[x22,#-16]
+
+ cbnz x20,.Louter
+
+ // Final step. We see if result is larger than modulus, and
+ // if it is, subtract the modulus. But comparison implies
+ // subtraction. So we subtract modulus, see if it borrowed,
+ // and conditionally copy original value.
+ ldr x23,[sp] // tp[0]
+ add x22,sp,#8
+ ldr x14,[x3],#8 // np[0]
+ subs x21,x5,#8 // j=num-1 and clear borrow
+ mov x1,x0
+.Lsub:
+ sbcs x8,x23,x14 // tp[j]-np[j]
+ ldr x23,[x22],#8
+ sub x21,x21,#8 // j--
+ ldr x14,[x3],#8
+ str x8,[x1],#8 // rp[j]=tp[j]-np[j]
+ cbnz x21,.Lsub
+
+ sbcs x8,x23,x14
+ sbcs x19,x19,xzr // did it borrow?
+ str x8,[x1],#8 // rp[num-1]
+
+ ldr x23,[sp] // tp[0]
+ add x22,sp,#8
+ ldr x8,[x0],#8 // rp[0]
+ sub x5,x5,#8 // num--
+ nop
+.Lcond_copy:
+ sub x5,x5,#8 // num--
+ csel x14,x23,x8,lo // did it borrow?
+ ldr x23,[x22],#8
+ ldr x8,[x0],#8
+ stur xzr,[x22,#-16] // wipe tp
+ stur x14,[x0,#-16]
+ cbnz x5,.Lcond_copy
+
+ csel x14,x23,x8,lo
+ stur xzr,[x22,#-8] // wipe tp
+ stur x14,[x0,#-8]
+
+ ldp x19,x20,[x29,#16]
+ mov sp,x29
+ ldp x21,x22,[x29,#32]
+ mov x0,#1
+ ldp x23,x24,[x29,#48]
+ ldr x29,[sp],#64
+ ret
+.size bn_mul_mont,.-bn_mul_mont
+.type bn_mul8x_mont_neon,%function
+.align 5
+bn_mul8x_mont_neon:
+ stp x29,x30,[sp,#-80]!
+ mov x16,sp
+ stp d8,d9,[sp,#16]
+ stp d10,d11,[sp,#32]
+ stp d12,d13,[sp,#48]
+ stp d14,d15,[sp,#64]
+ lsl x5,x5,#1
+ eor v14.16b,v14.16b,v14.16b
+
+.align 4
+.LNEON_8n:
+ eor v6.16b,v6.16b,v6.16b
+ sub x7,sp,#128
+ eor v7.16b,v7.16b,v7.16b
+ sub x7,x7,x5,lsl#4
+ eor v8.16b,v8.16b,v8.16b
+ and x7,x7,#-64
+ eor v9.16b,v9.16b,v9.16b
+ mov sp,x7 // alloca
+ eor v10.16b,v10.16b,v10.16b
+ add x7,x7,#256
+ eor v11.16b,v11.16b,v11.16b
+ sub x8,x5,#8
+ eor v12.16b,v12.16b,v12.16b
+ eor v13.16b,v13.16b,v13.16b
+
+.LNEON_8n_init:
+ st1 {v6.2d,v7.2d},[x7],#32
+ subs x8,x8,#8
+ st1 {v8.2d,v9.2d},[x7],#32
+ st1 {v10.2d,v11.2d},[x7],#32
+ st1 {v12.2d,v13.2d},[x7],#32
+ bne .LNEON_8n_init
+
+ add x6,sp,#256
+ ld1 {v0.4s,v1.4s},[x1],#32
+ add x10,sp,#8
+ ldr s30,[x4],#4
+ mov x9,x5
+ b .LNEON_8n_outer
+
+.align 4
+.LNEON_8n_outer:
+ ldr s28,[x2],#4 // *b++
+ uxtl v28.4s,v28.4h
+ add x7,sp,#128
+ ld1 {v2.4s,v3.4s},[x3],#32
+
+ umlal v6.2d,v28.2s,v0.s[0]
+ umlal v7.2d,v28.2s,v0.s[1]
+ umlal v8.2d,v28.2s,v0.s[2]
+ shl v29.2d,v6.2d,#16
+ ext v29.16b,v29.16b,v29.16b,#8
+ umlal v9.2d,v28.2s,v0.s[3]
+ add v29.2d,v29.2d,v6.2d
+ umlal v10.2d,v28.2s,v1.s[0]
+ mul v29.2s,v29.2s,v30.2s
+ umlal v11.2d,v28.2s,v1.s[1]
+ st1 {v28.2s},[sp] // put aside smashed b[8*i+0]
+ umlal v12.2d,v28.2s,v1.s[2]
+ uxtl v29.4s,v29.4h
+ umlal v13.2d,v28.2s,v1.s[3]
+ ldr s28,[x2],#4 // *b++
+ umlal v6.2d,v29.2s,v2.s[0]
+ umlal v7.2d,v29.2s,v2.s[1]
+ uxtl v28.4s,v28.4h
+ umlal v8.2d,v29.2s,v2.s[2]
+ ushr v15.2d,v6.2d,#16
+ umlal v9.2d,v29.2s,v2.s[3]
+ umlal v10.2d,v29.2s,v3.s[0]
+ ext v6.16b,v6.16b,v6.16b,#8
+ add v6.2d,v6.2d,v15.2d
+ umlal v11.2d,v29.2s,v3.s[1]
+ ushr v6.2d,v6.2d,#16
+ umlal v12.2d,v29.2s,v3.s[2]
+ umlal v13.2d,v29.2s,v3.s[3]
+ add v16.2d,v7.2d,v6.2d
+ ins v7.d[0],v16.d[0]
+ st1 {v29.2s},[x10],#8 // put aside smashed m[8*i+0]
+ umlal v7.2d,v28.2s,v0.s[0]
+ ld1 {v6.2d},[x6],#16
+ umlal v8.2d,v28.2s,v0.s[1]
+ umlal v9.2d,v28.2s,v0.s[2]
+ shl v29.2d,v7.2d,#16
+ ext v29.16b,v29.16b,v29.16b,#8
+ umlal v10.2d,v28.2s,v0.s[3]
+ add v29.2d,v29.2d,v7.2d
+ umlal v11.2d,v28.2s,v1.s[0]
+ mul v29.2s,v29.2s,v30.2s
+ umlal v12.2d,v28.2s,v1.s[1]
+ st1 {v28.2s},[x10],#8 // put aside smashed b[8*i+1]
+ umlal v13.2d,v28.2s,v1.s[2]
+ uxtl v29.4s,v29.4h
+ umlal v6.2d,v28.2s,v1.s[3]
+ ldr s28,[x2],#4 // *b++
+ umlal v7.2d,v29.2s,v2.s[0]
+ umlal v8.2d,v29.2s,v2.s[1]
+ uxtl v28.4s,v28.4h
+ umlal v9.2d,v29.2s,v2.s[2]
+ ushr v15.2d,v7.2d,#16
+ umlal v10.2d,v29.2s,v2.s[3]
+ umlal v11.2d,v29.2s,v3.s[0]
+ ext v7.16b,v7.16b,v7.16b,#8
+ add v7.2d,v7.2d,v15.2d
+ umlal v12.2d,v29.2s,v3.s[1]
+ ushr v7.2d,v7.2d,#16
+ umlal v13.2d,v29.2s,v3.s[2]
+ umlal v6.2d,v29.2s,v3.s[3]
+ add v16.2d,v8.2d,v7.2d
+ ins v8.d[0],v16.d[0]
+ st1 {v29.2s},[x10],#8 // put aside smashed m[8*i+1]
+ umlal v8.2d,v28.2s,v0.s[0]
+ ld1 {v7.2d},[x6],#16
+ umlal v9.2d,v28.2s,v0.s[1]
+ umlal v10.2d,v28.2s,v0.s[2]
+ shl v29.2d,v8.2d,#16
+ ext v29.16b,v29.16b,v29.16b,#8
+ umlal v11.2d,v28.2s,v0.s[3]
+ add v29.2d,v29.2d,v8.2d
+ umlal v12.2d,v28.2s,v1.s[0]
+ mul v29.2s,v29.2s,v30.2s
+ umlal v13.2d,v28.2s,v1.s[1]
+ st1 {v28.2s},[x10],#8 // put aside smashed b[8*i+2]
+ umlal v6.2d,v28.2s,v1.s[2]
+ uxtl v29.4s,v29.4h
+ umlal v7.2d,v28.2s,v1.s[3]
+ ldr s28,[x2],#4 // *b++
+ umlal v8.2d,v29.2s,v2.s[0]
+ umlal v9.2d,v29.2s,v2.s[1]
+ uxtl v28.4s,v28.4h
+ umlal v10.2d,v29.2s,v2.s[2]
+ ushr v15.2d,v8.2d,#16
+ umlal v11.2d,v29.2s,v2.s[3]
+ umlal v12.2d,v29.2s,v3.s[0]
+ ext v8.16b,v8.16b,v8.16b,#8
+ add v8.2d,v8.2d,v15.2d
+ umlal v13.2d,v29.2s,v3.s[1]
+ ushr v8.2d,v8.2d,#16
+ umlal v6.2d,v29.2s,v3.s[2]
+ umlal v7.2d,v29.2s,v3.s[3]
+ add v16.2d,v9.2d,v8.2d
+ ins v9.d[0],v16.d[0]
+ st1 {v29.2s},[x10],#8 // put aside smashed m[8*i+2]
+ umlal v9.2d,v28.2s,v0.s[0]
+ ld1 {v8.2d},[x6],#16
+ umlal v10.2d,v28.2s,v0.s[1]
+ umlal v11.2d,v28.2s,v0.s[2]
+ shl v29.2d,v9.2d,#16
+ ext v29.16b,v29.16b,v29.16b,#8
+ umlal v12.2d,v28.2s,v0.s[3]
+ add v29.2d,v29.2d,v9.2d
+ umlal v13.2d,v28.2s,v1.s[0]
+ mul v29.2s,v29.2s,v30.2s
+ umlal v6.2d,v28.2s,v1.s[1]
+ st1 {v28.2s},[x10],#8 // put aside smashed b[8*i+3]
+ umlal v7.2d,v28.2s,v1.s[2]
+ uxtl v29.4s,v29.4h
+ umlal v8.2d,v28.2s,v1.s[3]
+ ldr s28,[x2],#4 // *b++
+ umlal v9.2d,v29.2s,v2.s[0]
+ umlal v10.2d,v29.2s,v2.s[1]
+ uxtl v28.4s,v28.4h
+ umlal v11.2d,v29.2s,v2.s[2]
+ ushr v15.2d,v9.2d,#16
+ umlal v12.2d,v29.2s,v2.s[3]
+ umlal v13.2d,v29.2s,v3.s[0]
+ ext v9.16b,v9.16b,v9.16b,#8
+ add v9.2d,v9.2d,v15.2d
+ umlal v6.2d,v29.2s,v3.s[1]
+ ushr v9.2d,v9.2d,#16
+ umlal v7.2d,v29.2s,v3.s[2]
+ umlal v8.2d,v29.2s,v3.s[3]
+ add v16.2d,v10.2d,v9.2d
+ ins v10.d[0],v16.d[0]
+ st1 {v29.2s},[x10],#8 // put aside smashed m[8*i+3]
+ umlal v10.2d,v28.2s,v0.s[0]
+ ld1 {v9.2d},[x6],#16
+ umlal v11.2d,v28.2s,v0.s[1]
+ umlal v12.2d,v28.2s,v0.s[2]
+ shl v29.2d,v10.2d,#16
+ ext v29.16b,v29.16b,v29.16b,#8
+ umlal v13.2d,v28.2s,v0.s[3]
+ add v29.2d,v29.2d,v10.2d
+ umlal v6.2d,v28.2s,v1.s[0]
+ mul v29.2s,v29.2s,v30.2s
+ umlal v7.2d,v28.2s,v1.s[1]
+ st1 {v28.2s},[x10],#8 // put aside smashed b[8*i+4]
+ umlal v8.2d,v28.2s,v1.s[2]
+ uxtl v29.4s,v29.4h
+ umlal v9.2d,v28.2s,v1.s[3]
+ ldr s28,[x2],#4 // *b++
+ umlal v10.2d,v29.2s,v2.s[0]
+ umlal v11.2d,v29.2s,v2.s[1]
+ uxtl v28.4s,v28.4h
+ umlal v12.2d,v29.2s,v2.s[2]
+ ushr v15.2d,v10.2d,#16
+ umlal v13.2d,v29.2s,v2.s[3]
+ umlal v6.2d,v29.2s,v3.s[0]
+ ext v10.16b,v10.16b,v10.16b,#8
+ add v10.2d,v10.2d,v15.2d
+ umlal v7.2d,v29.2s,v3.s[1]
+ ushr v10.2d,v10.2d,#16
+ umlal v8.2d,v29.2s,v3.s[2]
+ umlal v9.2d,v29.2s,v3.s[3]
+ add v16.2d,v11.2d,v10.2d
+ ins v11.d[0],v16.d[0]
+ st1 {v29.2s},[x10],#8 // put aside smashed m[8*i+4]
+ umlal v11.2d,v28.2s,v0.s[0]
+ ld1 {v10.2d},[x6],#16
+ umlal v12.2d,v28.2s,v0.s[1]
+ umlal v13.2d,v28.2s,v0.s[2]
+ shl v29.2d,v11.2d,#16
+ ext v29.16b,v29.16b,v29.16b,#8
+ umlal v6.2d,v28.2s,v0.s[3]
+ add v29.2d,v29.2d,v11.2d
+ umlal v7.2d,v28.2s,v1.s[0]
+ mul v29.2s,v29.2s,v30.2s
+ umlal v8.2d,v28.2s,v1.s[1]
+ st1 {v28.2s},[x10],#8 // put aside smashed b[8*i+5]
+ umlal v9.2d,v28.2s,v1.s[2]
+ uxtl v29.4s,v29.4h
+ umlal v10.2d,v28.2s,v1.s[3]
+ ldr s28,[x2],#4 // *b++
+ umlal v11.2d,v29.2s,v2.s[0]
+ umlal v12.2d,v29.2s,v2.s[1]
+ uxtl v28.4s,v28.4h
+ umlal v13.2d,v29.2s,v2.s[2]
+ ushr v15.2d,v11.2d,#16
+ umlal v6.2d,v29.2s,v2.s[3]
+ umlal v7.2d,v29.2s,v3.s[0]
+ ext v11.16b,v11.16b,v11.16b,#8
+ add v11.2d,v11.2d,v15.2d
+ umlal v8.2d,v29.2s,v3.s[1]
+ ushr v11.2d,v11.2d,#16
+ umlal v9.2d,v29.2s,v3.s[2]
+ umlal v10.2d,v29.2s,v3.s[3]
+ add v16.2d,v12.2d,v11.2d
+ ins v12.d[0],v16.d[0]
+ st1 {v29.2s},[x10],#8 // put aside smashed m[8*i+5]
+ umlal v12.2d,v28.2s,v0.s[0]
+ ld1 {v11.2d},[x6],#16
+ umlal v13.2d,v28.2s,v0.s[1]
+ umlal v6.2d,v28.2s,v0.s[2]
+ shl v29.2d,v12.2d,#16
+ ext v29.16b,v29.16b,v29.16b,#8
+ umlal v7.2d,v28.2s,v0.s[3]
+ add v29.2d,v29.2d,v12.2d
+ umlal v8.2d,v28.2s,v1.s[0]
+ mul v29.2s,v29.2s,v30.2s
+ umlal v9.2d,v28.2s,v1.s[1]
+ st1 {v28.2s},[x10],#8 // put aside smashed b[8*i+6]
+ umlal v10.2d,v28.2s,v1.s[2]
+ uxtl v29.4s,v29.4h
+ umlal v11.2d,v28.2s,v1.s[3]
+ ldr s28,[x2],#4 // *b++
+ umlal v12.2d,v29.2s,v2.s[0]
+ umlal v13.2d,v29.2s,v2.s[1]
+ uxtl v28.4s,v28.4h
+ umlal v6.2d,v29.2s,v2.s[2]
+ ushr v15.2d,v12.2d,#16
+ umlal v7.2d,v29.2s,v2.s[3]
+ umlal v8.2d,v29.2s,v3.s[0]
+ ext v12.16b,v12.16b,v12.16b,#8
+ add v12.2d,v12.2d,v15.2d
+ umlal v9.2d,v29.2s,v3.s[1]
+ ushr v12.2d,v12.2d,#16
+ umlal v10.2d,v29.2s,v3.s[2]
+ umlal v11.2d,v29.2s,v3.s[3]
+ add v16.2d,v13.2d,v12.2d
+ ins v13.d[0],v16.d[0]
+ st1 {v29.2s},[x10],#8 // put aside smashed m[8*i+6]
+ umlal v13.2d,v28.2s,v0.s[0]
+ ld1 {v12.2d},[x6],#16
+ umlal v6.2d,v28.2s,v0.s[1]
+ umlal v7.2d,v28.2s,v0.s[2]
+ shl v29.2d,v13.2d,#16
+ ext v29.16b,v29.16b,v29.16b,#8
+ umlal v8.2d,v28.2s,v0.s[3]
+ add v29.2d,v29.2d,v13.2d
+ umlal v9.2d,v28.2s,v1.s[0]
+ mul v29.2s,v29.2s,v30.2s
+ umlal v10.2d,v28.2s,v1.s[1]
+ st1 {v28.2s},[x10],#8 // put aside smashed b[8*i+7]
+ umlal v11.2d,v28.2s,v1.s[2]
+ uxtl v29.4s,v29.4h
+ umlal v12.2d,v28.2s,v1.s[3]
+ ld1 {v28.2s},[sp] // pull smashed b[8*i+0]
+ umlal v13.2d,v29.2s,v2.s[0]
+ ld1 {v0.4s,v1.4s},[x1],#32
+ umlal v6.2d,v29.2s,v2.s[1]
+ umlal v7.2d,v29.2s,v2.s[2]
+ mov v5.16b,v13.16b
+ ushr v5.2d,v5.2d,#16
+ ext v13.16b,v13.16b,v13.16b,#8
+ umlal v8.2d,v29.2s,v2.s[3]
+ umlal v9.2d,v29.2s,v3.s[0]
+ add v13.2d,v13.2d,v5.2d
+ umlal v10.2d,v29.2s,v3.s[1]
+ ushr v13.2d,v13.2d,#16
+ eor v15.16b,v15.16b,v15.16b
+ ins v13.d[1],v15.d[0]
+ umlal v11.2d,v29.2s,v3.s[2]
+ umlal v12.2d,v29.2s,v3.s[3]
+ add v6.2d,v6.2d,v13.2d
+ st1 {v29.2s},[x10],#8 // put aside smashed m[8*i+7]
+ add x10,sp,#8 // rewind
+ sub x8,x5,#8
+ b .LNEON_8n_inner
+
+.align 4
+.LNEON_8n_inner:
+ subs x8,x8,#8
+ umlal v6.2d,v28.2s,v0.s[0]
+ ld1 {v13.2d},[x6]
+ umlal v7.2d,v28.2s,v0.s[1]
+ ld1 {v29.2s},[x10],#8 // pull smashed m[8*i+0]
+ umlal v8.2d,v28.2s,v0.s[2]
+ ld1 {v2.4s,v3.4s},[x3],#32
+ umlal v9.2d,v28.2s,v0.s[3]
+ b.eq .LInner_jump
+ add x6,x6,#16 // don't advance in last iteration
+.LInner_jump:
+ umlal v10.2d,v28.2s,v1.s[0]
+ umlal v11.2d,v28.2s,v1.s[1]
+ umlal v12.2d,v28.2s,v1.s[2]
+ umlal v13.2d,v28.2s,v1.s[3]
+ ld1 {v28.2s},[x10],#8 // pull smashed b[8*i+1]
+ umlal v6.2d,v29.2s,v2.s[0]
+ umlal v7.2d,v29.2s,v2.s[1]
+ umlal v8.2d,v29.2s,v2.s[2]
+ umlal v9.2d,v29.2s,v2.s[3]
+ umlal v10.2d,v29.2s,v3.s[0]
+ umlal v11.2d,v29.2s,v3.s[1]
+ umlal v12.2d,v29.2s,v3.s[2]
+ umlal v13.2d,v29.2s,v3.s[3]
+ st1 {v6.2d},[x7],#16
+ umlal v7.2d,v28.2s,v0.s[0]
+ ld1 {v6.2d},[x6]
+ umlal v8.2d,v28.2s,v0.s[1]
+ ld1 {v29.2s},[x10],#8 // pull smashed m[8*i+1]
+ umlal v9.2d,v28.2s,v0.s[2]
+ b.eq .LInner_jump1
+ add x6,x6,#16 // don't advance in last iteration
+.LInner_jump1:
+ umlal v10.2d,v28.2s,v0.s[3]
+ umlal v11.2d,v28.2s,v1.s[0]
+ umlal v12.2d,v28.2s,v1.s[1]
+ umlal v13.2d,v28.2s,v1.s[2]
+ umlal v6.2d,v28.2s,v1.s[3]
+ ld1 {v28.2s},[x10],#8 // pull smashed b[8*i+2]
+ umlal v7.2d,v29.2s,v2.s[0]
+ umlal v8.2d,v29.2s,v2.s[1]
+ umlal v9.2d,v29.2s,v2.s[2]
+ umlal v10.2d,v29.2s,v2.s[3]
+ umlal v11.2d,v29.2s,v3.s[0]
+ umlal v12.2d,v29.2s,v3.s[1]
+ umlal v13.2d,v29.2s,v3.s[2]
+ umlal v6.2d,v29.2s,v3.s[3]
+ st1 {v7.2d},[x7],#16
+ umlal v8.2d,v28.2s,v0.s[0]
+ ld1 {v7.2d},[x6]
+ umlal v9.2d,v28.2s,v0.s[1]
+ ld1 {v29.2s},[x10],#8 // pull smashed m[8*i+2]
+ umlal v10.2d,v28.2s,v0.s[2]
+ b.eq .LInner_jump2
+ add x6,x6,#16 // don't advance in last iteration
+.LInner_jump2:
+ umlal v11.2d,v28.2s,v0.s[3]
+ umlal v12.2d,v28.2s,v1.s[0]
+ umlal v13.2d,v28.2s,v1.s[1]
+ umlal v6.2d,v28.2s,v1.s[2]
+ umlal v7.2d,v28.2s,v1.s[3]
+ ld1 {v28.2s},[x10],#8 // pull smashed b[8*i+3]
+ umlal v8.2d,v29.2s,v2.s[0]
+ umlal v9.2d,v29.2s,v2.s[1]
+ umlal v10.2d,v29.2s,v2.s[2]
+ umlal v11.2d,v29.2s,v2.s[3]
+ umlal v12.2d,v29.2s,v3.s[0]
+ umlal v13.2d,v29.2s,v3.s[1]
+ umlal v6.2d,v29.2s,v3.s[2]
+ umlal v7.2d,v29.2s,v3.s[3]
+ st1 {v8.2d},[x7],#16
+ umlal v9.2d,v28.2s,v0.s[0]
+ ld1 {v8.2d},[x6]
+ umlal v10.2d,v28.2s,v0.s[1]
+ ld1 {v29.2s},[x10],#8 // pull smashed m[8*i+3]
+ umlal v11.2d,v28.2s,v0.s[2]
+ b.eq .LInner_jump3
+ add x6,x6,#16 // don't advance in last iteration
+.LInner_jump3:
+ umlal v12.2d,v28.2s,v0.s[3]
+ umlal v13.2d,v28.2s,v1.s[0]
+ umlal v6.2d,v28.2s,v1.s[1]
+ umlal v7.2d,v28.2s,v1.s[2]
+ umlal v8.2d,v28.2s,v1.s[3]
+ ld1 {v28.2s},[x10],#8 // pull smashed b[8*i+4]
+ umlal v9.2d,v29.2s,v2.s[0]
+ umlal v10.2d,v29.2s,v2.s[1]
+ umlal v11.2d,v29.2s,v2.s[2]
+ umlal v12.2d,v29.2s,v2.s[3]
+ umlal v13.2d,v29.2s,v3.s[0]
+ umlal v6.2d,v29.2s,v3.s[1]
+ umlal v7.2d,v29.2s,v3.s[2]
+ umlal v8.2d,v29.2s,v3.s[3]
+ st1 {v9.2d},[x7],#16
+ umlal v10.2d,v28.2s,v0.s[0]
+ ld1 {v9.2d},[x6]
+ umlal v11.2d,v28.2s,v0.s[1]
+ ld1 {v29.2s},[x10],#8 // pull smashed m[8*i+4]
+ umlal v12.2d,v28.2s,v0.s[2]
+ b.eq .LInner_jump4
+ add x6,x6,#16 // don't advance in last iteration
+.LInner_jump4:
+ umlal v13.2d,v28.2s,v0.s[3]
+ umlal v6.2d,v28.2s,v1.s[0]
+ umlal v7.2d,v28.2s,v1.s[1]
+ umlal v8.2d,v28.2s,v1.s[2]
+ umlal v9.2d,v28.2s,v1.s[3]
+ ld1 {v28.2s},[x10],#8 // pull smashed b[8*i+5]
+ umlal v10.2d,v29.2s,v2.s[0]
+ umlal v11.2d,v29.2s,v2.s[1]
+ umlal v12.2d,v29.2s,v2.s[2]
+ umlal v13.2d,v29.2s,v2.s[3]
+ umlal v6.2d,v29.2s,v3.s[0]
+ umlal v7.2d,v29.2s,v3.s[1]
+ umlal v8.2d,v29.2s,v3.s[2]
+ umlal v9.2d,v29.2s,v3.s[3]
+ st1 {v10.2d},[x7],#16
+ umlal v11.2d,v28.2s,v0.s[0]
+ ld1 {v10.2d},[x6]
+ umlal v12.2d,v28.2s,v0.s[1]
+ ld1 {v29.2s},[x10],#8 // pull smashed m[8*i+5]
+ umlal v13.2d,v28.2s,v0.s[2]
+ b.eq .LInner_jump5
+ add x6,x6,#16 // don't advance in last iteration
+.LInner_jump5:
+ umlal v6.2d,v28.2s,v0.s[3]
+ umlal v7.2d,v28.2s,v1.s[0]
+ umlal v8.2d,v28.2s,v1.s[1]
+ umlal v9.2d,v28.2s,v1.s[2]
+ umlal v10.2d,v28.2s,v1.s[3]
+ ld1 {v28.2s},[x10],#8 // pull smashed b[8*i+6]
+ umlal v11.2d,v29.2s,v2.s[0]
+ umlal v12.2d,v29.2s,v2.s[1]
+ umlal v13.2d,v29.2s,v2.s[2]
+ umlal v6.2d,v29.2s,v2.s[3]
+ umlal v7.2d,v29.2s,v3.s[0]
+ umlal v8.2d,v29.2s,v3.s[1]
+ umlal v9.2d,v29.2s,v3.s[2]
+ umlal v10.2d,v29.2s,v3.s[3]
+ st1 {v11.2d},[x7],#16
+ umlal v12.2d,v28.2s,v0.s[0]
+ ld1 {v11.2d},[x6]
+ umlal v13.2d,v28.2s,v0.s[1]
+ ld1 {v29.2s},[x10],#8 // pull smashed m[8*i+6]
+ umlal v6.2d,v28.2s,v0.s[2]
+ b.eq .LInner_jump6
+ add x6,x6,#16 // don't advance in last iteration
+.LInner_jump6:
+ umlal v7.2d,v28.2s,v0.s[3]
+ umlal v8.2d,v28.2s,v1.s[0]
+ umlal v9.2d,v28.2s,v1.s[1]
+ umlal v10.2d,v28.2s,v1.s[2]
+ umlal v11.2d,v28.2s,v1.s[3]
+ ld1 {v28.2s},[x10],#8 // pull smashed b[8*i+7]
+ umlal v12.2d,v29.2s,v2.s[0]
+ umlal v13.2d,v29.2s,v2.s[1]
+ umlal v6.2d,v29.2s,v2.s[2]
+ umlal v7.2d,v29.2s,v2.s[3]
+ umlal v8.2d,v29.2s,v3.s[0]
+ umlal v9.2d,v29.2s,v3.s[1]
+ umlal v10.2d,v29.2s,v3.s[2]
+ umlal v11.2d,v29.2s,v3.s[3]
+ st1 {v12.2d},[x7],#16
+ umlal v13.2d,v28.2s,v0.s[0]
+ ld1 {v12.2d},[x6]
+ umlal v6.2d,v28.2s,v0.s[1]
+ ld1 {v29.2s},[x10],#8 // pull smashed m[8*i+7]
+ umlal v7.2d,v28.2s,v0.s[2]
+ b.eq .LInner_jump7
+ add x6,x6,#16 // don't advance in last iteration
+.LInner_jump7:
+ umlal v8.2d,v28.2s,v0.s[3]
+ umlal v9.2d,v28.2s,v1.s[0]
+ umlal v10.2d,v28.2s,v1.s[1]
+ umlal v11.2d,v28.2s,v1.s[2]
+ umlal v12.2d,v28.2s,v1.s[3]
+ b.ne .LInner_after_rewind8
+ sub x1,x1,x5,lsl#2 // rewind
+.LInner_after_rewind8:
+ umlal v13.2d,v29.2s,v2.s[0]
+ ld1 {v28.2s},[sp] // pull smashed b[8*i+0]
+ umlal v6.2d,v29.2s,v2.s[1]
+ ld1 {v0.4s,v1.4s},[x1],#32
+ umlal v7.2d,v29.2s,v2.s[2]
+ add x10,sp,#8 // rewind
+ umlal v8.2d,v29.2s,v2.s[3]
+ umlal v9.2d,v29.2s,v3.s[0]
+ umlal v10.2d,v29.2s,v3.s[1]
+ umlal v11.2d,v29.2s,v3.s[2]
+ st1 {v13.2d},[x7],#16
+ umlal v12.2d,v29.2s,v3.s[3]
+
+ bne .LNEON_8n_inner
+ add x6,sp,#128
+ st1 {v6.2d,v7.2d},[x7],#32
+ eor v2.16b,v2.16b,v2.16b // v2
+ st1 {v8.2d,v9.2d},[x7],#32
+ eor v3.16b,v3.16b,v3.16b // v3
+ st1 {v10.2d,v11.2d},[x7],#32
+ st1 {v12.2d},[x7]
+
+ subs x9,x9,#8
+ ld1 {v6.2d,v7.2d},[x6],#32
+ ld1 {v8.2d,v9.2d},[x6],#32
+ ld1 {v10.2d,v11.2d},[x6],#32
+ ld1 {v12.2d,v13.2d},[x6],#32
+
+ b.eq .LInner_8n_jump_2steps
+ sub x3,x3,x5,lsl#2 // rewind
+ b .LNEON_8n_outer
+
+.LInner_8n_jump_2steps:
+ add x7,sp,#128
+ st1 {v2.2d,v3.2d}, [sp],#32 // start wiping stack frame
+ mov v5.16b,v6.16b
+ ushr v15.2d,v6.2d,#16
+ ext v6.16b,v6.16b,v6.16b,#8
+ st1 {v2.2d,v3.2d}, [sp],#32
+ add v6.2d,v6.2d,v15.2d
+ st1 {v2.2d,v3.2d}, [sp],#32
+ ushr v15.2d,v6.2d,#16
+ st1 {v2.2d,v3.2d}, [sp],#32
+ zip1 v6.4h,v5.4h,v6.4h
+ ins v15.d[1],v14.d[0]
+
+ mov x8,x5
+ b .LNEON_tail_entry
+
+.align 4
+.LNEON_tail:
+ add v6.2d,v6.2d,v15.2d
+ mov v5.16b,v6.16b
+ ushr v15.2d,v6.2d,#16
+ ext v6.16b,v6.16b,v6.16b,#8
+ ld1 {v8.2d,v9.2d}, [x6],#32
+ add v6.2d,v6.2d,v15.2d
+ ld1 {v10.2d,v11.2d}, [x6],#32
+ ushr v15.2d,v6.2d,#16
+ ld1 {v12.2d,v13.2d}, [x6],#32
+ zip1 v6.4h,v5.4h,v6.4h
+ ins v15.d[1],v14.d[0]
+
+.LNEON_tail_entry:
+ add v7.2d,v7.2d,v15.2d
+ st1 {v6.s}[0], [x7],#4
+ ushr v15.2d,v7.2d,#16
+ mov v5.16b,v7.16b
+ ext v7.16b,v7.16b,v7.16b,#8
+ add v7.2d,v7.2d,v15.2d
+ ushr v15.2d,v7.2d,#16
+ zip1 v7.4h,v5.4h,v7.4h
+ ins v15.d[1],v14.d[0]
+ add v8.2d,v8.2d,v15.2d
+ st1 {v7.s}[0], [x7],#4
+ ushr v15.2d,v8.2d,#16
+ mov v5.16b,v8.16b
+ ext v8.16b,v8.16b,v8.16b,#8
+ add v8.2d,v8.2d,v15.2d
+ ushr v15.2d,v8.2d,#16
+ zip1 v8.4h,v5.4h,v8.4h
+ ins v15.d[1],v14.d[0]
+ add v9.2d,v9.2d,v15.2d
+ st1 {v8.s}[0], [x7],#4
+ ushr v15.2d,v9.2d,#16
+ mov v5.16b,v9.16b
+ ext v9.16b,v9.16b,v9.16b,#8
+ add v9.2d,v9.2d,v15.2d
+ ushr v15.2d,v9.2d,#16
+ zip1 v9.4h,v5.4h,v9.4h
+ ins v15.d[1],v14.d[0]
+ add v10.2d,v10.2d,v15.2d
+ st1 {v9.s}[0], [x7],#4
+ ushr v15.2d,v10.2d,#16
+ mov v5.16b,v10.16b
+ ext v10.16b,v10.16b,v10.16b,#8
+ add v10.2d,v10.2d,v15.2d
+ ushr v15.2d,v10.2d,#16
+ zip1 v10.4h,v5.4h,v10.4h
+ ins v15.d[1],v14.d[0]
+ add v11.2d,v11.2d,v15.2d
+ st1 {v10.s}[0], [x7],#4
+ ushr v15.2d,v11.2d,#16
+ mov v5.16b,v11.16b
+ ext v11.16b,v11.16b,v11.16b,#8
+ add v11.2d,v11.2d,v15.2d
+ ushr v15.2d,v11.2d,#16
+ zip1 v11.4h,v5.4h,v11.4h
+ ins v15.d[1],v14.d[0]
+ add v12.2d,v12.2d,v15.2d
+ st1 {v11.s}[0], [x7],#4
+ ushr v15.2d,v12.2d,#16
+ mov v5.16b,v12.16b
+ ext v12.16b,v12.16b,v12.16b,#8
+ add v12.2d,v12.2d,v15.2d
+ ushr v15.2d,v12.2d,#16
+ zip1 v12.4h,v5.4h,v12.4h
+ ins v15.d[1],v14.d[0]
+ add v13.2d,v13.2d,v15.2d
+ st1 {v12.s}[0], [x7],#4
+ ushr v15.2d,v13.2d,#16
+ mov v5.16b,v13.16b
+ ext v13.16b,v13.16b,v13.16b,#8
+ add v13.2d,v13.2d,v15.2d
+ ushr v15.2d,v13.2d,#16
+ zip1 v13.4h,v5.4h,v13.4h
+ ins v15.d[1],v14.d[0]
+ ld1 {v6.2d,v7.2d}, [x6],#32
+ subs x8,x8,#8
+ st1 {v13.s}[0], [x7],#4
+ bne .LNEON_tail
+
+ st1 {v15.s}[0], [x7],#4 // top-most bit
+ sub x3,x3,x5,lsl#2 // rewind x3
+ subs x1,sp,#0 // clear carry flag
+ add x2,sp,x5,lsl#2
+
+.LNEON_sub:
+ ldp w4,w5,[x1],#8
+ ldp w6,w7,[x1],#8
+ ldp w8,w9,[x3],#8
+ ldp w10,w11,[x3],#8
+ sbcs w8,w4,w8
+ sbcs w9,w5,w9
+ sbcs w10,w6,w10
+ sbcs w11,w7,w11
+ sub x17,x2,x1
+ stp w8,w9,[x0],#8
+ stp w10,w11,[x0],#8
+ cbnz x17,.LNEON_sub
+
+ ldr w10, [x1] // load top-most bit
+ mov x11,sp
+ eor v0.16b,v0.16b,v0.16b
+ sub x11,x2,x11 // this is num*4
+ eor v1.16b,v1.16b,v1.16b
+ mov x1,sp
+ sub x0,x0,x11 // rewind x0
+ mov x3,x2 // second 3/4th of frame
+ sbcs w10,w10,wzr // result is carry flag
+
+.LNEON_copy_n_zap:
+ ldp w4,w5,[x1],#8
+ ldp w6,w7,[x1],#8
+ ldp w8,w9,[x0],#8
+ ldp w10,w11,[x0]
+ sub x0,x0,#8
+ b.cs .LCopy_1
+ mov w8,w4
+ mov w9,w5
+ mov w10,w6
+ mov w11,w7
+.LCopy_1:
+ st1 {v0.2d,v1.2d}, [x3],#32 // wipe
+ st1 {v0.2d,v1.2d}, [x3],#32 // wipe
+ ldp w4,w5,[x1],#8
+ ldp w6,w7,[x1],#8
+ stp w8,w9,[x0],#8
+ stp w10,w11,[x0],#8
+ sub x1,x1,#32
+ ldp w8,w9,[x0],#8
+ ldp w10,w11,[x0]
+ sub x0,x0,#8
+ b.cs .LCopy_2
+ mov w8, w4
+ mov w9, w5
+ mov w10, w6
+ mov w11, w7
+.LCopy_2:
+ st1 {v0.2d,v1.2d}, [x1],#32 // wipe
+ st1 {v0.2d,v1.2d}, [x3],#32 // wipe
+ sub x17,x2,x1 // preserves carry
+ stp w8,w9,[x0],#8
+ stp w10,w11,[x0],#8
+ cbnz x17,.LNEON_copy_n_zap
+
+ mov sp,x16
+ ldp d14,d15,[sp,#64]
+ ldp d12,d13,[sp,#48]
+ ldp d10,d11,[sp,#32]
+ ldp d8,d9,[sp,#16]
+ ldr x29,[sp],#80
+ ret // bx lr
+
+.size bn_mul8x_mont_neon,.-bn_mul8x_mont_neon
+.type __bn_sqr8x_mont,%function
+.align 5
+__bn_sqr8x_mont:
+ cmp x1,x2
+ b.ne __bn_mul4x_mont
+.Lsqr8x_mont:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-128]!
+ add x29,sp,#0
+ stp x19,x20,[sp,#16]
+ stp x21,x22,[sp,#32]
+ stp x23,x24,[sp,#48]
+ stp x25,x26,[sp,#64]
+ stp x27,x28,[sp,#80]
+ stp x0,x3,[sp,#96] // offload rp and np
+
+ ldp x6,x7,[x1,#8*0]
+ ldp x8,x9,[x1,#8*2]
+ ldp x10,x11,[x1,#8*4]
+ ldp x12,x13,[x1,#8*6]
+
+ sub x2,sp,x5,lsl#4
+ lsl x5,x5,#3
+ ldr x4,[x4] // *n0
+ mov sp,x2 // alloca
+ sub x27,x5,#8*8
+ b .Lsqr8x_zero_start
+
+.Lsqr8x_zero:
+ sub x27,x27,#8*8
+ stp xzr,xzr,[x2,#8*0]
+ stp xzr,xzr,[x2,#8*2]
+ stp xzr,xzr,[x2,#8*4]
+ stp xzr,xzr,[x2,#8*6]
+.Lsqr8x_zero_start:
+ stp xzr,xzr,[x2,#8*8]
+ stp xzr,xzr,[x2,#8*10]
+ stp xzr,xzr,[x2,#8*12]
+ stp xzr,xzr,[x2,#8*14]
+ add x2,x2,#8*16
+ cbnz x27,.Lsqr8x_zero
+
+ add x3,x1,x5
+ add x1,x1,#8*8
+ mov x19,xzr
+ mov x20,xzr
+ mov x21,xzr
+ mov x22,xzr
+ mov x23,xzr
+ mov x24,xzr
+ mov x25,xzr
+ mov x26,xzr
+ mov x2,sp
+ str x4,[x29,#112] // offload n0
+
+ // Multiply everything but a[i]*a[i]
+.align 4
+.Lsqr8x_outer_loop:
+ // a[1]a[0] (i)
+ // a[2]a[0]
+ // a[3]a[0]
+ // a[4]a[0]
+ // a[5]a[0]
+ // a[6]a[0]
+ // a[7]a[0]
+ // a[2]a[1] (ii)
+ // a[3]a[1]
+ // a[4]a[1]
+ // a[5]a[1]
+ // a[6]a[1]
+ // a[7]a[1]
+ // a[3]a[2] (iii)
+ // a[4]a[2]
+ // a[5]a[2]
+ // a[6]a[2]
+ // a[7]a[2]
+ // a[4]a[3] (iv)
+ // a[5]a[3]
+ // a[6]a[3]
+ // a[7]a[3]
+ // a[5]a[4] (v)
+ // a[6]a[4]
+ // a[7]a[4]
+ // a[6]a[5] (vi)
+ // a[7]a[5]
+ // a[7]a[6] (vii)
+
+ mul x14,x7,x6 // lo(a[1..7]*a[0]) (i)
+ mul x15,x8,x6
+ mul x16,x9,x6
+ mul x17,x10,x6
+ adds x20,x20,x14 // t[1]+lo(a[1]*a[0])
+ mul x14,x11,x6
+ adcs x21,x21,x15
+ mul x15,x12,x6
+ adcs x22,x22,x16
+ mul x16,x13,x6
+ adcs x23,x23,x17
+ umulh x17,x7,x6 // hi(a[1..7]*a[0])
+ adcs x24,x24,x14
+ umulh x14,x8,x6
+ adcs x25,x25,x15
+ umulh x15,x9,x6
+ adcs x26,x26,x16
+ umulh x16,x10,x6
+ stp x19,x20,[x2],#8*2 // t[0..1]
+ adc x19,xzr,xzr // t[8]
+ adds x21,x21,x17 // t[2]+lo(a[1]*a[0])
+ umulh x17,x11,x6
+ adcs x22,x22,x14
+ umulh x14,x12,x6
+ adcs x23,x23,x15
+ umulh x15,x13,x6
+ adcs x24,x24,x16
+ mul x16,x8,x7 // lo(a[2..7]*a[1]) (ii)
+ adcs x25,x25,x17
+ mul x17,x9,x7
+ adcs x26,x26,x14
+ mul x14,x10,x7
+ adc x19,x19,x15
+
+ mul x15,x11,x7
+ adds x22,x22,x16
+ mul x16,x12,x7
+ adcs x23,x23,x17
+ mul x17,x13,x7
+ adcs x24,x24,x14
+ umulh x14,x8,x7 // hi(a[2..7]*a[1])
+ adcs x25,x25,x15
+ umulh x15,x9,x7
+ adcs x26,x26,x16
+ umulh x16,x10,x7
+ adcs x19,x19,x17
+ umulh x17,x11,x7
+ stp x21,x22,[x2],#8*2 // t[2..3]
+ adc x20,xzr,xzr // t[9]
+ adds x23,x23,x14
+ umulh x14,x12,x7
+ adcs x24,x24,x15
+ umulh x15,x13,x7
+ adcs x25,x25,x16
+ mul x16,x9,x8 // lo(a[3..7]*a[2]) (iii)
+ adcs x26,x26,x17
+ mul x17,x10,x8
+ adcs x19,x19,x14
+ mul x14,x11,x8
+ adc x20,x20,x15
+
+ mul x15,x12,x8
+ adds x24,x24,x16
+ mul x16,x13,x8
+ adcs x25,x25,x17
+ umulh x17,x9,x8 // hi(a[3..7]*a[2])
+ adcs x26,x26,x14
+ umulh x14,x10,x8
+ adcs x19,x19,x15
+ umulh x15,x11,x8
+ adcs x20,x20,x16
+ umulh x16,x12,x8
+ stp x23,x24,[x2],#8*2 // t[4..5]
+ adc x21,xzr,xzr // t[10]
+ adds x25,x25,x17
+ umulh x17,x13,x8
+ adcs x26,x26,x14
+ mul x14,x10,x9 // lo(a[4..7]*a[3]) (iv)
+ adcs x19,x19,x15
+ mul x15,x11,x9
+ adcs x20,x20,x16
+ mul x16,x12,x9
+ adc x21,x21,x17
+
+ mul x17,x13,x9
+ adds x26,x26,x14
+ umulh x14,x10,x9 // hi(a[4..7]*a[3])
+ adcs x19,x19,x15
+ umulh x15,x11,x9
+ adcs x20,x20,x16
+ umulh x16,x12,x9
+ adcs x21,x21,x17
+ umulh x17,x13,x9
+ stp x25,x26,[x2],#8*2 // t[6..7]
+ adc x22,xzr,xzr // t[11]
+ adds x19,x19,x14
+ mul x14,x11,x10 // lo(a[5..7]*a[4]) (v)
+ adcs x20,x20,x15
+ mul x15,x12,x10
+ adcs x21,x21,x16
+ mul x16,x13,x10
+ adc x22,x22,x17
+
+ umulh x17,x11,x10 // hi(a[5..7]*a[4])
+ adds x20,x20,x14
+ umulh x14,x12,x10
+ adcs x21,x21,x15
+ umulh x15,x13,x10
+ adcs x22,x22,x16
+ mul x16,x12,x11 // lo(a[6..7]*a[5]) (vi)
+ adc x23,xzr,xzr // t[12]
+ adds x21,x21,x17
+ mul x17,x13,x11
+ adcs x22,x22,x14
+ umulh x14,x12,x11 // hi(a[6..7]*a[5])
+ adc x23,x23,x15
+
+ umulh x15,x13,x11
+ adds x22,x22,x16
+ mul x16,x13,x12 // lo(a[7]*a[6]) (vii)
+ adcs x23,x23,x17
+ umulh x17,x13,x12 // hi(a[7]*a[6])
+ adc x24,xzr,xzr // t[13]
+ adds x23,x23,x14
+ sub x27,x3,x1 // done yet?
+ adc x24,x24,x15
+
+ adds x24,x24,x16
+ sub x14,x3,x5 // rewinded ap
+ adc x25,xzr,xzr // t[14]
+ add x25,x25,x17
+
+ cbz x27,.Lsqr8x_outer_break
+
+ mov x4,x6
+ ldp x6,x7,[x2,#8*0]
+ ldp x8,x9,[x2,#8*2]
+ ldp x10,x11,[x2,#8*4]
+ ldp x12,x13,[x2,#8*6]
+ adds x19,x19,x6
+ adcs x20,x20,x7
+ ldp x6,x7,[x1,#8*0]
+ adcs x21,x21,x8
+ adcs x22,x22,x9
+ ldp x8,x9,[x1,#8*2]
+ adcs x23,x23,x10
+ adcs x24,x24,x11
+ ldp x10,x11,[x1,#8*4]
+ adcs x25,x25,x12
+ mov x0,x1
+ adcs x26,xzr,x13
+ ldp x12,x13,[x1,#8*6]
+ add x1,x1,#8*8
+ //adc x28,xzr,xzr // moved below
+ mov x27,#-8*8
+
+ // a[8]a[0]
+ // a[9]a[0]
+ // a[a]a[0]
+ // a[b]a[0]
+ // a[c]a[0]
+ // a[d]a[0]
+ // a[e]a[0]
+ // a[f]a[0]
+ // a[8]a[1]
+ // a[f]a[1]........................
+ // a[8]a[2]
+ // a[f]a[2]........................
+ // a[8]a[3]
+ // a[f]a[3]........................
+ // a[8]a[4]
+ // a[f]a[4]........................
+ // a[8]a[5]
+ // a[f]a[5]........................
+ // a[8]a[6]
+ // a[f]a[6]........................
+ // a[8]a[7]
+ // a[f]a[7]........................
+.Lsqr8x_mul:
+ mul x14,x6,x4
+ adc x28,xzr,xzr // carry bit, modulo-scheduled
+ mul x15,x7,x4
+ add x27,x27,#8
+ mul x16,x8,x4
+ mul x17,x9,x4
+ adds x19,x19,x14
+ mul x14,x10,x4
+ adcs x20,x20,x15
+ mul x15,x11,x4
+ adcs x21,x21,x16
+ mul x16,x12,x4
+ adcs x22,x22,x17
+ mul x17,x13,x4
+ adcs x23,x23,x14
+ umulh x14,x6,x4
+ adcs x24,x24,x15
+ umulh x15,x7,x4
+ adcs x25,x25,x16
+ umulh x16,x8,x4
+ adcs x26,x26,x17
+ umulh x17,x9,x4
+ adc x28,x28,xzr
+ str x19,[x2],#8
+ adds x19,x20,x14
+ umulh x14,x10,x4
+ adcs x20,x21,x15
+ umulh x15,x11,x4
+ adcs x21,x22,x16
+ umulh x16,x12,x4
+ adcs x22,x23,x17
+ umulh x17,x13,x4
+ ldr x4,[x0,x27]
+ adcs x23,x24,x14
+ adcs x24,x25,x15
+ adcs x25,x26,x16
+ adcs x26,x28,x17
+ //adc x28,xzr,xzr // moved above
+ cbnz x27,.Lsqr8x_mul
+ // note that carry flag is guaranteed
+ // to be zero at this point
+ cmp x1,x3 // done yet?
+ b.eq .Lsqr8x_break
+
+ ldp x6,x7,[x2,#8*0]
+ ldp x8,x9,[x2,#8*2]
+ ldp x10,x11,[x2,#8*4]
+ ldp x12,x13,[x2,#8*6]
+ adds x19,x19,x6
+ ldur x4,[x0,#-8*8]
+ adcs x20,x20,x7
+ ldp x6,x7,[x1,#8*0]
+ adcs x21,x21,x8
+ adcs x22,x22,x9
+ ldp x8,x9,[x1,#8*2]
+ adcs x23,x23,x10
+ adcs x24,x24,x11
+ ldp x10,x11,[x1,#8*4]
+ adcs x25,x25,x12
+ mov x27,#-8*8
+ adcs x26,x26,x13
+ ldp x12,x13,[x1,#8*6]
+ add x1,x1,#8*8
+ //adc x28,xzr,xzr // moved above
+ b .Lsqr8x_mul
+
+.align 4
+.Lsqr8x_break:
+ ldp x6,x7,[x0,#8*0]
+ add x1,x0,#8*8
+ ldp x8,x9,[x0,#8*2]
+ sub x14,x3,x1 // is it last iteration?
+ ldp x10,x11,[x0,#8*4]
+ sub x15,x2,x14
+ ldp x12,x13,[x0,#8*6]
+ cbz x14,.Lsqr8x_outer_loop
+
+ stp x19,x20,[x2,#8*0]
+ ldp x19,x20,[x15,#8*0]
+ stp x21,x22,[x2,#8*2]
+ ldp x21,x22,[x15,#8*2]
+ stp x23,x24,[x2,#8*4]
+ ldp x23,x24,[x15,#8*4]
+ stp x25,x26,[x2,#8*6]
+ mov x2,x15
+ ldp x25,x26,[x15,#8*6]
+ b .Lsqr8x_outer_loop
+
+.align 4
+.Lsqr8x_outer_break:
+ // Now multiply above result by 2 and add a[n-1]*a[n-1]|...|a[0]*a[0]
+ ldp x7,x9,[x14,#8*0] // recall that x14 is &a[0]
+ ldp x15,x16,[sp,#8*1]
+ ldp x11,x13,[x14,#8*2]
+ add x1,x14,#8*4
+ ldp x17,x14,[sp,#8*3]
+
+ stp x19,x20,[x2,#8*0]
+ mul x19,x7,x7
+ stp x21,x22,[x2,#8*2]
+ umulh x7,x7,x7
+ stp x23,x24,[x2,#8*4]
+ mul x8,x9,x9
+ stp x25,x26,[x2,#8*6]
+ mov x2,sp
+ umulh x9,x9,x9
+ adds x20,x7,x15,lsl#1
+ extr x15,x16,x15,#63
+ sub x27,x5,#8*4
+
+.Lsqr4x_shift_n_add:
+ adcs x21,x8,x15
+ extr x16,x17,x16,#63
+ sub x27,x27,#8*4
+ adcs x22,x9,x16
+ ldp x15,x16,[x2,#8*5]
+ mul x10,x11,x11
+ ldp x7,x9,[x1],#8*2
+ umulh x11,x11,x11
+ mul x12,x13,x13
+ umulh x13,x13,x13
+ extr x17,x14,x17,#63
+ stp x19,x20,[x2,#8*0]
+ adcs x23,x10,x17
+ extr x14,x15,x14,#63
+ stp x21,x22,[x2,#8*2]
+ adcs x24,x11,x14
+ ldp x17,x14,[x2,#8*7]
+ extr x15,x16,x15,#63
+ adcs x25,x12,x15
+ extr x16,x17,x16,#63
+ adcs x26,x13,x16
+ ldp x15,x16,[x2,#8*9]
+ mul x6,x7,x7
+ ldp x11,x13,[x1],#8*2
+ umulh x7,x7,x7
+ mul x8,x9,x9
+ umulh x9,x9,x9
+ stp x23,x24,[x2,#8*4]
+ extr x17,x14,x17,#63
+ stp x25,x26,[x2,#8*6]
+ add x2,x2,#8*8
+ adcs x19,x6,x17
+ extr x14,x15,x14,#63
+ adcs x20,x7,x14
+ ldp x17,x14,[x2,#8*3]
+ extr x15,x16,x15,#63
+ cbnz x27,.Lsqr4x_shift_n_add
+ ldp x1,x4,[x29,#104] // pull np and n0
+
+ adcs x21,x8,x15
+ extr x16,x17,x16,#63
+ adcs x22,x9,x16
+ ldp x15,x16,[x2,#8*5]
+ mul x10,x11,x11
+ umulh x11,x11,x11
+ stp x19,x20,[x2,#8*0]
+ mul x12,x13,x13
+ umulh x13,x13,x13
+ stp x21,x22,[x2,#8*2]
+ extr x17,x14,x17,#63
+ adcs x23,x10,x17
+ extr x14,x15,x14,#63
+ ldp x19,x20,[sp,#8*0]
+ adcs x24,x11,x14
+ extr x15,x16,x15,#63
+ ldp x6,x7,[x1,#8*0]
+ adcs x25,x12,x15
+ extr x16,xzr,x16,#63
+ ldp x8,x9,[x1,#8*2]
+ adc x26,x13,x16
+ ldp x10,x11,[x1,#8*4]
+
+ // Reduce by 512 bits per iteration
+ mul x28,x4,x19 // t[0]*n0
+ ldp x12,x13,[x1,#8*6]
+ add x3,x1,x5
+ ldp x21,x22,[sp,#8*2]
+ stp x23,x24,[x2,#8*4]
+ ldp x23,x24,[sp,#8*4]
+ stp x25,x26,[x2,#8*6]
+ ldp x25,x26,[sp,#8*6]
+ add x1,x1,#8*8
+ mov x30,xzr // initial top-most carry
+ mov x2,sp
+ mov x27,#8
+
+.Lsqr8x_reduction:
+ // (*) mul x14,x6,x28 // lo(n[0-7])*lo(t[0]*n0)
+ mul x15,x7,x28
+ sub x27,x27,#1
+ mul x16,x8,x28
+ str x28,[x2],#8 // put aside t[0]*n0 for tail processing
+ mul x17,x9,x28
+ // (*) adds xzr,x19,x14
+ subs xzr,x19,#1 // (*)
+ mul x14,x10,x28
+ adcs x19,x20,x15
+ mul x15,x11,x28
+ adcs x20,x21,x16
+ mul x16,x12,x28
+ adcs x21,x22,x17
+ mul x17,x13,x28
+ adcs x22,x23,x14
+ umulh x14,x6,x28 // hi(n[0-7])*lo(t[0]*n0)
+ adcs x23,x24,x15
+ umulh x15,x7,x28
+ adcs x24,x25,x16
+ umulh x16,x8,x28
+ adcs x25,x26,x17
+ umulh x17,x9,x28
+ adc x26,xzr,xzr
+ adds x19,x19,x14
+ umulh x14,x10,x28
+ adcs x20,x20,x15
+ umulh x15,x11,x28
+ adcs x21,x21,x16
+ umulh x16,x12,x28
+ adcs x22,x22,x17
+ umulh x17,x13,x28
+ mul x28,x4,x19 // next t[0]*n0
+ adcs x23,x23,x14
+ adcs x24,x24,x15
+ adcs x25,x25,x16
+ adc x26,x26,x17
+ cbnz x27,.Lsqr8x_reduction
+
+ ldp x14,x15,[x2,#8*0]
+ ldp x16,x17,[x2,#8*2]
+ mov x0,x2
+ sub x27,x3,x1 // done yet?
+ adds x19,x19,x14
+ adcs x20,x20,x15
+ ldp x14,x15,[x2,#8*4]
+ adcs x21,x21,x16
+ adcs x22,x22,x17
+ ldp x16,x17,[x2,#8*6]
+ adcs x23,x23,x14
+ adcs x24,x24,x15
+ adcs x25,x25,x16
+ adcs x26,x26,x17
+ //adc x28,xzr,xzr // moved below
+ cbz x27,.Lsqr8x8_post_condition
+
+ ldur x4,[x2,#-8*8]
+ ldp x6,x7,[x1,#8*0]
+ ldp x8,x9,[x1,#8*2]
+ ldp x10,x11,[x1,#8*4]
+ mov x27,#-8*8
+ ldp x12,x13,[x1,#8*6]
+ add x1,x1,#8*8
+
+.Lsqr8x_tail:
+ mul x14,x6,x4
+ adc x28,xzr,xzr // carry bit, modulo-scheduled
+ mul x15,x7,x4
+ add x27,x27,#8
+ mul x16,x8,x4
+ mul x17,x9,x4
+ adds x19,x19,x14
+ mul x14,x10,x4
+ adcs x20,x20,x15
+ mul x15,x11,x4
+ adcs x21,x21,x16
+ mul x16,x12,x4
+ adcs x22,x22,x17
+ mul x17,x13,x4
+ adcs x23,x23,x14
+ umulh x14,x6,x4
+ adcs x24,x24,x15
+ umulh x15,x7,x4
+ adcs x25,x25,x16
+ umulh x16,x8,x4
+ adcs x26,x26,x17
+ umulh x17,x9,x4
+ adc x28,x28,xzr
+ str x19,[x2],#8
+ adds x19,x20,x14
+ umulh x14,x10,x4
+ adcs x20,x21,x15
+ umulh x15,x11,x4
+ adcs x21,x22,x16
+ umulh x16,x12,x4
+ adcs x22,x23,x17
+ umulh x17,x13,x4
+ ldr x4,[x0,x27]
+ adcs x23,x24,x14
+ adcs x24,x25,x15
+ adcs x25,x26,x16
+ adcs x26,x28,x17
+ //adc x28,xzr,xzr // moved above
+ cbnz x27,.Lsqr8x_tail
+ // note that carry flag is guaranteed
+ // to be zero at this point
+ ldp x6,x7,[x2,#8*0]
+ sub x27,x3,x1 // done yet?
+ sub x16,x3,x5 // rewinded np
+ ldp x8,x9,[x2,#8*2]
+ ldp x10,x11,[x2,#8*4]
+ ldp x12,x13,[x2,#8*6]
+ cbz x27,.Lsqr8x_tail_break
+
+ ldur x4,[x0,#-8*8]
+ adds x19,x19,x6
+ adcs x20,x20,x7
+ ldp x6,x7,[x1,#8*0]
+ adcs x21,x21,x8
+ adcs x22,x22,x9
+ ldp x8,x9,[x1,#8*2]
+ adcs x23,x23,x10
+ adcs x24,x24,x11
+ ldp x10,x11,[x1,#8*4]
+ adcs x25,x25,x12
+ mov x27,#-8*8
+ adcs x26,x26,x13
+ ldp x12,x13,[x1,#8*6]
+ add x1,x1,#8*8
+ //adc x28,xzr,xzr // moved above
+ b .Lsqr8x_tail
+
+.align 4
+.Lsqr8x_tail_break:
+ ldr x4,[x29,#112] // pull n0
+ add x27,x2,#8*8 // end of current t[num] window
+
+ subs xzr,x30,#1 // "move" top-most carry to carry bit
+ adcs x14,x19,x6
+ adcs x15,x20,x7
+ ldp x19,x20,[x0,#8*0]
+ adcs x21,x21,x8
+ ldp x6,x7,[x16,#8*0] // recall that x16 is &n[0]
+ adcs x22,x22,x9
+ ldp x8,x9,[x16,#8*2]
+ adcs x23,x23,x10
+ adcs x24,x24,x11
+ ldp x10,x11,[x16,#8*4]
+ adcs x25,x25,x12
+ adcs x26,x26,x13
+ ldp x12,x13,[x16,#8*6]
+ add x1,x16,#8*8
+ adc x30,xzr,xzr // top-most carry
+ mul x28,x4,x19
+ stp x14,x15,[x2,#8*0]
+ stp x21,x22,[x2,#8*2]
+ ldp x21,x22,[x0,#8*2]
+ stp x23,x24,[x2,#8*4]
+ ldp x23,x24,[x0,#8*4]
+ cmp x27,x29 // did we hit the bottom?
+ stp x25,x26,[x2,#8*6]
+ mov x2,x0 // slide the window
+ ldp x25,x26,[x0,#8*6]
+ mov x27,#8
+ b.ne .Lsqr8x_reduction
+
+ // Final step. We see if result is larger than modulus, and
+ // if it is, subtract the modulus. But comparison implies
+ // subtraction. So we subtract modulus, see if it borrowed,
+ // and conditionally copy original value.
+ ldr x0,[x29,#96] // pull rp
+ add x2,x2,#8*8
+ subs x14,x19,x6
+ sbcs x15,x20,x7
+ sub x27,x5,#8*8
+ mov x3,x0 // x0 copy
+
+.Lsqr8x_sub:
+ sbcs x16,x21,x8
+ ldp x6,x7,[x1,#8*0]
+ sbcs x17,x22,x9
+ stp x14,x15,[x0,#8*0]
+ sbcs x14,x23,x10
+ ldp x8,x9,[x1,#8*2]
+ sbcs x15,x24,x11
+ stp x16,x17,[x0,#8*2]
+ sbcs x16,x25,x12
+ ldp x10,x11,[x1,#8*4]
+ sbcs x17,x26,x13
+ ldp x12,x13,[x1,#8*6]
+ add x1,x1,#8*8
+ ldp x19,x20,[x2,#8*0]
+ sub x27,x27,#8*8
+ ldp x21,x22,[x2,#8*2]
+ ldp x23,x24,[x2,#8*4]
+ ldp x25,x26,[x2,#8*6]
+ add x2,x2,#8*8
+ stp x14,x15,[x0,#8*4]
+ sbcs x14,x19,x6
+ stp x16,x17,[x0,#8*6]
+ add x0,x0,#8*8
+ sbcs x15,x20,x7
+ cbnz x27,.Lsqr8x_sub
+
+ sbcs x16,x21,x8
+ mov x2,sp
+ add x1,sp,x5
+ ldp x6,x7,[x3,#8*0]
+ sbcs x17,x22,x9
+ stp x14,x15,[x0,#8*0]
+ sbcs x14,x23,x10
+ ldp x8,x9,[x3,#8*2]
+ sbcs x15,x24,x11
+ stp x16,x17,[x0,#8*2]
+ sbcs x16,x25,x12
+ ldp x19,x20,[x1,#8*0]
+ sbcs x17,x26,x13
+ ldp x21,x22,[x1,#8*2]
+ sbcs xzr,x30,xzr // did it borrow?
+ ldr x30,[x29,#8] // pull return address
+ stp x14,x15,[x0,#8*4]
+ stp x16,x17,[x0,#8*6]
+
+ sub x27,x5,#8*4
+.Lsqr4x_cond_copy:
+ sub x27,x27,#8*4
+ csel x14,x19,x6,lo
+ stp xzr,xzr,[x2,#8*0]
+ csel x15,x20,x7,lo
+ ldp x6,x7,[x3,#8*4]
+ ldp x19,x20,[x1,#8*4]
+ csel x16,x21,x8,lo
+ stp xzr,xzr,[x2,#8*2]
+ add x2,x2,#8*4
+ csel x17,x22,x9,lo
+ ldp x8,x9,[x3,#8*6]
+ ldp x21,x22,[x1,#8*6]
+ add x1,x1,#8*4
+ stp x14,x15,[x3,#8*0]
+ stp x16,x17,[x3,#8*2]
+ add x3,x3,#8*4
+ stp xzr,xzr,[x1,#8*0]
+ stp xzr,xzr,[x1,#8*2]
+ cbnz x27,.Lsqr4x_cond_copy
+
+ csel x14,x19,x6,lo
+ stp xzr,xzr,[x2,#8*0]
+ csel x15,x20,x7,lo
+ stp xzr,xzr,[x2,#8*2]
+ csel x16,x21,x8,lo
+ csel x17,x22,x9,lo
+ stp x14,x15,[x3,#8*0]
+ stp x16,x17,[x3,#8*2]
+
+ b .Lsqr8x_done
+
+.align 4
+.Lsqr8x8_post_condition:
+ adc x28,xzr,xzr
+ ldr x30,[x29,#8] // pull return address
+ // x19-7,x28 hold result, x6-7 hold modulus
+ subs x6,x19,x6
+ ldr x1,[x29,#96] // pull rp
+ sbcs x7,x20,x7
+ stp xzr,xzr,[sp,#8*0]
+ sbcs x8,x21,x8
+ stp xzr,xzr,[sp,#8*2]
+ sbcs x9,x22,x9
+ stp xzr,xzr,[sp,#8*4]
+ sbcs x10,x23,x10
+ stp xzr,xzr,[sp,#8*6]
+ sbcs x11,x24,x11
+ stp xzr,xzr,[sp,#8*8]
+ sbcs x12,x25,x12
+ stp xzr,xzr,[sp,#8*10]
+ sbcs x13,x26,x13
+ stp xzr,xzr,[sp,#8*12]
+ sbcs x28,x28,xzr // did it borrow?
+ stp xzr,xzr,[sp,#8*14]
+
+ // x6-7 hold result-modulus
+ csel x6,x19,x6,lo
+ csel x7,x20,x7,lo
+ csel x8,x21,x8,lo
+ csel x9,x22,x9,lo
+ stp x6,x7,[x1,#8*0]
+ csel x10,x23,x10,lo
+ csel x11,x24,x11,lo
+ stp x8,x9,[x1,#8*2]
+ csel x12,x25,x12,lo
+ csel x13,x26,x13,lo
+ stp x10,x11,[x1,#8*4]
+ stp x12,x13,[x1,#8*6]
+
+.Lsqr8x_done:
+ ldp x19,x20,[x29,#16]
+ mov sp,x29
+ ldp x21,x22,[x29,#32]
+ mov x0,#1
+ ldp x23,x24,[x29,#48]
+ ldp x25,x26,[x29,#64]
+ ldp x27,x28,[x29,#80]
+ ldr x29,[sp],#128
+.inst 0xd50323bf // autiasp
+ ret
+.size __bn_sqr8x_mont,.-__bn_sqr8x_mont
+.type __bn_mul4x_mont,%function
+.align 5
+__bn_mul4x_mont:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-128]!
+ add x29,sp,#0
+ stp x19,x20,[sp,#16]
+ stp x21,x22,[sp,#32]
+ stp x23,x24,[sp,#48]
+ stp x25,x26,[sp,#64]
+ stp x27,x28,[sp,#80]
+
+ sub x26,sp,x5,lsl#3
+ lsl x5,x5,#3
+ ldr x4,[x4] // *n0
+ sub sp,x26,#8*4 // alloca
+
+ add x10,x2,x5
+ add x27,x1,x5
+ stp x0,x10,[x29,#96] // offload rp and &b[num]
+
+ ldr x24,[x2,#8*0] // b[0]
+ ldp x6,x7,[x1,#8*0] // a[0..3]
+ ldp x8,x9,[x1,#8*2]
+ add x1,x1,#8*4
+ mov x19,xzr
+ mov x20,xzr
+ mov x21,xzr
+ mov x22,xzr
+ ldp x14,x15,[x3,#8*0] // n[0..3]
+ ldp x16,x17,[x3,#8*2]
+ adds x3,x3,#8*4 // clear carry bit
+ mov x0,xzr
+ mov x28,#0
+ mov x26,sp
+
+.Loop_mul4x_1st_reduction:
+ mul x10,x6,x24 // lo(a[0..3]*b[0])
+ adc x0,x0,xzr // modulo-scheduled
+ mul x11,x7,x24
+ add x28,x28,#8
+ mul x12,x8,x24
+ and x28,x28,#31
+ mul x13,x9,x24
+ adds x19,x19,x10
+ umulh x10,x6,x24 // hi(a[0..3]*b[0])
+ adcs x20,x20,x11
+ mul x25,x19,x4 // t[0]*n0
+ adcs x21,x21,x12
+ umulh x11,x7,x24
+ adcs x22,x22,x13
+ umulh x12,x8,x24
+ adc x23,xzr,xzr
+ umulh x13,x9,x24
+ ldr x24,[x2,x28] // next b[i] (or b[0])
+ adds x20,x20,x10
+ // (*) mul x10,x14,x25 // lo(n[0..3]*t[0]*n0)
+ str x25,[x26],#8 // put aside t[0]*n0 for tail processing
+ adcs x21,x21,x11
+ mul x11,x15,x25
+ adcs x22,x22,x12
+ mul x12,x16,x25
+ adc x23,x23,x13 // can't overflow
+ mul x13,x17,x25
+ // (*) adds xzr,x19,x10
+ subs xzr,x19,#1 // (*)
+ umulh x10,x14,x25 // hi(n[0..3]*t[0]*n0)
+ adcs x19,x20,x11
+ umulh x11,x15,x25
+ adcs x20,x21,x12
+ umulh x12,x16,x25
+ adcs x21,x22,x13
+ umulh x13,x17,x25
+ adcs x22,x23,x0
+ adc x0,xzr,xzr
+ adds x19,x19,x10
+ sub x10,x27,x1
+ adcs x20,x20,x11
+ adcs x21,x21,x12
+ adcs x22,x22,x13
+ //adc x0,x0,xzr
+ cbnz x28,.Loop_mul4x_1st_reduction
+
+ cbz x10,.Lmul4x4_post_condition
+
+ ldp x6,x7,[x1,#8*0] // a[4..7]
+ ldp x8,x9,[x1,#8*2]
+ add x1,x1,#8*4
+ ldr x25,[sp] // a[0]*n0
+ ldp x14,x15,[x3,#8*0] // n[4..7]
+ ldp x16,x17,[x3,#8*2]
+ add x3,x3,#8*4
+
+.Loop_mul4x_1st_tail:
+ mul x10,x6,x24 // lo(a[4..7]*b[i])
+ adc x0,x0,xzr // modulo-scheduled
+ mul x11,x7,x24
+ add x28,x28,#8
+ mul x12,x8,x24
+ and x28,x28,#31
+ mul x13,x9,x24
+ adds x19,x19,x10
+ umulh x10,x6,x24 // hi(a[4..7]*b[i])
+ adcs x20,x20,x11
+ umulh x11,x7,x24
+ adcs x21,x21,x12
+ umulh x12,x8,x24
+ adcs x22,x22,x13
+ umulh x13,x9,x24
+ adc x23,xzr,xzr
+ ldr x24,[x2,x28] // next b[i] (or b[0])
+ adds x20,x20,x10
+ mul x10,x14,x25 // lo(n[4..7]*a[0]*n0)
+ adcs x21,x21,x11
+ mul x11,x15,x25
+ adcs x22,x22,x12
+ mul x12,x16,x25
+ adc x23,x23,x13 // can't overflow
+ mul x13,x17,x25
+ adds x19,x19,x10
+ umulh x10,x14,x25 // hi(n[4..7]*a[0]*n0)
+ adcs x20,x20,x11
+ umulh x11,x15,x25
+ adcs x21,x21,x12
+ umulh x12,x16,x25
+ adcs x22,x22,x13
+ adcs x23,x23,x0
+ umulh x13,x17,x25
+ adc x0,xzr,xzr
+ ldr x25,[sp,x28] // next t[0]*n0
+ str x19,[x26],#8 // result!!!
+ adds x19,x20,x10
+ sub x10,x27,x1 // done yet?
+ adcs x20,x21,x11
+ adcs x21,x22,x12
+ adcs x22,x23,x13
+ //adc x0,x0,xzr
+ cbnz x28,.Loop_mul4x_1st_tail
+
+ sub x11,x27,x5 // rewinded x1
+ cbz x10,.Lmul4x_proceed
+
+ ldp x6,x7,[x1,#8*0]
+ ldp x8,x9,[x1,#8*2]
+ add x1,x1,#8*4
+ ldp x14,x15,[x3,#8*0]
+ ldp x16,x17,[x3,#8*2]
+ add x3,x3,#8*4
+ b .Loop_mul4x_1st_tail
+
+.align 5
+.Lmul4x_proceed:
+ ldr x24,[x2,#8*4]! // *++b
+ adc x30,x0,xzr
+ ldp x6,x7,[x11,#8*0] // a[0..3]
+ sub x3,x3,x5 // rewind np
+ ldp x8,x9,[x11,#8*2]
+ add x1,x11,#8*4
+
+ stp x19,x20,[x26,#8*0] // result!!!
+ ldp x19,x20,[sp,#8*4] // t[0..3]
+ stp x21,x22,[x26,#8*2] // result!!!
+ ldp x21,x22,[sp,#8*6]
+
+ ldp x14,x15,[x3,#8*0] // n[0..3]
+ mov x26,sp
+ ldp x16,x17,[x3,#8*2]
+ adds x3,x3,#8*4 // clear carry bit
+ mov x0,xzr
+
+.align 4
+.Loop_mul4x_reduction:
+ mul x10,x6,x24 // lo(a[0..3]*b[4])
+ adc x0,x0,xzr // modulo-scheduled
+ mul x11,x7,x24
+ add x28,x28,#8
+ mul x12,x8,x24
+ and x28,x28,#31
+ mul x13,x9,x24
+ adds x19,x19,x10
+ umulh x10,x6,x24 // hi(a[0..3]*b[4])
+ adcs x20,x20,x11
+ mul x25,x19,x4 // t[0]*n0
+ adcs x21,x21,x12
+ umulh x11,x7,x24
+ adcs x22,x22,x13
+ umulh x12,x8,x24
+ adc x23,xzr,xzr
+ umulh x13,x9,x24
+ ldr x24,[x2,x28] // next b[i]
+ adds x20,x20,x10
+ // (*) mul x10,x14,x25
+ str x25,[x26],#8 // put aside t[0]*n0 for tail processing
+ adcs x21,x21,x11
+ mul x11,x15,x25 // lo(n[0..3]*t[0]*n0
+ adcs x22,x22,x12
+ mul x12,x16,x25
+ adc x23,x23,x13 // can't overflow
+ mul x13,x17,x25
+ // (*) adds xzr,x19,x10
+ subs xzr,x19,#1 // (*)
+ umulh x10,x14,x25 // hi(n[0..3]*t[0]*n0
+ adcs x19,x20,x11
+ umulh x11,x15,x25
+ adcs x20,x21,x12
+ umulh x12,x16,x25
+ adcs x21,x22,x13
+ umulh x13,x17,x25
+ adcs x22,x23,x0
+ adc x0,xzr,xzr
+ adds x19,x19,x10
+ adcs x20,x20,x11
+ adcs x21,x21,x12
+ adcs x22,x22,x13
+ //adc x0,x0,xzr
+ cbnz x28,.Loop_mul4x_reduction
+
+ adc x0,x0,xzr
+ ldp x10,x11,[x26,#8*4] // t[4..7]
+ ldp x12,x13,[x26,#8*6]
+ ldp x6,x7,[x1,#8*0] // a[4..7]
+ ldp x8,x9,[x1,#8*2]
+ add x1,x1,#8*4
+ adds x19,x19,x10
+ adcs x20,x20,x11
+ adcs x21,x21,x12
+ adcs x22,x22,x13
+ //adc x0,x0,xzr
+
+ ldr x25,[sp] // t[0]*n0
+ ldp x14,x15,[x3,#8*0] // n[4..7]
+ ldp x16,x17,[x3,#8*2]
+ add x3,x3,#8*4
+
+.align 4
+.Loop_mul4x_tail:
+ mul x10,x6,x24 // lo(a[4..7]*b[4])
+ adc x0,x0,xzr // modulo-scheduled
+ mul x11,x7,x24
+ add x28,x28,#8
+ mul x12,x8,x24
+ and x28,x28,#31
+ mul x13,x9,x24
+ adds x19,x19,x10
+ umulh x10,x6,x24 // hi(a[4..7]*b[4])
+ adcs x20,x20,x11
+ umulh x11,x7,x24
+ adcs x21,x21,x12
+ umulh x12,x8,x24
+ adcs x22,x22,x13
+ umulh x13,x9,x24
+ adc x23,xzr,xzr
+ ldr x24,[x2,x28] // next b[i]
+ adds x20,x20,x10
+ mul x10,x14,x25 // lo(n[4..7]*t[0]*n0)
+ adcs x21,x21,x11
+ mul x11,x15,x25
+ adcs x22,x22,x12
+ mul x12,x16,x25
+ adc x23,x23,x13 // can't overflow
+ mul x13,x17,x25
+ adds x19,x19,x10
+ umulh x10,x14,x25 // hi(n[4..7]*t[0]*n0)
+ adcs x20,x20,x11
+ umulh x11,x15,x25
+ adcs x21,x21,x12
+ umulh x12,x16,x25
+ adcs x22,x22,x13
+ umulh x13,x17,x25
+ adcs x23,x23,x0
+ ldr x25,[sp,x28] // next a[0]*n0
+ adc x0,xzr,xzr
+ str x19,[x26],#8 // result!!!
+ adds x19,x20,x10
+ sub x10,x27,x1 // done yet?
+ adcs x20,x21,x11
+ adcs x21,x22,x12
+ adcs x22,x23,x13
+ //adc x0,x0,xzr
+ cbnz x28,.Loop_mul4x_tail
+
+ sub x11,x3,x5 // rewinded np?
+ adc x0,x0,xzr
+ cbz x10,.Loop_mul4x_break
+
+ ldp x10,x11,[x26,#8*4]
+ ldp x12,x13,[x26,#8*6]
+ ldp x6,x7,[x1,#8*0]
+ ldp x8,x9,[x1,#8*2]
+ add x1,x1,#8*4
+ adds x19,x19,x10
+ adcs x20,x20,x11
+ adcs x21,x21,x12
+ adcs x22,x22,x13
+ //adc x0,x0,xzr
+ ldp x14,x15,[x3,#8*0]
+ ldp x16,x17,[x3,#8*2]
+ add x3,x3,#8*4
+ b .Loop_mul4x_tail
+
+.align 4
+.Loop_mul4x_break:
+ ldp x12,x13,[x29,#96] // pull rp and &b[num]
+ adds x19,x19,x30
+ add x2,x2,#8*4 // bp++
+ adcs x20,x20,xzr
+ sub x1,x1,x5 // rewind ap
+ adcs x21,x21,xzr
+ stp x19,x20,[x26,#8*0] // result!!!
+ adcs x22,x22,xzr
+ ldp x19,x20,[sp,#8*4] // t[0..3]
+ adc x30,x0,xzr
+ stp x21,x22,[x26,#8*2] // result!!!
+ cmp x2,x13 // done yet?
+ ldp x21,x22,[sp,#8*6]
+ ldp x14,x15,[x11,#8*0] // n[0..3]
+ ldp x16,x17,[x11,#8*2]
+ add x3,x11,#8*4
+ b.eq .Lmul4x_post
+
+ ldr x24,[x2]
+ ldp x6,x7,[x1,#8*0] // a[0..3]
+ ldp x8,x9,[x1,#8*2]
+ adds x1,x1,#8*4 // clear carry bit
+ mov x0,xzr
+ mov x26,sp
+ b .Loop_mul4x_reduction
+
+.align 4
+.Lmul4x_post:
+ // Final step. We see if result is larger than modulus, and
+ // if it is, subtract the modulus. But comparison implies
+ // subtraction. So we subtract modulus, see if it borrowed,
+ // and conditionally copy original value.
+ mov x0,x12
+ mov x27,x12 // x0 copy
+ subs x10,x19,x14
+ add x26,sp,#8*8
+ sbcs x11,x20,x15
+ sub x28,x5,#8*4
+
+.Lmul4x_sub:
+ sbcs x12,x21,x16
+ ldp x14,x15,[x3,#8*0]
+ sub x28,x28,#8*4
+ ldp x19,x20,[x26,#8*0]
+ sbcs x13,x22,x17
+ ldp x16,x17,[x3,#8*2]
+ add x3,x3,#8*4
+ ldp x21,x22,[x26,#8*2]
+ add x26,x26,#8*4
+ stp x10,x11,[x0,#8*0]
+ sbcs x10,x19,x14
+ stp x12,x13,[x0,#8*2]
+ add x0,x0,#8*4
+ sbcs x11,x20,x15
+ cbnz x28,.Lmul4x_sub
+
+ sbcs x12,x21,x16
+ mov x26,sp
+ add x1,sp,#8*4
+ ldp x6,x7,[x27,#8*0]
+ sbcs x13,x22,x17
+ stp x10,x11,[x0,#8*0]
+ ldp x8,x9,[x27,#8*2]
+ stp x12,x13,[x0,#8*2]
+ ldp x19,x20,[x1,#8*0]
+ ldp x21,x22,[x1,#8*2]
+ sbcs xzr,x30,xzr // did it borrow?
+ ldr x30,[x29,#8] // pull return address
+
+ sub x28,x5,#8*4
+.Lmul4x_cond_copy:
+ sub x28,x28,#8*4
+ csel x10,x19,x6,lo
+ stp xzr,xzr,[x26,#8*0]
+ csel x11,x20,x7,lo
+ ldp x6,x7,[x27,#8*4]
+ ldp x19,x20,[x1,#8*4]
+ csel x12,x21,x8,lo
+ stp xzr,xzr,[x26,#8*2]
+ add x26,x26,#8*4
+ csel x13,x22,x9,lo
+ ldp x8,x9,[x27,#8*6]
+ ldp x21,x22,[x1,#8*6]
+ add x1,x1,#8*4
+ stp x10,x11,[x27,#8*0]
+ stp x12,x13,[x27,#8*2]
+ add x27,x27,#8*4
+ cbnz x28,.Lmul4x_cond_copy
+
+ csel x10,x19,x6,lo
+ stp xzr,xzr,[x26,#8*0]
+ csel x11,x20,x7,lo
+ stp xzr,xzr,[x26,#8*2]
+ csel x12,x21,x8,lo
+ stp xzr,xzr,[x26,#8*3]
+ csel x13,x22,x9,lo
+ stp xzr,xzr,[x26,#8*4]
+ stp x10,x11,[x27,#8*0]
+ stp x12,x13,[x27,#8*2]
+
+ b .Lmul4x_done
+
+.align 4
+.Lmul4x4_post_condition:
+ adc x0,x0,xzr
+ ldr x1,[x29,#96] // pull rp
+ // x19-3,x0 hold result, x14-7 hold modulus
+ subs x6,x19,x14
+ ldr x30,[x29,#8] // pull return address
+ sbcs x7,x20,x15
+ stp xzr,xzr,[sp,#8*0]
+ sbcs x8,x21,x16
+ stp xzr,xzr,[sp,#8*2]
+ sbcs x9,x22,x17
+ stp xzr,xzr,[sp,#8*4]
+ sbcs xzr,x0,xzr // did it borrow?
+ stp xzr,xzr,[sp,#8*6]
+
+ // x6-3 hold result-modulus
+ csel x6,x19,x6,lo
+ csel x7,x20,x7,lo
+ csel x8,x21,x8,lo
+ csel x9,x22,x9,lo
+ stp x6,x7,[x1,#8*0]
+ stp x8,x9,[x1,#8*2]
+
+.Lmul4x_done:
+ ldp x19,x20,[x29,#16]
+ mov sp,x29
+ ldp x21,x22,[x29,#32]
+ mov x0,#1
+ ldp x23,x24,[x29,#48]
+ ldp x25,x26,[x29,#64]
+ ldp x27,x28,[x29,#80]
+ ldr x29,[sp],#128
+.inst 0xd50323bf // autiasp
+ ret
+.size __bn_mul4x_mont,.-__bn_mul4x_mont
+.byte 77,111,110,116,103,111,109,101,114,121,32,77,117,108,116,105,112,108,105,99,97,116,105,111,110,32,102,111,114,32,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
+.align 2
+.align 4
diff --git a/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/ec/ecp_nistz256-armv8.S b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/ec/ecp_nistz256-armv8.S
new file mode 100644
index 000000000000..efd46af5e434
--- /dev/null
+++ b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/ec/ecp_nistz256-armv8.S
@@ -0,0 +1,4242 @@
+#include "arm_arch.h"
+
+.text
+.globl ecp_nistz256_precomputed
+.type ecp_nistz256_precomputed,%object
+.align 12
+ecp_nistz256_precomputed:
+.byte 0x3c,0x4d,0x27,0xcc,0xf5,0x4a,0x4f,0x8f,0xe8,0xc8,0x04,0x68,0x09,0x4a,0x5b,0x80,0x9d,0x7a,0xe8,0x31,0x08,0x76,0x68,0x19,0x9f,0x08,0xb4,0x1f,0x32,0x43,0x89,0xd8,0x34,0xd3,0xf5,0xb7,0xb5,0xee,0x42,0x3e,0x91,0x01,0x06,0x7c,0xbf,0xd9,0x97,0x12,0xd3,0x1a,0xc9,0x04,0x8d,0x53,0x83,0x14,0x28,0xf0,0x8e,0x19,0xcc,0x91,0xe5,0x80
+.byte 0x14,0xd6,0xc1,0x8d,0x61,0x66,0x3b,0xa7,0x20,0x1e,0xe4,0x77,0xd7,0x66,0x05,0xfb,0x5c,0xa9,0x9a,0x7a,0xb2,0x30,0x50,0x28,0x87,0x80,0xfe,0xcd,0xe1,0xb3,0xff,0xa3,0x45,0x3c,0x7e,0x9b,0x08,0xc0,0xc1,0x9f,0x2e,0xad,0x7d,0x89,0x79,0x90,0x60,0xc6,0xac,0x17,0x64,0x59,0x4d,0xcf,0x56,0x7a,0xca,0x82,0xaa,0x6e,0x04,0x2f,0x1f,0x8b
+.byte 0xa9,0xdd,0xeb,0x91,0x5c,0x77,0x17,0x99,0x4e,0xc2,0x45,0x69,0x2e,0xcf,0x60,0xc6,0x3c,0xad,0x65,0x33,0x35,0x6f,0xe4,0xd0,0x37,0x1f,0xe2,0x2c,0x66,0x98,0x55,0xe3,0x66,0xa2,0xc6,0x21,0xce,0x63,0x59,0x2e,0xd2,0x2b,0x8a,0x5a,0xcd,0xee,0xa7,0xad,0xf6,0x8c,0x3f,0x44,0x6c,0x12,0x30,0x8d,0xca,0xea,0x46,0x8a,0x4c,0x96,0xf9,0x96
+.byte 0x18,0x10,0x4e,0x46,0xc4,0x3e,0xa0,0x94,0x26,0x9d,0x62,0xd2,0x4b,0xb0,0xbc,0x0b,0xd5,0x56,0xa5,0xd2,0xc1,0x2f,0x2d,0x15,0xd8,0xed,0x97,0x17,0xcb,0x32,0x67,0xc5,0x0f,0x7c,0xde,0xa8,0x8c,0x4d,0xa0,0xb8,0x2e,0xed,0x24,0xd5,0xd5,0x49,0xca,0x77,0x1f,0x48,0x3b,0x83,0x54,0xb2,0xe7,0x7e,0x7a,0xa7,0x5c,0xed,0x7f,0xa1,0x9f,0x05
+.byte 0xd4,0xd4,0x90,0x0d,0xae,0x37,0x4e,0xd1,0x8f,0xd1,0x0a,0xa7,0x63,0x5b,0xb7,0x65,0xcb,0xc8,0xba,0x29,0xec,0x35,0x53,0xb2,0xac,0x32,0xf4,0xb7,0x6a,0xb1,0x69,0xcf,0x56,0x14,0x7f,0xd6,0xc5,0xca,0x88,0x1d,0x49,0xcf,0xfd,0x1f,0xcc,0xb1,0x13,0x30,0x42,0xd0,0x1c,0x6e,0x38,0x8e,0xf9,0x40,0xe7,0xe8,0xd6,0x28,0x1a,0x75,0x31,0xf3
+.byte 0x30,0x46,0x3f,0xb5,0x8a,0x47,0x35,0x4c,0x6e,0xdb,0x26,0x1a,0x25,0xa3,0xd8,0x0b,0x1d,0x51,0x12,0x91,0x4c,0x11,0x76,0x83,0x19,0xad,0x2a,0x3e,0xb4,0x1c,0x3c,0xfc,0x14,0x20,0x84,0x58,0x7b,0xc3,0x94,0x68,0x60,0x5c,0x3f,0x7c,0x26,0xb5,0x75,0x41,0x0b,0xc2,0xec,0xf3,0x96,0x5b,0xbb,0x41,0x32,0x00,0x4e,0x68,0xeb,0xf1,0xd9,0x96
+.byte 0xe7,0x00,0xac,0xb0,0x1b,0x39,0x46,0xf1,0xc9,0x18,0x7d,0xb7,0xc4,0x42,0xbc,0x8b,0x09,0x3e,0xa9,0x97,0x2e,0xc6,0xf8,0x38,0xa3,0xe4,0x2c,0x52,0x5d,0x24,0xf7,0xc5,0x15,0xab,0x16,0x5e,0x46,0x2c,0xd8,0xd7,0x4d,0xb3,0xf2,0xfd,0xe4,0x75,0x3c,0x34,0x95,0xb9,0x8c,0x92,0x35,0x42,0x8b,0xc4,0xc8,0x6c,0xd4,0x1e,0x67,0x35,0xd3,0x6d
+.byte 0x79,0x85,0xff,0x74,0xbe,0x40,0x07,0x27,0x75,0x2c,0xea,0x04,0xcc,0xa2,0x72,0x80,0x97,0x5f,0xfe,0x8a,0x56,0x0f,0xf4,0x6d,0xa4,0x61,0x04,0x4b,0x5e,0xb4,0xe2,0xd8,0x87,0xb6,0xfd,0x3d,0x00,0x8a,0xa9,0xe4,0x62,0x5f,0x4f,0xec,0x1e,0x40,0x28,0x6b,0x21,0x0f,0x50,0x26,0x97,0xa0,0x25,0x8f,0x3e,0xf2,0x69,0xdc,0x36,0xe5,0xb8,0xdb
+.byte 0x01,0x7d,0xfb,0x73,0x7d,0x3e,0xf7,0x55,0x41,0x39,0xe0,0x33,0x0d,0xe3,0x4b,0x6b,0x7b,0x3e,0x6e,0xdc,0x7d,0x9a,0x6e,0x35,0xb0,0x38,0x13,0x92,0x80,0xa1,0xe6,0xbf,0x03,0x9d,0xb7,0x7f,0x55,0xce,0x46,0x3c,0x22,0xc7,0xfa,0xfb,0x18,0xba,0x06,0xa0,0x09,0x78,0x3f,0xc0,0x79,0x5f,0xe6,0x6a,0x29,0xaf,0xd1,0xc7,0x84,0xa7,0xed,0xb9
+.byte 0xb6,0x82,0x81,0xc1,0x53,0xee,0x00,0x34,0xa8,0x81,0xdf,0x5a,0xd3,0x07,0x7e,0x2e,0x17,0x40,0xa1,0x2b,0xf4,0x2a,0x1f,0x9a,0x67,0x75,0x73,0xa8,0x58,0x65,0x17,0xdf,0xf1,0x84,0x76,0xc5,0x8d,0x48,0x93,0xe1,0x28,0xa5,0x73,0x10,0x6e,0x9e,0x39,0x03,0x69,0x52,0xdf,0xf9,0x46,0x7c,0x5b,0xf3,0x5b,0x9a,0x63,0xd9,0x4f,0xf5,0x8e,0x73
+.byte 0xed,0x33,0x7d,0x23,0xb9,0x6c,0x3c,0x9b,0xa7,0xcf,0x7f,0x34,0x6f,0x97,0xe2,0xfe,0x0a,0x8b,0xe1,0x86,0x83,0x91,0x2e,0xdd,0x6b,0xb1,0xbf,0xa6,0x92,0x4f,0x30,0x79,0x68,0x91,0x3e,0x06,0x17,0xe9,0x0b,0x25,0x07,0xa6,0x88,0x91,0x6c,0x6e,0xc8,0xd8,0xdc,0x68,0x5e,0x45,0xf2,0x55,0xef,0x56,0x38,0x29,0xd0,0x89,0x40,0x58,0x51,0x9f
+.byte 0x5f,0xa4,0x08,0xc6,0x94,0x34,0xd2,0x6f,0x59,0x0f,0x6e,0xca,0x85,0x7f,0x56,0x3f,0xac,0x8f,0x25,0x0f,0x47,0xe3,0x9e,0x40,0xed,0xd8,0xae,0x30,0x0d,0xb4,0x47,0x40,0x4b,0xa3,0x23,0x1b,0x7f,0x0f,0xff,0xdf,0x6f,0x1d,0x87,0xb2,0x94,0xa0,0x36,0xbb,0x53,0x13,0x1e,0xaf,0x92,0xf8,0x07,0x95,0xc7,0xe4,0xa8,0x41,0xa9,0xed,0xf0,0x08
+.byte 0xfc,0xc1,0x4a,0xed,0x9a,0x4f,0x13,0xc5,0xed,0x8a,0x95,0xf5,0x69,0xf7,0xee,0x75,0xb6,0x4d,0xba,0x8f,0x65,0x23,0xe8,0x50,0x9e,0x7a,0xd7,0x28,0x3a,0x49,0xe7,0x4c,0x7c,0xc6,0x64,0xbd,0x8c,0x17,0x14,0x0b,0xb5,0xe3,0xb4,0xab,0x0b,0x9a,0xa9,0x29,0x84,0xaa,0xba,0x69,0xc4,0x2e,0xbf,0xca,0x57,0x0d,0xd3,0x36,0x21,0x61,0x00,0x13
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+.byte 0x57,0x6e,0x7e,0x36,0xe0,0x31,0xad,0x10,0x76,0xb7,0x45,0xd9,0x3a,0x92,0x66,0x69,0x13,0x61,0x59,0x87,0xfd,0x6b,0xf1,0x46,0x0a,0x7a,0x3f,0x29,0x88,0x5b,0x7d,0xef,0x07,0x02,0xa8,0xa1,0xdc,0xd4,0x0e,0x77,0x8f,0x68,0x32,0xbd,0x8e,0xd6,0x0b,0xe4,0xd1,0x75,0xc1,0xb0,0x74,0x6c,0x0e,0xc3,0x46,0x79,0x36,0x3b,0x5f,0x0e,0xa0,0xad
+.byte 0x28,0x8c,0xcb,0x01,0x8e,0x58,0x14,0x09,0xf1,0xd4,0x3b,0x2e,0xdc,0xbf,0x37,0x95,0x26,0xda,0xb6,0xcf,0xc8,0xa1,0xd4,0xec,0x72,0xf3,0x44,0xf5,0x4e,0x27,0x9b,0x2e,0x7c,0xfa,0x37,0x16,0x1d,0x7f,0x90,0x86,0xae,0x96,0x3b,0xe1,0xda,0xf7,0xc4,0x54,0x0b,0x51,0x7e,0x83,0xbe,0xed,0xd6,0x5f,0xd2,0x6d,0xbb,0xd3,0xc6,0x53,0x95,0x65
+.byte 0x3d,0x19,0xc2,0xc5,0xdf,0x47,0x00,0x2c,0x4b,0x2d,0xec,0x32,0xd5,0x28,0xb5,0x30,0xe0,0x79,0x15,0x2e,0xab,0x97,0xa8,0xcf,0xc5,0x40,0x98,0x30,0x22,0x9f,0xbc,0xdb,0x65,0x06,0xfc,0x58,0xe5,0x55,0x5b,0xe2,0xf8,0x6e,0xc6,0xfc,0xec,0x6c,0x14,0xd2,0xe3,0x9a,0x71,0x8a,0x61,0xea,0x39,0xc6,0x77,0x94,0xdf,0x7b,0x99,0x71,0xdd,0x18
+.byte 0xc6,0x03,0x2d,0x49,0xf6,0xc3,0xe8,0x2b,0x7e,0x3f,0x28,0xfc,0xc8,0xa1,0xb0,0x15,0x31,0x7e,0x83,0xb8,0x14,0x34,0x0e,0x7f,0xde,0x74,0x7b,0xbf,0xb7,0x8e,0xd9,0x31,0x90,0x16,0xb6,0x57,0x14,0x4a,0xc6,0x67,0x3d,0xb9,0x46,0x92,0xf2,0xf9,0x94,0x36,0x2b,0xd6,0x1f,0x84,0xa5,0x8c,0x0f,0xd9,0x8c,0x5f,0x97,0x7a,0x7b,0xff,0xc9,0xf5
+.byte 0x5e,0x13,0x5f,0x19,0x58,0xba,0xa6,0xe8,0x29,0xf4,0xb8,0x7e,0x98,0xb7,0xef,0x1b,0x00,0xe8,0x90,0x8f,0x86,0x4c,0xe0,0x51,0x13,0x8b,0xa1,0x37,0x40,0x38,0x51,0x2f,0x5a,0x9b,0x63,0x8f,0xce,0x9a,0x97,0x07,0x0d,0x8e,0xce,0xb1,0x66,0x89,0x78,0xca,0xa6,0x0c,0x20,0xc4,0xf1,0xe3,0xab,0xe2,0x1c,0x83,0x2b,0x46,0x97,0xe8,0x8f,0x94
+.byte 0xb4,0x71,0x40,0xde,0xa1,0x05,0x4b,0xed,0xbf,0x0c,0x46,0xe1,0x25,0xf1,0xd0,0x5a,0xdb,0x9c,0x2a,0x09,0x03,0x80,0x24,0xc1,0x22,0x02,0xa5,0xde,0xf6,0x4c,0xbc,0x93,0x37,0xa9,0x28,0xb3,0x92,0x19,0xa8,0x3f,0x71,0x90,0x62,0x78,0xaa,0x9a,0x0c,0xab,0x50,0xaf,0x89,0x2b,0xf1,0xf4,0x12,0xbd,0xc9,0xd5,0xee,0x64,0x8b,0x48,0x21,0xd6
+.byte 0xa1,0xa1,0xf2,0x68,0x4a,0xf8,0x06,0x3e,0x20,0x31,0x66,0xb7,0x2f,0x64,0x01,0x5a,0x46,0x14,0x85,0xfb,0xde,0x04,0xc3,0xe4,0xd6,0x25,0x14,0xa0,0xbe,0x4d,0x39,0xd8,0xe0,0x9b,0xb7,0x6b,0x00,0xe6,0x46,0xfb,0xcc,0xa8,0xad,0x67,0x12,0x2c,0x53,0x2c,0xb6,0x9f,0x6e,0xfe,0xbc,0xcc,0x2c,0xa8,0x09,0x17,0x00,0x8e,0xf1,0xf4,0x3e,0xa9
+.byte 0x92,0x4d,0x83,0xe6,0x3c,0xf0,0xd3,0x1c,0xaf,0x84,0x2c,0x59,0x7e,0xda,0x1e,0xfd,0x7d,0xf3,0xef,0x93,0x05,0x03,0xb0,0x76,0x69,0xb5,0x51,0xa8,0x65,0x8f,0x8a,0xf8,0x55,0x92,0x08,0xfe,0xbf,0xc1,0x95,0x98,0x58,0xb1,0xd3,0xb6,0x78,0x4f,0x2f,0x25,0xcb,0x9d,0x32,0x4f,0xa6,0xcc,0xf8,0x36,0xff,0x72,0xb3,0x93,0x3d,0xd8,0x0b,0xe6
+.byte 0xc6,0xf6,0xed,0xcc,0x2a,0xa5,0x44,0x6e,0xe2,0x2d,0x6e,0x02,0xb4,0x7c,0x24,0x7f,0x57,0x02,0x84,0x61,0x8e,0xbd,0x32,0x4e,0x41,0x92,0x01,0x1b,0x8b,0x1d,0xd1,0x1e,0x31,0xc1,0x4c,0x5b,0x0c,0xa7,0x48,0x52,0x67,0xc2,0xd9,0xdc,0x86,0x9d,0xbd,0x6c,0x19,0x95,0x00,0xf0,0xd4,0x47,0xaf,0xfe,0x5d,0xa5,0x81,0xbd,0x1b,0x42,0x62,0xce
+.byte 0x18,0x1b,0xa3,0x6f,0xf5,0x0b,0xb7,0x6a,0x3d,0xe3,0xcc,0x41,0x27,0xcd,0x49,0x4b,0xe5,0x2b,0xc4,0x28,0xfa,0xbe,0xd5,0x7e,0xb7,0xac,0xab,0x64,0x3b,0xe3,0x87,0xb1,0x33,0x8b,0xa8,0xe5,0x75,0xce,0x61,0x57,0x89,0xad,0x5f,0x61,0xdd,0x7c,0x06,0x2a,0x3f,0x50,0xb8,0x7e,0xd2,0xfb,0x32,0x83,0x07,0xd4,0xc5,0x3f,0xad,0x64,0x59,0x1f
+.byte 0x21,0x59,0x6f,0x1b,0xd7,0x40,0x89,0x28,0x18,0xac,0xca,0xee,0x92,0x1c,0x0d,0x88,0x98,0x7a,0x75,0x68,0xe0,0xe2,0x96,0xda,0x88,0xb3,0xc6,0x21,0x02,0x34,0xfa,0xae,0x0b,0x38,0xcf,0x1c,0x6c,0x7a,0xc9,0xd9,0x5f,0xf0,0x4c,0x73,0xfd,0xe6,0x14,0xf3,0x39,0xed,0xbc,0x28,0x2f,0xf8,0x79,0x02,0x39,0x05,0xf3,0x6a,0x88,0xd9,0x03,0xe2
+.byte 0xb9,0x65,0x81,0x3a,0x34,0x80,0x3f,0x17,0x37,0x1e,0xe8,0x7d,0x41,0x49,0xfb,0x70,0x5d,0x58,0x3a,0x71,0x7b,0x3e,0xd3,0x83,0x0b,0x1b,0x11,0xfc,0x53,0xce,0xc6,0xc4,0x39,0x55,0xbe,0xbe,0x32,0xa5,0x88,0xab,0xcd,0x38,0x78,0x3e,0x52,0xaf,0x64,0x42,0x10,0xc3,0x70,0x81,0x76,0xe9,0x7d,0x8e,0x46,0x41,0xca,0x2c,0x0c,0x4c,0x30,0xd3
+.byte 0xca,0x38,0xa3,0x97,0x2e,0x0f,0xa5,0x18,0x3b,0xaa,0x0f,0x00,0x75,0x35,0x9c,0xcd,0x28,0x83,0xd4,0xa7,0x7c,0xb9,0xcd,0xb5,0x55,0x29,0x4c,0x14,0xcd,0xfc,0x8f,0xaf,0x7d,0x69,0x4f,0xf7,0x0f,0xed,0x7c,0xa5,0x79,0x9d,0x36,0xbb,0x72,0xbc,0xf2,0x14,0xfd,0xf0,0x04,0x2a,0x89,0x1e,0xf7,0x80,0x4c,0x5e,0xb8,0xc1,0xdb,0xfa,0x3c,0x27
+.byte 0xbb,0x30,0x08,0x2b,0xd2,0xf8,0xdb,0xe0,0x8c,0x00,0xe4,0xca,0xa9,0xde,0xb0,0x14,0x5b,0xec,0x6b,0xe6,0x5c,0x90,0x17,0x02,0x59,0x5f,0x5f,0x51,0xf8,0x30,0x10,0x11,0xc4,0xdf,0x37,0x30,0x32,0xb1,0x4d,0x49,0xfe,0x82,0x87,0xd2,0x42,0xf5,0x38,0x76,0xf9,0xa5,0x28,0xfc,0x14,0xb2,0xe0,0x72,0x82,0xde,0xc8,0x47,0x9e,0x8f,0x8a,0xb5
+.byte 0x85,0x44,0x42,0x12,0xc6,0xc0,0xa5,0x60,0x5a,0x27,0xd0,0x36,0x14,0x7b,0x2a,0x83,0x98,0x92,0x08,0xe9,0x03,0xc9,0xc3,0xd3,0x36,0x97,0xba,0x5e,0xd5,0x51,0xcc,0x44,0xeb,0x81,0x76,0xae,0x28,0x94,0x0b,0xf6,0xc7,0xeb,0xae,0x61,0x6f,0x7b,0x34,0xb5,0x8c,0x5f,0x31,0xb6,0x23,0xe3,0xe7,0x4b,0x60,0xe6,0xba,0x8d,0x0e,0xd1,0xb2,0x37
+.byte 0x72,0x3d,0xc1,0x75,0x9b,0x5e,0xcb,0x0f,0xf9,0xe4,0xdb,0x82,0x4c,0xc4,0x37,0xef,0x9d,0xde,0x16,0x85,0xe9,0xc2,0x03,0xd8,0x5b,0xa1,0xff,0xfa,0xd4,0xd7,0x5c,0x34,0xb6,0x1e,0x25,0x96,0xf5,0x8b,0xc3,0xee,0x16,0x1f,0xf8,0x55,0x4e,0x1c,0x83,0x80,0x77,0x1d,0x4f,0xb6,0x95,0x1c,0x91,0x7d,0x50,0x25,0xf4,0x2a,0x5d,0x2e,0xc7,0x8a
+.byte 0x14,0xf8,0xb9,0xbc,0xab,0x5b,0xcd,0x47,0xb5,0xaf,0x85,0xc0,0x34,0x27,0x7d,0x6a,0x8c,0x84,0x8a,0xae,0x68,0x60,0x0e,0xa1,0x45,0xf7,0x83,0x66,0x91,0x69,0x30,0xed,0x26,0x5e,0xf5,0x48,0x6b,0x20,0xb3,0x11,0x50,0xf7,0x70,0x9d,0x10,0x50,0x44,0x87,0xfe,0x96,0x5c,0xc6,0xa4,0xa4,0xed,0x5e,0x7f,0x3d,0x90,0x19,0xbe,0x31,0xa3,0xdd
+.byte 0x44,0xbb,0x9b,0x51,0x5a,0x06,0x1d,0x2e,0xd7,0xef,0xd1,0x81,0xb6,0xec,0xc6,0x89,0xfb,0x13,0xc5,0x21,0xef,0x9a,0x1a,0x48,0xf2,0xf8,0xb3,0xa3,0xec,0x7f,0x85,0xc1,0xc6,0x8c,0x5f,0xa9,0x30,0x38,0x25,0x1e,0x8d,0xcf,0x18,0x24,0xef,0x5a,0x9a,0x14,0x31,0xc0,0x2c,0x88,0xa5,0x3f,0x50,0x8b,0xb1,0xda,0x5d,0x26,0xd9,0xd3,0x81,0xb1
+.byte 0xec,0xf0,0x42,0x88,0xd0,0x81,0x51,0xf9,0x1b,0xbc,0x43,0xa4,0x37,0xf1,0xd7,0x90,0x21,0x7e,0xa0,0x3e,0x63,0xfb,0x21,0xfa,0x12,0xfb,0xde,0xc7,0xbf,0xb3,0x58,0xe7,0x76,0x42,0x20,0x01,0x3d,0x66,0x80,0xf1,0xb8,0xaf,0xfa,0x7d,0x96,0x89,0x36,0x48,0x95,0xd9,0x6e,0x6d,0xe6,0x4f,0xff,0x2a,0x47,0x61,0xf2,0x04,0xb7,0x83,0x14,0xce
+.byte 0x0a,0x3c,0x73,0x17,0x50,0x88,0x03,0x25,0x4a,0xe3,0x13,0x55,0x8b,0x7e,0x50,0x38,0xfc,0x14,0x0b,0x04,0x8e,0xa8,0x5b,0xd6,0x72,0x20,0x60,0xe9,0xaa,0x22,0x82,0x11,0xc6,0xc4,0xd7,0xb9,0xc8,0x0c,0x7e,0x05,0xfb,0x90,0xe4,0x9c,0x28,0x89,0x29,0x99,0x63,0x4d,0xec,0x7b,0x50,0xbd,0xd8,0xa3,0x5b,0x50,0x77,0x19,0x81,0x92,0xce,0x82
+.size ecp_nistz256_precomputed,.-ecp_nistz256_precomputed
+.align 5
+.Lpoly:
+.quad 0xffffffffffffffff,0x00000000ffffffff,0x0000000000000000,0xffffffff00000001
+.LRR: // 2^512 mod P precomputed for NIST P256 polynomial
+.quad 0x0000000000000003,0xfffffffbffffffff,0xfffffffffffffffe,0x00000004fffffffd
+.Lone_mont:
+.quad 0x0000000000000001,0xffffffff00000000,0xffffffffffffffff,0x00000000fffffffe
+.Lone:
+.quad 1,0,0,0
+.Lord:
+.quad 0xf3b9cac2fc632551,0xbce6faada7179e84,0xffffffffffffffff,0xffffffff00000000
+.LordK:
+.quad 0xccd1c8aaee00bc4f
+.byte 69,67,80,95,78,73,83,84,90,50,53,54,32,102,111,114,32,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
+.align 2
+
+// void ecp_nistz256_to_mont(BN_ULONG x0[4],const BN_ULONG x1[4]);
+.globl ecp_nistz256_to_mont
+.type ecp_nistz256_to_mont,%function
+.align 6
+ecp_nistz256_to_mont:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-32]!
+ add x29,sp,#0
+ stp x19,x20,[sp,#16]
+
+ ldr x3,.LRR // bp[0]
+ ldp x4,x5,[x1]
+ ldp x6,x7,[x1,#16]
+ ldr x12,.Lpoly+8
+ ldr x13,.Lpoly+24
+ adr x2,.LRR // &bp[0]
+
+ bl __ecp_nistz256_mul_mont
+
+ ldp x19,x20,[sp,#16]
+ ldp x29,x30,[sp],#32
+.inst 0xd50323bf // autiasp
+ ret
+.size ecp_nistz256_to_mont,.-ecp_nistz256_to_mont
+
+// void ecp_nistz256_from_mont(BN_ULONG x0[4],const BN_ULONG x1[4]);
+.globl ecp_nistz256_from_mont
+.type ecp_nistz256_from_mont,%function
+.align 4
+ecp_nistz256_from_mont:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-32]!
+ add x29,sp,#0
+ stp x19,x20,[sp,#16]
+
+ mov x3,#1 // bp[0]
+ ldp x4,x5,[x1]
+ ldp x6,x7,[x1,#16]
+ ldr x12,.Lpoly+8
+ ldr x13,.Lpoly+24
+ adr x2,.Lone // &bp[0]
+
+ bl __ecp_nistz256_mul_mont
+
+ ldp x19,x20,[sp,#16]
+ ldp x29,x30,[sp],#32
+.inst 0xd50323bf // autiasp
+ ret
+.size ecp_nistz256_from_mont,.-ecp_nistz256_from_mont
+
+// void ecp_nistz256_mul_mont(BN_ULONG x0[4],const BN_ULONG x1[4],
+// const BN_ULONG x2[4]);
+.globl ecp_nistz256_mul_mont
+.type ecp_nistz256_mul_mont,%function
+.align 4
+ecp_nistz256_mul_mont:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-32]!
+ add x29,sp,#0
+ stp x19,x20,[sp,#16]
+
+ ldr x3,[x2] // bp[0]
+ ldp x4,x5,[x1]
+ ldp x6,x7,[x1,#16]
+ ldr x12,.Lpoly+8
+ ldr x13,.Lpoly+24
+
+ bl __ecp_nistz256_mul_mont
+
+ ldp x19,x20,[sp,#16]
+ ldp x29,x30,[sp],#32
+.inst 0xd50323bf // autiasp
+ ret
+.size ecp_nistz256_mul_mont,.-ecp_nistz256_mul_mont
+
+// void ecp_nistz256_sqr_mont(BN_ULONG x0[4],const BN_ULONG x1[4]);
+.globl ecp_nistz256_sqr_mont
+.type ecp_nistz256_sqr_mont,%function
+.align 4
+ecp_nistz256_sqr_mont:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-32]!
+ add x29,sp,#0
+ stp x19,x20,[sp,#16]
+
+ ldp x4,x5,[x1]
+ ldp x6,x7,[x1,#16]
+ ldr x12,.Lpoly+8
+ ldr x13,.Lpoly+24
+
+ bl __ecp_nistz256_sqr_mont
+
+ ldp x19,x20,[sp,#16]
+ ldp x29,x30,[sp],#32
+.inst 0xd50323bf // autiasp
+ ret
+.size ecp_nistz256_sqr_mont,.-ecp_nistz256_sqr_mont
+
+// void ecp_nistz256_add(BN_ULONG x0[4],const BN_ULONG x1[4],
+// const BN_ULONG x2[4]);
+.globl ecp_nistz256_add
+.type ecp_nistz256_add,%function
+.align 4
+ecp_nistz256_add:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+
+ ldp x14,x15,[x1]
+ ldp x8,x9,[x2]
+ ldp x16,x17,[x1,#16]
+ ldp x10,x11,[x2,#16]
+ ldr x12,.Lpoly+8
+ ldr x13,.Lpoly+24
+
+ bl __ecp_nistz256_add
+
+ ldp x29,x30,[sp],#16
+.inst 0xd50323bf // autiasp
+ ret
+.size ecp_nistz256_add,.-ecp_nistz256_add
+
+// void ecp_nistz256_div_by_2(BN_ULONG x0[4],const BN_ULONG x1[4]);
+.globl ecp_nistz256_div_by_2
+.type ecp_nistz256_div_by_2,%function
+.align 4
+ecp_nistz256_div_by_2:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+
+ ldp x14,x15,[x1]
+ ldp x16,x17,[x1,#16]
+ ldr x12,.Lpoly+8
+ ldr x13,.Lpoly+24
+
+ bl __ecp_nistz256_div_by_2
+
+ ldp x29,x30,[sp],#16
+.inst 0xd50323bf // autiasp
+ ret
+.size ecp_nistz256_div_by_2,.-ecp_nistz256_div_by_2
+
+// void ecp_nistz256_mul_by_2(BN_ULONG x0[4],const BN_ULONG x1[4]);
+.globl ecp_nistz256_mul_by_2
+.type ecp_nistz256_mul_by_2,%function
+.align 4
+ecp_nistz256_mul_by_2:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+
+ ldp x14,x15,[x1]
+ ldp x16,x17,[x1,#16]
+ ldr x12,.Lpoly+8
+ ldr x13,.Lpoly+24
+ mov x8,x14
+ mov x9,x15
+ mov x10,x16
+ mov x11,x17
+
+ bl __ecp_nistz256_add // ret = a+a // 2*a
+
+ ldp x29,x30,[sp],#16
+.inst 0xd50323bf // autiasp
+ ret
+.size ecp_nistz256_mul_by_2,.-ecp_nistz256_mul_by_2
+
+// void ecp_nistz256_mul_by_3(BN_ULONG x0[4],const BN_ULONG x1[4]);
+.globl ecp_nistz256_mul_by_3
+.type ecp_nistz256_mul_by_3,%function
+.align 4
+ecp_nistz256_mul_by_3:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+
+ ldp x14,x15,[x1]
+ ldp x16,x17,[x1,#16]
+ ldr x12,.Lpoly+8
+ ldr x13,.Lpoly+24
+ mov x8,x14
+ mov x9,x15
+ mov x10,x16
+ mov x11,x17
+ mov x4,x14
+ mov x5,x15
+ mov x6,x16
+ mov x7,x17
+
+ bl __ecp_nistz256_add // ret = a+a // 2*a
+
+ mov x8,x4
+ mov x9,x5
+ mov x10,x6
+ mov x11,x7
+
+ bl __ecp_nistz256_add // ret += a // 2*a+a=3*a
+
+ ldp x29,x30,[sp],#16
+.inst 0xd50323bf // autiasp
+ ret
+.size ecp_nistz256_mul_by_3,.-ecp_nistz256_mul_by_3
+
+// void ecp_nistz256_sub(BN_ULONG x0[4],const BN_ULONG x1[4],
+// const BN_ULONG x2[4]);
+.globl ecp_nistz256_sub
+.type ecp_nistz256_sub,%function
+.align 4
+ecp_nistz256_sub:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+
+ ldp x14,x15,[x1]
+ ldp x16,x17,[x1,#16]
+ ldr x12,.Lpoly+8
+ ldr x13,.Lpoly+24
+
+ bl __ecp_nistz256_sub_from
+
+ ldp x29,x30,[sp],#16
+.inst 0xd50323bf // autiasp
+ ret
+.size ecp_nistz256_sub,.-ecp_nistz256_sub
+
+// void ecp_nistz256_neg(BN_ULONG x0[4],const BN_ULONG x1[4]);
+.globl ecp_nistz256_neg
+.type ecp_nistz256_neg,%function
+.align 4
+ecp_nistz256_neg:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+
+ mov x2,x1
+ mov x14,xzr // a = 0
+ mov x15,xzr
+ mov x16,xzr
+ mov x17,xzr
+ ldr x12,.Lpoly+8
+ ldr x13,.Lpoly+24
+
+ bl __ecp_nistz256_sub_from
+
+ ldp x29,x30,[sp],#16
+.inst 0xd50323bf // autiasp
+ ret
+.size ecp_nistz256_neg,.-ecp_nistz256_neg
+
+// note that __ecp_nistz256_mul_mont expects a[0-3] input pre-loaded
+// to x4-x7 and b[0] - to x3
+.type __ecp_nistz256_mul_mont,%function
+.align 4
+__ecp_nistz256_mul_mont:
+ mul x14,x4,x3 // a[0]*b[0]
+ umulh x8,x4,x3
+
+ mul x15,x5,x3 // a[1]*b[0]
+ umulh x9,x5,x3
+
+ mul x16,x6,x3 // a[2]*b[0]
+ umulh x10,x6,x3
+
+ mul x17,x7,x3 // a[3]*b[0]
+ umulh x11,x7,x3
+ ldr x3,[x2,#8] // b[1]
+
+ adds x15,x15,x8 // accumulate high parts of multiplication
+ lsl x8,x14,#32
+ adcs x16,x16,x9
+ lsr x9,x14,#32
+ adcs x17,x17,x10
+ adc x19,xzr,x11
+ mov x20,xzr
+ subs x10,x14,x8 // "*0xffff0001"
+ sbc x11,x14,x9
+ adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0]
+ mul x8,x4,x3 // lo(a[0]*b[i])
+ adcs x15,x16,x9
+ mul x9,x5,x3 // lo(a[1]*b[i])
+ adcs x16,x17,x10 // +=acc[0]*0xffff0001
+ mul x10,x6,x3 // lo(a[2]*b[i])
+ adcs x17,x19,x11
+ mul x11,x7,x3 // lo(a[3]*b[i])
+ adc x19,x20,xzr
+
+ adds x14,x14,x8 // accumulate low parts of multiplication
+ umulh x8,x4,x3 // hi(a[0]*b[i])
+ adcs x15,x15,x9
+ umulh x9,x5,x3 // hi(a[1]*b[i])
+ adcs x16,x16,x10
+ umulh x10,x6,x3 // hi(a[2]*b[i])
+ adcs x17,x17,x11
+ umulh x11,x7,x3 // hi(a[3]*b[i])
+ adc x19,x19,xzr
+ ldr x3,[x2,#8*(1+1)] // b[1+1]
+ adds x15,x15,x8 // accumulate high parts of multiplication
+ lsl x8,x14,#32
+ adcs x16,x16,x9
+ lsr x9,x14,#32
+ adcs x17,x17,x10
+ adcs x19,x19,x11
+ adc x20,xzr,xzr
+ subs x10,x14,x8 // "*0xffff0001"
+ sbc x11,x14,x9
+ adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0]
+ mul x8,x4,x3 // lo(a[0]*b[i])
+ adcs x15,x16,x9
+ mul x9,x5,x3 // lo(a[1]*b[i])
+ adcs x16,x17,x10 // +=acc[0]*0xffff0001
+ mul x10,x6,x3 // lo(a[2]*b[i])
+ adcs x17,x19,x11
+ mul x11,x7,x3 // lo(a[3]*b[i])
+ adc x19,x20,xzr
+
+ adds x14,x14,x8 // accumulate low parts of multiplication
+ umulh x8,x4,x3 // hi(a[0]*b[i])
+ adcs x15,x15,x9
+ umulh x9,x5,x3 // hi(a[1]*b[i])
+ adcs x16,x16,x10
+ umulh x10,x6,x3 // hi(a[2]*b[i])
+ adcs x17,x17,x11
+ umulh x11,x7,x3 // hi(a[3]*b[i])
+ adc x19,x19,xzr
+ ldr x3,[x2,#8*(2+1)] // b[2+1]
+ adds x15,x15,x8 // accumulate high parts of multiplication
+ lsl x8,x14,#32
+ adcs x16,x16,x9
+ lsr x9,x14,#32
+ adcs x17,x17,x10
+ adcs x19,x19,x11
+ adc x20,xzr,xzr
+ subs x10,x14,x8 // "*0xffff0001"
+ sbc x11,x14,x9
+ adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0]
+ mul x8,x4,x3 // lo(a[0]*b[i])
+ adcs x15,x16,x9
+ mul x9,x5,x3 // lo(a[1]*b[i])
+ adcs x16,x17,x10 // +=acc[0]*0xffff0001
+ mul x10,x6,x3 // lo(a[2]*b[i])
+ adcs x17,x19,x11
+ mul x11,x7,x3 // lo(a[3]*b[i])
+ adc x19,x20,xzr
+
+ adds x14,x14,x8 // accumulate low parts of multiplication
+ umulh x8,x4,x3 // hi(a[0]*b[i])
+ adcs x15,x15,x9
+ umulh x9,x5,x3 // hi(a[1]*b[i])
+ adcs x16,x16,x10
+ umulh x10,x6,x3 // hi(a[2]*b[i])
+ adcs x17,x17,x11
+ umulh x11,x7,x3 // hi(a[3]*b[i])
+ adc x19,x19,xzr
+ adds x15,x15,x8 // accumulate high parts of multiplication
+ lsl x8,x14,#32
+ adcs x16,x16,x9
+ lsr x9,x14,#32
+ adcs x17,x17,x10
+ adcs x19,x19,x11
+ adc x20,xzr,xzr
+ // last reduction
+ subs x10,x14,x8 // "*0xffff0001"
+ sbc x11,x14,x9
+ adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0]
+ adcs x15,x16,x9
+ adcs x16,x17,x10 // +=acc[0]*0xffff0001
+ adcs x17,x19,x11
+ adc x19,x20,xzr
+
+ adds x8,x14,#1 // subs x8,x14,#-1 // tmp = ret-modulus
+ sbcs x9,x15,x12
+ sbcs x10,x16,xzr
+ sbcs x11,x17,x13
+ sbcs xzr,x19,xzr // did it borrow?
+
+ csel x14,x14,x8,lo // ret = borrow ? ret : ret-modulus
+ csel x15,x15,x9,lo
+ csel x16,x16,x10,lo
+ stp x14,x15,[x0]
+ csel x17,x17,x11,lo
+ stp x16,x17,[x0,#16]
+
+ ret
+.size __ecp_nistz256_mul_mont,.-__ecp_nistz256_mul_mont
+
+// note that __ecp_nistz256_sqr_mont expects a[0-3] input pre-loaded
+// to x4-x7
+.type __ecp_nistz256_sqr_mont,%function
+.align 4
+__ecp_nistz256_sqr_mont:
+ // | | | | | |a1*a0| |
+ // | | | | |a2*a0| | |
+ // | |a3*a2|a3*a0| | | |
+ // | | | |a2*a1| | | |
+ // | | |a3*a1| | | | |
+ // *| | | | | | | | 2|
+ // +|a3*a3|a2*a2|a1*a1|a0*a0|
+ // |--+--+--+--+--+--+--+--|
+ // |A7|A6|A5|A4|A3|A2|A1|A0|, where Ax is , i.e. follow
+ //
+ // "can't overflow" below mark carrying into high part of
+ // multiplication result, which can't overflow, because it
+ // can never be all ones.
+
+ mul x15,x5,x4 // a[1]*a[0]
+ umulh x9,x5,x4
+ mul x16,x6,x4 // a[2]*a[0]
+ umulh x10,x6,x4
+ mul x17,x7,x4 // a[3]*a[0]
+ umulh x19,x7,x4
+
+ adds x16,x16,x9 // accumulate high parts of multiplication
+ mul x8,x6,x5 // a[2]*a[1]
+ umulh x9,x6,x5
+ adcs x17,x17,x10
+ mul x10,x7,x5 // a[3]*a[1]
+ umulh x11,x7,x5
+ adc x19,x19,xzr // can't overflow
+
+ mul x20,x7,x6 // a[3]*a[2]
+ umulh x1,x7,x6
+
+ adds x9,x9,x10 // accumulate high parts of multiplication
+ mul x14,x4,x4 // a[0]*a[0]
+ adc x10,x11,xzr // can't overflow
+
+ adds x17,x17,x8 // accumulate low parts of multiplication
+ umulh x4,x4,x4
+ adcs x19,x19,x9
+ mul x9,x5,x5 // a[1]*a[1]
+ adcs x20,x20,x10
+ umulh x5,x5,x5
+ adc x1,x1,xzr // can't overflow
+
+ adds x15,x15,x15 // acc[1-6]*=2
+ mul x10,x6,x6 // a[2]*a[2]
+ adcs x16,x16,x16
+ umulh x6,x6,x6
+ adcs x17,x17,x17
+ mul x11,x7,x7 // a[3]*a[3]
+ adcs x19,x19,x19
+ umulh x7,x7,x7
+ adcs x20,x20,x20
+ adcs x1,x1,x1
+ adc x2,xzr,xzr
+
+ adds x15,x15,x4 // +a[i]*a[i]
+ adcs x16,x16,x9
+ adcs x17,x17,x5
+ adcs x19,x19,x10
+ adcs x20,x20,x6
+ lsl x8,x14,#32
+ adcs x1,x1,x11
+ lsr x9,x14,#32
+ adc x2,x2,x7
+ subs x10,x14,x8 // "*0xffff0001"
+ sbc x11,x14,x9
+ adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0]
+ adcs x15,x16,x9
+ lsl x8,x14,#32
+ adcs x16,x17,x10 // +=acc[0]*0xffff0001
+ lsr x9,x14,#32
+ adc x17,x11,xzr // can't overflow
+ subs x10,x14,x8 // "*0xffff0001"
+ sbc x11,x14,x9
+ adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0]
+ adcs x15,x16,x9
+ lsl x8,x14,#32
+ adcs x16,x17,x10 // +=acc[0]*0xffff0001
+ lsr x9,x14,#32
+ adc x17,x11,xzr // can't overflow
+ subs x10,x14,x8 // "*0xffff0001"
+ sbc x11,x14,x9
+ adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0]
+ adcs x15,x16,x9
+ lsl x8,x14,#32
+ adcs x16,x17,x10 // +=acc[0]*0xffff0001
+ lsr x9,x14,#32
+ adc x17,x11,xzr // can't overflow
+ subs x10,x14,x8 // "*0xffff0001"
+ sbc x11,x14,x9
+ adds x14,x15,x8 // +=acc[0]<<96 and omit acc[0]
+ adcs x15,x16,x9
+ adcs x16,x17,x10 // +=acc[0]*0xffff0001
+ adc x17,x11,xzr // can't overflow
+
+ adds x14,x14,x19 // accumulate upper half
+ adcs x15,x15,x20
+ adcs x16,x16,x1
+ adcs x17,x17,x2
+ adc x19,xzr,xzr
+
+ adds x8,x14,#1 // subs x8,x14,#-1 // tmp = ret-modulus
+ sbcs x9,x15,x12
+ sbcs x10,x16,xzr
+ sbcs x11,x17,x13
+ sbcs xzr,x19,xzr // did it borrow?
+
+ csel x14,x14,x8,lo // ret = borrow ? ret : ret-modulus
+ csel x15,x15,x9,lo
+ csel x16,x16,x10,lo
+ stp x14,x15,[x0]
+ csel x17,x17,x11,lo
+ stp x16,x17,[x0,#16]
+
+ ret
+.size __ecp_nistz256_sqr_mont,.-__ecp_nistz256_sqr_mont
+
+// Note that __ecp_nistz256_add expects both input vectors pre-loaded to
+// x4-x7 and x8-x11. This is done because it's used in multiple
+// contexts, e.g. in multiplication by 2 and 3...
+.type __ecp_nistz256_add,%function
+.align 4
+__ecp_nistz256_add:
+ adds x14,x14,x8 // ret = a+b
+ adcs x15,x15,x9
+ adcs x16,x16,x10
+ adcs x17,x17,x11
+ adc x1,xzr,xzr // zap x1
+
+ adds x8,x14,#1 // subs x8,x4,#-1 // tmp = ret-modulus
+ sbcs x9,x15,x12
+ sbcs x10,x16,xzr
+ sbcs x11,x17,x13
+ sbcs xzr,x1,xzr // did subtraction borrow?
+
+ csel x14,x14,x8,lo // ret = borrow ? ret : ret-modulus
+ csel x15,x15,x9,lo
+ csel x16,x16,x10,lo
+ stp x14,x15,[x0]
+ csel x17,x17,x11,lo
+ stp x16,x17,[x0,#16]
+
+ ret
+.size __ecp_nistz256_add,.-__ecp_nistz256_add
+
+.type __ecp_nistz256_sub_from,%function
+.align 4
+__ecp_nistz256_sub_from:
+ ldp x8,x9,[x2]
+ ldp x10,x11,[x2,#16]
+ subs x14,x14,x8 // ret = a-b
+ sbcs x15,x15,x9
+ sbcs x16,x16,x10
+ sbcs x17,x17,x11
+ sbc x1,xzr,xzr // zap x1
+
+ subs x8,x14,#1 // adds x8,x4,#-1 // tmp = ret+modulus
+ adcs x9,x15,x12
+ adcs x10,x16,xzr
+ adc x11,x17,x13
+ cmp x1,xzr // did subtraction borrow?
+
+ csel x14,x14,x8,eq // ret = borrow ? ret+modulus : ret
+ csel x15,x15,x9,eq
+ csel x16,x16,x10,eq
+ stp x14,x15,[x0]
+ csel x17,x17,x11,eq
+ stp x16,x17,[x0,#16]
+
+ ret
+.size __ecp_nistz256_sub_from,.-__ecp_nistz256_sub_from
+
+.type __ecp_nistz256_sub_morf,%function
+.align 4
+__ecp_nistz256_sub_morf:
+ ldp x8,x9,[x2]
+ ldp x10,x11,[x2,#16]
+ subs x14,x8,x14 // ret = b-a
+ sbcs x15,x9,x15
+ sbcs x16,x10,x16
+ sbcs x17,x11,x17
+ sbc x1,xzr,xzr // zap x1
+
+ subs x8,x14,#1 // adds x8,x4,#-1 // tmp = ret+modulus
+ adcs x9,x15,x12
+ adcs x10,x16,xzr
+ adc x11,x17,x13
+ cmp x1,xzr // did subtraction borrow?
+
+ csel x14,x14,x8,eq // ret = borrow ? ret+modulus : ret
+ csel x15,x15,x9,eq
+ csel x16,x16,x10,eq
+ stp x14,x15,[x0]
+ csel x17,x17,x11,eq
+ stp x16,x17,[x0,#16]
+
+ ret
+.size __ecp_nistz256_sub_morf,.-__ecp_nistz256_sub_morf
+
+.type __ecp_nistz256_div_by_2,%function
+.align 4
+__ecp_nistz256_div_by_2:
+ subs x8,x14,#1 // adds x8,x4,#-1 // tmp = a+modulus
+ adcs x9,x15,x12
+ adcs x10,x16,xzr
+ adcs x11,x17,x13
+ adc x1,xzr,xzr // zap x1
+ tst x14,#1 // is a even?
+
+ csel x14,x14,x8,eq // ret = even ? a : a+modulus
+ csel x15,x15,x9,eq
+ csel x16,x16,x10,eq
+ csel x17,x17,x11,eq
+ csel x1,xzr,x1,eq
+
+ lsr x14,x14,#1 // ret >>= 1
+ orr x14,x14,x15,lsl#63
+ lsr x15,x15,#1
+ orr x15,x15,x16,lsl#63
+ lsr x16,x16,#1
+ orr x16,x16,x17,lsl#63
+ lsr x17,x17,#1
+ stp x14,x15,[x0]
+ orr x17,x17,x1,lsl#63
+ stp x16,x17,[x0,#16]
+
+ ret
+.size __ecp_nistz256_div_by_2,.-__ecp_nistz256_div_by_2
+.globl ecp_nistz256_point_double
+.type ecp_nistz256_point_double,%function
+.align 5
+ecp_nistz256_point_double:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-96]!
+ add x29,sp,#0
+ stp x19,x20,[sp,#16]
+ stp x21,x22,[sp,#32]
+ sub sp,sp,#32*4
+
+.Ldouble_shortcut:
+ ldp x14,x15,[x1,#32]
+ mov x21,x0
+ ldp x16,x17,[x1,#48]
+ mov x22,x1
+ ldr x12,.Lpoly+8
+ mov x8,x14
+ ldr x13,.Lpoly+24
+ mov x9,x15
+ ldp x4,x5,[x22,#64] // forward load for p256_sqr_mont
+ mov x10,x16
+ mov x11,x17
+ ldp x6,x7,[x22,#64+16]
+ add x0,sp,#0
+ bl __ecp_nistz256_add // p256_mul_by_2(S, in_y);
+
+ add x0,sp,#64
+ bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Zsqr, in_z);
+
+ ldp x8,x9,[x22]
+ ldp x10,x11,[x22,#16]
+ mov x4,x14 // put Zsqr aside for p256_sub
+ mov x5,x15
+ mov x6,x16
+ mov x7,x17
+ add x0,sp,#32
+ bl __ecp_nistz256_add // p256_add(M, Zsqr, in_x);
+
+ add x2,x22,#0
+ mov x14,x4 // restore Zsqr
+ mov x15,x5
+ ldp x4,x5,[sp,#0] // forward load for p256_sqr_mont
+ mov x16,x6
+ mov x17,x7
+ ldp x6,x7,[sp,#0+16]
+ add x0,sp,#64
+ bl __ecp_nistz256_sub_morf // p256_sub(Zsqr, in_x, Zsqr);
+
+ add x0,sp,#0
+ bl __ecp_nistz256_sqr_mont // p256_sqr_mont(S, S);
+
+ ldr x3,[x22,#32]
+ ldp x4,x5,[x22,#64]
+ ldp x6,x7,[x22,#64+16]
+ add x2,x22,#32
+ add x0,sp,#96
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(tmp0, in_z, in_y);
+
+ mov x8,x14
+ mov x9,x15
+ ldp x4,x5,[sp,#0] // forward load for p256_sqr_mont
+ mov x10,x16
+ mov x11,x17
+ ldp x6,x7,[sp,#0+16]
+ add x0,x21,#64
+ bl __ecp_nistz256_add // p256_mul_by_2(res_z, tmp0);
+
+ add x0,sp,#96
+ bl __ecp_nistz256_sqr_mont // p256_sqr_mont(tmp0, S);
+
+ ldr x3,[sp,#64] // forward load for p256_mul_mont
+ ldp x4,x5,[sp,#32]
+ ldp x6,x7,[sp,#32+16]
+ add x0,x21,#32
+ bl __ecp_nistz256_div_by_2 // p256_div_by_2(res_y, tmp0);
+
+ add x2,sp,#64
+ add x0,sp,#32
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(M, M, Zsqr);
+
+ mov x8,x14 // duplicate M
+ mov x9,x15
+ mov x10,x16
+ mov x11,x17
+ mov x4,x14 // put M aside
+ mov x5,x15
+ mov x6,x16
+ mov x7,x17
+ add x0,sp,#32
+ bl __ecp_nistz256_add
+ mov x8,x4 // restore M
+ mov x9,x5
+ ldr x3,[x22] // forward load for p256_mul_mont
+ mov x10,x6
+ ldp x4,x5,[sp,#0]
+ mov x11,x7
+ ldp x6,x7,[sp,#0+16]
+ bl __ecp_nistz256_add // p256_mul_by_3(M, M);
+
+ add x2,x22,#0
+ add x0,sp,#0
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(S, S, in_x);
+
+ mov x8,x14
+ mov x9,x15
+ ldp x4,x5,[sp,#32] // forward load for p256_sqr_mont
+ mov x10,x16
+ mov x11,x17
+ ldp x6,x7,[sp,#32+16]
+ add x0,sp,#96
+ bl __ecp_nistz256_add // p256_mul_by_2(tmp0, S);
+
+ add x0,x21,#0
+ bl __ecp_nistz256_sqr_mont // p256_sqr_mont(res_x, M);
+
+ add x2,sp,#96
+ bl __ecp_nistz256_sub_from // p256_sub(res_x, res_x, tmp0);
+
+ add x2,sp,#0
+ add x0,sp,#0
+ bl __ecp_nistz256_sub_morf // p256_sub(S, S, res_x);
+
+ ldr x3,[sp,#32]
+ mov x4,x14 // copy S
+ mov x5,x15
+ mov x6,x16
+ mov x7,x17
+ add x2,sp,#32
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(S, S, M);
+
+ add x2,x21,#32
+ add x0,x21,#32
+ bl __ecp_nistz256_sub_from // p256_sub(res_y, S, res_y);
+
+ add sp,x29,#0 // destroy frame
+ ldp x19,x20,[x29,#16]
+ ldp x21,x22,[x29,#32]
+ ldp x29,x30,[sp],#96
+.inst 0xd50323bf // autiasp
+ ret
+.size ecp_nistz256_point_double,.-ecp_nistz256_point_double
+.globl ecp_nistz256_point_add
+.type ecp_nistz256_point_add,%function
+.align 5
+ecp_nistz256_point_add:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-96]!
+ add x29,sp,#0
+ stp x19,x20,[sp,#16]
+ stp x21,x22,[sp,#32]
+ stp x23,x24,[sp,#48]
+ stp x25,x26,[sp,#64]
+ stp x27,x28,[sp,#80]
+ sub sp,sp,#32*12
+
+ ldp x4,x5,[x2,#64] // in2_z
+ ldp x6,x7,[x2,#64+16]
+ mov x21,x0
+ mov x22,x1
+ mov x23,x2
+ ldr x12,.Lpoly+8
+ ldr x13,.Lpoly+24
+ orr x8,x4,x5
+ orr x10,x6,x7
+ orr x25,x8,x10
+ cmp x25,#0
+ csetm x25,ne // ~in2infty
+ add x0,sp,#192
+ bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Z2sqr, in2_z);
+
+ ldp x4,x5,[x22,#64] // in1_z
+ ldp x6,x7,[x22,#64+16]
+ orr x8,x4,x5
+ orr x10,x6,x7
+ orr x24,x8,x10
+ cmp x24,#0
+ csetm x24,ne // ~in1infty
+ add x0,sp,#128
+ bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Z1sqr, in1_z);
+
+ ldr x3,[x23,#64]
+ ldp x4,x5,[sp,#192]
+ ldp x6,x7,[sp,#192+16]
+ add x2,x23,#64
+ add x0,sp,#320
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(S1, Z2sqr, in2_z);
+
+ ldr x3,[x22,#64]
+ ldp x4,x5,[sp,#128]
+ ldp x6,x7,[sp,#128+16]
+ add x2,x22,#64
+ add x0,sp,#352
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(S2, Z1sqr, in1_z);
+
+ ldr x3,[x22,#32]
+ ldp x4,x5,[sp,#320]
+ ldp x6,x7,[sp,#320+16]
+ add x2,x22,#32
+ add x0,sp,#320
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(S1, S1, in1_y);
+
+ ldr x3,[x23,#32]
+ ldp x4,x5,[sp,#352]
+ ldp x6,x7,[sp,#352+16]
+ add x2,x23,#32
+ add x0,sp,#352
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(S2, S2, in2_y);
+
+ add x2,sp,#320
+ ldr x3,[sp,#192] // forward load for p256_mul_mont
+ ldp x4,x5,[x22]
+ ldp x6,x7,[x22,#16]
+ add x0,sp,#160
+ bl __ecp_nistz256_sub_from // p256_sub(R, S2, S1);
+
+ orr x14,x14,x15 // see if result is zero
+ orr x16,x16,x17
+ orr x26,x14,x16 // ~is_equal(S1,S2)
+
+ add x2,sp,#192
+ add x0,sp,#256
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(U1, in1_x, Z2sqr);
+
+ ldr x3,[sp,#128]
+ ldp x4,x5,[x23]
+ ldp x6,x7,[x23,#16]
+ add x2,sp,#128
+ add x0,sp,#288
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(U2, in2_x, Z1sqr);
+
+ add x2,sp,#256
+ ldp x4,x5,[sp,#160] // forward load for p256_sqr_mont
+ ldp x6,x7,[sp,#160+16]
+ add x0,sp,#96
+ bl __ecp_nistz256_sub_from // p256_sub(H, U2, U1);
+
+ orr x14,x14,x15 // see if result is zero
+ orr x16,x16,x17
+ orr x14,x14,x16 // ~is_equal(U1,U2)
+
+ mvn x27,x24 // -1/0 -> 0/-1
+ mvn x28,x25 // -1/0 -> 0/-1
+ orr x14,x14,x27
+ orr x14,x14,x28
+ orr x14,x14,x26
+ cbnz x14,.Ladd_proceed // if(~is_equal(U1,U2) | in1infty | in2infty | ~is_equal(S1,S2))
+
+.Ladd_double:
+ mov x1,x22
+ mov x0,x21
+ ldp x23,x24,[x29,#48]
+ ldp x25,x26,[x29,#64]
+ ldp x27,x28,[x29,#80]
+ add sp,sp,#32*(12-4) // difference in stack frames
+ b .Ldouble_shortcut
+
+.align 4
+.Ladd_proceed:
+ add x0,sp,#192
+ bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Rsqr, R);
+
+ ldr x3,[x22,#64]
+ ldp x4,x5,[sp,#96]
+ ldp x6,x7,[sp,#96+16]
+ add x2,x22,#64
+ add x0,sp,#64
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(res_z, H, in1_z);
+
+ ldp x4,x5,[sp,#96]
+ ldp x6,x7,[sp,#96+16]
+ add x0,sp,#128
+ bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Hsqr, H);
+
+ ldr x3,[x23,#64]
+ ldp x4,x5,[sp,#64]
+ ldp x6,x7,[sp,#64+16]
+ add x2,x23,#64
+ add x0,sp,#64
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(res_z, res_z, in2_z);
+
+ ldr x3,[sp,#96]
+ ldp x4,x5,[sp,#128]
+ ldp x6,x7,[sp,#128+16]
+ add x2,sp,#96
+ add x0,sp,#224
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(Hcub, Hsqr, H);
+
+ ldr x3,[sp,#128]
+ ldp x4,x5,[sp,#256]
+ ldp x6,x7,[sp,#256+16]
+ add x2,sp,#128
+ add x0,sp,#288
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(U2, U1, Hsqr);
+
+ mov x8,x14
+ mov x9,x15
+ mov x10,x16
+ mov x11,x17
+ add x0,sp,#128
+ bl __ecp_nistz256_add // p256_mul_by_2(Hsqr, U2);
+
+ add x2,sp,#192
+ add x0,sp,#0
+ bl __ecp_nistz256_sub_morf // p256_sub(res_x, Rsqr, Hsqr);
+
+ add x2,sp,#224
+ bl __ecp_nistz256_sub_from // p256_sub(res_x, res_x, Hcub);
+
+ add x2,sp,#288
+ ldr x3,[sp,#224] // forward load for p256_mul_mont
+ ldp x4,x5,[sp,#320]
+ ldp x6,x7,[sp,#320+16]
+ add x0,sp,#32
+ bl __ecp_nistz256_sub_morf // p256_sub(res_y, U2, res_x);
+
+ add x2,sp,#224
+ add x0,sp,#352
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(S2, S1, Hcub);
+
+ ldr x3,[sp,#160]
+ ldp x4,x5,[sp,#32]
+ ldp x6,x7,[sp,#32+16]
+ add x2,sp,#160
+ add x0,sp,#32
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(res_y, res_y, R);
+
+ add x2,sp,#352
+ bl __ecp_nistz256_sub_from // p256_sub(res_y, res_y, S2);
+
+ ldp x4,x5,[sp,#0] // res
+ ldp x6,x7,[sp,#0+16]
+ ldp x8,x9,[x23] // in2
+ ldp x10,x11,[x23,#16]
+ ldp x14,x15,[x22,#0] // in1
+ cmp x24,#0 // ~, remember?
+ ldp x16,x17,[x22,#0+16]
+ csel x8,x4,x8,ne
+ csel x9,x5,x9,ne
+ ldp x4,x5,[sp,#0+0+32] // res
+ csel x10,x6,x10,ne
+ csel x11,x7,x11,ne
+ cmp x25,#0 // ~, remember?
+ ldp x6,x7,[sp,#0+0+48]
+ csel x14,x8,x14,ne
+ csel x15,x9,x15,ne
+ ldp x8,x9,[x23,#0+32] // in2
+ csel x16,x10,x16,ne
+ csel x17,x11,x17,ne
+ ldp x10,x11,[x23,#0+48]
+ stp x14,x15,[x21,#0]
+ stp x16,x17,[x21,#0+16]
+ ldp x14,x15,[x22,#32] // in1
+ cmp x24,#0 // ~, remember?
+ ldp x16,x17,[x22,#32+16]
+ csel x8,x4,x8,ne
+ csel x9,x5,x9,ne
+ ldp x4,x5,[sp,#0+32+32] // res
+ csel x10,x6,x10,ne
+ csel x11,x7,x11,ne
+ cmp x25,#0 // ~, remember?
+ ldp x6,x7,[sp,#0+32+48]
+ csel x14,x8,x14,ne
+ csel x15,x9,x15,ne
+ ldp x8,x9,[x23,#32+32] // in2
+ csel x16,x10,x16,ne
+ csel x17,x11,x17,ne
+ ldp x10,x11,[x23,#32+48]
+ stp x14,x15,[x21,#32]
+ stp x16,x17,[x21,#32+16]
+ ldp x14,x15,[x22,#64] // in1
+ cmp x24,#0 // ~, remember?
+ ldp x16,x17,[x22,#64+16]
+ csel x8,x4,x8,ne
+ csel x9,x5,x9,ne
+ csel x10,x6,x10,ne
+ csel x11,x7,x11,ne
+ cmp x25,#0 // ~, remember?
+ csel x14,x8,x14,ne
+ csel x15,x9,x15,ne
+ csel x16,x10,x16,ne
+ csel x17,x11,x17,ne
+ stp x14,x15,[x21,#64]
+ stp x16,x17,[x21,#64+16]
+
+.Ladd_done:
+ add sp,x29,#0 // destroy frame
+ ldp x19,x20,[x29,#16]
+ ldp x21,x22,[x29,#32]
+ ldp x23,x24,[x29,#48]
+ ldp x25,x26,[x29,#64]
+ ldp x27,x28,[x29,#80]
+ ldp x29,x30,[sp],#96
+.inst 0xd50323bf // autiasp
+ ret
+.size ecp_nistz256_point_add,.-ecp_nistz256_point_add
+.globl ecp_nistz256_point_add_affine
+.type ecp_nistz256_point_add_affine,%function
+.align 5
+ecp_nistz256_point_add_affine:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-80]!
+ add x29,sp,#0
+ stp x19,x20,[sp,#16]
+ stp x21,x22,[sp,#32]
+ stp x23,x24,[sp,#48]
+ stp x25,x26,[sp,#64]
+ sub sp,sp,#32*10
+
+ mov x21,x0
+ mov x22,x1
+ mov x23,x2
+ ldr x12,.Lpoly+8
+ ldr x13,.Lpoly+24
+
+ ldp x4,x5,[x1,#64] // in1_z
+ ldp x6,x7,[x1,#64+16]
+ orr x8,x4,x5
+ orr x10,x6,x7
+ orr x24,x8,x10
+ cmp x24,#0
+ csetm x24,ne // ~in1infty
+
+ ldp x14,x15,[x2] // in2_x
+ ldp x16,x17,[x2,#16]
+ ldp x8,x9,[x2,#32] // in2_y
+ ldp x10,x11,[x2,#48]
+ orr x14,x14,x15
+ orr x16,x16,x17
+ orr x8,x8,x9
+ orr x10,x10,x11
+ orr x14,x14,x16
+ orr x8,x8,x10
+ orr x25,x14,x8
+ cmp x25,#0
+ csetm x25,ne // ~in2infty
+
+ add x0,sp,#128
+ bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Z1sqr, in1_z);
+
+ mov x4,x14
+ mov x5,x15
+ mov x6,x16
+ mov x7,x17
+ ldr x3,[x23]
+ add x2,x23,#0
+ add x0,sp,#96
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(U2, Z1sqr, in2_x);
+
+ add x2,x22,#0
+ ldr x3,[x22,#64] // forward load for p256_mul_mont
+ ldp x4,x5,[sp,#128]
+ ldp x6,x7,[sp,#128+16]
+ add x0,sp,#160
+ bl __ecp_nistz256_sub_from // p256_sub(H, U2, in1_x);
+
+ add x2,x22,#64
+ add x0,sp,#128
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(S2, Z1sqr, in1_z);
+
+ ldr x3,[x22,#64]
+ ldp x4,x5,[sp,#160]
+ ldp x6,x7,[sp,#160+16]
+ add x2,x22,#64
+ add x0,sp,#64
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(res_z, H, in1_z);
+
+ ldr x3,[x23,#32]
+ ldp x4,x5,[sp,#128]
+ ldp x6,x7,[sp,#128+16]
+ add x2,x23,#32
+ add x0,sp,#128
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(S2, S2, in2_y);
+
+ add x2,x22,#32
+ ldp x4,x5,[sp,#160] // forward load for p256_sqr_mont
+ ldp x6,x7,[sp,#160+16]
+ add x0,sp,#192
+ bl __ecp_nistz256_sub_from // p256_sub(R, S2, in1_y);
+
+ add x0,sp,#224
+ bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Hsqr, H);
+
+ ldp x4,x5,[sp,#192]
+ ldp x6,x7,[sp,#192+16]
+ add x0,sp,#288
+ bl __ecp_nistz256_sqr_mont // p256_sqr_mont(Rsqr, R);
+
+ ldr x3,[sp,#160]
+ ldp x4,x5,[sp,#224]
+ ldp x6,x7,[sp,#224+16]
+ add x2,sp,#160
+ add x0,sp,#256
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(Hcub, Hsqr, H);
+
+ ldr x3,[x22]
+ ldp x4,x5,[sp,#224]
+ ldp x6,x7,[sp,#224+16]
+ add x2,x22,#0
+ add x0,sp,#96
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(U2, in1_x, Hsqr);
+
+ mov x8,x14
+ mov x9,x15
+ mov x10,x16
+ mov x11,x17
+ add x0,sp,#224
+ bl __ecp_nistz256_add // p256_mul_by_2(Hsqr, U2);
+
+ add x2,sp,#288
+ add x0,sp,#0
+ bl __ecp_nistz256_sub_morf // p256_sub(res_x, Rsqr, Hsqr);
+
+ add x2,sp,#256
+ bl __ecp_nistz256_sub_from // p256_sub(res_x, res_x, Hcub);
+
+ add x2,sp,#96
+ ldr x3,[x22,#32] // forward load for p256_mul_mont
+ ldp x4,x5,[sp,#256]
+ ldp x6,x7,[sp,#256+16]
+ add x0,sp,#32
+ bl __ecp_nistz256_sub_morf // p256_sub(res_y, U2, res_x);
+
+ add x2,x22,#32
+ add x0,sp,#128
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(S2, in1_y, Hcub);
+
+ ldr x3,[sp,#192]
+ ldp x4,x5,[sp,#32]
+ ldp x6,x7,[sp,#32+16]
+ add x2,sp,#192
+ add x0,sp,#32
+ bl __ecp_nistz256_mul_mont // p256_mul_mont(res_y, res_y, R);
+
+ add x2,sp,#128
+ bl __ecp_nistz256_sub_from // p256_sub(res_y, res_y, S2);
+
+ ldp x4,x5,[sp,#0] // res
+ ldp x6,x7,[sp,#0+16]
+ ldp x8,x9,[x23] // in2
+ ldp x10,x11,[x23,#16]
+ ldp x14,x15,[x22,#0] // in1
+ cmp x24,#0 // ~, remember?
+ ldp x16,x17,[x22,#0+16]
+ csel x8,x4,x8,ne
+ csel x9,x5,x9,ne
+ ldp x4,x5,[sp,#0+0+32] // res
+ csel x10,x6,x10,ne
+ csel x11,x7,x11,ne
+ cmp x25,#0 // ~, remember?
+ ldp x6,x7,[sp,#0+0+48]
+ csel x14,x8,x14,ne
+ csel x15,x9,x15,ne
+ ldp x8,x9,[x23,#0+32] // in2
+ csel x16,x10,x16,ne
+ csel x17,x11,x17,ne
+ ldp x10,x11,[x23,#0+48]
+ stp x14,x15,[x21,#0]
+ stp x16,x17,[x21,#0+16]
+ adr x23,.Lone_mont-64
+ ldp x14,x15,[x22,#32] // in1
+ cmp x24,#0 // ~, remember?
+ ldp x16,x17,[x22,#32+16]
+ csel x8,x4,x8,ne
+ csel x9,x5,x9,ne
+ ldp x4,x5,[sp,#0+32+32] // res
+ csel x10,x6,x10,ne
+ csel x11,x7,x11,ne
+ cmp x25,#0 // ~, remember?
+ ldp x6,x7,[sp,#0+32+48]
+ csel x14,x8,x14,ne
+ csel x15,x9,x15,ne
+ ldp x8,x9,[x23,#32+32] // in2
+ csel x16,x10,x16,ne
+ csel x17,x11,x17,ne
+ ldp x10,x11,[x23,#32+48]
+ stp x14,x15,[x21,#32]
+ stp x16,x17,[x21,#32+16]
+ ldp x14,x15,[x22,#64] // in1
+ cmp x24,#0 // ~, remember?
+ ldp x16,x17,[x22,#64+16]
+ csel x8,x4,x8,ne
+ csel x9,x5,x9,ne
+ csel x10,x6,x10,ne
+ csel x11,x7,x11,ne
+ cmp x25,#0 // ~, remember?
+ csel x14,x8,x14,ne
+ csel x15,x9,x15,ne
+ csel x16,x10,x16,ne
+ csel x17,x11,x17,ne
+ stp x14,x15,[x21,#64]
+ stp x16,x17,[x21,#64+16]
+
+ add sp,x29,#0 // destroy frame
+ ldp x19,x20,[x29,#16]
+ ldp x21,x22,[x29,#32]
+ ldp x23,x24,[x29,#48]
+ ldp x25,x26,[x29,#64]
+ ldp x29,x30,[sp],#80
+.inst 0xd50323bf // autiasp
+ ret
+.size ecp_nistz256_point_add_affine,.-ecp_nistz256_point_add_affine
+////////////////////////////////////////////////////////////////////////
+// void ecp_nistz256_ord_mul_mont(uint64_t res[4], uint64_t a[4],
+// uint64_t b[4]);
+.globl ecp_nistz256_ord_mul_mont
+.type ecp_nistz256_ord_mul_mont,%function
+.align 4
+ecp_nistz256_ord_mul_mont:
+ stp x29,x30,[sp,#-64]!
+ add x29,sp,#0
+ stp x19,x20,[sp,#16]
+ stp x21,x22,[sp,#32]
+ stp x23,x24,[sp,#48]
+
+ adr x23,.Lord
+ ldr x3,[x2] // bp[0]
+ ldp x4,x5,[x1]
+ ldp x6,x7,[x1,#16]
+
+ ldp x12,x13,[x23,#0]
+ ldp x21,x22,[x23,#16]
+ ldr x23,[x23,#32]
+
+ mul x14,x4,x3 // a[0]*b[0]
+ umulh x8,x4,x3
+
+ mul x15,x5,x3 // a[1]*b[0]
+ umulh x9,x5,x3
+
+ mul x16,x6,x3 // a[2]*b[0]
+ umulh x10,x6,x3
+
+ mul x17,x7,x3 // a[3]*b[0]
+ umulh x19,x7,x3
+
+ mul x24,x14,x23
+
+ adds x15,x15,x8 // accumulate high parts of multiplication
+ adcs x16,x16,x9
+ adcs x17,x17,x10
+ adc x19,x19,xzr
+ mov x20,xzr
+ ldr x3,[x2,#8*1] // b[i]
+
+ lsl x8,x24,#32
+ subs x16,x16,x24
+ lsr x9,x24,#32
+ sbcs x17,x17,x8
+ sbcs x19,x19,x9
+ sbc x20,x20,xzr
+
+ subs xzr,x14,#1
+ umulh x9,x12,x24
+ mul x10,x13,x24
+ umulh x11,x13,x24
+
+ adcs x10,x10,x9
+ mul x8,x4,x3
+ adc x11,x11,xzr
+ mul x9,x5,x3
+
+ adds x14,x15,x10
+ mul x10,x6,x3
+ adcs x15,x16,x11
+ mul x11,x7,x3
+ adcs x16,x17,x24
+ adcs x17,x19,x24
+ adc x19,x20,xzr
+
+ adds x14,x14,x8 // accumulate low parts
+ umulh x8,x4,x3
+ adcs x15,x15,x9
+ umulh x9,x5,x3
+ adcs x16,x16,x10
+ umulh x10,x6,x3
+ adcs x17,x17,x11
+ umulh x11,x7,x3
+ adc x19,x19,xzr
+ mul x24,x14,x23
+ adds x15,x15,x8 // accumulate high parts
+ adcs x16,x16,x9
+ adcs x17,x17,x10
+ adcs x19,x19,x11
+ adc x20,xzr,xzr
+ ldr x3,[x2,#8*2] // b[i]
+
+ lsl x8,x24,#32
+ subs x16,x16,x24
+ lsr x9,x24,#32
+ sbcs x17,x17,x8
+ sbcs x19,x19,x9
+ sbc x20,x20,xzr
+
+ subs xzr,x14,#1
+ umulh x9,x12,x24
+ mul x10,x13,x24
+ umulh x11,x13,x24
+
+ adcs x10,x10,x9
+ mul x8,x4,x3
+ adc x11,x11,xzr
+ mul x9,x5,x3
+
+ adds x14,x15,x10
+ mul x10,x6,x3
+ adcs x15,x16,x11
+ mul x11,x7,x3
+ adcs x16,x17,x24
+ adcs x17,x19,x24
+ adc x19,x20,xzr
+
+ adds x14,x14,x8 // accumulate low parts
+ umulh x8,x4,x3
+ adcs x15,x15,x9
+ umulh x9,x5,x3
+ adcs x16,x16,x10
+ umulh x10,x6,x3
+ adcs x17,x17,x11
+ umulh x11,x7,x3
+ adc x19,x19,xzr
+ mul x24,x14,x23
+ adds x15,x15,x8 // accumulate high parts
+ adcs x16,x16,x9
+ adcs x17,x17,x10
+ adcs x19,x19,x11
+ adc x20,xzr,xzr
+ ldr x3,[x2,#8*3] // b[i]
+
+ lsl x8,x24,#32
+ subs x16,x16,x24
+ lsr x9,x24,#32
+ sbcs x17,x17,x8
+ sbcs x19,x19,x9
+ sbc x20,x20,xzr
+
+ subs xzr,x14,#1
+ umulh x9,x12,x24
+ mul x10,x13,x24
+ umulh x11,x13,x24
+
+ adcs x10,x10,x9
+ mul x8,x4,x3
+ adc x11,x11,xzr
+ mul x9,x5,x3
+
+ adds x14,x15,x10
+ mul x10,x6,x3
+ adcs x15,x16,x11
+ mul x11,x7,x3
+ adcs x16,x17,x24
+ adcs x17,x19,x24
+ adc x19,x20,xzr
+
+ adds x14,x14,x8 // accumulate low parts
+ umulh x8,x4,x3
+ adcs x15,x15,x9
+ umulh x9,x5,x3
+ adcs x16,x16,x10
+ umulh x10,x6,x3
+ adcs x17,x17,x11
+ umulh x11,x7,x3
+ adc x19,x19,xzr
+ mul x24,x14,x23
+ adds x15,x15,x8 // accumulate high parts
+ adcs x16,x16,x9
+ adcs x17,x17,x10
+ adcs x19,x19,x11
+ adc x20,xzr,xzr
+ lsl x8,x24,#32 // last reduction
+ subs x16,x16,x24
+ lsr x9,x24,#32
+ sbcs x17,x17,x8
+ sbcs x19,x19,x9
+ sbc x20,x20,xzr
+
+ subs xzr,x14,#1
+ umulh x9,x12,x24
+ mul x10,x13,x24
+ umulh x11,x13,x24
+
+ adcs x10,x10,x9
+ adc x11,x11,xzr
+
+ adds x14,x15,x10
+ adcs x15,x16,x11
+ adcs x16,x17,x24
+ adcs x17,x19,x24
+ adc x19,x20,xzr
+
+ subs x8,x14,x12 // ret -= modulus
+ sbcs x9,x15,x13
+ sbcs x10,x16,x21
+ sbcs x11,x17,x22
+ sbcs xzr,x19,xzr
+
+ csel x14,x14,x8,lo // ret = borrow ? ret : ret-modulus
+ csel x15,x15,x9,lo
+ csel x16,x16,x10,lo
+ stp x14,x15,[x0]
+ csel x17,x17,x11,lo
+ stp x16,x17,[x0,#16]
+
+ ldp x19,x20,[sp,#16]
+ ldp x21,x22,[sp,#32]
+ ldp x23,x24,[sp,#48]
+ ldr x29,[sp],#64
+ ret
+.size ecp_nistz256_ord_mul_mont,.-ecp_nistz256_ord_mul_mont
+
+////////////////////////////////////////////////////////////////////////
+// void ecp_nistz256_ord_sqr_mont(uint64_t res[4], uint64_t a[4],
+// uint64_t rep);
+.globl ecp_nistz256_ord_sqr_mont
+.type ecp_nistz256_ord_sqr_mont,%function
+.align 4
+ecp_nistz256_ord_sqr_mont:
+ stp x29,x30,[sp,#-64]!
+ add x29,sp,#0
+ stp x19,x20,[sp,#16]
+ stp x21,x22,[sp,#32]
+ stp x23,x24,[sp,#48]
+
+ adr x23,.Lord
+ ldp x4,x5,[x1]
+ ldp x6,x7,[x1,#16]
+
+ ldp x12,x13,[x23,#0]
+ ldp x21,x22,[x23,#16]
+ ldr x23,[x23,#32]
+ b .Loop_ord_sqr
+
+.align 4
+.Loop_ord_sqr:
+ sub x2,x2,#1
+ ////////////////////////////////////////////////////////////////
+ // | | | | | |a1*a0| |
+ // | | | | |a2*a0| | |
+ // | |a3*a2|a3*a0| | | |
+ // | | | |a2*a1| | | |
+ // | | |a3*a1| | | | |
+ // *| | | | | | | | 2|
+ // +|a3*a3|a2*a2|a1*a1|a0*a0|
+ // |--+--+--+--+--+--+--+--|
+ // |A7|A6|A5|A4|A3|A2|A1|A0|, where Ax is , i.e. follow
+ //
+ // "can't overflow" below mark carrying into high part of
+ // multiplication result, which can't overflow, because it
+ // can never be all ones.
+
+ mul x15,x5,x4 // a[1]*a[0]
+ umulh x9,x5,x4
+ mul x16,x6,x4 // a[2]*a[0]
+ umulh x10,x6,x4
+ mul x17,x7,x4 // a[3]*a[0]
+ umulh x19,x7,x4
+
+ adds x16,x16,x9 // accumulate high parts of multiplication
+ mul x8,x6,x5 // a[2]*a[1]
+ umulh x9,x6,x5
+ adcs x17,x17,x10
+ mul x10,x7,x5 // a[3]*a[1]
+ umulh x11,x7,x5
+ adc x19,x19,xzr // can't overflow
+
+ mul x20,x7,x6 // a[3]*a[2]
+ umulh x1,x7,x6
+
+ adds x9,x9,x10 // accumulate high parts of multiplication
+ mul x14,x4,x4 // a[0]*a[0]
+ adc x10,x11,xzr // can't overflow
+
+ adds x17,x17,x8 // accumulate low parts of multiplication
+ umulh x4,x4,x4
+ adcs x19,x19,x9
+ mul x9,x5,x5 // a[1]*a[1]
+ adcs x20,x20,x10
+ umulh x5,x5,x5
+ adc x1,x1,xzr // can't overflow
+
+ adds x15,x15,x15 // acc[1-6]*=2
+ mul x10,x6,x6 // a[2]*a[2]
+ adcs x16,x16,x16
+ umulh x6,x6,x6
+ adcs x17,x17,x17
+ mul x11,x7,x7 // a[3]*a[3]
+ adcs x19,x19,x19
+ umulh x7,x7,x7
+ adcs x20,x20,x20
+ adcs x1,x1,x1
+ adc x3,xzr,xzr
+
+ adds x15,x15,x4 // +a[i]*a[i]
+ mul x24,x14,x23
+ adcs x16,x16,x9
+ adcs x17,x17,x5
+ adcs x19,x19,x10
+ adcs x20,x20,x6
+ adcs x1,x1,x11
+ adc x3,x3,x7
+ subs xzr,x14,#1
+ umulh x9,x12,x24
+ mul x10,x13,x24
+ umulh x11,x13,x24
+
+ adcs x10,x10,x9
+ adc x11,x11,xzr
+
+ adds x14,x15,x10
+ adcs x15,x16,x11
+ adcs x16,x17,x24
+ adc x17,xzr,x24 // can't overflow
+ mul x11,x14,x23
+ lsl x8,x24,#32
+ subs x15,x15,x24
+ lsr x9,x24,#32
+ sbcs x16,x16,x8
+ sbc x17,x17,x9 // can't borrow
+ subs xzr,x14,#1
+ umulh x9,x12,x11
+ mul x10,x13,x11
+ umulh x24,x13,x11
+
+ adcs x10,x10,x9
+ adc x24,x24,xzr
+
+ adds x14,x15,x10
+ adcs x15,x16,x24
+ adcs x16,x17,x11
+ adc x17,xzr,x11 // can't overflow
+ mul x24,x14,x23
+ lsl x8,x11,#32
+ subs x15,x15,x11
+ lsr x9,x11,#32
+ sbcs x16,x16,x8
+ sbc x17,x17,x9 // can't borrow
+ subs xzr,x14,#1
+ umulh x9,x12,x24
+ mul x10,x13,x24
+ umulh x11,x13,x24
+
+ adcs x10,x10,x9
+ adc x11,x11,xzr
+
+ adds x14,x15,x10
+ adcs x15,x16,x11
+ adcs x16,x17,x24
+ adc x17,xzr,x24 // can't overflow
+ mul x11,x14,x23
+ lsl x8,x24,#32
+ subs x15,x15,x24
+ lsr x9,x24,#32
+ sbcs x16,x16,x8
+ sbc x17,x17,x9 // can't borrow
+ subs xzr,x14,#1
+ umulh x9,x12,x11
+ mul x10,x13,x11
+ umulh x24,x13,x11
+
+ adcs x10,x10,x9
+ adc x24,x24,xzr
+
+ adds x14,x15,x10
+ adcs x15,x16,x24
+ adcs x16,x17,x11
+ adc x17,xzr,x11 // can't overflow
+ lsl x8,x11,#32
+ subs x15,x15,x11
+ lsr x9,x11,#32
+ sbcs x16,x16,x8
+ sbc x17,x17,x9 // can't borrow
+ adds x14,x14,x19 // accumulate upper half
+ adcs x15,x15,x20
+ adcs x16,x16,x1
+ adcs x17,x17,x3
+ adc x19,xzr,xzr
+
+ subs x8,x14,x12 // ret -= modulus
+ sbcs x9,x15,x13
+ sbcs x10,x16,x21
+ sbcs x11,x17,x22
+ sbcs xzr,x19,xzr
+
+ csel x4,x14,x8,lo // ret = borrow ? ret : ret-modulus
+ csel x5,x15,x9,lo
+ csel x6,x16,x10,lo
+ csel x7,x17,x11,lo
+
+ cbnz x2,.Loop_ord_sqr
+
+ stp x4,x5,[x0]
+ stp x6,x7,[x0,#16]
+
+ ldp x19,x20,[sp,#16]
+ ldp x21,x22,[sp,#32]
+ ldp x23,x24,[sp,#48]
+ ldr x29,[sp],#64
+ ret
+.size ecp_nistz256_ord_sqr_mont,.-ecp_nistz256_ord_sqr_mont
+// void ecp_nistz256_scatter_w5(void *x0,const P256_POINT *x1,
+// int x2);
+.globl ecp_nistz256_scatter_w5
+.type ecp_nistz256_scatter_w5,%function
+.align 4
+ecp_nistz256_scatter_w5:
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+
+ add x0,x0,x2,lsl#2
+
+ ldp x4,x5,[x1] // X
+ ldp x6,x7,[x1,#16]
+ stur w4,[x0,#64*0-4]
+ lsr x4,x4,#32
+ str w5,[x0,#64*1-4]
+ lsr x5,x5,#32
+ str w6,[x0,#64*2-4]
+ lsr x6,x6,#32
+ str w7,[x0,#64*3-4]
+ lsr x7,x7,#32
+ str w4,[x0,#64*4-4]
+ str w5,[x0,#64*5-4]
+ str w6,[x0,#64*6-4]
+ str w7,[x0,#64*7-4]
+ add x0,x0,#64*8
+
+ ldp x4,x5,[x1,#32] // Y
+ ldp x6,x7,[x1,#48]
+ stur w4,[x0,#64*0-4]
+ lsr x4,x4,#32
+ str w5,[x0,#64*1-4]
+ lsr x5,x5,#32
+ str w6,[x0,#64*2-4]
+ lsr x6,x6,#32
+ str w7,[x0,#64*3-4]
+ lsr x7,x7,#32
+ str w4,[x0,#64*4-4]
+ str w5,[x0,#64*5-4]
+ str w6,[x0,#64*6-4]
+ str w7,[x0,#64*7-4]
+ add x0,x0,#64*8
+
+ ldp x4,x5,[x1,#64] // Z
+ ldp x6,x7,[x1,#80]
+ stur w4,[x0,#64*0-4]
+ lsr x4,x4,#32
+ str w5,[x0,#64*1-4]
+ lsr x5,x5,#32
+ str w6,[x0,#64*2-4]
+ lsr x6,x6,#32
+ str w7,[x0,#64*3-4]
+ lsr x7,x7,#32
+ str w4,[x0,#64*4-4]
+ str w5,[x0,#64*5-4]
+ str w6,[x0,#64*6-4]
+ str w7,[x0,#64*7-4]
+
+ ldr x29,[sp],#16
+ ret
+.size ecp_nistz256_scatter_w5,.-ecp_nistz256_scatter_w5
+
+// void ecp_nistz256_gather_w5(P256_POINT *x0,const void *x1,
+// int x2);
+.globl ecp_nistz256_gather_w5
+.type ecp_nistz256_gather_w5,%function
+.align 4
+ecp_nistz256_gather_w5:
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+
+ cmp x2,xzr
+ csetm x3,ne
+ add x2,x2,x3
+ add x1,x1,x2,lsl#2
+
+ ldr w4,[x1,#64*0]
+ ldr w5,[x1,#64*1]
+ ldr w6,[x1,#64*2]
+ ldr w7,[x1,#64*3]
+ ldr w8,[x1,#64*4]
+ ldr w9,[x1,#64*5]
+ ldr w10,[x1,#64*6]
+ ldr w11,[x1,#64*7]
+ add x1,x1,#64*8
+ orr x4,x4,x8,lsl#32
+ orr x5,x5,x9,lsl#32
+ orr x6,x6,x10,lsl#32
+ orr x7,x7,x11,lsl#32
+ csel x4,x4,xzr,ne
+ csel x5,x5,xzr,ne
+ csel x6,x6,xzr,ne
+ csel x7,x7,xzr,ne
+ stp x4,x5,[x0] // X
+ stp x6,x7,[x0,#16]
+
+ ldr w4,[x1,#64*0]
+ ldr w5,[x1,#64*1]
+ ldr w6,[x1,#64*2]
+ ldr w7,[x1,#64*3]
+ ldr w8,[x1,#64*4]
+ ldr w9,[x1,#64*5]
+ ldr w10,[x1,#64*6]
+ ldr w11,[x1,#64*7]
+ add x1,x1,#64*8
+ orr x4,x4,x8,lsl#32
+ orr x5,x5,x9,lsl#32
+ orr x6,x6,x10,lsl#32
+ orr x7,x7,x11,lsl#32
+ csel x4,x4,xzr,ne
+ csel x5,x5,xzr,ne
+ csel x6,x6,xzr,ne
+ csel x7,x7,xzr,ne
+ stp x4,x5,[x0,#32] // Y
+ stp x6,x7,[x0,#48]
+
+ ldr w4,[x1,#64*0]
+ ldr w5,[x1,#64*1]
+ ldr w6,[x1,#64*2]
+ ldr w7,[x1,#64*3]
+ ldr w8,[x1,#64*4]
+ ldr w9,[x1,#64*5]
+ ldr w10,[x1,#64*6]
+ ldr w11,[x1,#64*7]
+ orr x4,x4,x8,lsl#32
+ orr x5,x5,x9,lsl#32
+ orr x6,x6,x10,lsl#32
+ orr x7,x7,x11,lsl#32
+ csel x4,x4,xzr,ne
+ csel x5,x5,xzr,ne
+ csel x6,x6,xzr,ne
+ csel x7,x7,xzr,ne
+ stp x4,x5,[x0,#64] // Z
+ stp x6,x7,[x0,#80]
+
+ ldr x29,[sp],#16
+ ret
+.size ecp_nistz256_gather_w5,.-ecp_nistz256_gather_w5
+
+// void ecp_nistz256_scatter_w7(void *x0,const P256_POINT_AFFINE *x1,
+// int x2);
+.globl ecp_nistz256_scatter_w7
+.type ecp_nistz256_scatter_w7,%function
+.align 4
+ecp_nistz256_scatter_w7:
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+
+ add x0,x0,x2
+ mov x2,#64/8
+.Loop_scatter_w7:
+ ldr x3,[x1],#8
+ subs x2,x2,#1
+ prfm pstl1strm,[x0,#4096+64*0]
+ prfm pstl1strm,[x0,#4096+64*1]
+ prfm pstl1strm,[x0,#4096+64*2]
+ prfm pstl1strm,[x0,#4096+64*3]
+ prfm pstl1strm,[x0,#4096+64*4]
+ prfm pstl1strm,[x0,#4096+64*5]
+ prfm pstl1strm,[x0,#4096+64*6]
+ prfm pstl1strm,[x0,#4096+64*7]
+ strb w3,[x0,#64*0]
+ lsr x3,x3,#8
+ strb w3,[x0,#64*1]
+ lsr x3,x3,#8
+ strb w3,[x0,#64*2]
+ lsr x3,x3,#8
+ strb w3,[x0,#64*3]
+ lsr x3,x3,#8
+ strb w3,[x0,#64*4]
+ lsr x3,x3,#8
+ strb w3,[x0,#64*5]
+ lsr x3,x3,#8
+ strb w3,[x0,#64*6]
+ lsr x3,x3,#8
+ strb w3,[x0,#64*7]
+ add x0,x0,#64*8
+ b.ne .Loop_scatter_w7
+
+ ldr x29,[sp],#16
+ ret
+.size ecp_nistz256_scatter_w7,.-ecp_nistz256_scatter_w7
+
+// void ecp_nistz256_gather_w7(P256_POINT_AFFINE *x0,const void *x1,
+// int x2);
+.globl ecp_nistz256_gather_w7
+.type ecp_nistz256_gather_w7,%function
+.align 4
+ecp_nistz256_gather_w7:
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+
+ cmp x2,xzr
+ csetm x3,ne
+ add x2,x2,x3
+ add x1,x1,x2
+ mov x2,#64/8
+ nop
+.Loop_gather_w7:
+ ldrb w4,[x1,#64*0]
+ prfm pldl1strm,[x1,#4096+64*0]
+ subs x2,x2,#1
+ ldrb w5,[x1,#64*1]
+ prfm pldl1strm,[x1,#4096+64*1]
+ ldrb w6,[x1,#64*2]
+ prfm pldl1strm,[x1,#4096+64*2]
+ ldrb w7,[x1,#64*3]
+ prfm pldl1strm,[x1,#4096+64*3]
+ ldrb w8,[x1,#64*4]
+ prfm pldl1strm,[x1,#4096+64*4]
+ ldrb w9,[x1,#64*5]
+ prfm pldl1strm,[x1,#4096+64*5]
+ ldrb w10,[x1,#64*6]
+ prfm pldl1strm,[x1,#4096+64*6]
+ ldrb w11,[x1,#64*7]
+ prfm pldl1strm,[x1,#4096+64*7]
+ add x1,x1,#64*8
+ orr x4,x4,x5,lsl#8
+ orr x6,x6,x7,lsl#8
+ orr x8,x8,x9,lsl#8
+ orr x4,x4,x6,lsl#16
+ orr x10,x10,x11,lsl#8
+ orr x4,x4,x8,lsl#32
+ orr x4,x4,x10,lsl#48
+ and x4,x4,x3
+ str x4,[x0],#8
+ b.ne .Loop_gather_w7
+
+ ldr x29,[sp],#16
+ ret
+.size ecp_nistz256_gather_w7,.-ecp_nistz256_gather_w7
diff --git a/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/modes/aes-gcm-armv8_64.S b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/modes/aes-gcm-armv8_64.S
new file mode 100644
index 000000000000..6b0bda3ad8d5
--- /dev/null
+++ b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/modes/aes-gcm-armv8_64.S
@@ -0,0 +1,6389 @@
+#include "arm_arch.h"
+
+#if __ARM_MAX_ARCH__>=8
+.arch armv8-a+crypto
+.text
+.globl aes_gcm_enc_128_kernel
+.type aes_gcm_enc_128_kernel,%function
+.align 4
+aes_gcm_enc_128_kernel:
+ cbz x1, .L128_enc_ret
+ stp x19, x20, [sp, #-112]!
+ mov x16, x4
+ mov x8, x5
+ stp x21, x22, [sp, #16]
+ stp x23, x24, [sp, #32]
+ stp d8, d9, [sp, #48]
+ stp d10, d11, [sp, #64]
+ stp d12, d13, [sp, #80]
+ stp d14, d15, [sp, #96]
+
+ ldp x10, x11, [x16] //ctr96_b64, ctr96_t32
+#ifdef __AARCH64EB__
+ rev x10, x10
+ rev x11, x11
+#endif
+ ldp x13, x14, [x8, #160] //load rk10
+#ifdef __AARCH64EB__
+ ror x13, x13, #32
+ ror x14, x14, #32
+#endif
+ ld1 {v11.16b}, [x3]
+ ext v11.16b, v11.16b, v11.16b, #8
+ rev64 v11.16b, v11.16b
+ lsr x5, x1, #3 //byte_len
+ mov x15, x5
+
+ ld1 {v18.4s}, [x8], #16 //load rk0
+ add x4, x0, x1, lsr #3 //end_input_ptr
+ sub x5, x5, #1 //byte_len - 1
+
+ lsr x12, x11, #32
+ ldr q15, [x3, #112] //load h4l | h4h
+#ifndef __AARCH64EB__
+ ext v15.16b, v15.16b, v15.16b, #8
+#endif
+ fmov d1, x10 //CTR block 1
+ rev w12, w12 //rev_ctr32
+
+ add w12, w12, #1 //increment rev_ctr32
+ orr w11, w11, w11
+ ld1 {v19.4s}, [x8], #16 //load rk1
+
+ rev w9, w12 //CTR block 1
+ add w12, w12, #1 //CTR block 1
+ fmov d3, x10 //CTR block 3
+
+ orr x9, x11, x9, lsl #32 //CTR block 1
+ ld1 { v0.16b}, [x16] //special case vector load initial counter so we can start first AES block as quickly as possible
+
+ fmov v1.d[1], x9 //CTR block 1
+ rev w9, w12 //CTR block 2
+
+ fmov d2, x10 //CTR block 2
+ orr x9, x11, x9, lsl #32 //CTR block 2
+ add w12, w12, #1 //CTR block 2
+
+ fmov v2.d[1], x9 //CTR block 2
+ rev w9, w12 //CTR block 3
+
+ orr x9, x11, x9, lsl #32 //CTR block 3
+ ld1 {v20.4s}, [x8], #16 //load rk2
+
+ add w12, w12, #1 //CTR block 3
+ fmov v3.d[1], x9 //CTR block 3
+
+ ldr q14, [x3, #80] //load h3l | h3h
+#ifndef __AARCH64EB__
+ ext v14.16b, v14.16b, v14.16b, #8
+#endif
+ aese v1.16b, v18.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 0
+ ld1 {v21.4s}, [x8], #16 //load rk3
+
+ aese v2.16b, v18.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 0
+ ldr q12, [x3, #32] //load h1l | h1h
+#ifndef __AARCH64EB__
+ ext v12.16b, v12.16b, v12.16b, #8
+#endif
+
+ aese v0.16b, v18.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 0
+ ld1 {v22.4s}, [x8], #16 //load rk4
+
+ aese v3.16b, v18.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 0
+ ld1 {v23.4s}, [x8], #16 //load rk5
+
+ aese v2.16b, v19.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 1
+ trn2 v17.2d, v14.2d, v15.2d //h4l | h3l
+
+ aese v0.16b, v19.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 1
+ ld1 {v24.4s}, [x8], #16 //load rk6
+
+ aese v1.16b, v19.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 1
+ ld1 {v25.4s}, [x8], #16 //load rk7
+
+ aese v3.16b, v19.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 1
+ trn1 v9.2d, v14.2d, v15.2d //h4h | h3h
+
+ aese v0.16b, v20.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 2
+ ld1 {v26.4s}, [x8], #16 //load rk8
+
+ aese v1.16b, v20.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 2
+ ldr q13, [x3, #64] //load h2l | h2h
+#ifndef __AARCH64EB__
+ ext v13.16b, v13.16b, v13.16b, #8
+#endif
+
+ aese v3.16b, v20.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 2
+
+ aese v2.16b, v20.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 2
+ eor v17.16b, v17.16b, v9.16b //h4k | h3k
+
+ aese v0.16b, v21.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 3
+
+ aese v1.16b, v21.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 3
+
+ aese v2.16b, v21.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 3
+ ld1 {v27.4s}, [x8], #16 //load rk9
+
+ aese v3.16b, v21.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 3
+
+ and x5, x5, #0xffffffffffffffc0 //number of bytes to be processed in main loop (at least 1 byte must be handled by tail)
+ trn2 v16.2d, v12.2d, v13.2d //h2l | h1l
+
+ aese v3.16b, v22.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 4
+ add x5, x5, x0
+
+ aese v2.16b, v22.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 4
+ cmp x0, x5 //check if we have <= 4 blocks
+
+ aese v0.16b, v22.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 4
+
+ aese v3.16b, v23.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 5
+
+ aese v2.16b, v23.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 5
+
+ aese v0.16b, v23.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 5
+
+ aese v3.16b, v24.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 6
+
+ aese v1.16b, v22.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 4
+
+ aese v2.16b, v24.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 6
+ trn1 v8.2d, v12.2d, v13.2d //h2h | h1h
+
+ aese v0.16b, v24.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 6
+
+ aese v1.16b, v23.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 5
+
+ aese v3.16b, v25.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 7
+
+ aese v0.16b, v25.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 7
+
+ aese v1.16b, v24.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 6
+
+ aese v2.16b, v25.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 7
+
+ aese v0.16b, v26.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 8
+
+ aese v1.16b, v25.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 7
+
+ aese v2.16b, v26.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 8
+
+ aese v3.16b, v26.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 8
+
+ aese v1.16b, v26.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 8
+
+ aese v2.16b, v27.16b //AES block 2 - round 9
+
+ aese v0.16b, v27.16b //AES block 0 - round 9
+
+ eor v16.16b, v16.16b, v8.16b //h2k | h1k
+
+ aese v1.16b, v27.16b //AES block 1 - round 9
+
+ aese v3.16b, v27.16b //AES block 3 - round 9
+ b.ge .L128_enc_tail //handle tail
+
+ ldp x6, x7, [x0, #0] //AES block 0 - load plaintext
+#ifdef __AARCH64EB__
+ rev x6, x6
+ rev x7, x7
+#endif
+ ldp x21, x22, [x0, #32] //AES block 2 - load plaintext
+#ifdef __AARCH64EB__
+ rev x21, x21
+ rev x22, x22
+#endif
+ ldp x19, x20, [x0, #16] //AES block 1 - load plaintext
+#ifdef __AARCH64EB__
+ rev x19, x19
+ rev x20, x20
+#endif
+ ldp x23, x24, [x0, #48] //AES block 3 - load plaintext
+#ifdef __AARCH64EB__
+ rev x23, x23
+ rev x24, x24
+#endif
+ eor x6, x6, x13 //AES block 0 - round 10 low
+ eor x7, x7, x14 //AES block 0 - round 10 high
+
+ eor x21, x21, x13 //AES block 2 - round 10 low
+ fmov d4, x6 //AES block 0 - mov low
+
+ eor x19, x19, x13 //AES block 1 - round 10 low
+ eor x22, x22, x14 //AES block 2 - round 10 high
+ fmov v4.d[1], x7 //AES block 0 - mov high
+
+ fmov d5, x19 //AES block 1 - mov low
+ eor x20, x20, x14 //AES block 1 - round 10 high
+
+ eor x23, x23, x13 //AES block 3 - round 10 low
+ fmov v5.d[1], x20 //AES block 1 - mov high
+
+ fmov d6, x21 //AES block 2 - mov low
+ eor x24, x24, x14 //AES block 3 - round 10 high
+ rev w9, w12 //CTR block 4
+
+ fmov v6.d[1], x22 //AES block 2 - mov high
+ orr x9, x11, x9, lsl #32 //CTR block 4
+
+ eor v4.16b, v4.16b, v0.16b //AES block 0 - result
+ fmov d0, x10 //CTR block 4
+ add w12, w12, #1 //CTR block 4
+
+ fmov v0.d[1], x9 //CTR block 4
+ rev w9, w12 //CTR block 5
+
+ eor v5.16b, v5.16b, v1.16b //AES block 1 - result
+ fmov d1, x10 //CTR block 5
+ orr x9, x11, x9, lsl #32 //CTR block 5
+
+ add w12, w12, #1 //CTR block 5
+ add x0, x0, #64 //AES input_ptr update
+ fmov v1.d[1], x9 //CTR block 5
+
+ fmov d7, x23 //AES block 3 - mov low
+ rev w9, w12 //CTR block 6
+ st1 { v4.16b}, [x2], #16 //AES block 0 - store result
+
+ fmov v7.d[1], x24 //AES block 3 - mov high
+ orr x9, x11, x9, lsl #32 //CTR block 6
+
+ add w12, w12, #1 //CTR block 6
+ eor v6.16b, v6.16b, v2.16b //AES block 2 - result
+ st1 { v5.16b}, [x2], #16 //AES block 1 - store result
+
+ fmov d2, x10 //CTR block 6
+ cmp x0, x5 //check if we have <= 8 blocks
+
+ fmov v2.d[1], x9 //CTR block 6
+ rev w9, w12 //CTR block 7
+ st1 { v6.16b}, [x2], #16 //AES block 2 - store result
+
+ orr x9, x11, x9, lsl #32 //CTR block 7
+
+ eor v7.16b, v7.16b, v3.16b //AES block 3 - result
+ st1 { v7.16b}, [x2], #16 //AES block 3 - store result
+ b.ge .L128_enc_prepretail //do prepretail
+
+.L128_enc_main_loop: //main loop start
+ ldp x23, x24, [x0, #48] //AES block 4k+3 - load plaintext
+#ifdef __AARCH64EB__
+ rev x23, x23
+ rev x24, x24
+#endif
+ rev64 v4.16b, v4.16b //GHASH block 4k (only t0 is free)
+ rev64 v6.16b, v6.16b //GHASH block 4k+2 (t0, t1, and t2 free)
+
+ aese v2.16b, v18.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 0
+ fmov d3, x10 //CTR block 4k+3
+
+ ext v11.16b, v11.16b, v11.16b, #8 //PRE 0
+ rev64 v5.16b, v5.16b //GHASH block 4k+1 (t0 and t1 free)
+
+ aese v1.16b, v18.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 0
+ add w12, w12, #1 //CTR block 4k+3
+ fmov v3.d[1], x9 //CTR block 4k+3
+
+ aese v0.16b, v18.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 0
+ mov d31, v6.d[1] //GHASH block 4k+2 - mid
+
+ aese v2.16b, v19.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 1
+ mov d30, v5.d[1] //GHASH block 4k+1 - mid
+
+ aese v1.16b, v19.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 1
+ eor v4.16b, v4.16b, v11.16b //PRE 1
+
+ aese v3.16b, v18.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 0
+ eor x24, x24, x14 //AES block 4k+3 - round 10 high
+
+ pmull2 v28.1q, v5.2d, v14.2d //GHASH block 4k+1 - high
+ eor v31.8b, v31.8b, v6.8b //GHASH block 4k+2 - mid
+ ldp x6, x7, [x0, #0] //AES block 4k+4 - load plaintext
+#ifdef __AARCH64EB__
+ rev x6, x6
+ rev x7, x7
+#endif
+ aese v0.16b, v19.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 1
+ rev w9, w12 //CTR block 4k+8
+
+ eor v30.8b, v30.8b, v5.8b //GHASH block 4k+1 - mid
+ mov d8, v4.d[1] //GHASH block 4k - mid
+ orr x9, x11, x9, lsl #32 //CTR block 4k+8
+
+ pmull2 v9.1q, v4.2d, v15.2d //GHASH block 4k - high
+ add w12, w12, #1 //CTR block 4k+8
+ mov d10, v17.d[1] //GHASH block 4k - mid
+
+ aese v0.16b, v20.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 2
+
+ pmull v11.1q, v4.1d, v15.1d //GHASH block 4k - low
+ eor v8.8b, v8.8b, v4.8b //GHASH block 4k - mid
+
+ aese v1.16b, v20.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 2
+
+ aese v0.16b, v21.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 3
+ eor v9.16b, v9.16b, v28.16b //GHASH block 4k+1 - high
+
+ pmull v28.1q, v6.1d, v13.1d //GHASH block 4k+2 - low
+
+ pmull v10.1q, v8.1d, v10.1d //GHASH block 4k - mid
+ rev64 v7.16b, v7.16b //GHASH block 4k+3 (t0, t1, t2 and t3 free)
+
+ pmull v30.1q, v30.1d, v17.1d //GHASH block 4k+1 - mid
+
+ pmull v29.1q, v5.1d, v14.1d //GHASH block 4k+1 - low
+ ins v31.d[1], v31.d[0] //GHASH block 4k+2 - mid
+
+ pmull2 v8.1q, v6.2d, v13.2d //GHASH block 4k+2 - high
+ eor x7, x7, x14 //AES block 4k+4 - round 10 high
+
+ eor v10.16b, v10.16b, v30.16b //GHASH block 4k+1 - mid
+ mov d30, v7.d[1] //GHASH block 4k+3 - mid
+
+ aese v3.16b, v19.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 1
+ eor v11.16b, v11.16b, v29.16b //GHASH block 4k+1 - low
+
+ aese v2.16b, v20.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 2
+ eor x6, x6, x13 //AES block 4k+4 - round 10 low
+
+ aese v1.16b, v21.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 3
+ eor v30.8b, v30.8b, v7.8b //GHASH block 4k+3 - mid
+
+ pmull2 v4.1q, v7.2d, v12.2d //GHASH block 4k+3 - high
+
+ aese v2.16b, v21.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 3
+ eor v9.16b, v9.16b, v8.16b //GHASH block 4k+2 - high
+
+ pmull2 v31.1q, v31.2d, v16.2d //GHASH block 4k+2 - mid
+
+ pmull v29.1q, v7.1d, v12.1d //GHASH block 4k+3 - low
+ movi v8.8b, #0xc2
+
+ pmull v30.1q, v30.1d, v16.1d //GHASH block 4k+3 - mid
+ eor v11.16b, v11.16b, v28.16b //GHASH block 4k+2 - low
+
+ aese v1.16b, v22.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 4
+
+ aese v3.16b, v20.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 2
+ shl d8, d8, #56 //mod_constant
+
+ aese v0.16b, v22.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 4
+ eor v9.16b, v9.16b, v4.16b //GHASH block 4k+3 - high
+
+ aese v1.16b, v23.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 5
+ ldp x19, x20, [x0, #16] //AES block 4k+5 - load plaintext
+#ifdef __AARCH64EB__
+ rev x19, x19
+ rev x20, x20
+#endif
+ aese v3.16b, v21.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 3
+ eor v10.16b, v10.16b, v31.16b //GHASH block 4k+2 - mid
+
+ aese v0.16b, v23.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 5
+ ldp x21, x22, [x0, #32] //AES block 4k+6 - load plaintext
+#ifdef __AARCH64EB__
+ rev x21, x21
+ rev x22, x22
+#endif
+ pmull v31.1q, v9.1d, v8.1d //MODULO - top 64b align with mid
+ eor v11.16b, v11.16b, v29.16b //GHASH block 4k+3 - low
+
+ aese v2.16b, v22.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 4
+ eor x19, x19, x13 //AES block 4k+5 - round 10 low
+
+ aese v3.16b, v22.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 4
+ eor v10.16b, v10.16b, v30.16b //GHASH block 4k+3 - mid
+
+ aese v1.16b, v24.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 6
+ eor x23, x23, x13 //AES block 4k+3 - round 10 low
+
+ aese v2.16b, v23.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 5
+ eor v30.16b, v11.16b, v9.16b //MODULO - karatsuba tidy up
+
+ fmov d4, x6 //AES block 4k+4 - mov low
+ aese v0.16b, v24.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 6
+ fmov v4.d[1], x7 //AES block 4k+4 - mov high
+
+ add x0, x0, #64 //AES input_ptr update
+ fmov d7, x23 //AES block 4k+3 - mov low
+ ext v9.16b, v9.16b, v9.16b, #8 //MODULO - other top alignment
+
+ aese v3.16b, v23.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 5
+ fmov d5, x19 //AES block 4k+5 - mov low
+
+ aese v0.16b, v25.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 7
+ eor v10.16b, v10.16b, v30.16b //MODULO - karatsuba tidy up
+
+ aese v2.16b, v24.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 6
+ eor x20, x20, x14 //AES block 4k+5 - round 10 high
+
+ aese v1.16b, v25.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 7
+ fmov v5.d[1], x20 //AES block 4k+5 - mov high
+
+ aese v0.16b, v26.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 8
+ fmov v7.d[1], x24 //AES block 4k+3 - mov high
+
+ aese v3.16b, v24.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 6
+ cmp x0, x5 //.LOOP CONTROL
+
+ aese v1.16b, v26.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 8
+ eor v10.16b, v10.16b, v31.16b //MODULO - fold into mid
+
+ aese v0.16b, v27.16b //AES block 4k+4 - round 9
+ eor x21, x21, x13 //AES block 4k+6 - round 10 low
+ eor x22, x22, x14 //AES block 4k+6 - round 10 high
+
+ aese v3.16b, v25.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 7
+ fmov d6, x21 //AES block 4k+6 - mov low
+
+ aese v1.16b, v27.16b //AES block 4k+5 - round 9
+ fmov v6.d[1], x22 //AES block 4k+6 - mov high
+
+ aese v2.16b, v25.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 7
+ eor v4.16b, v4.16b, v0.16b //AES block 4k+4 - result
+
+ fmov d0, x10 //CTR block 4k+8
+ aese v3.16b, v26.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 8
+
+ fmov v0.d[1], x9 //CTR block 4k+8
+ rev w9, w12 //CTR block 4k+9
+ eor v10.16b, v10.16b, v9.16b //MODULO - fold into mid
+
+ aese v2.16b, v26.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 8
+ eor v5.16b, v5.16b, v1.16b //AES block 4k+5 - result
+
+ add w12, w12, #1 //CTR block 4k+9
+ orr x9, x11, x9, lsl #32 //CTR block 4k+9
+ fmov d1, x10 //CTR block 4k+9
+
+ pmull v9.1q, v10.1d, v8.1d //MODULO - mid 64b align with low
+ fmov v1.d[1], x9 //CTR block 4k+9
+ rev w9, w12 //CTR block 4k+10
+
+ aese v2.16b, v27.16b //AES block 4k+6 - round 9
+ st1 { v4.16b}, [x2], #16 //AES block 4k+4 - store result
+ eor v6.16b, v6.16b, v2.16b //AES block 4k+6 - result
+ orr x9, x11, x9, lsl #32 //CTR block 4k+10
+
+ aese v3.16b, v27.16b //AES block 4k+7 - round 9
+ add w12, w12, #1 //CTR block 4k+10
+ ext v10.16b, v10.16b, v10.16b, #8 //MODULO - other mid alignment
+ fmov d2, x10 //CTR block 4k+10
+
+ eor v11.16b, v11.16b, v9.16b //MODULO - fold into low
+ st1 { v5.16b}, [x2], #16 //AES block 4k+5 - store result
+
+ fmov v2.d[1], x9 //CTR block 4k+10
+ st1 { v6.16b}, [x2], #16 //AES block 4k+6 - store result
+ rev w9, w12 //CTR block 4k+11
+
+ orr x9, x11, x9, lsl #32 //CTR block 4k+11
+ eor v7.16b, v7.16b, v3.16b //AES block 4k+3 - result
+
+ eor v11.16b, v11.16b, v10.16b //MODULO - fold into low
+ st1 { v7.16b}, [x2], #16 //AES block 4k+3 - store result
+ b.lt .L128_enc_main_loop
+
+.L128_enc_prepretail: //PREPRETAIL
+ rev64 v4.16b, v4.16b //GHASH block 4k (only t0 is free)
+ fmov d3, x10 //CTR block 4k+3
+ rev64 v5.16b, v5.16b //GHASH block 4k+1 (t0 and t1 free)
+
+ ext v11.16b, v11.16b, v11.16b, #8 //PRE 0
+ add w12, w12, #1 //CTR block 4k+3
+ fmov v3.d[1], x9 //CTR block 4k+3
+
+ aese v1.16b, v18.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 0
+ rev64 v6.16b, v6.16b //GHASH block 4k+2 (t0, t1, and t2 free)
+
+ pmull v29.1q, v5.1d, v14.1d //GHASH block 4k+1 - low
+
+ rev64 v7.16b, v7.16b //GHASH block 4k+3 (t0, t1, t2 and t3 free)
+ eor v4.16b, v4.16b, v11.16b //PRE 1
+
+ pmull2 v28.1q, v5.2d, v14.2d //GHASH block 4k+1 - high
+
+ aese v3.16b, v18.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 0
+ mov d30, v5.d[1] //GHASH block 4k+1 - mid
+
+ pmull v11.1q, v4.1d, v15.1d //GHASH block 4k - low
+ mov d8, v4.d[1] //GHASH block 4k - mid
+
+ mov d31, v6.d[1] //GHASH block 4k+2 - mid
+ mov d10, v17.d[1] //GHASH block 4k - mid
+
+ aese v1.16b, v19.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 1
+ eor v30.8b, v30.8b, v5.8b //GHASH block 4k+1 - mid
+
+ eor v8.8b, v8.8b, v4.8b //GHASH block 4k - mid
+
+ pmull2 v9.1q, v4.2d, v15.2d //GHASH block 4k - high
+ eor v31.8b, v31.8b, v6.8b //GHASH block 4k+2 - mid
+
+ aese v3.16b, v19.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 1
+
+ pmull v30.1q, v30.1d, v17.1d //GHASH block 4k+1 - mid
+ eor v11.16b, v11.16b, v29.16b //GHASH block 4k+1 - low
+
+ pmull v10.1q, v8.1d, v10.1d //GHASH block 4k - mid
+
+ aese v0.16b, v18.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 0
+ ins v31.d[1], v31.d[0] //GHASH block 4k+2 - mid
+
+ aese v2.16b, v18.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 0
+
+ eor v10.16b, v10.16b, v30.16b //GHASH block 4k+1 - mid
+ mov d30, v7.d[1] //GHASH block 4k+3 - mid
+
+ aese v0.16b, v19.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 1
+ eor v9.16b, v9.16b, v28.16b //GHASH block 4k+1 - high
+
+ pmull2 v31.1q, v31.2d, v16.2d //GHASH block 4k+2 - mid
+
+ pmull2 v8.1q, v6.2d, v13.2d //GHASH block 4k+2 - high
+ eor v30.8b, v30.8b, v7.8b //GHASH block 4k+3 - mid
+
+ pmull2 v4.1q, v7.2d, v12.2d //GHASH block 4k+3 - high
+
+ pmull v28.1q, v6.1d, v13.1d //GHASH block 4k+2 - low
+
+ aese v2.16b, v19.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 1
+ eor v9.16b, v9.16b, v8.16b //GHASH block 4k+2 - high
+
+ aese v0.16b, v20.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 2
+
+ pmull v29.1q, v7.1d, v12.1d //GHASH block 4k+3 - low
+ movi v8.8b, #0xc2
+
+ aese v2.16b, v20.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 2
+ eor v11.16b, v11.16b, v28.16b //GHASH block 4k+2 - low
+
+ aese v3.16b, v20.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 2
+
+ pmull v30.1q, v30.1d, v16.1d //GHASH block 4k+3 - mid
+ eor v10.16b, v10.16b, v31.16b //GHASH block 4k+2 - mid
+
+ aese v2.16b, v21.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 3
+
+ aese v1.16b, v20.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 2
+ eor v9.16b, v9.16b, v4.16b //GHASH block 4k+3 - high
+
+ aese v0.16b, v21.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 3
+
+ eor v10.16b, v10.16b, v30.16b //GHASH block 4k+3 - mid
+ shl d8, d8, #56 //mod_constant
+
+ aese v1.16b, v21.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 3
+ eor v11.16b, v11.16b, v29.16b //GHASH block 4k+3 - low
+
+ aese v0.16b, v22.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 4
+
+ pmull v28.1q, v9.1d, v8.1d
+ eor v10.16b, v10.16b, v9.16b //karatsuba tidy up
+
+ aese v1.16b, v22.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 4
+
+ aese v0.16b, v23.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 5
+ ext v9.16b, v9.16b, v9.16b, #8
+
+ aese v3.16b, v21.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 3
+
+ aese v2.16b, v22.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 4
+ eor v10.16b, v10.16b, v11.16b
+
+ aese v0.16b, v24.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 6
+
+ aese v3.16b, v22.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 4
+
+ aese v1.16b, v23.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 5
+
+ aese v2.16b, v23.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 5
+ eor v10.16b, v10.16b, v28.16b
+
+ aese v3.16b, v23.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 5
+
+ aese v1.16b, v24.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 6
+
+ aese v2.16b, v24.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 6
+
+ aese v3.16b, v24.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 6
+ eor v10.16b, v10.16b, v9.16b
+
+ aese v0.16b, v25.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 7
+
+ aese v2.16b, v25.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 7
+
+ aese v3.16b, v25.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 7
+
+ pmull v28.1q, v10.1d, v8.1d
+
+ aese v1.16b, v25.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 7
+ ext v10.16b, v10.16b, v10.16b, #8
+
+ aese v3.16b, v26.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 8
+
+ aese v0.16b, v26.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 8
+ eor v11.16b, v11.16b, v28.16b
+
+ aese v1.16b, v26.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 8
+
+ aese v3.16b, v27.16b //AES block 4k+7 - round 9
+
+ aese v2.16b, v26.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 8
+
+ aese v0.16b, v27.16b //AES block 4k+4 - round 9
+
+ aese v1.16b, v27.16b //AES block 4k+5 - round 9
+ eor v11.16b, v11.16b, v10.16b
+
+ aese v2.16b, v27.16b //AES block 4k+6 - round 9
+.L128_enc_tail: //TAIL
+
+ sub x5, x4, x0 //main_end_input_ptr is number of bytes left to process
+ ldp x6, x7, [x0], #16 //AES block 4k+4 - load plaintext
+#ifdef __AARCH64EB__
+ rev x6, x6
+ rev x7, x7
+#endif
+ cmp x5, #48
+
+ ext v8.16b, v11.16b, v11.16b, #8 //prepare final partial tag
+ eor x6, x6, x13 //AES block 4k+4 - round 10 low
+ eor x7, x7, x14 //AES block 4k+4 - round 10 high
+
+ fmov d4, x6 //AES block 4k+4 - mov low
+
+ fmov v4.d[1], x7 //AES block 4k+4 - mov high
+
+ eor v5.16b, v4.16b, v0.16b //AES block 4k+4 - result
+
+ b.gt .L128_enc_blocks_more_than_3
+
+ sub w12, w12, #1
+ movi v11.8b, #0
+ mov v3.16b, v2.16b
+
+ cmp x5, #32
+ mov v2.16b, v1.16b
+ movi v9.8b, #0
+
+ movi v10.8b, #0
+ b.gt .L128_enc_blocks_more_than_2
+
+ mov v3.16b, v1.16b
+ cmp x5, #16
+
+ sub w12, w12, #1
+ b.gt .L128_enc_blocks_more_than_1
+
+ sub w12, w12, #1
+ b .L128_enc_blocks_less_than_1
+.L128_enc_blocks_more_than_3: //blocks left > 3
+ st1 { v5.16b}, [x2], #16 //AES final-3 block - store result
+
+ ldp x6, x7, [x0], #16 //AES final-2 block - load input low & high
+#ifdef __AARCH64EB__
+ rev x6, x6
+ rev x7, x7
+#endif
+ rev64 v4.16b, v5.16b //GHASH final-3 block
+
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+ eor x7, x7, x14 //AES final-2 block - round 10 high
+ eor x6, x6, x13 //AES final-2 block - round 10 low
+
+ fmov d5, x6 //AES final-2 block - mov low
+
+ movi v8.8b, #0 //suppress further partial tag feed in
+ fmov v5.d[1], x7 //AES final-2 block - mov high
+
+ pmull v11.1q, v4.1d, v15.1d //GHASH final-3 block - low
+ mov d22, v4.d[1] //GHASH final-3 block - mid
+
+ pmull2 v9.1q, v4.2d, v15.2d //GHASH final-3 block - high
+
+ mov d10, v17.d[1] //GHASH final-3 block - mid
+
+ eor v5.16b, v5.16b, v1.16b //AES final-2 block - result
+ eor v22.8b, v22.8b, v4.8b //GHASH final-3 block - mid
+
+ pmull v10.1q, v22.1d, v10.1d //GHASH final-3 block - mid
+.L128_enc_blocks_more_than_2: //blocks left > 2
+
+ st1 { v5.16b}, [x2], #16 //AES final-2 block - store result
+
+ rev64 v4.16b, v5.16b //GHASH final-2 block
+ ldp x6, x7, [x0], #16 //AES final-1 block - load input low & high
+#ifdef __AARCH64EB__
+ rev x6, x6
+ rev x7, x7
+#endif
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+
+ eor x6, x6, x13 //AES final-1 block - round 10 low
+
+ fmov d5, x6 //AES final-1 block - mov low
+ eor x7, x7, x14 //AES final-1 block - round 10 high
+
+ pmull2 v20.1q, v4.2d, v14.2d //GHASH final-2 block - high
+ fmov v5.d[1], x7 //AES final-1 block - mov high
+
+ mov d22, v4.d[1] //GHASH final-2 block - mid
+
+ pmull v21.1q, v4.1d, v14.1d //GHASH final-2 block - low
+
+ eor v9.16b, v9.16b, v20.16b //GHASH final-2 block - high
+
+ eor v22.8b, v22.8b, v4.8b //GHASH final-2 block - mid
+
+ eor v5.16b, v5.16b, v2.16b //AES final-1 block - result
+
+ eor v11.16b, v11.16b, v21.16b //GHASH final-2 block - low
+
+ pmull v22.1q, v22.1d, v17.1d //GHASH final-2 block - mid
+
+ movi v8.8b, #0 //suppress further partial tag feed in
+
+ eor v10.16b, v10.16b, v22.16b //GHASH final-2 block - mid
+.L128_enc_blocks_more_than_1: //blocks left > 1
+
+ st1 { v5.16b}, [x2], #16 //AES final-1 block - store result
+
+ rev64 v4.16b, v5.16b //GHASH final-1 block
+ ldp x6, x7, [x0], #16 //AES final block - load input low & high
+#ifdef __AARCH64EB__
+ rev x6, x6
+ rev x7, x7
+#endif
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+
+ eor x7, x7, x14 //AES final block - round 10 high
+ eor x6, x6, x13 //AES final block - round 10 low
+
+ fmov d5, x6 //AES final block - mov low
+
+ pmull2 v20.1q, v4.2d, v13.2d //GHASH final-1 block - high
+ fmov v5.d[1], x7 //AES final block - mov high
+
+ mov d22, v4.d[1] //GHASH final-1 block - mid
+
+ pmull v21.1q, v4.1d, v13.1d //GHASH final-1 block - low
+
+ eor v22.8b, v22.8b, v4.8b //GHASH final-1 block - mid
+
+ eor v5.16b, v5.16b, v3.16b //AES final block - result
+
+ ins v22.d[1], v22.d[0] //GHASH final-1 block - mid
+
+ pmull2 v22.1q, v22.2d, v16.2d //GHASH final-1 block - mid
+
+ eor v11.16b, v11.16b, v21.16b //GHASH final-1 block - low
+
+ eor v9.16b, v9.16b, v20.16b //GHASH final-1 block - high
+
+ eor v10.16b, v10.16b, v22.16b //GHASH final-1 block - mid
+ movi v8.8b, #0 //suppress further partial tag feed in
+.L128_enc_blocks_less_than_1: //blocks left <= 1
+
+ and x1, x1, #127 //bit_length %= 128
+ mvn x13, xzr //rk10_l = 0xffffffffffffffff
+
+ mvn x14, xzr //rk10_h = 0xffffffffffffffff
+ sub x1, x1, #128 //bit_length -= 128
+
+ neg x1, x1 //bit_length = 128 - #bits in input (in range [1,128])
+
+ and x1, x1, #127 //bit_length %= 128
+
+ lsr x14, x14, x1 //rk10_h is mask for top 64b of last block
+ cmp x1, #64
+
+ csel x6, x13, x14, lt
+ csel x7, x14, xzr, lt
+
+ fmov d0, x6 //ctr0b is mask for last block
+
+ fmov v0.d[1], x7
+
+ and v5.16b, v5.16b, v0.16b //possibly partial last block has zeroes in highest bits
+
+ rev64 v4.16b, v5.16b //GHASH final block
+
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+
+ mov d8, v4.d[1] //GHASH final block - mid
+
+ pmull v21.1q, v4.1d, v12.1d //GHASH final block - low
+ ld1 { v18.16b}, [x2] //load existing bytes where the possibly partial last block is to be stored
+
+ eor v8.8b, v8.8b, v4.8b //GHASH final block - mid
+#ifndef __AARCH64EB__
+ rev w9, w12
+#else
+ mov w9, w12
+#endif
+ pmull2 v20.1q, v4.2d, v12.2d //GHASH final block - high
+
+ pmull v8.1q, v8.1d, v16.1d //GHASH final block - mid
+
+ eor v11.16b, v11.16b, v21.16b //GHASH final block - low
+
+ eor v9.16b, v9.16b, v20.16b //GHASH final block - high
+
+ eor v10.16b, v10.16b, v8.16b //GHASH final block - mid
+ movi v8.8b, #0xc2
+
+ eor v30.16b, v11.16b, v9.16b //MODULO - karatsuba tidy up
+
+ shl d8, d8, #56 //mod_constant
+
+ eor v10.16b, v10.16b, v30.16b //MODULO - karatsuba tidy up
+
+ pmull v31.1q, v9.1d, v8.1d //MODULO - top 64b align with mid
+
+ ext v9.16b, v9.16b, v9.16b, #8 //MODULO - other top alignment
+
+ eor v10.16b, v10.16b, v31.16b //MODULO - fold into mid
+
+ eor v10.16b, v10.16b, v9.16b //MODULO - fold into mid
+
+ pmull v9.1q, v10.1d, v8.1d //MODULO - mid 64b align with low
+
+ ext v10.16b, v10.16b, v10.16b, #8 //MODULO - other mid alignment
+
+ bif v5.16b, v18.16b, v0.16b //insert existing bytes in top end of result before storing
+
+ eor v11.16b, v11.16b, v9.16b //MODULO - fold into low
+ st1 { v5.16b}, [x2] //store all 16B
+
+ str w9, [x16, #12] //store the updated counter
+
+ eor v11.16b, v11.16b, v10.16b //MODULO - fold into low
+ ext v11.16b, v11.16b, v11.16b, #8
+ rev64 v11.16b, v11.16b
+ mov x0, x15
+ st1 { v11.16b }, [x3]
+ ldp x21, x22, [sp, #16]
+ ldp x23, x24, [sp, #32]
+ ldp d8, d9, [sp, #48]
+ ldp d10, d11, [sp, #64]
+ ldp d12, d13, [sp, #80]
+ ldp d14, d15, [sp, #96]
+ ldp x19, x20, [sp], #112
+ ret
+
+.L128_enc_ret:
+ mov w0, #0x0
+ ret
+.size aes_gcm_enc_128_kernel,.-aes_gcm_enc_128_kernel
+.globl aes_gcm_dec_128_kernel
+.type aes_gcm_dec_128_kernel,%function
+.align 4
+aes_gcm_dec_128_kernel:
+ cbz x1, .L128_dec_ret
+ stp x19, x20, [sp, #-112]!
+ mov x16, x4
+ mov x8, x5
+ stp x21, x22, [sp, #16]
+ stp x23, x24, [sp, #32]
+ stp d8, d9, [sp, #48]
+ stp d10, d11, [sp, #64]
+ stp d12, d13, [sp, #80]
+ stp d14, d15, [sp, #96]
+
+ lsr x5, x1, #3 //byte_len
+ mov x15, x5
+ ldp x10, x11, [x16] //ctr96_b64, ctr96_t32
+#ifdef __AARCH64EB__
+ rev x10, x10
+ rev x11, x11
+#endif
+ ldp x13, x14, [x8, #160] //load rk10
+#ifdef __AARCH64EB__
+ ror x14, x14, 32
+ ror x13, x13, 32
+#endif
+ sub x5, x5, #1 //byte_len - 1
+ ld1 {v18.4s}, [x8], #16 //load rk0
+
+ and x5, x5, #0xffffffffffffffc0 //number of bytes to be processed in main loop (at least 1 byte must be handled by tail)
+ ld1 { v0.16b}, [x16] //special case vector load initial counter so we can start first AES block as quickly as possible
+
+ ldr q13, [x3, #64] //load h2l | h2h
+#ifndef __AARCH64EB__
+ ext v13.16b, v13.16b, v13.16b, #8
+#endif
+ lsr x12, x11, #32
+ fmov d2, x10 //CTR block 2
+
+ ld1 {v19.4s}, [x8], #16 //load rk1
+ orr w11, w11, w11
+ rev w12, w12 //rev_ctr32
+
+ fmov d1, x10 //CTR block 1
+ add w12, w12, #1 //increment rev_ctr32
+
+ aese v0.16b, v18.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 0
+ rev w9, w12 //CTR block 1
+
+ orr x9, x11, x9, lsl #32 //CTR block 1
+ ld1 {v20.4s}, [x8], #16 //load rk2
+ add w12, w12, #1 //CTR block 1
+
+ fmov v1.d[1], x9 //CTR block 1
+ rev w9, w12 //CTR block 2
+ add w12, w12, #1 //CTR block 2
+
+ aese v0.16b, v19.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 1
+ orr x9, x11, x9, lsl #32 //CTR block 2
+
+ fmov v2.d[1], x9 //CTR block 2
+ rev w9, w12 //CTR block 3
+
+ fmov d3, x10 //CTR block 3
+ orr x9, x11, x9, lsl #32 //CTR block 3
+ add w12, w12, #1 //CTR block 3
+
+ fmov v3.d[1], x9 //CTR block 3
+ add x4, x0, x1, lsr #3 //end_input_ptr
+
+ aese v1.16b, v18.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 0
+ ld1 {v21.4s}, [x8], #16 //load rk3
+
+ aese v0.16b, v20.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 2
+ ld1 {v22.4s}, [x8], #16 //load rk4
+
+ aese v2.16b, v18.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 0
+ ld1 {v23.4s}, [x8], #16 //load rk5
+
+ aese v1.16b, v19.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 1
+ ld1 {v24.4s}, [x8], #16 //load rk6
+
+ aese v3.16b, v18.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 0
+
+ aese v2.16b, v19.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 1
+
+ aese v1.16b, v20.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 2
+
+ aese v3.16b, v19.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 1
+ ld1 { v11.16b}, [x3]
+ ext v11.16b, v11.16b, v11.16b, #8
+ rev64 v11.16b, v11.16b
+
+ aese v0.16b, v21.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 3
+ ld1 {v25.4s}, [x8], #16 //load rk7
+
+ aese v1.16b, v21.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 3
+
+ aese v3.16b, v20.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 2
+
+ aese v2.16b, v20.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 2
+ ld1 {v26.4s}, [x8], #16 //load rk8
+
+ aese v1.16b, v22.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 4
+
+ aese v3.16b, v21.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 3
+
+ aese v2.16b, v21.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 3
+ ldr q14, [x3, #80] //load h3l | h3h
+#ifndef __AARCH64EB__
+ ext v14.16b, v14.16b, v14.16b, #8
+#endif
+ aese v0.16b, v22.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 4
+ ld1 {v27.4s}, [x8], #16 //load rk9
+
+ aese v1.16b, v23.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 5
+
+ aese v2.16b, v22.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 4
+
+ aese v3.16b, v22.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 4
+
+ aese v0.16b, v23.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 5
+
+ aese v2.16b, v23.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 5
+ ldr q12, [x3, #32] //load h1l | h1h
+#ifndef __AARCH64EB__
+ ext v12.16b, v12.16b, v12.16b, #8
+#endif
+ aese v3.16b, v23.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 5
+
+ aese v0.16b, v24.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 6
+
+ aese v1.16b, v24.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 6
+
+ aese v3.16b, v24.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 6
+
+ aese v2.16b, v24.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 6
+ trn1 v8.2d, v12.2d, v13.2d //h2h | h1h
+
+ ldr q15, [x3, #112] //load h4l | h4h
+#ifndef __AARCH64EB__
+ ext v15.16b, v15.16b, v15.16b, #8
+#endif
+ trn2 v16.2d, v12.2d, v13.2d //h2l | h1l
+ add x5, x5, x0
+
+ aese v1.16b, v25.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 7
+
+ aese v2.16b, v25.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 7
+
+ aese v0.16b, v25.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 7
+ eor v16.16b, v16.16b, v8.16b //h2k | h1k
+
+ aese v3.16b, v25.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 7
+
+ aese v1.16b, v26.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 8
+ trn2 v17.2d, v14.2d, v15.2d //h4l | h3l
+
+ aese v2.16b, v26.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 8
+
+ aese v3.16b, v26.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 8
+
+ aese v0.16b, v26.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 8
+ trn1 v9.2d, v14.2d, v15.2d //h4h | h3h
+
+ aese v2.16b, v27.16b //AES block 2 - round 9
+
+ aese v3.16b, v27.16b //AES block 3 - round 9
+
+ aese v0.16b, v27.16b //AES block 0 - round 9
+ cmp x0, x5 //check if we have <= 4 blocks
+
+ aese v1.16b, v27.16b //AES block 1 - round 9
+ eor v17.16b, v17.16b, v9.16b //h4k | h3k
+ b.ge .L128_dec_tail //handle tail
+
+ ld1 {v4.16b, v5.16b}, [x0], #32 //AES block 0 - load ciphertext; AES block 1 - load ciphertext
+
+ eor v1.16b, v5.16b, v1.16b //AES block 1 - result
+ ld1 {v6.16b}, [x0], #16 //AES block 2 - load ciphertext
+
+ eor v0.16b, v4.16b, v0.16b //AES block 0 - result
+ rev64 v4.16b, v4.16b //GHASH block 0
+ rev w9, w12 //CTR block 4
+
+ orr x9, x11, x9, lsl #32 //CTR block 4
+ add w12, w12, #1 //CTR block 4
+ ld1 {v7.16b}, [x0], #16 //AES block 3 - load ciphertext
+
+ rev64 v5.16b, v5.16b //GHASH block 1
+ mov x19, v1.d[0] //AES block 1 - mov low
+
+ mov x20, v1.d[1] //AES block 1 - mov high
+
+ mov x6, v0.d[0] //AES block 0 - mov low
+ cmp x0, x5 //check if we have <= 8 blocks
+
+ mov x7, v0.d[1] //AES block 0 - mov high
+
+ fmov d0, x10 //CTR block 4
+
+ fmov v0.d[1], x9 //CTR block 4
+ rev w9, w12 //CTR block 5
+ eor x19, x19, x13 //AES block 1 - round 10 low
+#ifdef __AARCH64EB__
+ rev x19, x19
+#endif
+ fmov d1, x10 //CTR block 5
+ add w12, w12, #1 //CTR block 5
+ orr x9, x11, x9, lsl #32 //CTR block 5
+
+ fmov v1.d[1], x9 //CTR block 5
+ rev w9, w12 //CTR block 6
+ add w12, w12, #1 //CTR block 6
+
+ orr x9, x11, x9, lsl #32 //CTR block 6
+
+ eor x20, x20, x14 //AES block 1 - round 10 high
+#ifdef __AARCH64EB__
+ rev x20, x20
+#endif
+ eor x6, x6, x13 //AES block 0 - round 10 low
+#ifdef __AARCH64EB__
+ rev x6, x6
+#endif
+ eor v2.16b, v6.16b, v2.16b //AES block 2 - result
+
+ eor x7, x7, x14 //AES block 0 - round 10 high
+#ifdef __AARCH64EB__
+ rev x7, x7
+#endif
+ stp x6, x7, [x2], #16 //AES block 0 - store result
+
+ stp x19, x20, [x2], #16 //AES block 1 - store result
+ b.ge .L128_dec_prepretail //do prepretail
+
+.L128_dec_main_loop: //main loop start
+ eor v3.16b, v7.16b, v3.16b //AES block 4k+3 - result
+ ext v11.16b, v11.16b, v11.16b, #8 //PRE 0
+ mov x21, v2.d[0] //AES block 4k+2 - mov low
+
+ pmull2 v28.1q, v5.2d, v14.2d //GHASH block 4k+1 - high
+ mov x22, v2.d[1] //AES block 4k+2 - mov high
+
+ aese v1.16b, v18.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 0
+ fmov d2, x10 //CTR block 4k+6
+
+ rev64 v6.16b, v6.16b //GHASH block 4k+2
+ fmov v2.d[1], x9 //CTR block 4k+6
+ rev w9, w12 //CTR block 4k+7
+
+ mov x23, v3.d[0] //AES block 4k+3 - mov low
+ eor v4.16b, v4.16b, v11.16b //PRE 1
+ mov d30, v5.d[1] //GHASH block 4k+1 - mid
+
+ aese v1.16b, v19.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 1
+ rev64 v7.16b, v7.16b //GHASH block 4k+3
+
+ pmull v29.1q, v5.1d, v14.1d //GHASH block 4k+1 - low
+ mov x24, v3.d[1] //AES block 4k+3 - mov high
+ orr x9, x11, x9, lsl #32 //CTR block 4k+7
+
+ pmull v11.1q, v4.1d, v15.1d //GHASH block 4k - low
+ fmov d3, x10 //CTR block 4k+7
+ eor v30.8b, v30.8b, v5.8b //GHASH block 4k+1 - mid
+
+ aese v1.16b, v20.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 2
+ fmov v3.d[1], x9 //CTR block 4k+7
+
+ aese v2.16b, v18.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 0
+ mov d10, v17.d[1] //GHASH block 4k - mid
+
+ pmull2 v9.1q, v4.2d, v15.2d //GHASH block 4k - high
+ eor v11.16b, v11.16b, v29.16b //GHASH block 4k+1 - low
+
+ pmull v29.1q, v7.1d, v12.1d //GHASH block 4k+3 - low
+
+ aese v1.16b, v21.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 3
+ mov d8, v4.d[1] //GHASH block 4k - mid
+
+ aese v3.16b, v18.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 0
+ eor v9.16b, v9.16b, v28.16b //GHASH block 4k+1 - high
+
+ aese v0.16b, v18.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 0
+
+ pmull v28.1q, v6.1d, v13.1d //GHASH block 4k+2 - low
+ eor v8.8b, v8.8b, v4.8b //GHASH block 4k - mid
+
+ aese v3.16b, v19.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 1
+ eor x23, x23, x13 //AES block 4k+3 - round 10 low
+#ifdef __AARCH64EB__
+ rev x23, x23
+#endif
+ pmull v30.1q, v30.1d, v17.1d //GHASH block 4k+1 - mid
+ eor x22, x22, x14 //AES block 4k+2 - round 10 high
+#ifdef __AARCH64EB__
+ rev x22, x22
+#endif
+ mov d31, v6.d[1] //GHASH block 4k+2 - mid
+
+ aese v0.16b, v19.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 1
+ eor v11.16b, v11.16b, v28.16b //GHASH block 4k+2 - low
+
+ pmull v10.1q, v8.1d, v10.1d //GHASH block 4k - mid
+
+ aese v3.16b, v20.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 2
+ eor v31.8b, v31.8b, v6.8b //GHASH block 4k+2 - mid
+
+ aese v0.16b, v20.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 2
+
+ aese v1.16b, v22.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 4
+ eor v10.16b, v10.16b, v30.16b //GHASH block 4k+1 - mid
+
+ pmull2 v8.1q, v6.2d, v13.2d //GHASH block 4k+2 - high
+
+ aese v0.16b, v21.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 3
+ ins v31.d[1], v31.d[0] //GHASH block 4k+2 - mid
+
+ pmull2 v4.1q, v7.2d, v12.2d //GHASH block 4k+3 - high
+
+ aese v2.16b, v19.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 1
+ mov d30, v7.d[1] //GHASH block 4k+3 - mid
+
+ aese v0.16b, v22.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 4
+ eor v9.16b, v9.16b, v8.16b //GHASH block 4k+2 - high
+
+ pmull2 v31.1q, v31.2d, v16.2d //GHASH block 4k+2 - mid
+ eor x24, x24, x14 //AES block 4k+3 - round 10 high
+#ifdef __AARCH64EB__
+ rev x24, x24
+#endif
+ aese v2.16b, v20.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 2
+ eor v30.8b, v30.8b, v7.8b //GHASH block 4k+3 - mid
+
+ aese v1.16b, v23.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 5
+ eor x21, x21, x13 //AES block 4k+2 - round 10 low
+#ifdef __AARCH64EB__
+ rev x21, x21
+#endif
+ aese v0.16b, v23.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 5
+ movi v8.8b, #0xc2
+
+ aese v2.16b, v21.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 3
+ eor v11.16b, v11.16b, v29.16b //GHASH block 4k+3 - low
+
+ aese v1.16b, v24.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 6
+
+ aese v0.16b, v24.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 6
+ eor v10.16b, v10.16b, v31.16b //GHASH block 4k+2 - mid
+
+ aese v2.16b, v22.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 4
+ stp x21, x22, [x2], #16 //AES block 4k+2 - store result
+
+ pmull v30.1q, v30.1d, v16.1d //GHASH block 4k+3 - mid
+ eor v9.16b, v9.16b, v4.16b //GHASH block 4k+3 - high
+ ld1 {v4.16b}, [x0], #16 //AES block 4k+3 - load ciphertext
+
+ aese v1.16b, v25.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 7
+ add w12, w12, #1 //CTR block 4k+7
+
+ aese v0.16b, v25.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 7
+ shl d8, d8, #56 //mod_constant
+
+ aese v2.16b, v23.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 5
+ eor v10.16b, v10.16b, v30.16b //GHASH block 4k+3 - mid
+
+ aese v1.16b, v26.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 8
+ stp x23, x24, [x2], #16 //AES block 4k+3 - store result
+
+ aese v0.16b, v26.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 8
+ eor v30.16b, v11.16b, v9.16b //MODULO - karatsuba tidy up
+
+ aese v3.16b, v21.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 3
+ rev w9, w12 //CTR block 4k+8
+
+ pmull v31.1q, v9.1d, v8.1d //MODULO - top 64b align with mid
+ ld1 {v5.16b}, [x0], #16 //AES block 4k+4 - load ciphertext
+ ext v9.16b, v9.16b, v9.16b, #8 //MODULO - other top alignment
+
+ aese v0.16b, v27.16b //AES block 4k+4 - round 9
+ orr x9, x11, x9, lsl #32 //CTR block 4k+8
+
+ aese v3.16b, v22.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 4
+ eor v10.16b, v10.16b, v30.16b //MODULO - karatsuba tidy up
+
+ aese v1.16b, v27.16b //AES block 4k+5 - round 9
+
+ aese v2.16b, v24.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 6
+ eor v0.16b, v4.16b, v0.16b //AES block 4k+4 - result
+
+ aese v3.16b, v23.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 5
+ ld1 {v6.16b}, [x0], #16 //AES block 4k+5 - load ciphertext
+
+ add w12, w12, #1 //CTR block 4k+8
+ eor v10.16b, v10.16b, v31.16b //MODULO - fold into mid
+ eor v1.16b, v5.16b, v1.16b //AES block 4k+5 - result
+
+ aese v2.16b, v25.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 7
+ ld1 {v7.16b}, [x0], #16 //AES block 4k+6 - load ciphertext
+
+ aese v3.16b, v24.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 6
+
+ rev64 v5.16b, v5.16b //GHASH block 4k+5
+ eor v10.16b, v10.16b, v9.16b //MODULO - fold into mid
+ mov x7, v0.d[1] //AES block 4k+4 - mov high
+
+ aese v2.16b, v26.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 8
+ mov x6, v0.d[0] //AES block 4k+4 - mov low
+
+ aese v3.16b, v25.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 7
+ fmov d0, x10 //CTR block 4k+8
+
+ pmull v8.1q, v10.1d, v8.1d //MODULO - mid 64b align with low
+ fmov v0.d[1], x9 //CTR block 4k+8
+ rev w9, w12 //CTR block 4k+9
+
+ aese v2.16b, v27.16b //AES block 4k+6 - round 9
+ orr x9, x11, x9, lsl #32 //CTR block 4k+9
+ ext v10.16b, v10.16b, v10.16b, #8 //MODULO - other mid alignment
+
+ aese v3.16b, v26.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 8
+ eor x7, x7, x14 //AES block 4k+4 - round 10 high
+#ifdef __AARCH64EB__
+ rev x7, x7
+#endif
+ eor v11.16b, v11.16b, v8.16b //MODULO - fold into low
+ mov x20, v1.d[1] //AES block 4k+5 - mov high
+ eor x6, x6, x13 //AES block 4k+4 - round 10 low
+#ifdef __AARCH64EB__
+ rev x6, x6
+#endif
+ eor v2.16b, v6.16b, v2.16b //AES block 4k+6 - result
+ mov x19, v1.d[0] //AES block 4k+5 - mov low
+ add w12, w12, #1 //CTR block 4k+9
+
+ aese v3.16b, v27.16b //AES block 4k+7 - round 9
+ fmov d1, x10 //CTR block 4k+9
+ cmp x0, x5 //.LOOP CONTROL
+
+ rev64 v4.16b, v4.16b //GHASH block 4k+4
+ eor v11.16b, v11.16b, v10.16b //MODULO - fold into low
+ fmov v1.d[1], x9 //CTR block 4k+9
+
+ rev w9, w12 //CTR block 4k+10
+ add w12, w12, #1 //CTR block 4k+10
+
+ eor x20, x20, x14 //AES block 4k+5 - round 10 high
+#ifdef __AARCH64EB__
+ rev x20, x20
+#endif
+ stp x6, x7, [x2], #16 //AES block 4k+4 - store result
+
+ eor x19, x19, x13 //AES block 4k+5 - round 10 low
+#ifdef __AARCH64EB__
+ rev x19, x19
+#endif
+ stp x19, x20, [x2], #16 //AES block 4k+5 - store result
+
+ orr x9, x11, x9, lsl #32 //CTR block 4k+10
+ b.lt .L128_dec_main_loop
+
+.L128_dec_prepretail: //PREPRETAIL
+ ext v11.16b, v11.16b, v11.16b, #8 //PRE 0
+ mov x21, v2.d[0] //AES block 4k+2 - mov low
+ mov d30, v5.d[1] //GHASH block 4k+1 - mid
+
+ aese v0.16b, v18.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 0
+ eor v3.16b, v7.16b, v3.16b //AES block 4k+3 - result
+
+ aese v1.16b, v18.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 0
+ mov x22, v2.d[1] //AES block 4k+2 - mov high
+
+ eor v4.16b, v4.16b, v11.16b //PRE 1
+ fmov d2, x10 //CTR block 4k+6
+ rev64 v6.16b, v6.16b //GHASH block 4k+2
+
+ aese v0.16b, v19.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 1
+ fmov v2.d[1], x9 //CTR block 4k+6
+
+ rev w9, w12 //CTR block 4k+7
+ mov x23, v3.d[0] //AES block 4k+3 - mov low
+ eor v30.8b, v30.8b, v5.8b //GHASH block 4k+1 - mid
+
+ pmull v11.1q, v4.1d, v15.1d //GHASH block 4k - low
+ mov d10, v17.d[1] //GHASH block 4k - mid
+ mov x24, v3.d[1] //AES block 4k+3 - mov high
+
+ aese v1.16b, v19.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 1
+ mov d31, v6.d[1] //GHASH block 4k+2 - mid
+
+ aese v0.16b, v20.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 2
+ orr x9, x11, x9, lsl #32 //CTR block 4k+7
+
+ pmull v29.1q, v5.1d, v14.1d //GHASH block 4k+1 - low
+ mov d8, v4.d[1] //GHASH block 4k - mid
+ fmov d3, x10 //CTR block 4k+7
+
+ aese v2.16b, v18.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 0
+ fmov v3.d[1], x9 //CTR block 4k+7
+
+ pmull v30.1q, v30.1d, v17.1d //GHASH block 4k+1 - mid
+ eor v31.8b, v31.8b, v6.8b //GHASH block 4k+2 - mid
+
+ rev64 v7.16b, v7.16b //GHASH block 4k+3
+
+ aese v2.16b, v19.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 1
+ eor v8.8b, v8.8b, v4.8b //GHASH block 4k - mid
+
+ pmull2 v9.1q, v4.2d, v15.2d //GHASH block 4k - high
+
+ aese v3.16b, v18.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 0
+ ins v31.d[1], v31.d[0] //GHASH block 4k+2 - mid
+
+ pmull2 v28.1q, v5.2d, v14.2d //GHASH block 4k+1 - high
+
+ pmull v10.1q, v8.1d, v10.1d //GHASH block 4k - mid
+ eor v11.16b, v11.16b, v29.16b //GHASH block 4k+1 - low
+
+ pmull v29.1q, v7.1d, v12.1d //GHASH block 4k+3 - low
+
+ pmull2 v31.1q, v31.2d, v16.2d //GHASH block 4k+2 - mid
+ eor v9.16b, v9.16b, v28.16b //GHASH block 4k+1 - high
+
+ eor v10.16b, v10.16b, v30.16b //GHASH block 4k+1 - mid
+
+ pmull2 v4.1q, v7.2d, v12.2d //GHASH block 4k+3 - high
+
+ pmull2 v8.1q, v6.2d, v13.2d //GHASH block 4k+2 - high
+ mov d30, v7.d[1] //GHASH block 4k+3 - mid
+
+ aese v1.16b, v20.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 2
+ eor v10.16b, v10.16b, v31.16b //GHASH block 4k+2 - mid
+
+ pmull v28.1q, v6.1d, v13.1d //GHASH block 4k+2 - low
+
+ eor v9.16b, v9.16b, v8.16b //GHASH block 4k+2 - high
+ movi v8.8b, #0xc2
+
+ aese v3.16b, v19.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 1
+ eor v30.8b, v30.8b, v7.8b //GHASH block 4k+3 - mid
+
+ eor v11.16b, v11.16b, v28.16b //GHASH block 4k+2 - low
+
+ aese v2.16b, v20.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 2
+ eor v9.16b, v9.16b, v4.16b //GHASH block 4k+3 - high
+
+ aese v3.16b, v20.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 2
+ eor x23, x23, x13 //AES block 4k+3 - round 10 low
+#ifdef __AARCH64EB__
+ rev x23, x23
+#endif
+ pmull v30.1q, v30.1d, v16.1d //GHASH block 4k+3 - mid
+ eor x21, x21, x13 //AES block 4k+2 - round 10 low
+#ifdef __AARCH64EB__
+ rev x21, x21
+#endif
+ eor v11.16b, v11.16b, v29.16b //GHASH block 4k+3 - low
+
+ aese v2.16b, v21.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 3
+
+ aese v1.16b, v21.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 3
+ shl d8, d8, #56 //mod_constant
+
+ aese v0.16b, v21.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 3
+
+ aese v2.16b, v22.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 4
+ eor v10.16b, v10.16b, v30.16b //GHASH block 4k+3 - mid
+
+ aese v1.16b, v22.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 4
+
+ aese v3.16b, v21.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 3
+ eor v30.16b, v11.16b, v9.16b //MODULO - karatsuba tidy up
+
+ aese v2.16b, v23.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 5
+
+ aese v1.16b, v23.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 5
+
+ aese v3.16b, v22.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 4
+
+ aese v0.16b, v22.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 4
+ eor v10.16b, v10.16b, v30.16b //MODULO - karatsuba tidy up
+
+ pmull v31.1q, v9.1d, v8.1d //MODULO - top 64b align with mid
+
+ aese v1.16b, v24.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 6
+ ext v9.16b, v9.16b, v9.16b, #8 //MODULO - other top alignment
+
+ aese v3.16b, v23.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 5
+
+ aese v0.16b, v23.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 5
+ eor v10.16b, v10.16b, v31.16b //MODULO - fold into mid
+
+ aese v1.16b, v25.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 7
+
+ aese v2.16b, v24.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 6
+
+ aese v0.16b, v24.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 6
+
+ aese v1.16b, v26.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 8
+ eor v10.16b, v10.16b, v9.16b //MODULO - fold into mid
+
+ aese v3.16b, v24.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 6
+
+ aese v0.16b, v25.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 7
+
+ aese v1.16b, v27.16b //AES block 4k+5 - round 9
+
+ pmull v8.1q, v10.1d, v8.1d //MODULO - mid 64b align with low
+ eor x24, x24, x14 //AES block 4k+3 - round 10 high
+#ifdef __AARCH64EB__
+ rev x24, x24
+#endif
+ aese v2.16b, v25.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 7
+ ext v10.16b, v10.16b, v10.16b, #8 //MODULO - other mid alignment
+
+ aese v3.16b, v25.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 7
+
+ aese v0.16b, v26.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 8
+ eor v11.16b, v11.16b, v8.16b //MODULO - fold into low
+
+ aese v2.16b, v26.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 8
+
+ aese v3.16b, v26.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 8
+ eor x22, x22, x14 //AES block 4k+2 - round 10 high
+#ifdef __AARCH64EB__
+ rev x22, x22
+#endif
+ aese v0.16b, v27.16b //AES block 4k+4 - round 9
+ stp x21, x22, [x2], #16 //AES block 4k+2 - store result
+
+ aese v2.16b, v27.16b //AES block 4k+6 - round 9
+ add w12, w12, #1 //CTR block 4k+7
+ stp x23, x24, [x2], #16 //AES block 4k+3 - store result
+
+ aese v3.16b, v27.16b //AES block 4k+7 - round 9
+ eor v11.16b, v11.16b, v10.16b //MODULO - fold into low
+.L128_dec_tail: //TAIL
+
+ sub x5, x4, x0 //main_end_input_ptr is number of bytes left to process
+ ld1 { v5.16b}, [x0], #16 //AES block 4k+4 - load ciphertext
+
+ eor v0.16b, v5.16b, v0.16b //AES block 4k+4 - result
+
+ mov x7, v0.d[1] //AES block 4k+4 - mov high
+
+ mov x6, v0.d[0] //AES block 4k+4 - mov low
+
+ cmp x5, #48
+
+ eor x7, x7, x14 //AES block 4k+4 - round 10 high
+#ifdef __AARCH64EB__
+ rev x7, x7
+#endif
+ ext v8.16b, v11.16b, v11.16b, #8 //prepare final partial tag
+ eor x6, x6, x13 //AES block 4k+4 - round 10 low
+#ifdef __AARCH64EB__
+ rev x6, x6
+#endif
+ b.gt .L128_dec_blocks_more_than_3
+
+ mov v3.16b, v2.16b
+ sub w12, w12, #1
+ movi v11.8b, #0
+
+ movi v9.8b, #0
+ mov v2.16b, v1.16b
+
+ movi v10.8b, #0
+ cmp x5, #32
+ b.gt .L128_dec_blocks_more_than_2
+
+ cmp x5, #16
+
+ mov v3.16b, v1.16b
+ sub w12, w12, #1
+ b.gt .L128_dec_blocks_more_than_1
+
+ sub w12, w12, #1
+ b .L128_dec_blocks_less_than_1
+.L128_dec_blocks_more_than_3: //blocks left > 3
+ rev64 v4.16b, v5.16b //GHASH final-3 block
+ ld1 { v5.16b}, [x0], #16 //AES final-2 block - load ciphertext
+
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+
+ mov d10, v17.d[1] //GHASH final-3 block - mid
+ stp x6, x7, [x2], #16 //AES final-3 block - store result
+ eor v0.16b, v5.16b, v1.16b //AES final-2 block - result
+
+ mov d22, v4.d[1] //GHASH final-3 block - mid
+ mov x7, v0.d[1] //AES final-2 block - mov high
+
+ pmull v11.1q, v4.1d, v15.1d //GHASH final-3 block - low
+ mov x6, v0.d[0] //AES final-2 block - mov low
+
+ pmull2 v9.1q, v4.2d, v15.2d //GHASH final-3 block - high
+
+ eor v22.8b, v22.8b, v4.8b //GHASH final-3 block - mid
+
+ movi v8.8b, #0 //suppress further partial tag feed in
+ eor x7, x7, x14 //AES final-2 block - round 10 high
+#ifdef __AARCH64EB__
+ rev x7, x7
+#endif
+ pmull v10.1q, v22.1d, v10.1d //GHASH final-3 block - mid
+ eor x6, x6, x13 //AES final-2 block - round 10 low
+#ifdef __AARCH64EB__
+ rev x6, x6
+#endif
+.L128_dec_blocks_more_than_2: //blocks left > 2
+
+ rev64 v4.16b, v5.16b //GHASH final-2 block
+ ld1 { v5.16b}, [x0], #16 //AES final-1 block - load ciphertext
+
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+
+ eor v0.16b, v5.16b, v2.16b //AES final-1 block - result
+ stp x6, x7, [x2], #16 //AES final-2 block - store result
+
+ mov d22, v4.d[1] //GHASH final-2 block - mid
+
+ pmull v21.1q, v4.1d, v14.1d //GHASH final-2 block - low
+
+ pmull2 v20.1q, v4.2d, v14.2d //GHASH final-2 block - high
+ mov x6, v0.d[0] //AES final-1 block - mov low
+
+ mov x7, v0.d[1] //AES final-1 block - mov high
+ eor v22.8b, v22.8b, v4.8b //GHASH final-2 block - mid
+
+ movi v8.8b, #0 //suppress further partial tag feed in
+
+ pmull v22.1q, v22.1d, v17.1d //GHASH final-2 block - mid
+
+ eor x6, x6, x13 //AES final-1 block - round 10 low
+#ifdef __AARCH64EB__
+ rev x6, x6
+#endif
+ eor v11.16b, v11.16b, v21.16b //GHASH final-2 block - low
+
+ eor v9.16b, v9.16b, v20.16b //GHASH final-2 block - high
+
+ eor v10.16b, v10.16b, v22.16b //GHASH final-2 block - mid
+ eor x7, x7, x14 //AES final-1 block - round 10 high
+#ifdef __AARCH64EB__
+ rev x7, x7
+#endif
+.L128_dec_blocks_more_than_1: //blocks left > 1
+
+ rev64 v4.16b, v5.16b //GHASH final-1 block
+
+ ld1 { v5.16b}, [x0], #16 //AES final block - load ciphertext
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+
+ mov d22, v4.d[1] //GHASH final-1 block - mid
+
+ eor v0.16b, v5.16b, v3.16b //AES final block - result
+
+ eor v22.8b, v22.8b, v4.8b //GHASH final-1 block - mid
+
+ stp x6, x7, [x2], #16 //AES final-1 block - store result
+ mov x6, v0.d[0] //AES final block - mov low
+
+ mov x7, v0.d[1] //AES final block - mov high
+ ins v22.d[1], v22.d[0] //GHASH final-1 block - mid
+
+ pmull v21.1q, v4.1d, v13.1d //GHASH final-1 block - low
+
+ pmull2 v20.1q, v4.2d, v13.2d //GHASH final-1 block - high
+
+ pmull2 v22.1q, v22.2d, v16.2d //GHASH final-1 block - mid
+ movi v8.8b, #0 //suppress further partial tag feed in
+
+ eor v11.16b, v11.16b, v21.16b //GHASH final-1 block - low
+
+ eor v9.16b, v9.16b, v20.16b //GHASH final-1 block - high
+ eor x7, x7, x14 //AES final block - round 10 high
+#ifdef __AARCH64EB__
+ rev x7, x7
+#endif
+ eor x6, x6, x13 //AES final block - round 10 low
+#ifdef __AARCH64EB__
+ rev x6, x6
+#endif
+ eor v10.16b, v10.16b, v22.16b //GHASH final-1 block - mid
+.L128_dec_blocks_less_than_1: //blocks left <= 1
+
+ mvn x14, xzr //rk10_h = 0xffffffffffffffff
+ and x1, x1, #127 //bit_length %= 128
+
+ mvn x13, xzr //rk10_l = 0xffffffffffffffff
+ sub x1, x1, #128 //bit_length -= 128
+
+ neg x1, x1 //bit_length = 128 - #bits in input (in range [1,128])
+
+ and x1, x1, #127 //bit_length %= 128
+
+ lsr x14, x14, x1 //rk10_h is mask for top 64b of last block
+ cmp x1, #64
+
+ csel x10, x14, xzr, lt
+ csel x9, x13, x14, lt
+
+ fmov d0, x9 //ctr0b is mask for last block
+
+ mov v0.d[1], x10
+
+ and v5.16b, v5.16b, v0.16b //possibly partial last block has zeroes in highest bits
+
+ rev64 v4.16b, v5.16b //GHASH final block
+
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+
+ ldp x4, x5, [x2] //load existing bytes we need to not overwrite
+
+ and x7, x7, x10
+
+ pmull2 v20.1q, v4.2d, v12.2d //GHASH final block - high
+ mov d8, v4.d[1] //GHASH final block - mid
+
+ eor v8.8b, v8.8b, v4.8b //GHASH final block - mid
+ eor v9.16b, v9.16b, v20.16b //GHASH final block - high
+
+ pmull v8.1q, v8.1d, v16.1d //GHASH final block - mid
+
+ pmull v21.1q, v4.1d, v12.1d //GHASH final block - low
+ bic x4, x4, x9 //mask out low existing bytes
+ and x6, x6, x9
+
+#ifndef __AARCH64EB__
+ rev w9, w12
+#else
+ mov w9, w12
+#endif
+
+ eor v10.16b, v10.16b, v8.16b //GHASH final block - mid
+ movi v8.8b, #0xc2
+
+ eor v11.16b, v11.16b, v21.16b //GHASH final block - low
+
+ bic x5, x5, x10 //mask out high existing bytes
+ shl d8, d8, #56 //mod_constant
+
+ eor v30.16b, v11.16b, v9.16b //MODULO - karatsuba tidy up
+
+ pmull v31.1q, v9.1d, v8.1d //MODULO - top 64b align with mid
+
+ eor v10.16b, v10.16b, v30.16b //MODULO - karatsuba tidy up
+
+ orr x6, x6, x4
+ str w9, [x16, #12] //store the updated counter
+
+ orr x7, x7, x5
+ stp x6, x7, [x2]
+ ext v9.16b, v9.16b, v9.16b, #8 //MODULO - other top alignment
+
+ eor v10.16b, v10.16b, v31.16b //MODULO - fold into mid
+
+ eor v10.16b, v10.16b, v9.16b //MODULO - fold into mid
+
+ pmull v8.1q, v10.1d, v8.1d //MODULO - mid 64b align with low
+ ext v10.16b, v10.16b, v10.16b, #8 //MODULO - other mid alignment
+
+ eor v11.16b, v11.16b, v8.16b //MODULO - fold into low
+
+ eor v11.16b, v11.16b, v10.16b //MODULO - fold into low
+ ext v11.16b, v11.16b, v11.16b, #8
+ rev64 v11.16b, v11.16b
+ mov x0, x15
+ st1 { v11.16b }, [x3]
+
+ ldp x21, x22, [sp, #16]
+ ldp x23, x24, [sp, #32]
+ ldp d8, d9, [sp, #48]
+ ldp d10, d11, [sp, #64]
+ ldp d12, d13, [sp, #80]
+ ldp d14, d15, [sp, #96]
+ ldp x19, x20, [sp], #112
+ ret
+
+.L128_dec_ret:
+ mov w0, #0x0
+ ret
+.size aes_gcm_dec_128_kernel,.-aes_gcm_dec_128_kernel
+.globl aes_gcm_enc_192_kernel
+.type aes_gcm_enc_192_kernel,%function
+.align 4
+aes_gcm_enc_192_kernel:
+ cbz x1, .L192_enc_ret
+ stp x19, x20, [sp, #-112]!
+ mov x16, x4
+ mov x8, x5
+ stp x21, x22, [sp, #16]
+ stp x23, x24, [sp, #32]
+ stp d8, d9, [sp, #48]
+ stp d10, d11, [sp, #64]
+ stp d12, d13, [sp, #80]
+ stp d14, d15, [sp, #96]
+
+ ldp x10, x11, [x16] //ctr96_b64, ctr96_t32
+#ifdef __AARCH64EB__
+ rev x10, x10
+ rev x11, x11
+#endif
+ ldp x13, x14, [x8, #192] //load rk12
+#ifdef __AARCH64EB__
+ ror x13, x13, #32
+ ror x14, x14, #32
+#endif
+ ld1 {v18.4s}, [x8], #16 //load rk0
+
+ ld1 {v19.4s}, [x8], #16 //load rk1
+
+ ld1 {v20.4s}, [x8], #16 //load rk2
+
+ lsr x12, x11, #32
+ ld1 {v21.4s}, [x8], #16 //load rk3
+ orr w11, w11, w11
+
+ ld1 {v22.4s}, [x8], #16 //load rk4
+ rev w12, w12 //rev_ctr32
+
+ add w12, w12, #1 //increment rev_ctr32
+ fmov d3, x10 //CTR block 3
+
+ rev w9, w12 //CTR block 1
+ add w12, w12, #1 //CTR block 1
+ fmov d1, x10 //CTR block 1
+
+ orr x9, x11, x9, lsl #32 //CTR block 1
+ ld1 { v0.16b}, [x16] //special case vector load initial counter so we can start first AES block as quickly as possible
+
+ fmov v1.d[1], x9 //CTR block 1
+ rev w9, w12 //CTR block 2
+ add w12, w12, #1 //CTR block 2
+
+ fmov d2, x10 //CTR block 2
+ orr x9, x11, x9, lsl #32 //CTR block 2
+
+ fmov v2.d[1], x9 //CTR block 2
+ rev w9, w12 //CTR block 3
+
+ orr x9, x11, x9, lsl #32 //CTR block 3
+ ld1 {v23.4s}, [x8], #16 //load rk5
+
+ fmov v3.d[1], x9 //CTR block 3
+
+ ld1 {v24.4s}, [x8], #16 //load rk6
+
+ ld1 {v25.4s}, [x8], #16 //load rk7
+
+ aese v0.16b, v18.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 0
+ ld1 { v11.16b}, [x3]
+ ext v11.16b, v11.16b, v11.16b, #8
+ rev64 v11.16b, v11.16b
+
+ aese v3.16b, v18.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 0
+ ld1 {v26.4s}, [x8], #16 //load rk8
+
+ aese v1.16b, v18.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 0
+ ldr q15, [x3, #112] //load h4l | h4h
+#ifndef __AARCH64EB__
+ ext v15.16b, v15.16b, v15.16b, #8
+#endif
+ aese v2.16b, v18.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 0
+ ld1 {v27.4s}, [x8], #16 //load rk9
+
+ aese v0.16b, v19.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 1
+ ld1 {v28.4s}, [x8], #16 //load rk10
+
+ aese v1.16b, v19.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 1
+ ldr q12, [x3, #32] //load h1l | h1h
+#ifndef __AARCH64EB__
+ ext v12.16b, v12.16b, v12.16b, #8
+#endif
+ aese v2.16b, v19.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 1
+ ld1 {v29.4s}, [x8], #16 //load rk11
+
+ aese v3.16b, v19.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 1
+ ldr q14, [x3, #80] //load h3l | h3h
+#ifndef __AARCH64EB__
+ ext v14.16b, v14.16b, v14.16b, #8
+#endif
+ aese v0.16b, v20.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 2
+
+ aese v2.16b, v20.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 2
+
+ aese v3.16b, v20.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 2
+
+ aese v0.16b, v21.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 3
+ trn1 v9.2d, v14.2d, v15.2d //h4h | h3h
+
+ aese v2.16b, v21.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 3
+
+ aese v1.16b, v20.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 2
+ trn2 v17.2d, v14.2d, v15.2d //h4l | h3l
+
+ aese v0.16b, v22.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 4
+
+ aese v3.16b, v21.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 3
+
+ aese v1.16b, v21.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 3
+
+ aese v0.16b, v23.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 5
+
+ aese v2.16b, v22.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 4
+
+ aese v1.16b, v22.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 4
+
+ aese v0.16b, v24.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 6
+
+ aese v3.16b, v22.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 4
+
+ aese v2.16b, v23.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 5
+
+ aese v1.16b, v23.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 5
+
+ aese v3.16b, v23.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 5
+
+ aese v2.16b, v24.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 6
+ ldr q13, [x3, #64] //load h2l | h2h
+#ifndef __AARCH64EB__
+ ext v13.16b, v13.16b, v13.16b, #8
+#endif
+ aese v1.16b, v24.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 6
+
+ aese v3.16b, v24.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 6
+
+ aese v0.16b, v25.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 7
+
+ aese v1.16b, v25.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 7
+ trn2 v16.2d, v12.2d, v13.2d //h2l | h1l
+
+ aese v3.16b, v25.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 7
+
+ aese v0.16b, v26.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 8
+
+ aese v2.16b, v25.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 7
+ trn1 v8.2d, v12.2d, v13.2d //h2h | h1h
+
+ aese v1.16b, v26.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 8
+
+ aese v3.16b, v26.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 8
+
+ aese v2.16b, v26.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 8
+
+ aese v0.16b, v27.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 9
+
+ aese v3.16b, v27.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 9
+
+ aese v2.16b, v27.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 9
+
+ aese v1.16b, v27.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 9
+
+ aese v0.16b, v28.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 10
+
+ aese v2.16b, v28.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 10
+
+ aese v1.16b, v28.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 10
+ lsr x5, x1, #3 //byte_len
+ mov x15, x5
+
+ aese v3.16b, v28.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 10
+ sub x5, x5, #1 //byte_len - 1
+
+ eor v16.16b, v16.16b, v8.16b //h2k | h1k
+ and x5, x5, #0xffffffffffffffc0 //number of bytes to be processed in main loop (at least 1 byte must be handled by tail)
+
+ eor v17.16b, v17.16b, v9.16b //h4k | h3k
+
+ aese v2.16b, v29.16b //AES block 2 - round 11
+ add x4, x0, x1, lsr #3 //end_input_ptr
+ add x5, x5, x0
+
+ aese v1.16b, v29.16b //AES block 1 - round 11
+ cmp x0, x5 //check if we have <= 4 blocks
+
+ aese v0.16b, v29.16b //AES block 0 - round 11
+ add w12, w12, #1 //CTR block 3
+
+ aese v3.16b, v29.16b //AES block 3 - round 11
+ b.ge .L192_enc_tail //handle tail
+
+ rev w9, w12 //CTR block 4
+ ldp x6, x7, [x0, #0] //AES block 0 - load plaintext
+#ifdef __AARCH64EB__
+ rev x6, x6
+ rev x7, x7
+#endif
+ orr x9, x11, x9, lsl #32 //CTR block 4
+ ldp x21, x22, [x0, #32] //AES block 2 - load plaintext
+#ifdef __AARCH64EB__
+ rev x21, x21
+ rev x22, x22
+#endif
+ ldp x23, x24, [x0, #48] //AES block 3 - load plaintext
+#ifdef __AARCH64EB__
+ rev x23, x23
+ rev x24, x24
+#endif
+ ldp x19, x20, [x0, #16] //AES block 1 - load plaintext
+#ifdef __AARCH64EB__
+ rev x19, x19
+ rev x20, x20
+#endif
+ add x0, x0, #64 //AES input_ptr update
+ cmp x0, x5 //check if we have <= 8 blocks
+
+ eor x6, x6, x13 //AES block 0 - round 12 low
+
+ eor x7, x7, x14 //AES block 0 - round 12 high
+ eor x22, x22, x14 //AES block 2 - round 12 high
+ fmov d4, x6 //AES block 0 - mov low
+
+ eor x24, x24, x14 //AES block 3 - round 12 high
+ fmov v4.d[1], x7 //AES block 0 - mov high
+
+ eor x21, x21, x13 //AES block 2 - round 12 low
+ eor x19, x19, x13 //AES block 1 - round 12 low
+
+ fmov d5, x19 //AES block 1 - mov low
+ eor x20, x20, x14 //AES block 1 - round 12 high
+
+ fmov v5.d[1], x20 //AES block 1 - mov high
+
+ eor x23, x23, x13 //AES block 3 - round 12 low
+ fmov d6, x21 //AES block 2 - mov low
+
+ add w12, w12, #1 //CTR block 4
+ eor v4.16b, v4.16b, v0.16b //AES block 0 - result
+ fmov d0, x10 //CTR block 4
+
+ fmov v0.d[1], x9 //CTR block 4
+ rev w9, w12 //CTR block 5
+
+ orr x9, x11, x9, lsl #32 //CTR block 5
+ add w12, w12, #1 //CTR block 5
+
+ fmov d7, x23 //AES block 3 - mov low
+ st1 { v4.16b}, [x2], #16 //AES block 0 - store result
+
+ fmov v6.d[1], x22 //AES block 2 - mov high
+
+ eor v5.16b, v5.16b, v1.16b //AES block 1 - result
+ fmov d1, x10 //CTR block 5
+ st1 { v5.16b}, [x2], #16 //AES block 1 - store result
+
+ fmov v7.d[1], x24 //AES block 3 - mov high
+
+ fmov v1.d[1], x9 //CTR block 5
+ rev w9, w12 //CTR block 6
+
+ orr x9, x11, x9, lsl #32 //CTR block 6
+
+ add w12, w12, #1 //CTR block 6
+ eor v6.16b, v6.16b, v2.16b //AES block 2 - result
+ fmov d2, x10 //CTR block 6
+
+ fmov v2.d[1], x9 //CTR block 6
+ rev w9, w12 //CTR block 7
+
+ orr x9, x11, x9, lsl #32 //CTR block 7
+ st1 { v6.16b}, [x2], #16 //AES block 2 - store result
+
+ eor v7.16b, v7.16b, v3.16b //AES block 3 - result
+ st1 { v7.16b}, [x2], #16 //AES block 3 - store result
+ b.ge .L192_enc_prepretail //do prepretail
+
+.L192_enc_main_loop: //main loop start
+ aese v2.16b, v18.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 0
+ rev64 v5.16b, v5.16b //GHASH block 4k+1 (t0 and t1 free)
+
+ aese v1.16b, v18.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 0
+ ldp x19, x20, [x0, #16] //AES block 4k+5 - load plaintext
+#ifdef __AARCH64EB__
+ rev x19, x19
+ rev x20, x20
+#endif
+ ext v11.16b, v11.16b, v11.16b, #8 //PRE 0
+ fmov d3, x10 //CTR block 4k+3
+ rev64 v4.16b, v4.16b //GHASH block 4k (only t0 is free)
+
+ aese v2.16b, v19.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 1
+ fmov v3.d[1], x9 //CTR block 4k+3
+
+ pmull2 v30.1q, v5.2d, v14.2d //GHASH block 4k+1 - high
+ rev64 v7.16b, v7.16b //GHASH block 4k+3 (t0, t1, t2 and t3 free)
+ ldp x21, x22, [x0, #32] //AES block 4k+6 - load plaintext
+#ifdef __AARCH64EB__
+ rev x21, x21
+ rev x22, x22
+#endif
+ aese v0.16b, v18.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 0
+ ldp x23, x24, [x0, #48] //AES block 4k+3 - load plaintext
+#ifdef __AARCH64EB__
+ rev x23, x23
+ rev x24, x24
+#endif
+ pmull v31.1q, v5.1d, v14.1d //GHASH block 4k+1 - low
+ eor v4.16b, v4.16b, v11.16b //PRE 1
+
+ aese v1.16b, v19.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 1
+
+ aese v0.16b, v19.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 1
+ rev64 v6.16b, v6.16b //GHASH block 4k+2 (t0, t1, and t2 free)
+
+ aese v3.16b, v18.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 0
+ eor x24, x24, x14 //AES block 4k+3 - round 12 high
+
+ pmull v11.1q, v4.1d, v15.1d //GHASH block 4k - low
+ mov d8, v4.d[1] //GHASH block 4k - mid
+
+ aese v0.16b, v20.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 2
+
+ aese v3.16b, v19.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 1
+ eor x21, x21, x13 //AES block 4k+6 - round 12 low
+
+ eor v8.8b, v8.8b, v4.8b //GHASH block 4k - mid
+ eor v11.16b, v11.16b, v31.16b //GHASH block 4k+1 - low
+
+ aese v0.16b, v21.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 3
+ eor x19, x19, x13 //AES block 4k+5 - round 12 low
+
+ aese v1.16b, v20.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 2
+ mov d31, v6.d[1] //GHASH block 4k+2 - mid
+
+ pmull2 v9.1q, v4.2d, v15.2d //GHASH block 4k - high
+ mov d4, v5.d[1] //GHASH block 4k+1 - mid
+
+ aese v2.16b, v20.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 2
+
+ aese v1.16b, v21.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 3
+
+ mov d10, v17.d[1] //GHASH block 4k - mid
+ eor v9.16b, v9.16b, v30.16b //GHASH block 4k+1 - high
+
+ aese v3.16b, v20.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 2
+ eor v31.8b, v31.8b, v6.8b //GHASH block 4k+2 - mid
+
+ pmull2 v30.1q, v6.2d, v13.2d //GHASH block 4k+2 - high
+
+ aese v0.16b, v22.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 4
+ eor v4.8b, v4.8b, v5.8b //GHASH block 4k+1 - mid
+
+ aese v3.16b, v21.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 3
+
+ pmull2 v5.1q, v7.2d, v12.2d //GHASH block 4k+3 - high
+ eor x20, x20, x14 //AES block 4k+5 - round 12 high
+ ins v31.d[1], v31.d[0] //GHASH block 4k+2 - mid
+
+ aese v0.16b, v23.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 5
+ add w12, w12, #1 //CTR block 4k+3
+
+ aese v3.16b, v22.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 4
+ eor v9.16b, v9.16b, v30.16b //GHASH block 4k+2 - high
+
+ pmull v4.1q, v4.1d, v17.1d //GHASH block 4k+1 - mid
+ eor x22, x22, x14 //AES block 4k+6 - round 12 high
+
+ pmull2 v31.1q, v31.2d, v16.2d //GHASH block 4k+2 - mid
+ eor x23, x23, x13 //AES block 4k+3 - round 12 low
+ mov d30, v7.d[1] //GHASH block 4k+3 - mid
+
+ pmull v10.1q, v8.1d, v10.1d //GHASH block 4k - mid
+ rev w9, w12 //CTR block 4k+8
+
+ pmull v8.1q, v6.1d, v13.1d //GHASH block 4k+2 - low
+ orr x9, x11, x9, lsl #32 //CTR block 4k+8
+
+ aese v2.16b, v21.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 3
+ eor v30.8b, v30.8b, v7.8b //GHASH block 4k+3 - mid
+
+ aese v1.16b, v22.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 4
+ ldp x6, x7, [x0, #0] //AES block 4k+4 - load plaintext
+#ifdef __AARCH64EB__
+ rev x6, x6
+ rev x7, x7
+#endif
+ aese v0.16b, v24.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 6
+ eor v11.16b, v11.16b, v8.16b //GHASH block 4k+2 - low
+
+ aese v2.16b, v22.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 4
+ add x0, x0, #64 //AES input_ptr update
+
+ aese v1.16b, v23.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 5
+ movi v8.8b, #0xc2
+
+ pmull v6.1q, v7.1d, v12.1d //GHASH block 4k+3 - low
+ eor x7, x7, x14 //AES block 4k+4 - round 12 high
+ eor v10.16b, v10.16b, v4.16b //GHASH block 4k+1 - mid
+
+ aese v2.16b, v23.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 5
+ eor x6, x6, x13 //AES block 4k+4 - round 12 low
+
+ aese v1.16b, v24.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 6
+ shl d8, d8, #56 //mod_constant
+
+ aese v3.16b, v23.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 5
+ eor v9.16b, v9.16b, v5.16b //GHASH block 4k+3 - high
+
+ aese v0.16b, v25.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 7
+ fmov d5, x19 //AES block 4k+5 - mov low
+
+ aese v1.16b, v25.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 7
+ eor v10.16b, v10.16b, v31.16b //GHASH block 4k+2 - mid
+
+ aese v3.16b, v24.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 6
+ fmov v5.d[1], x20 //AES block 4k+5 - mov high
+
+ aese v0.16b, v26.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 8
+ eor v11.16b, v11.16b, v6.16b //GHASH block 4k+3 - low
+
+ pmull v30.1q, v30.1d, v16.1d //GHASH block 4k+3 - mid
+ cmp x0, x5 //.LOOP CONTROL
+ fmov d4, x6 //AES block 4k+4 - mov low
+
+ aese v2.16b, v24.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 6
+ fmov v4.d[1], x7 //AES block 4k+4 - mov high
+
+ aese v1.16b, v26.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 8
+ fmov d7, x23 //AES block 4k+3 - mov low
+
+ eor v10.16b, v10.16b, v30.16b //GHASH block 4k+3 - mid
+ eor v30.16b, v11.16b, v9.16b //MODULO - karatsuba tidy up
+ add w12, w12, #1 //CTR block 4k+8
+
+ aese v2.16b, v25.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 7
+ fmov v7.d[1], x24 //AES block 4k+3 - mov high
+
+ pmull v31.1q, v9.1d, v8.1d //MODULO - top 64b align with mid
+ ext v9.16b, v9.16b, v9.16b, #8 //MODULO - other top alignment
+ fmov d6, x21 //AES block 4k+6 - mov low
+
+ aese v3.16b, v25.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 7
+
+ aese v0.16b, v27.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 9
+ eor v10.16b, v10.16b, v30.16b //MODULO - karatsuba tidy up
+
+ aese v2.16b, v26.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 8
+
+ aese v3.16b, v26.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 8
+
+ aese v1.16b, v27.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 9
+
+ aese v0.16b, v28.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 10
+ eor v10.16b, v10.16b, v31.16b //MODULO - fold into mid
+
+ aese v3.16b, v27.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 9
+
+ aese v2.16b, v27.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 9
+
+ aese v0.16b, v29.16b //AES block 4k+4 - round 11
+
+ aese v1.16b, v28.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 10
+ eor v10.16b, v10.16b, v9.16b //MODULO - fold into mid
+
+ aese v2.16b, v28.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 10
+
+ eor v4.16b, v4.16b, v0.16b //AES block 4k+4 - result
+ fmov d0, x10 //CTR block 4k+8
+
+ aese v1.16b, v29.16b //AES block 4k+5 - round 11
+ fmov v0.d[1], x9 //CTR block 4k+8
+ rev w9, w12 //CTR block 4k+9
+
+ pmull v9.1q, v10.1d, v8.1d //MODULO - mid 64b align with low
+ fmov v6.d[1], x22 //AES block 4k+6 - mov high
+ st1 { v4.16b}, [x2], #16 //AES block 4k+4 - store result
+
+ aese v3.16b, v28.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 10
+ orr x9, x11, x9, lsl #32 //CTR block 4k+9
+
+ eor v5.16b, v5.16b, v1.16b //AES block 4k+5 - result
+ add w12, w12, #1 //CTR block 4k+9
+ fmov d1, x10 //CTR block 4k+9
+
+ aese v2.16b, v29.16b //AES block 4k+6 - round 11
+ fmov v1.d[1], x9 //CTR block 4k+9
+ rev w9, w12 //CTR block 4k+10
+
+ add w12, w12, #1 //CTR block 4k+10
+ ext v10.16b, v10.16b, v10.16b, #8 //MODULO - other mid alignment
+ orr x9, x11, x9, lsl #32 //CTR block 4k+10
+
+ st1 { v5.16b}, [x2], #16 //AES block 4k+5 - store result
+ eor v11.16b, v11.16b, v9.16b //MODULO - fold into low
+
+ aese v3.16b, v29.16b //AES block 4k+7 - round 11
+ eor v6.16b, v6.16b, v2.16b //AES block 4k+6 - result
+ fmov d2, x10 //CTR block 4k+10
+
+ st1 { v6.16b}, [x2], #16 //AES block 4k+6 - store result
+ fmov v2.d[1], x9 //CTR block 4k+10
+ rev w9, w12 //CTR block 4k+11
+
+ eor v11.16b, v11.16b, v10.16b //MODULO - fold into low
+ orr x9, x11, x9, lsl #32 //CTR block 4k+11
+
+ eor v7.16b, v7.16b, v3.16b //AES block 4k+3 - result
+ st1 { v7.16b}, [x2], #16 //AES block 4k+3 - store result
+ b.lt .L192_enc_main_loop
+
+.L192_enc_prepretail: //PREPRETAIL
+ aese v0.16b, v18.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 0
+ rev64 v4.16b, v4.16b //GHASH block 4k (only t0 is free)
+
+ fmov d3, x10 //CTR block 4k+3
+ ext v11.16b, v11.16b, v11.16b, #8 //PRE 0
+ add w12, w12, #1 //CTR block 4k+3
+
+ aese v1.16b, v18.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 0
+ rev64 v5.16b, v5.16b //GHASH block 4k+1 (t0 and t1 free)
+
+ aese v2.16b, v18.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 0
+
+ fmov v3.d[1], x9 //CTR block 4k+3
+ eor v4.16b, v4.16b, v11.16b //PRE 1
+ mov d10, v17.d[1] //GHASH block 4k - mid
+
+ aese v1.16b, v19.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 1
+ rev64 v6.16b, v6.16b //GHASH block 4k+2 (t0, t1, and t2 free)
+
+ pmull2 v30.1q, v5.2d, v14.2d //GHASH block 4k+1 - high
+
+ pmull v11.1q, v4.1d, v15.1d //GHASH block 4k - low
+ mov d8, v4.d[1] //GHASH block 4k - mid
+
+ pmull v31.1q, v5.1d, v14.1d //GHASH block 4k+1 - low
+ rev64 v7.16b, v7.16b //GHASH block 4k+3 (t0, t1, t2 and t3 free)
+
+ pmull2 v9.1q, v4.2d, v15.2d //GHASH block 4k - high
+
+ eor v8.8b, v8.8b, v4.8b //GHASH block 4k - mid
+ mov d4, v5.d[1] //GHASH block 4k+1 - mid
+
+ eor v11.16b, v11.16b, v31.16b //GHASH block 4k+1 - low
+ mov d31, v6.d[1] //GHASH block 4k+2 - mid
+
+ aese v3.16b, v18.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 0
+ eor v9.16b, v9.16b, v30.16b //GHASH block 4k+1 - high
+
+ pmull2 v30.1q, v6.2d, v13.2d //GHASH block 4k+2 - high
+
+ eor v4.8b, v4.8b, v5.8b //GHASH block 4k+1 - mid
+ eor v31.8b, v31.8b, v6.8b //GHASH block 4k+2 - mid
+
+ aese v3.16b, v19.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 1
+
+ aese v2.16b, v19.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 1
+ eor v9.16b, v9.16b, v30.16b //GHASH block 4k+2 - high
+
+ aese v0.16b, v19.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 1
+
+ aese v1.16b, v20.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 2
+ mov d30, v7.d[1] //GHASH block 4k+3 - mid
+
+ pmull2 v5.1q, v7.2d, v12.2d //GHASH block 4k+3 - high
+ ins v31.d[1], v31.d[0] //GHASH block 4k+2 - mid
+
+ aese v0.16b, v20.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 2
+
+ pmull v10.1q, v8.1d, v10.1d //GHASH block 4k - mid
+ eor v30.8b, v30.8b, v7.8b //GHASH block 4k+3 - mid
+
+ aese v1.16b, v21.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 3
+
+ pmull2 v31.1q, v31.2d, v16.2d //GHASH block 4k+2 - mid
+
+ pmull v4.1q, v4.1d, v17.1d //GHASH block 4k+1 - mid
+
+ pmull v30.1q, v30.1d, v16.1d //GHASH block 4k+3 - mid
+ eor v9.16b, v9.16b, v5.16b //GHASH block 4k+3 - high
+
+ pmull v8.1q, v6.1d, v13.1d //GHASH block 4k+2 - low
+
+ aese v0.16b, v21.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 3
+ eor v10.16b, v10.16b, v4.16b //GHASH block 4k+1 - mid
+
+ aese v3.16b, v20.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 2
+
+ aese v2.16b, v20.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 2
+ eor v11.16b, v11.16b, v8.16b //GHASH block 4k+2 - low
+
+ aese v0.16b, v22.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 4
+
+ aese v3.16b, v21.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 3
+ eor v10.16b, v10.16b, v31.16b //GHASH block 4k+2 - mid
+
+ aese v2.16b, v21.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 3
+
+ pmull v6.1q, v7.1d, v12.1d //GHASH block 4k+3 - low
+ movi v8.8b, #0xc2
+
+ aese v3.16b, v22.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 4
+
+ aese v2.16b, v22.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 4
+
+ aese v1.16b, v22.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 4
+ eor v10.16b, v10.16b, v30.16b //GHASH block 4k+3 - mid
+
+ aese v3.16b, v23.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 5
+
+ aese v2.16b, v23.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 5
+
+ aese v1.16b, v23.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 5
+ eor v11.16b, v11.16b, v6.16b //GHASH block 4k+3 - low
+
+ aese v0.16b, v23.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 5
+
+ aese v3.16b, v24.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 6
+ eor v10.16b, v10.16b, v9.16b //karatsuba tidy up
+
+ aese v1.16b, v24.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 6
+
+ aese v0.16b, v24.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 6
+ shl d8, d8, #56 //mod_constant
+
+ aese v3.16b, v25.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 7
+
+ aese v1.16b, v25.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 7
+ eor v10.16b, v10.16b, v11.16b
+
+ aese v0.16b, v25.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 7
+
+ pmull v30.1q, v9.1d, v8.1d
+
+ aese v2.16b, v24.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 6
+ ext v9.16b, v9.16b, v9.16b, #8
+
+ aese v0.16b, v26.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 8
+
+ aese v1.16b, v26.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 8
+ eor v10.16b, v10.16b, v30.16b
+
+ aese v2.16b, v25.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 7
+
+ aese v3.16b, v26.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 8
+
+ aese v0.16b, v27.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 9
+
+ aese v2.16b, v26.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 8
+ eor v10.16b, v10.16b, v9.16b
+
+ aese v3.16b, v27.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 9
+
+ aese v1.16b, v27.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 9
+
+ aese v2.16b, v27.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 9
+
+ pmull v30.1q, v10.1d, v8.1d
+
+ ext v10.16b, v10.16b, v10.16b, #8
+
+ aese v3.16b, v28.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 10
+
+ aese v0.16b, v28.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 10
+
+ aese v2.16b, v28.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 10
+
+ aese v1.16b, v28.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 10
+ eor v11.16b, v11.16b, v30.16b
+
+ aese v0.16b, v29.16b //AES block 4k+4 - round 11
+
+ aese v3.16b, v29.16b //AES block 4k+7 - round 11
+
+ aese v2.16b, v29.16b //AES block 4k+6 - round 11
+
+ aese v1.16b, v29.16b //AES block 4k+5 - round 11
+ eor v11.16b, v11.16b, v10.16b
+.L192_enc_tail: //TAIL
+
+ sub x5, x4, x0 //main_end_input_ptr is number of bytes left to process
+ ldp x6, x7, [x0], #16 //AES block 4k+4 - load plaintext
+#ifdef __AARCH64EB__
+ rev x6, x6
+ rev x7, x7
+#endif
+ eor x6, x6, x13 //AES block 4k+4 - round 12 low
+ eor x7, x7, x14 //AES block 4k+4 - round 12 high
+
+ fmov d4, x6 //AES block 4k+4 - mov low
+
+ fmov v4.d[1], x7 //AES block 4k+4 - mov high
+ cmp x5, #48
+
+ eor v5.16b, v4.16b, v0.16b //AES block 4k+4 - result
+
+ ext v8.16b, v11.16b, v11.16b, #8 //prepare final partial tag
+ b.gt .L192_enc_blocks_more_than_3
+
+ sub w12, w12, #1
+ movi v10.8b, #0
+
+ mov v3.16b, v2.16b
+ movi v9.8b, #0
+ cmp x5, #32
+
+ mov v2.16b, v1.16b
+ movi v11.8b, #0
+ b.gt .L192_enc_blocks_more_than_2
+
+ sub w12, w12, #1
+
+ mov v3.16b, v1.16b
+ cmp x5, #16
+ b.gt .L192_enc_blocks_more_than_1
+
+ sub w12, w12, #1
+ b .L192_enc_blocks_less_than_1
+.L192_enc_blocks_more_than_3: //blocks left > 3
+ st1 { v5.16b}, [x2], #16 //AES final-3 block - store result
+
+ ldp x6, x7, [x0], #16 //AES final-2 block - load input low & high
+#ifdef __AARCH64EB__
+ rev x6, x6
+ rev x7, x7
+#endif
+ rev64 v4.16b, v5.16b //GHASH final-3 block
+
+ eor x6, x6, x13 //AES final-2 block - round 12 low
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+
+ eor x7, x7, x14 //AES final-2 block - round 12 high
+ fmov d5, x6 //AES final-2 block - mov low
+
+ fmov v5.d[1], x7 //AES final-2 block - mov high
+
+ mov d22, v4.d[1] //GHASH final-3 block - mid
+
+ pmull v11.1q, v4.1d, v15.1d //GHASH final-3 block - low
+
+ mov d10, v17.d[1] //GHASH final-3 block - mid
+
+ eor v22.8b, v22.8b, v4.8b //GHASH final-3 block - mid
+
+ movi v8.8b, #0 //suppress further partial tag feed in
+
+ pmull2 v9.1q, v4.2d, v15.2d //GHASH final-3 block - high
+
+ pmull v10.1q, v22.1d, v10.1d //GHASH final-3 block - mid
+ eor v5.16b, v5.16b, v1.16b //AES final-2 block - result
+.L192_enc_blocks_more_than_2: //blocks left > 2
+
+ st1 { v5.16b}, [x2], #16 //AES final-2 block - store result
+
+ rev64 v4.16b, v5.16b //GHASH final-2 block
+ ldp x6, x7, [x0], #16 //AES final-1 block - load input low & high
+#ifdef __AARCH64EB__
+ rev x6, x6
+ rev x7, x7
+#endif
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+
+ eor x7, x7, x14 //AES final-1 block - round 12 high
+
+ pmull2 v20.1q, v4.2d, v14.2d //GHASH final-2 block - high
+ mov d22, v4.d[1] //GHASH final-2 block - mid
+
+ pmull v21.1q, v4.1d, v14.1d //GHASH final-2 block - low
+ eor x6, x6, x13 //AES final-1 block - round 12 low
+
+ fmov d5, x6 //AES final-1 block - mov low
+
+ fmov v5.d[1], x7 //AES final-1 block - mov high
+ eor v9.16b, v9.16b, v20.16b //GHASH final-2 block - high
+ eor v22.8b, v22.8b, v4.8b //GHASH final-2 block - mid
+
+ eor v11.16b, v11.16b, v21.16b //GHASH final-2 block - low
+
+ pmull v22.1q, v22.1d, v17.1d //GHASH final-2 block - mid
+
+ movi v8.8b, #0 //suppress further partial tag feed in
+
+ eor v5.16b, v5.16b, v2.16b //AES final-1 block - result
+
+ eor v10.16b, v10.16b, v22.16b //GHASH final-2 block - mid
+.L192_enc_blocks_more_than_1: //blocks left > 1
+
+ st1 { v5.16b}, [x2], #16 //AES final-1 block - store result
+
+ ldp x6, x7, [x0], #16 //AES final block - load input low & high
+#ifdef __AARCH64EB__
+ rev x6, x6
+ rev x7, x7
+#endif
+ rev64 v4.16b, v5.16b //GHASH final-1 block
+
+ eor x6, x6, x13 //AES final block - round 12 low
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+ movi v8.8b, #0 //suppress further partial tag feed in
+
+ mov d22, v4.d[1] //GHASH final-1 block - mid
+
+ eor v22.8b, v22.8b, v4.8b //GHASH final-1 block - mid
+ eor x7, x7, x14 //AES final block - round 12 high
+ fmov d5, x6 //AES final block - mov low
+
+ pmull2 v20.1q, v4.2d, v13.2d //GHASH final-1 block - high
+ fmov v5.d[1], x7 //AES final block - mov high
+
+ ins v22.d[1], v22.d[0] //GHASH final-1 block - mid
+
+ eor v9.16b, v9.16b, v20.16b //GHASH final-1 block - high
+
+ pmull v21.1q, v4.1d, v13.1d //GHASH final-1 block - low
+
+ pmull2 v22.1q, v22.2d, v16.2d //GHASH final-1 block - mid
+
+ eor v5.16b, v5.16b, v3.16b //AES final block - result
+
+ eor v11.16b, v11.16b, v21.16b //GHASH final-1 block - low
+
+ eor v10.16b, v10.16b, v22.16b //GHASH final-1 block - mid
+.L192_enc_blocks_less_than_1: //blocks left <= 1
+
+ ld1 { v18.16b}, [x2] //load existing bytes where the possibly partial last block is to be stored
+#ifndef __AARCH64EB__
+ rev w9, w12
+#else
+ mov w9, w12
+#endif
+ and x1, x1, #127 //bit_length %= 128
+
+ sub x1, x1, #128 //bit_length -= 128
+ mvn x14, xzr //rk12_h = 0xffffffffffffffff
+
+ neg x1, x1 //bit_length = 128 - #bits in input (in range [1,128])
+ mvn x13, xzr //rk12_l = 0xffffffffffffffff
+
+ and x1, x1, #127 //bit_length %= 128
+
+ lsr x14, x14, x1 //rk12_h is mask for top 64b of last block
+ cmp x1, #64
+
+ csel x6, x13, x14, lt
+ csel x7, x14, xzr, lt
+
+ fmov d0, x6 //ctr0b is mask for last block
+
+ fmov v0.d[1], x7
+
+ and v5.16b, v5.16b, v0.16b //possibly partial last block has zeroes in highest bits
+
+ rev64 v4.16b, v5.16b //GHASH final block
+
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+
+ mov d8, v4.d[1] //GHASH final block - mid
+
+ pmull v21.1q, v4.1d, v12.1d //GHASH final block - low
+
+ pmull2 v20.1q, v4.2d, v12.2d //GHASH final block - high
+
+ eor v8.8b, v8.8b, v4.8b //GHASH final block - mid
+
+ eor v11.16b, v11.16b, v21.16b //GHASH final block - low
+
+ eor v9.16b, v9.16b, v20.16b //GHASH final block - high
+
+ pmull v8.1q, v8.1d, v16.1d //GHASH final block - mid
+
+ eor v10.16b, v10.16b, v8.16b //GHASH final block - mid
+ movi v8.8b, #0xc2
+
+ eor v30.16b, v11.16b, v9.16b //MODULO - karatsuba tidy up
+
+ shl d8, d8, #56 //mod_constant
+
+ bif v5.16b, v18.16b, v0.16b //insert existing bytes in top end of result before storing
+
+ eor v10.16b, v10.16b, v30.16b //MODULO - karatsuba tidy up
+
+ pmull v31.1q, v9.1d, v8.1d //MODULO - top 64b align with mid
+
+ ext v9.16b, v9.16b, v9.16b, #8 //MODULO - other top alignment
+
+ eor v10.16b, v10.16b, v31.16b //MODULO - fold into mid
+
+ eor v10.16b, v10.16b, v9.16b //MODULO - fold into mid
+
+ pmull v9.1q, v10.1d, v8.1d //MODULO - mid 64b align with low
+
+ ext v10.16b, v10.16b, v10.16b, #8 //MODULO - other mid alignment
+
+ eor v11.16b, v11.16b, v9.16b //MODULO - fold into low
+ str w9, [x16, #12] //store the updated counter
+
+ st1 { v5.16b}, [x2] //store all 16B
+
+ eor v11.16b, v11.16b, v10.16b //MODULO - fold into low
+ ext v11.16b, v11.16b, v11.16b, #8
+ rev64 v11.16b, v11.16b
+ mov x0, x15
+ st1 { v11.16b }, [x3]
+
+ ldp x21, x22, [sp, #16]
+ ldp x23, x24, [sp, #32]
+ ldp d8, d9, [sp, #48]
+ ldp d10, d11, [sp, #64]
+ ldp d12, d13, [sp, #80]
+ ldp d14, d15, [sp, #96]
+ ldp x19, x20, [sp], #112
+ ret
+
+.L192_enc_ret:
+ mov w0, #0x0
+ ret
+.size aes_gcm_enc_192_kernel,.-aes_gcm_enc_192_kernel
+.globl aes_gcm_dec_192_kernel
+.type aes_gcm_dec_192_kernel,%function
+.align 4
+aes_gcm_dec_192_kernel:
+ cbz x1, .L192_dec_ret
+ stp x19, x20, [sp, #-112]!
+ mov x16, x4
+ mov x8, x5
+ stp x21, x22, [sp, #16]
+ stp x23, x24, [sp, #32]
+ stp d8, d9, [sp, #48]
+ stp d10, d11, [sp, #64]
+ stp d12, d13, [sp, #80]
+ stp d14, d15, [sp, #96]
+
+ add x4, x0, x1, lsr #3 //end_input_ptr
+ ldp x10, x11, [x16] //ctr96_b64, ctr96_t32
+#ifdef __AARCH64EB__
+ rev x10, x10
+ rev x11, x11
+#endif
+ ldp x13, x14, [x8, #192] //load rk12
+#ifdef __AARCH64EB__
+ ror x13, x13, #32
+ ror x14, x14, #32
+#endif
+ ld1 { v0.16b}, [x16] //special case vector load initial counter so we can start first AES block as quickly as possible
+
+ ld1 {v18.4s}, [x8], #16 //load rk0
+
+ lsr x5, x1, #3 //byte_len
+ mov x15, x5
+ ld1 {v19.4s}, [x8], #16 //load rk1
+
+ lsr x12, x11, #32
+ orr w11, w11, w11
+ fmov d3, x10 //CTR block 3
+
+ rev w12, w12 //rev_ctr32
+ fmov d1, x10 //CTR block 1
+
+ add w12, w12, #1 //increment rev_ctr32
+ ld1 {v20.4s}, [x8], #16 //load rk2
+
+ aese v0.16b, v18.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 0
+ rev w9, w12 //CTR block 1
+
+ add w12, w12, #1 //CTR block 1
+ orr x9, x11, x9, lsl #32 //CTR block 1
+ ld1 {v21.4s}, [x8], #16 //load rk3
+
+ fmov v1.d[1], x9 //CTR block 1
+ rev w9, w12 //CTR block 2
+ add w12, w12, #1 //CTR block 2
+
+ fmov d2, x10 //CTR block 2
+ orr x9, x11, x9, lsl #32 //CTR block 2
+
+ fmov v2.d[1], x9 //CTR block 2
+ rev w9, w12 //CTR block 3
+
+ aese v0.16b, v19.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 1
+ orr x9, x11, x9, lsl #32 //CTR block 3
+
+ fmov v3.d[1], x9 //CTR block 3
+
+ ld1 {v22.4s}, [x8], #16 //load rk4
+
+ aese v0.16b, v20.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 2
+
+ aese v2.16b, v18.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 0
+ ld1 {v23.4s}, [x8], #16 //load rk5
+
+ aese v1.16b, v18.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 0
+ ldr q15, [x3, #112] //load h4l | h4h
+#ifndef __AARCH64EB__
+ ext v15.16b, v15.16b, v15.16b, #8
+#endif
+ aese v3.16b, v18.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 0
+ ldr q13, [x3, #64] //load h2l | h2h
+#ifndef __AARCH64EB__
+ ext v13.16b, v13.16b, v13.16b, #8
+#endif
+ aese v2.16b, v19.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 1
+ ldr q14, [x3, #80] //load h3l | h3h
+#ifndef __AARCH64EB__
+ ext v14.16b, v14.16b, v14.16b, #8
+#endif
+ aese v1.16b, v19.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 1
+
+ aese v3.16b, v19.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 1
+ ldr q12, [x3, #32] //load h1l | h1h
+#ifndef __AARCH64EB__
+ ext v12.16b, v12.16b, v12.16b, #8
+#endif
+ aese v2.16b, v20.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 2
+ ld1 {v24.4s}, [x8], #16 //load rk6
+
+ aese v0.16b, v21.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 3
+ ld1 {v25.4s}, [x8], #16 //load rk7
+
+ aese v1.16b, v20.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 2
+ ld1 {v26.4s}, [x8], #16 //load rk8
+
+ aese v3.16b, v20.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 2
+ ld1 {v27.4s}, [x8], #16 //load rk9
+
+ aese v2.16b, v21.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 3
+ ld1 { v11.16b}, [x3]
+ ext v11.16b, v11.16b, v11.16b, #8
+ rev64 v11.16b, v11.16b
+
+ aese v1.16b, v21.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 3
+ add w12, w12, #1 //CTR block 3
+
+ aese v3.16b, v21.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 3
+ trn1 v9.2d, v14.2d, v15.2d //h4h | h3h
+
+ aese v0.16b, v22.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 4
+ ld1 {v28.4s}, [x8], #16 //load rk10
+
+ aese v1.16b, v22.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 4
+ trn2 v17.2d, v14.2d, v15.2d //h4l | h3l
+
+ aese v2.16b, v22.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 4
+
+ aese v3.16b, v22.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 4
+ trn2 v16.2d, v12.2d, v13.2d //h2l | h1l
+
+ aese v0.16b, v23.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 5
+ ld1 {v29.4s}, [x8], #16 //load rk11
+
+ aese v1.16b, v23.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 5
+
+ aese v2.16b, v23.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 5
+
+ aese v3.16b, v23.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 5
+
+ aese v0.16b, v24.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 6
+
+ aese v2.16b, v24.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 6
+
+ aese v3.16b, v24.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 6
+
+ aese v0.16b, v25.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 7
+
+ aese v2.16b, v25.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 7
+
+ aese v3.16b, v25.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 7
+
+ aese v1.16b, v24.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 6
+
+ aese v2.16b, v26.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 8
+
+ aese v3.16b, v26.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 8
+
+ aese v1.16b, v25.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 7
+
+ aese v2.16b, v27.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 9
+
+ aese v3.16b, v27.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 9
+
+ aese v1.16b, v26.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 8
+ sub x5, x5, #1 //byte_len - 1
+
+ aese v0.16b, v26.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 8
+ and x5, x5, #0xffffffffffffffc0 //number of bytes to be processed in main loop (at least 1 byte must be handled by tail)
+
+ aese v3.16b, v28.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 10
+ add x5, x5, x0
+
+ aese v1.16b, v27.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 9
+ cmp x0, x5 //check if we have <= 4 blocks
+
+ aese v0.16b, v27.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 9
+ trn1 v8.2d, v12.2d, v13.2d //h2h | h1h
+
+ aese v3.16b, v29.16b //AES block 3 - round 11
+
+ aese v2.16b, v28.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 10
+
+ aese v1.16b, v28.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 10
+
+ aese v0.16b, v28.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 10
+ eor v16.16b, v16.16b, v8.16b //h2k | h1k
+
+ aese v2.16b, v29.16b //AES block 2 - round 11
+
+ aese v1.16b, v29.16b //AES block 1 - round 11
+ eor v17.16b, v17.16b, v9.16b //h4k | h3k
+
+ aese v0.16b, v29.16b //AES block 0 - round 11
+ b.ge .L192_dec_tail //handle tail
+
+ ld1 {v4.16b, v5.16b}, [x0], #32 //AES block 0,1 - load ciphertext
+
+ eor v1.16b, v5.16b, v1.16b //AES block 1 - result
+
+ eor v0.16b, v4.16b, v0.16b //AES block 0 - result
+ rev w9, w12 //CTR block 4
+ ld1 {v6.16b, v7.16b}, [x0], #32 //AES block 2,3 - load ciphertext
+
+ mov x19, v1.d[0] //AES block 1 - mov low
+
+ mov x20, v1.d[1] //AES block 1 - mov high
+
+ mov x6, v0.d[0] //AES block 0 - mov low
+ orr x9, x11, x9, lsl #32 //CTR block 4
+ add w12, w12, #1 //CTR block 4
+
+ mov x7, v0.d[1] //AES block 0 - mov high
+ rev64 v4.16b, v4.16b //GHASH block 0
+
+ fmov d0, x10 //CTR block 4
+ rev64 v5.16b, v5.16b //GHASH block 1
+ cmp x0, x5 //check if we have <= 8 blocks
+
+ eor x19, x19, x13 //AES block 1 - round 12 low
+#ifdef __AARCH64EB__
+ rev x19, x19
+#endif
+ fmov v0.d[1], x9 //CTR block 4
+ rev w9, w12 //CTR block 5
+
+ orr x9, x11, x9, lsl #32 //CTR block 5
+ fmov d1, x10 //CTR block 5
+ eor x20, x20, x14 //AES block 1 - round 12 high
+#ifdef __AARCH64EB__
+ rev x20, x20
+#endif
+ add w12, w12, #1 //CTR block 5
+ fmov v1.d[1], x9 //CTR block 5
+ eor x6, x6, x13 //AES block 0 - round 12 low
+#ifdef __AARCH64EB__
+ rev x6, x6
+#endif
+ rev w9, w12 //CTR block 6
+ eor x7, x7, x14 //AES block 0 - round 12 high
+#ifdef __AARCH64EB__
+ rev x7, x7
+#endif
+ stp x6, x7, [x2], #16 //AES block 0 - store result
+ orr x9, x11, x9, lsl #32 //CTR block 6
+
+ stp x19, x20, [x2], #16 //AES block 1 - store result
+
+ add w12, w12, #1 //CTR block 6
+ eor v2.16b, v6.16b, v2.16b //AES block 2 - result
+ b.ge .L192_dec_prepretail //do prepretail
+
+.L192_dec_main_loop: //main loop start
+ aese v1.16b, v18.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 0
+ ext v11.16b, v11.16b, v11.16b, #8 //PRE 0
+
+ pmull v31.1q, v5.1d, v14.1d //GHASH block 4k+1 - low
+ mov x21, v2.d[0] //AES block 4k+2 - mov low
+
+ mov x22, v2.d[1] //AES block 4k+2 - mov high
+ eor v3.16b, v7.16b, v3.16b //AES block 4k+3 - result
+ rev64 v7.16b, v7.16b //GHASH block 4k+3
+
+ aese v1.16b, v19.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 1
+ fmov d2, x10 //CTR block 4k+6
+
+ aese v0.16b, v18.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 0
+ eor v4.16b, v4.16b, v11.16b //PRE 1
+
+ pmull2 v30.1q, v5.2d, v14.2d //GHASH block 4k+1 - high
+ fmov v2.d[1], x9 //CTR block 4k+6
+
+ aese v1.16b, v20.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 2
+ mov x24, v3.d[1] //AES block 4k+3 - mov high
+
+ aese v0.16b, v19.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 1
+ mov x23, v3.d[0] //AES block 4k+3 - mov low
+
+ pmull2 v9.1q, v4.2d, v15.2d //GHASH block 4k - high
+ fmov d3, x10 //CTR block 4k+7
+ mov d8, v4.d[1] //GHASH block 4k - mid
+
+ pmull v11.1q, v4.1d, v15.1d //GHASH block 4k - low
+ mov d10, v17.d[1] //GHASH block 4k - mid
+ rev w9, w12 //CTR block 4k+7
+
+ aese v2.16b, v18.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 0
+ orr x9, x11, x9, lsl #32 //CTR block 4k+7
+
+ fmov v3.d[1], x9 //CTR block 4k+7
+ eor v8.8b, v8.8b, v4.8b //GHASH block 4k - mid
+ mov d4, v5.d[1] //GHASH block 4k+1 - mid
+
+ aese v1.16b, v21.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 3
+
+ aese v0.16b, v20.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 2
+ eor x22, x22, x14 //AES block 4k+2 - round 12 high
+#ifdef __AARCH64EB__
+ rev x22, x22
+#endif
+ aese v2.16b, v19.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 1
+ eor v4.8b, v4.8b, v5.8b //GHASH block 4k+1 - mid
+
+ pmull v10.1q, v8.1d, v10.1d //GHASH block 4k - mid
+
+ aese v3.16b, v18.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 0
+ rev64 v6.16b, v6.16b //GHASH block 4k+2
+
+ aese v2.16b, v20.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 2
+
+ pmull v4.1q, v4.1d, v17.1d //GHASH block 4k+1 - mid
+ eor v11.16b, v11.16b, v31.16b //GHASH block 4k+1 - low
+ eor x21, x21, x13 //AES block 4k+2 - round 12 low
+#ifdef __AARCH64EB__
+ rev x21, x21
+#endif
+ aese v1.16b, v22.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 4
+
+ aese v0.16b, v21.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 3
+
+ eor v10.16b, v10.16b, v4.16b //GHASH block 4k+1 - mid
+ mov d31, v6.d[1] //GHASH block 4k+2 - mid
+
+ aese v3.16b, v19.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 1
+ eor v9.16b, v9.16b, v30.16b //GHASH block 4k+1 - high
+
+ aese v0.16b, v22.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 4
+
+ pmull2 v30.1q, v6.2d, v13.2d //GHASH block 4k+2 - high
+ eor v31.8b, v31.8b, v6.8b //GHASH block 4k+2 - mid
+
+ pmull v8.1q, v6.1d, v13.1d //GHASH block 4k+2 - low
+
+ aese v0.16b, v23.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 5
+
+ eor v9.16b, v9.16b, v30.16b //GHASH block 4k+2 - high
+ mov d30, v7.d[1] //GHASH block 4k+3 - mid
+
+ aese v1.16b, v23.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 5
+
+ pmull2 v5.1q, v7.2d, v12.2d //GHASH block 4k+3 - high
+
+ aese v3.16b, v20.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 2
+ eor v30.8b, v30.8b, v7.8b //GHASH block 4k+3 - mid
+
+ aese v1.16b, v24.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 6
+
+ aese v0.16b, v24.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 6
+ ins v31.d[1], v31.d[0] //GHASH block 4k+2 - mid
+
+ aese v3.16b, v21.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 3
+
+ pmull v30.1q, v30.1d, v16.1d //GHASH block 4k+3 - mid
+ eor v11.16b, v11.16b, v8.16b //GHASH block 4k+2 - low
+
+ aese v0.16b, v25.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 7
+
+ pmull2 v31.1q, v31.2d, v16.2d //GHASH block 4k+2 - mid
+ eor v9.16b, v9.16b, v5.16b //GHASH block 4k+3 - high
+
+ aese v1.16b, v25.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 7
+
+ aese v0.16b, v26.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 8
+ movi v8.8b, #0xc2
+
+ pmull v6.1q, v7.1d, v12.1d //GHASH block 4k+3 - low
+
+ aese v1.16b, v26.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 8
+ eor v10.16b, v10.16b, v31.16b //GHASH block 4k+2 - mid
+
+ aese v2.16b, v21.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 3
+
+ aese v0.16b, v27.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 9
+ eor v11.16b, v11.16b, v6.16b //GHASH block 4k+3 - low
+
+ aese v3.16b, v22.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 4
+
+ aese v2.16b, v22.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 4
+ eor v10.16b, v10.16b, v30.16b //GHASH block 4k+3 - mid
+
+ aese v0.16b, v28.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 10
+
+ aese v1.16b, v27.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 9
+ eor v30.16b, v11.16b, v9.16b //MODULO - karatsuba tidy up
+
+ aese v2.16b, v23.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 5
+
+ aese v3.16b, v23.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 5
+ shl d8, d8, #56 //mod_constant
+
+ aese v1.16b, v28.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 10
+
+ aese v2.16b, v24.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 6
+ ld1 {v4.16b}, [x0], #16 //AES block 4k+4 - load ciphertext
+
+ aese v3.16b, v24.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 6
+ eor v10.16b, v10.16b, v30.16b //MODULO - karatsuba tidy up
+
+ pmull v31.1q, v9.1d, v8.1d //MODULO - top 64b align with mid
+ ld1 {v5.16b}, [x0], #16 //AES block 4k+5 - load ciphertext
+ eor x23, x23, x13 //AES block 4k+3 - round 12 low
+#ifdef __AARCH64EB__
+ rev x23, x23
+#endif
+ aese v2.16b, v25.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 7
+ ext v9.16b, v9.16b, v9.16b, #8 //MODULO - other top alignment
+
+ aese v0.16b, v29.16b //AES block 4k+4 - round 11
+ add w12, w12, #1 //CTR block 4k+7
+
+ aese v3.16b, v25.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 7
+ eor v10.16b, v10.16b, v31.16b //MODULO - fold into mid
+
+ aese v2.16b, v26.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 8
+ ld1 {v6.16b}, [x0], #16 //AES block 4k+6 - load ciphertext
+
+ aese v1.16b, v29.16b //AES block 4k+5 - round 11
+ ld1 {v7.16b}, [x0], #16 //AES block 4k+7 - load ciphertext
+ rev w9, w12 //CTR block 4k+8
+
+ aese v3.16b, v26.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 8
+ stp x21, x22, [x2], #16 //AES block 4k+2 - store result
+
+ aese v2.16b, v27.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 9
+ eor v10.16b, v10.16b, v9.16b //MODULO - fold into mid
+
+ cmp x0, x5 //.LOOP CONTROL
+
+ eor v0.16b, v4.16b, v0.16b //AES block 4k+4 - result
+ eor x24, x24, x14 //AES block 4k+3 - round 12 high
+#ifdef __AARCH64EB__
+ rev x24, x24
+#endif
+ eor v1.16b, v5.16b, v1.16b //AES block 4k+5 - result
+
+ aese v2.16b, v28.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 10
+ orr x9, x11, x9, lsl #32 //CTR block 4k+8
+
+ aese v3.16b, v27.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 9
+
+ pmull v8.1q, v10.1d, v8.1d //MODULO - mid 64b align with low
+ mov x19, v1.d[0] //AES block 4k+5 - mov low
+
+ mov x6, v0.d[0] //AES block 4k+4 - mov low
+ stp x23, x24, [x2], #16 //AES block 4k+3 - store result
+ rev64 v5.16b, v5.16b //GHASH block 4k+5
+
+ aese v2.16b, v29.16b //AES block 4k+6 - round 11
+ mov x7, v0.d[1] //AES block 4k+4 - mov high
+
+ aese v3.16b, v28.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 10
+ mov x20, v1.d[1] //AES block 4k+5 - mov high
+
+ fmov d0, x10 //CTR block 4k+8
+ add w12, w12, #1 //CTR block 4k+8
+ ext v10.16b, v10.16b, v10.16b, #8 //MODULO - other mid alignment
+
+ eor v2.16b, v6.16b, v2.16b //AES block 4k+6 - result
+ fmov v0.d[1], x9 //CTR block 4k+8
+ rev w9, w12 //CTR block 4k+9
+
+ eor x6, x6, x13 //AES block 4k+4 - round 12 low
+#ifdef __AARCH64EB__
+ rev x6, x6
+#endif
+ orr x9, x11, x9, lsl #32 //CTR block 4k+9
+ eor v11.16b, v11.16b, v8.16b //MODULO - fold into low
+
+ fmov d1, x10 //CTR block 4k+9
+ add w12, w12, #1 //CTR block 4k+9
+ eor x19, x19, x13 //AES block 4k+5 - round 12 low
+#ifdef __AARCH64EB__
+ rev x19, x19
+#endif
+ fmov v1.d[1], x9 //CTR block 4k+9
+ rev w9, w12 //CTR block 4k+10
+ eor x20, x20, x14 //AES block 4k+5 - round 12 high
+#ifdef __AARCH64EB__
+ rev x20, x20
+#endif
+ eor x7, x7, x14 //AES block 4k+4 - round 12 high
+#ifdef __AARCH64EB__
+ rev x7, x7
+#endif
+ stp x6, x7, [x2], #16 //AES block 4k+4 - store result
+ eor v11.16b, v11.16b, v10.16b //MODULO - fold into low
+
+ add w12, w12, #1 //CTR block 4k+10
+ rev64 v4.16b, v4.16b //GHASH block 4k+4
+ orr x9, x11, x9, lsl #32 //CTR block 4k+10
+
+ aese v3.16b, v29.16b //AES block 4k+7 - round 11
+ stp x19, x20, [x2], #16 //AES block 4k+5 - store result
+ b.lt .L192_dec_main_loop
+
+.L192_dec_prepretail: //PREPRETAIL
+ mov x22, v2.d[1] //AES block 4k+2 - mov high
+ ext v11.16b, v11.16b, v11.16b, #8 //PRE 0
+ eor v3.16b, v7.16b, v3.16b //AES block 4k+3 - result
+
+ aese v1.16b, v18.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 0
+ mov x21, v2.d[0] //AES block 4k+2 - mov low
+
+ aese v0.16b, v18.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 0
+ mov d10, v17.d[1] //GHASH block 4k - mid
+
+ eor v4.16b, v4.16b, v11.16b //PRE 1
+ fmov d2, x10 //CTR block 4k+6
+
+ aese v1.16b, v19.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 1
+ mov x23, v3.d[0] //AES block 4k+3 - mov low
+
+ aese v0.16b, v19.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 1
+ mov x24, v3.d[1] //AES block 4k+3 - mov high
+
+ pmull v11.1q, v4.1d, v15.1d //GHASH block 4k - low
+ mov d8, v4.d[1] //GHASH block 4k - mid
+ fmov d3, x10 //CTR block 4k+7
+
+ aese v1.16b, v20.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 2
+ rev64 v6.16b, v6.16b //GHASH block 4k+2
+
+ pmull2 v9.1q, v4.2d, v15.2d //GHASH block 4k - high
+ fmov v2.d[1], x9 //CTR block 4k+6
+ rev w9, w12 //CTR block 4k+7
+
+ orr x9, x11, x9, lsl #32 //CTR block 4k+7
+ eor v8.8b, v8.8b, v4.8b //GHASH block 4k - mid
+ mov d4, v5.d[1] //GHASH block 4k+1 - mid
+
+ pmull v31.1q, v5.1d, v14.1d //GHASH block 4k+1 - low
+ eor x24, x24, x14 //AES block 4k+3 - round 12 high
+#ifdef __AARCH64EB__
+ rev x24, x24
+#endif
+ fmov v3.d[1], x9 //CTR block 4k+7
+
+ aese v0.16b, v20.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 2
+ eor x21, x21, x13 //AES block 4k+2 - round 12 low
+#ifdef __AARCH64EB__
+ rev x21, x21
+#endif
+ pmull2 v30.1q, v5.2d, v14.2d //GHASH block 4k+1 - high
+ eor x22, x22, x14 //AES block 4k+2 - round 12 high
+#ifdef __AARCH64EB__
+ rev x22, x22
+#endif
+ eor v4.8b, v4.8b, v5.8b //GHASH block 4k+1 - mid
+
+ pmull v10.1q, v8.1d, v10.1d //GHASH block 4k - mid
+ eor x23, x23, x13 //AES block 4k+3 - round 12 low
+#ifdef __AARCH64EB__
+ rev x23, x23
+#endif
+ stp x21, x22, [x2], #16 //AES block 4k+2 - store result
+
+ rev64 v7.16b, v7.16b //GHASH block 4k+3
+ stp x23, x24, [x2], #16 //AES block 4k+3 - store result
+
+ aese v3.16b, v18.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 0
+ eor v9.16b, v9.16b, v30.16b //GHASH block 4k+1 - high
+
+ pmull v4.1q, v4.1d, v17.1d //GHASH block 4k+1 - mid
+ add w12, w12, #1 //CTR block 4k+7
+
+ pmull2 v30.1q, v6.2d, v13.2d //GHASH block 4k+2 - high
+ eor v11.16b, v11.16b, v31.16b //GHASH block 4k+1 - low
+
+ aese v2.16b, v18.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 0
+
+ eor v10.16b, v10.16b, v4.16b //GHASH block 4k+1 - mid
+ mov d31, v6.d[1] //GHASH block 4k+2 - mid
+
+ aese v3.16b, v19.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 1
+
+ aese v2.16b, v19.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 1
+ eor v9.16b, v9.16b, v30.16b //GHASH block 4k+2 - high
+
+ eor v31.8b, v31.8b, v6.8b //GHASH block 4k+2 - mid
+
+ pmull v8.1q, v6.1d, v13.1d //GHASH block 4k+2 - low
+
+ aese v2.16b, v20.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 2
+ mov d30, v7.d[1] //GHASH block 4k+3 - mid
+
+ aese v3.16b, v20.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 2
+ ins v31.d[1], v31.d[0] //GHASH block 4k+2 - mid
+
+ pmull v6.1q, v7.1d, v12.1d //GHASH block 4k+3 - low
+
+ aese v0.16b, v21.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 3
+ eor v30.8b, v30.8b, v7.8b //GHASH block 4k+3 - mid
+
+ aese v1.16b, v21.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 3
+
+ pmull2 v31.1q, v31.2d, v16.2d //GHASH block 4k+2 - mid
+ eor v11.16b, v11.16b, v8.16b //GHASH block 4k+2 - low
+
+ aese v0.16b, v22.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 4
+
+ pmull2 v5.1q, v7.2d, v12.2d //GHASH block 4k+3 - high
+ movi v8.8b, #0xc2
+
+ pmull v30.1q, v30.1d, v16.1d //GHASH block 4k+3 - mid
+
+ aese v2.16b, v21.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 3
+
+ shl d8, d8, #56 //mod_constant
+ eor v9.16b, v9.16b, v5.16b //GHASH block 4k+3 - high
+
+ aese v0.16b, v23.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 5
+ eor v10.16b, v10.16b, v31.16b //GHASH block 4k+2 - mid
+
+ aese v2.16b, v22.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 4
+
+ pmull v31.1q, v9.1d, v8.1d //MODULO - top 64b align with mid
+ eor v11.16b, v11.16b, v6.16b //GHASH block 4k+3 - low
+
+ aese v0.16b, v24.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 6
+
+ aese v3.16b, v21.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 3
+ eor v10.16b, v10.16b, v30.16b //GHASH block 4k+3 - mid
+
+ aese v2.16b, v23.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 5
+
+ aese v0.16b, v25.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 7
+ eor v30.16b, v11.16b, v9.16b //MODULO - karatsuba tidy up
+
+ aese v3.16b, v22.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 4
+
+ aese v2.16b, v24.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 6
+ ext v9.16b, v9.16b, v9.16b, #8 //MODULO - other top alignment
+
+ aese v0.16b, v26.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 8
+
+ aese v3.16b, v23.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 5
+ eor v10.16b, v10.16b, v30.16b //MODULO - karatsuba tidy up
+
+ aese v1.16b, v22.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 4
+
+ aese v2.16b, v25.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 7
+
+ aese v0.16b, v27.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 9
+
+ aese v1.16b, v23.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 5
+
+ aese v3.16b, v24.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 6
+ eor v10.16b, v10.16b, v31.16b //MODULO - fold into mid
+
+ aese v0.16b, v28.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 10
+
+ aese v1.16b, v24.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 6
+
+ aese v3.16b, v25.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 7
+
+ aese v2.16b, v26.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 8
+ eor v10.16b, v10.16b, v9.16b //MODULO - fold into mid
+
+ aese v1.16b, v25.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 7
+
+ aese v3.16b, v26.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 8
+
+ aese v2.16b, v27.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 9
+
+ aese v1.16b, v26.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 8
+
+ aese v3.16b, v27.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 9
+
+ pmull v8.1q, v10.1d, v8.1d //MODULO - mid 64b align with low
+
+ aese v1.16b, v27.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 9
+
+ aese v2.16b, v28.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 10
+
+ aese v3.16b, v28.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 10
+ ext v10.16b, v10.16b, v10.16b, #8 //MODULO - other mid alignment
+
+ aese v1.16b, v28.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 10
+
+ aese v0.16b, v29.16b
+ eor v11.16b, v11.16b, v8.16b //MODULO - fold into low
+
+ aese v2.16b, v29.16b
+
+ aese v1.16b, v29.16b
+
+ aese v3.16b, v29.16b
+
+ eor v11.16b, v11.16b, v10.16b //MODULO - fold into low
+.L192_dec_tail: //TAIL
+
+ sub x5, x4, x0 //main_end_input_ptr is number of bytes left to process
+ ld1 { v5.16b}, [x0], #16 //AES block 4k+4 - load ciphertext
+
+ eor v0.16b, v5.16b, v0.16b //AES block 4k+4 - result
+
+ mov x7, v0.d[1] //AES block 4k+4 - mov high
+
+ mov x6, v0.d[0] //AES block 4k+4 - mov low
+
+ ext v8.16b, v11.16b, v11.16b, #8 //prepare final partial tag
+
+ cmp x5, #48
+
+ eor x7, x7, x14 //AES block 4k+4 - round 12 high
+#ifdef __AARCH64EB__
+ rev x7, x7
+#endif
+ eor x6, x6, x13 //AES block 4k+4 - round 12 low
+#ifdef __AARCH64EB__
+ rev x6, x6
+#endif
+ b.gt .L192_dec_blocks_more_than_3
+
+ movi v11.8b, #0
+ movi v9.8b, #0
+
+ mov v3.16b, v2.16b
+ mov v2.16b, v1.16b
+ sub w12, w12, #1
+
+ movi v10.8b, #0
+ cmp x5, #32
+ b.gt .L192_dec_blocks_more_than_2
+
+ mov v3.16b, v1.16b
+ cmp x5, #16
+ sub w12, w12, #1
+
+ b.gt .L192_dec_blocks_more_than_1
+
+ sub w12, w12, #1
+ b .L192_dec_blocks_less_than_1
+.L192_dec_blocks_more_than_3: //blocks left > 3
+ rev64 v4.16b, v5.16b //GHASH final-3 block
+ ld1 { v5.16b}, [x0], #16 //AES final-2 block - load ciphertext
+
+ stp x6, x7, [x2], #16 //AES final-3 block - store result
+
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+
+ eor v0.16b, v5.16b, v1.16b //AES final-2 block - result
+
+ pmull v11.1q, v4.1d, v15.1d //GHASH final-3 block - low
+ mov x6, v0.d[0] //AES final-2 block - mov low
+ mov d22, v4.d[1] //GHASH final-3 block - mid
+
+ mov x7, v0.d[1] //AES final-2 block - mov high
+
+ mov d10, v17.d[1] //GHASH final-3 block - mid
+ eor v22.8b, v22.8b, v4.8b //GHASH final-3 block - mid
+
+ pmull2 v9.1q, v4.2d, v15.2d //GHASH final-3 block - high
+
+ eor x6, x6, x13 //AES final-2 block - round 12 low
+#ifdef __AARCH64EB__
+ rev x6, x6
+#endif
+ movi v8.8b, #0 //suppress further partial tag feed in
+
+ pmull v10.1q, v22.1d, v10.1d //GHASH final-3 block - mid
+ eor x7, x7, x14 //AES final-2 block - round 12 high
+#ifdef __AARCH64EB__
+ rev x7, x7
+#endif
+.L192_dec_blocks_more_than_2: //blocks left > 2
+
+ rev64 v4.16b, v5.16b //GHASH final-2 block
+ ld1 { v5.16b}, [x0], #16 //AES final-1 block - load ciphertext
+
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+
+ movi v8.8b, #0 //suppress further partial tag feed in
+
+ eor v0.16b, v5.16b, v2.16b //AES final-1 block - result
+
+ mov d22, v4.d[1] //GHASH final-2 block - mid
+
+ pmull v21.1q, v4.1d, v14.1d //GHASH final-2 block - low
+
+ stp x6, x7, [x2], #16 //AES final-2 block - store result
+
+ eor v22.8b, v22.8b, v4.8b //GHASH final-2 block - mid
+ mov x7, v0.d[1] //AES final-1 block - mov high
+
+ eor v11.16b, v11.16b, v21.16b //GHASH final-2 block - low
+ mov x6, v0.d[0] //AES final-1 block - mov low
+
+ pmull2 v20.1q, v4.2d, v14.2d //GHASH final-2 block - high
+
+ pmull v22.1q, v22.1d, v17.1d //GHASH final-2 block - mid
+
+ eor v9.16b, v9.16b, v20.16b //GHASH final-2 block - high
+ eor x7, x7, x14 //AES final-1 block - round 12 high
+#ifdef __AARCH64EB__
+ rev x7, x7
+#endif
+ eor x6, x6, x13 //AES final-1 block - round 12 low
+#ifdef __AARCH64EB__
+ rev x6, x6
+#endif
+ eor v10.16b, v10.16b, v22.16b //GHASH final-2 block - mid
+.L192_dec_blocks_more_than_1: //blocks left > 1
+
+ rev64 v4.16b, v5.16b //GHASH final-1 block
+
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+ ld1 { v5.16b}, [x0], #16 //AES final block - load ciphertext
+
+ mov d22, v4.d[1] //GHASH final-1 block - mid
+
+ pmull2 v20.1q, v4.2d, v13.2d //GHASH final-1 block - high
+
+ eor v0.16b, v5.16b, v3.16b //AES final block - result
+ stp x6, x7, [x2], #16 //AES final-1 block - store result
+
+ eor v22.8b, v22.8b, v4.8b //GHASH final-1 block - mid
+
+ eor v9.16b, v9.16b, v20.16b //GHASH final-1 block - high
+
+ pmull v21.1q, v4.1d, v13.1d //GHASH final-1 block - low
+ mov x7, v0.d[1] //AES final block - mov high
+
+ ins v22.d[1], v22.d[0] //GHASH final-1 block - mid
+ mov x6, v0.d[0] //AES final block - mov low
+
+ pmull2 v22.1q, v22.2d, v16.2d //GHASH final-1 block - mid
+
+ movi v8.8b, #0 //suppress further partial tag feed in
+ eor v11.16b, v11.16b, v21.16b //GHASH final-1 block - low
+ eor x7, x7, x14 //AES final block - round 12 high
+#ifdef __AARCH64EB__
+ rev x7, x7
+#endif
+ eor x6, x6, x13 //AES final block - round 12 low
+#ifdef __AARCH64EB__
+ rev x6, x6
+#endif
+ eor v10.16b, v10.16b, v22.16b //GHASH final-1 block - mid
+.L192_dec_blocks_less_than_1: //blocks left <= 1
+
+ mvn x13, xzr //rk12_l = 0xffffffffffffffff
+ ldp x4, x5, [x2] //load existing bytes we need to not overwrite
+ and x1, x1, #127 //bit_length %= 128
+
+ sub x1, x1, #128 //bit_length -= 128
+
+ neg x1, x1 //bit_length = 128 - #bits in input (in range [1,128])
+
+ and x1, x1, #127 //bit_length %= 128
+ mvn x14, xzr //rk12_h = 0xffffffffffffffff
+
+ lsr x14, x14, x1 //rk12_h is mask for top 64b of last block
+ cmp x1, #64
+
+ csel x9, x13, x14, lt
+ csel x10, x14, xzr, lt
+
+ fmov d0, x9 //ctr0b is mask for last block
+ and x6, x6, x9
+ bic x4, x4, x9 //mask out low existing bytes
+
+ orr x6, x6, x4
+ mov v0.d[1], x10
+#ifndef __AARCH64EB__
+ rev w9, w12
+#else
+ mov w9, w12
+#endif
+
+ and v5.16b, v5.16b, v0.16b //possibly partial last block has zeroes in highest bits
+ str w9, [x16, #12] //store the updated counter
+
+ rev64 v4.16b, v5.16b //GHASH final block
+
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+ bic x5, x5, x10 //mask out high existing bytes
+
+ and x7, x7, x10
+
+ pmull2 v20.1q, v4.2d, v12.2d //GHASH final block - high
+ mov d8, v4.d[1] //GHASH final block - mid
+
+ pmull v21.1q, v4.1d, v12.1d //GHASH final block - low
+
+ eor v8.8b, v8.8b, v4.8b //GHASH final block - mid
+
+ eor v9.16b, v9.16b, v20.16b //GHASH final block - high
+
+ pmull v8.1q, v8.1d, v16.1d //GHASH final block - mid
+
+ eor v11.16b, v11.16b, v21.16b //GHASH final block - low
+
+ eor v10.16b, v10.16b, v8.16b //GHASH final block - mid
+ movi v8.8b, #0xc2
+
+ eor v30.16b, v11.16b, v9.16b //MODULO - karatsuba tidy up
+
+ shl d8, d8, #56 //mod_constant
+
+ eor v10.16b, v10.16b, v30.16b //MODULO - karatsuba tidy up
+
+ pmull v31.1q, v9.1d, v8.1d //MODULO - top 64b align with mid
+ orr x7, x7, x5
+ stp x6, x7, [x2]
+
+ ext v9.16b, v9.16b, v9.16b, #8 //MODULO - other top alignment
+
+ eor v10.16b, v10.16b, v31.16b //MODULO - fold into mid
+
+ eor v10.16b, v10.16b, v9.16b //MODULO - fold into mid
+
+ pmull v8.1q, v10.1d, v8.1d //MODULO - mid 64b align with low
+
+ eor v11.16b, v11.16b, v8.16b //MODULO - fold into low
+
+ ext v10.16b, v10.16b, v10.16b, #8 //MODULO - other mid alignment
+
+ eor v11.16b, v11.16b, v10.16b //MODULO - fold into low
+ ext v11.16b, v11.16b, v11.16b, #8
+ rev64 v11.16b, v11.16b
+ mov x0, x15
+ st1 { v11.16b }, [x3]
+
+ ldp x21, x22, [sp, #16]
+ ldp x23, x24, [sp, #32]
+ ldp d8, d9, [sp, #48]
+ ldp d10, d11, [sp, #64]
+ ldp d12, d13, [sp, #80]
+ ldp d14, d15, [sp, #96]
+ ldp x19, x20, [sp], #112
+ ret
+
+.L192_dec_ret:
+ mov w0, #0x0
+ ret
+.size aes_gcm_dec_192_kernel,.-aes_gcm_dec_192_kernel
+.globl aes_gcm_enc_256_kernel
+.type aes_gcm_enc_256_kernel,%function
+.align 4
+aes_gcm_enc_256_kernel:
+ cbz x1, .L256_enc_ret
+ stp x19, x20, [sp, #-112]!
+ mov x16, x4
+ mov x8, x5
+ stp x21, x22, [sp, #16]
+ stp x23, x24, [sp, #32]
+ stp d8, d9, [sp, #48]
+ stp d10, d11, [sp, #64]
+ stp d12, d13, [sp, #80]
+ stp d14, d15, [sp, #96]
+
+ add x4, x0, x1, lsr #3 //end_input_ptr
+ lsr x5, x1, #3 //byte_len
+ mov x15, x5
+ ldp x10, x11, [x16] //ctr96_b64, ctr96_t32
+#ifdef __AARCH64EB__
+ rev x10, x10
+ rev x11, x11
+#endif
+ ldp x13, x14, [x8, #224] //load rk14
+#ifdef __AARCH64EB__
+ ror x13, x13, #32
+ ror x14, x14, #32
+#endif
+ ld1 { v0.16b}, [x16] //special case vector load initial counter so we can start first AES block as quickly as possible
+ sub x5, x5, #1 //byte_len - 1
+
+ ld1 {v18.4s}, [x8], #16 //load rk0
+ and x5, x5, #0xffffffffffffffc0 //number of bytes to be processed in main loop (at least 1 byte must be handled by tail)
+
+ ld1 {v19.4s}, [x8], #16 //load rk1
+ add x5, x5, x0
+
+ lsr x12, x11, #32
+ fmov d2, x10 //CTR block 2
+ orr w11, w11, w11
+
+ rev w12, w12 //rev_ctr32
+ cmp x0, x5 //check if we have <= 4 blocks
+ fmov d1, x10 //CTR block 1
+
+ aese v0.16b, v18.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 0
+ add w12, w12, #1 //increment rev_ctr32
+
+ rev w9, w12 //CTR block 1
+ fmov d3, x10 //CTR block 3
+
+ orr x9, x11, x9, lsl #32 //CTR block 1
+ add w12, w12, #1 //CTR block 1
+ ld1 {v20.4s}, [x8], #16 //load rk2
+
+ fmov v1.d[1], x9 //CTR block 1
+ rev w9, w12 //CTR block 2
+ add w12, w12, #1 //CTR block 2
+
+ orr x9, x11, x9, lsl #32 //CTR block 2
+ ld1 {v21.4s}, [x8], #16 //load rk3
+
+ fmov v2.d[1], x9 //CTR block 2
+ rev w9, w12 //CTR block 3
+
+ aese v0.16b, v19.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 1
+ orr x9, x11, x9, lsl #32 //CTR block 3
+
+ fmov v3.d[1], x9 //CTR block 3
+
+ aese v1.16b, v18.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 0
+ ld1 {v22.4s}, [x8], #16 //load rk4
+
+ aese v0.16b, v20.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 2
+ ld1 {v23.4s}, [x8], #16 //load rk5
+
+ aese v2.16b, v18.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 0
+ ld1 {v24.4s}, [x8], #16 //load rk6
+
+ aese v1.16b, v19.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 1
+ ldr q14, [x3, #80] //load h3l | h3h
+#ifndef __AARCH64EB__
+ ext v14.16b, v14.16b, v14.16b, #8
+#endif
+ aese v3.16b, v18.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 0
+ ld1 {v25.4s}, [x8], #16 //load rk7
+
+ aese v2.16b, v19.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 1
+ ld1 {v26.4s}, [x8], #16 //load rk8
+
+ aese v1.16b, v20.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 2
+ ldr q13, [x3, #64] //load h2l | h2h
+#ifndef __AARCH64EB__
+ ext v13.16b, v13.16b, v13.16b, #8
+#endif
+ aese v3.16b, v19.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 1
+ ld1 {v27.4s}, [x8], #16 //load rk9
+
+ aese v2.16b, v20.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 2
+ ldr q15, [x3, #112] //load h4l | h4h
+#ifndef __AARCH64EB__
+ ext v15.16b, v15.16b, v15.16b, #8
+#endif
+ aese v1.16b, v21.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 3
+ ld1 {v28.4s}, [x8], #16 //load rk10
+
+ aese v3.16b, v20.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 2
+ ld1 {v29.4s}, [x8], #16 //load rk11
+
+ aese v2.16b, v21.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 3
+ add w12, w12, #1 //CTR block 3
+
+ aese v0.16b, v21.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 3
+
+ aese v3.16b, v21.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 3
+ ld1 { v11.16b}, [x3]
+ ext v11.16b, v11.16b, v11.16b, #8
+ rev64 v11.16b, v11.16b
+
+ aese v2.16b, v22.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 4
+
+ aese v0.16b, v22.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 4
+
+ aese v1.16b, v22.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 4
+
+ aese v3.16b, v22.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 4
+
+ aese v0.16b, v23.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 5
+
+ aese v1.16b, v23.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 5
+
+ aese v3.16b, v23.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 5
+
+ aese v2.16b, v23.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 5
+
+ aese v1.16b, v24.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 6
+ trn2 v17.2d, v14.2d, v15.2d //h4l | h3l
+
+ aese v3.16b, v24.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 6
+ ld1 {v30.4s}, [x8], #16 //load rk12
+
+ aese v0.16b, v24.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 6
+ ldr q12, [x3, #32] //load h1l | h1h
+#ifndef __AARCH64EB__
+ ext v12.16b, v12.16b, v12.16b, #8
+#endif
+ aese v2.16b, v24.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 6
+ ld1 {v31.4s}, [x8], #16 //load rk13
+
+ aese v1.16b, v25.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 7
+ trn1 v9.2d, v14.2d, v15.2d //h4h | h3h
+
+ aese v0.16b, v25.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 7
+
+ aese v2.16b, v25.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 7
+
+ aese v3.16b, v25.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 7
+ trn2 v16.2d, v12.2d, v13.2d //h2l | h1l
+
+ aese v1.16b, v26.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 8
+
+ aese v2.16b, v26.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 8
+
+ aese v3.16b, v26.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 8
+
+ aese v1.16b, v27.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 9
+
+ aese v2.16b, v27.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 9
+
+ aese v0.16b, v26.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 8
+
+ aese v1.16b, v28.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 10
+
+ aese v3.16b, v27.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 9
+
+ aese v0.16b, v27.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 9
+
+ aese v2.16b, v28.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 10
+
+ aese v3.16b, v28.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 10
+
+ aese v1.16b, v29.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 11
+
+ aese v2.16b, v29.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 11
+
+ aese v0.16b, v28.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 10
+
+ aese v1.16b, v30.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 12
+
+ aese v2.16b, v30.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 12
+
+ aese v0.16b, v29.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 11
+ eor v17.16b, v17.16b, v9.16b //h4k | h3k
+
+ aese v3.16b, v29.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 11
+
+ aese v2.16b, v31.16b //AES block 2 - round 13
+ trn1 v8.2d, v12.2d, v13.2d //h2h | h1h
+
+ aese v0.16b, v30.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 12
+
+ aese v3.16b, v30.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 12
+
+ aese v1.16b, v31.16b //AES block 1 - round 13
+
+ aese v0.16b, v31.16b //AES block 0 - round 13
+
+ aese v3.16b, v31.16b //AES block 3 - round 13
+ eor v16.16b, v16.16b, v8.16b //h2k | h1k
+ b.ge .L256_enc_tail //handle tail
+
+ ldp x19, x20, [x0, #16] //AES block 1 - load plaintext
+#ifdef __AARCH64EB__
+ rev x19, x19
+ rev x20, x20
+#endif
+ rev w9, w12 //CTR block 4
+ ldp x6, x7, [x0, #0] //AES block 0 - load plaintext
+#ifdef __AARCH64EB__
+ rev x6, x6
+ rev x7, x7
+#endif
+ ldp x23, x24, [x0, #48] //AES block 3 - load plaintext
+#ifdef __AARCH64EB__
+ rev x23, x23
+ rev x24, x24
+#endif
+ ldp x21, x22, [x0, #32] //AES block 2 - load plaintext
+#ifdef __AARCH64EB__
+ rev x21, x21
+ rev x22, x22
+#endif
+ add x0, x0, #64 //AES input_ptr update
+
+ eor x19, x19, x13 //AES block 1 - round 14 low
+ eor x20, x20, x14 //AES block 1 - round 14 high
+
+ fmov d5, x19 //AES block 1 - mov low
+ eor x6, x6, x13 //AES block 0 - round 14 low
+
+ eor x7, x7, x14 //AES block 0 - round 14 high
+ eor x24, x24, x14 //AES block 3 - round 14 high
+ fmov d4, x6 //AES block 0 - mov low
+
+ cmp x0, x5 //check if we have <= 8 blocks
+ fmov v4.d[1], x7 //AES block 0 - mov high
+ eor x23, x23, x13 //AES block 3 - round 14 low
+
+ eor x21, x21, x13 //AES block 2 - round 14 low
+ fmov v5.d[1], x20 //AES block 1 - mov high
+
+ fmov d6, x21 //AES block 2 - mov low
+ add w12, w12, #1 //CTR block 4
+
+ orr x9, x11, x9, lsl #32 //CTR block 4
+ fmov d7, x23 //AES block 3 - mov low
+ eor x22, x22, x14 //AES block 2 - round 14 high
+
+ fmov v6.d[1], x22 //AES block 2 - mov high
+
+ eor v4.16b, v4.16b, v0.16b //AES block 0 - result
+ fmov d0, x10 //CTR block 4
+
+ fmov v0.d[1], x9 //CTR block 4
+ rev w9, w12 //CTR block 5
+ add w12, w12, #1 //CTR block 5
+
+ eor v5.16b, v5.16b, v1.16b //AES block 1 - result
+ fmov d1, x10 //CTR block 5
+ orr x9, x11, x9, lsl #32 //CTR block 5
+
+ fmov v1.d[1], x9 //CTR block 5
+ rev w9, w12 //CTR block 6
+ st1 { v4.16b}, [x2], #16 //AES block 0 - store result
+
+ fmov v7.d[1], x24 //AES block 3 - mov high
+ orr x9, x11, x9, lsl #32 //CTR block 6
+ eor v6.16b, v6.16b, v2.16b //AES block 2 - result
+
+ st1 { v5.16b}, [x2], #16 //AES block 1 - store result
+
+ add w12, w12, #1 //CTR block 6
+ fmov d2, x10 //CTR block 6
+
+ fmov v2.d[1], x9 //CTR block 6
+ st1 { v6.16b}, [x2], #16 //AES block 2 - store result
+ rev w9, w12 //CTR block 7
+
+ orr x9, x11, x9, lsl #32 //CTR block 7
+
+ eor v7.16b, v7.16b, v3.16b //AES block 3 - result
+ st1 { v7.16b}, [x2], #16 //AES block 3 - store result
+ b.ge .L256_enc_prepretail //do prepretail
+
+.L256_enc_main_loop: //main loop start
+ aese v0.16b, v18.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 0
+ rev64 v4.16b, v4.16b //GHASH block 4k (only t0 is free)
+
+ aese v1.16b, v18.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 0
+ fmov d3, x10 //CTR block 4k+3
+
+ aese v2.16b, v18.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 0
+ ext v11.16b, v11.16b, v11.16b, #8 //PRE 0
+
+ aese v0.16b, v19.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 1
+ fmov v3.d[1], x9 //CTR block 4k+3
+
+ aese v1.16b, v19.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 1
+ ldp x23, x24, [x0, #48] //AES block 4k+7 - load plaintext
+#ifdef __AARCH64EB__
+ rev x23, x23
+ rev x24, x24
+#endif
+ aese v2.16b, v19.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 1
+ ldp x21, x22, [x0, #32] //AES block 4k+6 - load plaintext
+#ifdef __AARCH64EB__
+ rev x21, x21
+ rev x22, x22
+#endif
+ aese v0.16b, v20.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 2
+ eor v4.16b, v4.16b, v11.16b //PRE 1
+
+ aese v1.16b, v20.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 2
+
+ aese v3.16b, v18.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 0
+ eor x23, x23, x13 //AES block 4k+7 - round 14 low
+
+ aese v0.16b, v21.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 3
+ mov d10, v17.d[1] //GHASH block 4k - mid
+
+ pmull2 v9.1q, v4.2d, v15.2d //GHASH block 4k - high
+ eor x22, x22, x14 //AES block 4k+6 - round 14 high
+ mov d8, v4.d[1] //GHASH block 4k - mid
+
+ aese v3.16b, v19.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 1
+ rev64 v5.16b, v5.16b //GHASH block 4k+1 (t0 and t1 free)
+
+ aese v0.16b, v22.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 4
+
+ pmull v11.1q, v4.1d, v15.1d //GHASH block 4k - low
+ eor v8.8b, v8.8b, v4.8b //GHASH block 4k - mid
+
+ aese v2.16b, v20.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 2
+
+ aese v0.16b, v23.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 5
+ rev64 v7.16b, v7.16b //GHASH block 4k+3 (t0, t1, t2 and t3 free)
+
+ pmull2 v4.1q, v5.2d, v14.2d //GHASH block 4k+1 - high
+
+ pmull v10.1q, v8.1d, v10.1d //GHASH block 4k - mid
+ rev64 v6.16b, v6.16b //GHASH block 4k+2 (t0, t1, and t2 free)
+
+ pmull v8.1q, v5.1d, v14.1d //GHASH block 4k+1 - low
+
+ eor v9.16b, v9.16b, v4.16b //GHASH block 4k+1 - high
+ mov d4, v5.d[1] //GHASH block 4k+1 - mid
+
+ aese v1.16b, v21.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 3
+
+ aese v3.16b, v20.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 2
+ eor v11.16b, v11.16b, v8.16b //GHASH block 4k+1 - low
+
+ aese v2.16b, v21.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 3
+
+ aese v1.16b, v22.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 4
+ mov d8, v6.d[1] //GHASH block 4k+2 - mid
+
+ aese v3.16b, v21.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 3
+ eor v4.8b, v4.8b, v5.8b //GHASH block 4k+1 - mid
+
+ aese v2.16b, v22.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 4
+
+ aese v0.16b, v24.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 6
+ eor v8.8b, v8.8b, v6.8b //GHASH block 4k+2 - mid
+
+ aese v3.16b, v22.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 4
+
+ pmull v4.1q, v4.1d, v17.1d //GHASH block 4k+1 - mid
+
+ aese v0.16b, v25.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 7
+
+ aese v3.16b, v23.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 5
+ ins v8.d[1], v8.d[0] //GHASH block 4k+2 - mid
+
+ aese v1.16b, v23.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 5
+
+ aese v0.16b, v26.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 8
+
+ aese v2.16b, v23.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 5
+
+ aese v1.16b, v24.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 6
+ eor v10.16b, v10.16b, v4.16b //GHASH block 4k+1 - mid
+
+ pmull2 v4.1q, v6.2d, v13.2d //GHASH block 4k+2 - high
+
+ pmull v5.1q, v6.1d, v13.1d //GHASH block 4k+2 - low
+
+ aese v1.16b, v25.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 7
+
+ pmull v6.1q, v7.1d, v12.1d //GHASH block 4k+3 - low
+ eor v9.16b, v9.16b, v4.16b //GHASH block 4k+2 - high
+
+ aese v3.16b, v24.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 6
+ ldp x19, x20, [x0, #16] //AES block 4k+5 - load plaintext
+#ifdef __AARCH64EB__
+ rev x19, x19
+ rev x20, x20
+#endif
+ aese v1.16b, v26.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 8
+ mov d4, v7.d[1] //GHASH block 4k+3 - mid
+
+ aese v2.16b, v24.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 6
+ eor v11.16b, v11.16b, v5.16b //GHASH block 4k+2 - low
+
+ pmull2 v8.1q, v8.2d, v16.2d //GHASH block 4k+2 - mid
+
+ pmull2 v5.1q, v7.2d, v12.2d //GHASH block 4k+3 - high
+ eor v4.8b, v4.8b, v7.8b //GHASH block 4k+3 - mid
+
+ aese v2.16b, v25.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 7
+ eor x19, x19, x13 //AES block 4k+5 - round 14 low
+
+ aese v1.16b, v27.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 9
+ eor v10.16b, v10.16b, v8.16b //GHASH block 4k+2 - mid
+
+ aese v3.16b, v25.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 7
+ eor x21, x21, x13 //AES block 4k+6 - round 14 low
+
+ aese v0.16b, v27.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 9
+ movi v8.8b, #0xc2
+
+ pmull v4.1q, v4.1d, v16.1d //GHASH block 4k+3 - mid
+ eor v9.16b, v9.16b, v5.16b //GHASH block 4k+3 - high
+ fmov d5, x19 //AES block 4k+5 - mov low
+
+ aese v2.16b, v26.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 8
+ ldp x6, x7, [x0, #0] //AES block 4k+4 - load plaintext
+#ifdef __AARCH64EB__
+ rev x6, x6
+ rev x7, x7
+#endif
+ aese v0.16b, v28.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 10
+ shl d8, d8, #56 //mod_constant
+
+ aese v3.16b, v26.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 8
+ eor v11.16b, v11.16b, v6.16b //GHASH block 4k+3 - low
+
+ aese v2.16b, v27.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 9
+
+ aese v1.16b, v28.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 10
+ eor v10.16b, v10.16b, v4.16b //GHASH block 4k+3 - mid
+
+ aese v3.16b, v27.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 9
+ add w12, w12, #1 //CTR block 4k+3
+
+ aese v0.16b, v29.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 11
+ eor v4.16b, v11.16b, v9.16b //MODULO - karatsuba tidy up
+
+ aese v1.16b, v29.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 11
+ add x0, x0, #64 //AES input_ptr update
+
+ pmull v7.1q, v9.1d, v8.1d //MODULO - top 64b align with mid
+ rev w9, w12 //CTR block 4k+8
+ ext v9.16b, v9.16b, v9.16b, #8 //MODULO - other top alignment
+
+ aese v2.16b, v28.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 10
+ eor x6, x6, x13 //AES block 4k+4 - round 14 low
+
+ aese v1.16b, v30.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 12
+ eor v10.16b, v10.16b, v4.16b //MODULO - karatsuba tidy up
+
+ aese v3.16b, v28.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 10
+ eor x7, x7, x14 //AES block 4k+4 - round 14 high
+
+ fmov d4, x6 //AES block 4k+4 - mov low
+ orr x9, x11, x9, lsl #32 //CTR block 4k+8
+ eor v7.16b, v9.16b, v7.16b //MODULO - fold into mid
+
+ aese v0.16b, v30.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 12
+ eor x20, x20, x14 //AES block 4k+5 - round 14 high
+
+ aese v2.16b, v29.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 11
+ eor x24, x24, x14 //AES block 4k+7 - round 14 high
+
+ aese v3.16b, v29.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 11
+ add w12, w12, #1 //CTR block 4k+8
+
+ aese v0.16b, v31.16b //AES block 4k+4 - round 13
+ fmov v4.d[1], x7 //AES block 4k+4 - mov high
+ eor v10.16b, v10.16b, v7.16b //MODULO - fold into mid
+
+ aese v2.16b, v30.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 12
+ fmov d7, x23 //AES block 4k+7 - mov low
+
+ aese v1.16b, v31.16b //AES block 4k+5 - round 13
+ fmov v5.d[1], x20 //AES block 4k+5 - mov high
+
+ fmov d6, x21 //AES block 4k+6 - mov low
+ cmp x0, x5 //.LOOP CONTROL
+
+ fmov v6.d[1], x22 //AES block 4k+6 - mov high
+
+ pmull v9.1q, v10.1d, v8.1d //MODULO - mid 64b align with low
+ eor v4.16b, v4.16b, v0.16b //AES block 4k+4 - result
+ fmov d0, x10 //CTR block 4k+8
+
+ fmov v0.d[1], x9 //CTR block 4k+8
+ rev w9, w12 //CTR block 4k+9
+ add w12, w12, #1 //CTR block 4k+9
+
+ eor v5.16b, v5.16b, v1.16b //AES block 4k+5 - result
+ fmov d1, x10 //CTR block 4k+9
+ orr x9, x11, x9, lsl #32 //CTR block 4k+9
+
+ aese v3.16b, v30.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 12
+ fmov v1.d[1], x9 //CTR block 4k+9
+
+ aese v2.16b, v31.16b //AES block 4k+6 - round 13
+ rev w9, w12 //CTR block 4k+10
+ st1 { v4.16b}, [x2], #16 //AES block 4k+4 - store result
+
+ orr x9, x11, x9, lsl #32 //CTR block 4k+10
+ eor v11.16b, v11.16b, v9.16b //MODULO - fold into low
+ fmov v7.d[1], x24 //AES block 4k+7 - mov high
+
+ ext v10.16b, v10.16b, v10.16b, #8 //MODULO - other mid alignment
+ st1 { v5.16b}, [x2], #16 //AES block 4k+5 - store result
+ add w12, w12, #1 //CTR block 4k+10
+
+ aese v3.16b, v31.16b //AES block 4k+7 - round 13
+ eor v6.16b, v6.16b, v2.16b //AES block 4k+6 - result
+ fmov d2, x10 //CTR block 4k+10
+
+ st1 { v6.16b}, [x2], #16 //AES block 4k+6 - store result
+ fmov v2.d[1], x9 //CTR block 4k+10
+ rev w9, w12 //CTR block 4k+11
+
+ eor v11.16b, v11.16b, v10.16b //MODULO - fold into low
+ orr x9, x11, x9, lsl #32 //CTR block 4k+11
+
+ eor v7.16b, v7.16b, v3.16b //AES block 4k+7 - result
+ st1 { v7.16b}, [x2], #16 //AES block 4k+7 - store result
+ b.lt .L256_enc_main_loop
+
+.L256_enc_prepretail: //PREPRETAIL
+ aese v1.16b, v18.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 0
+ rev64 v6.16b, v6.16b //GHASH block 4k+2 (t0, t1, and t2 free)
+
+ aese v2.16b, v18.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 0
+ fmov d3, x10 //CTR block 4k+3
+
+ aese v0.16b, v18.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 0
+ rev64 v4.16b, v4.16b //GHASH block 4k (only t0 is free)
+
+ fmov v3.d[1], x9 //CTR block 4k+3
+ ext v11.16b, v11.16b, v11.16b, #8 //PRE 0
+
+ aese v2.16b, v19.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 1
+
+ aese v0.16b, v19.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 1
+
+ eor v4.16b, v4.16b, v11.16b //PRE 1
+ rev64 v5.16b, v5.16b //GHASH block 4k+1 (t0 and t1 free)
+
+ aese v2.16b, v20.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 2
+
+ aese v3.16b, v18.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 0
+ mov d10, v17.d[1] //GHASH block 4k - mid
+
+ aese v1.16b, v19.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 1
+
+ pmull v11.1q, v4.1d, v15.1d //GHASH block 4k - low
+ mov d8, v4.d[1] //GHASH block 4k - mid
+
+ pmull2 v9.1q, v4.2d, v15.2d //GHASH block 4k - high
+
+ aese v2.16b, v21.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 3
+
+ aese v1.16b, v20.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 2
+ eor v8.8b, v8.8b, v4.8b //GHASH block 4k - mid
+
+ aese v0.16b, v20.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 2
+
+ aese v3.16b, v19.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 1
+
+ aese v1.16b, v21.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 3
+
+ pmull v10.1q, v8.1d, v10.1d //GHASH block 4k - mid
+
+ pmull2 v4.1q, v5.2d, v14.2d //GHASH block 4k+1 - high
+
+ pmull v8.1q, v5.1d, v14.1d //GHASH block 4k+1 - low
+
+ aese v3.16b, v20.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 2
+
+ eor v9.16b, v9.16b, v4.16b //GHASH block 4k+1 - high
+ mov d4, v5.d[1] //GHASH block 4k+1 - mid
+
+ aese v0.16b, v21.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 3
+ eor v11.16b, v11.16b, v8.16b //GHASH block 4k+1 - low
+
+ aese v3.16b, v21.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 3
+
+ eor v4.8b, v4.8b, v5.8b //GHASH block 4k+1 - mid
+ mov d8, v6.d[1] //GHASH block 4k+2 - mid
+
+ aese v0.16b, v22.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 4
+ rev64 v7.16b, v7.16b //GHASH block 4k+3 (t0, t1, t2 and t3 free)
+
+ aese v3.16b, v22.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 4
+
+ pmull v4.1q, v4.1d, v17.1d //GHASH block 4k+1 - mid
+ eor v8.8b, v8.8b, v6.8b //GHASH block 4k+2 - mid
+ add w12, w12, #1 //CTR block 4k+3
+
+ pmull v5.1q, v6.1d, v13.1d //GHASH block 4k+2 - low
+
+ aese v3.16b, v23.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 5
+
+ aese v2.16b, v22.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 4
+ eor v10.16b, v10.16b, v4.16b //GHASH block 4k+1 - mid
+
+ pmull2 v4.1q, v6.2d, v13.2d //GHASH block 4k+2 - high
+
+ eor v11.16b, v11.16b, v5.16b //GHASH block 4k+2 - low
+ ins v8.d[1], v8.d[0] //GHASH block 4k+2 - mid
+
+ aese v2.16b, v23.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 5
+
+ eor v9.16b, v9.16b, v4.16b //GHASH block 4k+2 - high
+ mov d4, v7.d[1] //GHASH block 4k+3 - mid
+
+ aese v1.16b, v22.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 4
+
+ pmull2 v8.1q, v8.2d, v16.2d //GHASH block 4k+2 - mid
+
+ eor v4.8b, v4.8b, v7.8b //GHASH block 4k+3 - mid
+
+ pmull2 v5.1q, v7.2d, v12.2d //GHASH block 4k+3 - high
+
+ aese v1.16b, v23.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 5
+
+ pmull v4.1q, v4.1d, v16.1d //GHASH block 4k+3 - mid
+ eor v10.16b, v10.16b, v8.16b //GHASH block 4k+2 - mid
+
+ aese v0.16b, v23.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 5
+
+ aese v1.16b, v24.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 6
+
+ aese v2.16b, v24.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 6
+
+ aese v0.16b, v24.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 6
+ movi v8.8b, #0xc2
+
+ aese v3.16b, v24.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 6
+
+ aese v1.16b, v25.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 7
+ eor v9.16b, v9.16b, v5.16b //GHASH block 4k+3 - high
+
+ aese v0.16b, v25.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 7
+
+ aese v3.16b, v25.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 7
+ shl d8, d8, #56 //mod_constant
+
+ aese v1.16b, v26.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 8
+ eor v10.16b, v10.16b, v4.16b //GHASH block 4k+3 - mid
+
+ pmull v6.1q, v7.1d, v12.1d //GHASH block 4k+3 - low
+
+ aese v3.16b, v26.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 8
+
+ aese v1.16b, v27.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 9
+
+ aese v0.16b, v26.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 8
+ eor v11.16b, v11.16b, v6.16b //GHASH block 4k+3 - low
+
+ aese v3.16b, v27.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 9
+
+ eor v10.16b, v10.16b, v9.16b //karatsuba tidy up
+
+ pmull v4.1q, v9.1d, v8.1d
+ ext v9.16b, v9.16b, v9.16b, #8
+
+ aese v3.16b, v28.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 10
+
+ aese v2.16b, v25.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 7
+ eor v10.16b, v10.16b, v11.16b
+
+ aese v1.16b, v28.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 10
+
+ aese v0.16b, v27.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 9
+
+ aese v2.16b, v26.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 8
+
+ aese v1.16b, v29.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 11
+ eor v10.16b, v10.16b, v4.16b
+
+ aese v0.16b, v28.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 10
+
+ aese v2.16b, v27.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 9
+
+ aese v1.16b, v30.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 12
+
+ aese v0.16b, v29.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 11
+ eor v10.16b, v10.16b, v9.16b
+
+ aese v3.16b, v29.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 11
+
+ aese v2.16b, v28.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 10
+
+ aese v0.16b, v30.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 12
+
+ pmull v4.1q, v10.1d, v8.1d
+
+ aese v2.16b, v29.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 11
+ ext v10.16b, v10.16b, v10.16b, #8
+
+ aese v3.16b, v30.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 12
+
+ aese v1.16b, v31.16b //AES block 4k+5 - round 13
+ eor v11.16b, v11.16b, v4.16b
+
+ aese v2.16b, v30.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 12
+
+ aese v3.16b, v31.16b //AES block 4k+7 - round 13
+
+ aese v0.16b, v31.16b //AES block 4k+4 - round 13
+
+ aese v2.16b, v31.16b //AES block 4k+6 - round 13
+ eor v11.16b, v11.16b, v10.16b
+.L256_enc_tail: //TAIL
+
+ ext v8.16b, v11.16b, v11.16b, #8 //prepare final partial tag
+ sub x5, x4, x0 //main_end_input_ptr is number of bytes left to process
+ ldp x6, x7, [x0], #16 //AES block 4k+4 - load plaintext
+#ifdef __AARCH64EB__
+ rev x6, x6
+ rev x7, x7
+#endif
+ eor x6, x6, x13 //AES block 4k+4 - round 14 low
+ eor x7, x7, x14 //AES block 4k+4 - round 14 high
+
+ cmp x5, #48
+ fmov d4, x6 //AES block 4k+4 - mov low
+
+ fmov v4.d[1], x7 //AES block 4k+4 - mov high
+
+ eor v5.16b, v4.16b, v0.16b //AES block 4k+4 - result
+ b.gt .L256_enc_blocks_more_than_3
+
+ cmp x5, #32
+ mov v3.16b, v2.16b
+ movi v11.8b, #0
+
+ movi v9.8b, #0
+ sub w12, w12, #1
+
+ mov v2.16b, v1.16b
+ movi v10.8b, #0
+ b.gt .L256_enc_blocks_more_than_2
+
+ mov v3.16b, v1.16b
+ sub w12, w12, #1
+ cmp x5, #16
+
+ b.gt .L256_enc_blocks_more_than_1
+
+ sub w12, w12, #1
+ b .L256_enc_blocks_less_than_1
+.L256_enc_blocks_more_than_3: //blocks left > 3
+ st1 { v5.16b}, [x2], #16 //AES final-3 block - store result
+
+ ldp x6, x7, [x0], #16 //AES final-2 block - load input low & high
+#ifdef __AARCH64EB__
+ rev x6, x6
+ rev x7, x7
+#endif
+ rev64 v4.16b, v5.16b //GHASH final-3 block
+
+ eor x6, x6, x13 //AES final-2 block - round 14 low
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+
+ eor x7, x7, x14 //AES final-2 block - round 14 high
+
+ mov d22, v4.d[1] //GHASH final-3 block - mid
+ fmov d5, x6 //AES final-2 block - mov low
+
+ fmov v5.d[1], x7 //AES final-2 block - mov high
+
+ eor v22.8b, v22.8b, v4.8b //GHASH final-3 block - mid
+ movi v8.8b, #0 //suppress further partial tag feed in
+
+ mov d10, v17.d[1] //GHASH final-3 block - mid
+
+ pmull v11.1q, v4.1d, v15.1d //GHASH final-3 block - low
+
+ pmull2 v9.1q, v4.2d, v15.2d //GHASH final-3 block - high
+
+ pmull v10.1q, v22.1d, v10.1d //GHASH final-3 block - mid
+ eor v5.16b, v5.16b, v1.16b //AES final-2 block - result
+.L256_enc_blocks_more_than_2: //blocks left > 2
+
+ st1 { v5.16b}, [x2], #16 //AES final-2 block - store result
+
+ ldp x6, x7, [x0], #16 //AES final-1 block - load input low & high
+#ifdef __AARCH64EB__
+ rev x6, x6
+ rev x7, x7
+#endif
+ rev64 v4.16b, v5.16b //GHASH final-2 block
+
+ eor x6, x6, x13 //AES final-1 block - round 14 low
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+
+ fmov d5, x6 //AES final-1 block - mov low
+ eor x7, x7, x14 //AES final-1 block - round 14 high
+
+ fmov v5.d[1], x7 //AES final-1 block - mov high
+
+ movi v8.8b, #0 //suppress further partial tag feed in
+
+ pmull2 v20.1q, v4.2d, v14.2d //GHASH final-2 block - high
+ mov d22, v4.d[1] //GHASH final-2 block - mid
+
+ pmull v21.1q, v4.1d, v14.1d //GHASH final-2 block - low
+
+ eor v22.8b, v22.8b, v4.8b //GHASH final-2 block - mid
+
+ eor v5.16b, v5.16b, v2.16b //AES final-1 block - result
+
+ eor v9.16b, v9.16b, v20.16b //GHASH final-2 block - high
+
+ pmull v22.1q, v22.1d, v17.1d //GHASH final-2 block - mid
+
+ eor v11.16b, v11.16b, v21.16b //GHASH final-2 block - low
+
+ eor v10.16b, v10.16b, v22.16b //GHASH final-2 block - mid
+.L256_enc_blocks_more_than_1: //blocks left > 1
+
+ st1 { v5.16b}, [x2], #16 //AES final-1 block - store result
+
+ rev64 v4.16b, v5.16b //GHASH final-1 block
+
+ ldp x6, x7, [x0], #16 //AES final block - load input low & high
+#ifdef __AARCH64EB__
+ rev x6, x6
+ rev x7, x7
+#endif
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+
+ movi v8.8b, #0 //suppress further partial tag feed in
+
+ eor x6, x6, x13 //AES final block - round 14 low
+ mov d22, v4.d[1] //GHASH final-1 block - mid
+
+ pmull2 v20.1q, v4.2d, v13.2d //GHASH final-1 block - high
+ eor x7, x7, x14 //AES final block - round 14 high
+
+ eor v22.8b, v22.8b, v4.8b //GHASH final-1 block - mid
+
+ eor v9.16b, v9.16b, v20.16b //GHASH final-1 block - high
+
+ ins v22.d[1], v22.d[0] //GHASH final-1 block - mid
+ fmov d5, x6 //AES final block - mov low
+
+ fmov v5.d[1], x7 //AES final block - mov high
+
+ pmull2 v22.1q, v22.2d, v16.2d //GHASH final-1 block - mid
+
+ pmull v21.1q, v4.1d, v13.1d //GHASH final-1 block - low
+
+ eor v5.16b, v5.16b, v3.16b //AES final block - result
+ eor v10.16b, v10.16b, v22.16b //GHASH final-1 block - mid
+
+ eor v11.16b, v11.16b, v21.16b //GHASH final-1 block - low
+.L256_enc_blocks_less_than_1: //blocks left <= 1
+
+ and x1, x1, #127 //bit_length %= 128
+
+ mvn x13, xzr //rk14_l = 0xffffffffffffffff
+ sub x1, x1, #128 //bit_length -= 128
+
+ neg x1, x1 //bit_length = 128 - #bits in input (in range [1,128])
+ ld1 { v18.16b}, [x2] //load existing bytes where the possibly partial last block is to be stored
+
+ mvn x14, xzr //rk14_h = 0xffffffffffffffff
+ and x1, x1, #127 //bit_length %= 128
+
+ lsr x14, x14, x1 //rk14_h is mask for top 64b of last block
+ cmp x1, #64
+
+ csel x6, x13, x14, lt
+ csel x7, x14, xzr, lt
+
+ fmov d0, x6 //ctr0b is mask for last block
+
+ fmov v0.d[1], x7
+
+ and v5.16b, v5.16b, v0.16b //possibly partial last block has zeroes in highest bits
+
+ rev64 v4.16b, v5.16b //GHASH final block
+
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+
+ bif v5.16b, v18.16b, v0.16b //insert existing bytes in top end of result before storing
+
+ pmull2 v20.1q, v4.2d, v12.2d //GHASH final block - high
+ mov d8, v4.d[1] //GHASH final block - mid
+#ifndef __AARCH64EB__
+ rev w9, w12
+#else
+ mov w9, w12
+#endif
+
+ pmull v21.1q, v4.1d, v12.1d //GHASH final block - low
+
+ eor v9.16b, v9.16b, v20.16b //GHASH final block - high
+ eor v8.8b, v8.8b, v4.8b //GHASH final block - mid
+
+ pmull v8.1q, v8.1d, v16.1d //GHASH final block - mid
+
+ eor v11.16b, v11.16b, v21.16b //GHASH final block - low
+
+ eor v10.16b, v10.16b, v8.16b //GHASH final block - mid
+ movi v8.8b, #0xc2
+
+ eor v4.16b, v11.16b, v9.16b //MODULO - karatsuba tidy up
+
+ shl d8, d8, #56 //mod_constant
+
+ eor v10.16b, v10.16b, v4.16b //MODULO - karatsuba tidy up
+
+ pmull v7.1q, v9.1d, v8.1d //MODULO - top 64b align with mid
+
+ ext v9.16b, v9.16b, v9.16b, #8 //MODULO - other top alignment
+
+ eor v10.16b, v10.16b, v7.16b //MODULO - fold into mid
+
+ eor v10.16b, v10.16b, v9.16b //MODULO - fold into mid
+
+ pmull v9.1q, v10.1d, v8.1d //MODULO - mid 64b align with low
+
+ ext v10.16b, v10.16b, v10.16b, #8 //MODULO - other mid alignment
+
+ str w9, [x16, #12] //store the updated counter
+
+ st1 { v5.16b}, [x2] //store all 16B
+ eor v11.16b, v11.16b, v9.16b //MODULO - fold into low
+
+ eor v11.16b, v11.16b, v10.16b //MODULO - fold into low
+ ext v11.16b, v11.16b, v11.16b, #8
+ rev64 v11.16b, v11.16b
+ mov x0, x15
+ st1 { v11.16b }, [x3]
+
+ ldp x21, x22, [sp, #16]
+ ldp x23, x24, [sp, #32]
+ ldp d8, d9, [sp, #48]
+ ldp d10, d11, [sp, #64]
+ ldp d12, d13, [sp, #80]
+ ldp d14, d15, [sp, #96]
+ ldp x19, x20, [sp], #112
+ ret
+
+.L256_enc_ret:
+ mov w0, #0x0
+ ret
+.size aes_gcm_enc_256_kernel,.-aes_gcm_enc_256_kernel
+.globl aes_gcm_dec_256_kernel
+.type aes_gcm_dec_256_kernel,%function
+.align 4
+aes_gcm_dec_256_kernel:
+ cbz x1, .L256_dec_ret
+ stp x19, x20, [sp, #-112]!
+ mov x16, x4
+ mov x8, x5
+ stp x21, x22, [sp, #16]
+ stp x23, x24, [sp, #32]
+ stp d8, d9, [sp, #48]
+ stp d10, d11, [sp, #64]
+ stp d12, d13, [sp, #80]
+ stp d14, d15, [sp, #96]
+
+ lsr x5, x1, #3 //byte_len
+ mov x15, x5
+ ldp x10, x11, [x16] //ctr96_b64, ctr96_t32
+#ifdef __AARCH64EB__
+ rev x10, x10
+ rev x11, x11
+#endif
+ ldp x13, x14, [x8, #224] //load rk14
+#ifdef __AARCH64EB__
+ ror x14, x14, #32
+ ror x13, x13, #32
+#endif
+ ld1 {v18.4s}, [x8], #16 //load rk0
+ sub x5, x5, #1 //byte_len - 1
+
+ ld1 {v19.4s}, [x8], #16 //load rk1
+ and x5, x5, #0xffffffffffffffc0 //number of bytes to be processed in main loop (at least 1 byte must be handled by tail)
+
+ add x4, x0, x1, lsr #3 //end_input_ptr
+ ld1 {v20.4s}, [x8], #16 //load rk2
+
+ lsr x12, x11, #32
+ ld1 {v21.4s}, [x8], #16 //load rk3
+ orr w11, w11, w11
+
+ ld1 {v22.4s}, [x8], #16 //load rk4
+ add x5, x5, x0
+ rev w12, w12 //rev_ctr32
+
+ add w12, w12, #1 //increment rev_ctr32
+ fmov d3, x10 //CTR block 3
+
+ rev w9, w12 //CTR block 1
+ add w12, w12, #1 //CTR block 1
+ fmov d1, x10 //CTR block 1
+
+ orr x9, x11, x9, lsl #32 //CTR block 1
+ ld1 { v0.16b}, [x16] //special case vector load initial counter so we can start first AES block as quickly as possible
+
+ fmov v1.d[1], x9 //CTR block 1
+ rev w9, w12 //CTR block 2
+ add w12, w12, #1 //CTR block 2
+
+ fmov d2, x10 //CTR block 2
+ orr x9, x11, x9, lsl #32 //CTR block 2
+
+ fmov v2.d[1], x9 //CTR block 2
+ rev w9, w12 //CTR block 3
+
+ orr x9, x11, x9, lsl #32 //CTR block 3
+ ld1 {v23.4s}, [x8], #16 //load rk5
+
+ fmov v3.d[1], x9 //CTR block 3
+ add w12, w12, #1 //CTR block 3
+
+ ld1 {v24.4s}, [x8], #16 //load rk6
+
+ ld1 {v25.4s}, [x8], #16 //load rk7
+
+ ld1 {v26.4s}, [x8], #16 //load rk8
+
+ aese v0.16b, v18.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 0
+ ldr q14, [x3, #80] //load h3l | h3h
+#ifndef __AARCH64EB__
+ ext v14.16b, v14.16b, v14.16b, #8
+#endif
+
+ aese v3.16b, v18.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 0
+ ldr q15, [x3, #112] //load h4l | h4h
+#ifndef __AARCH64EB__
+ ext v15.16b, v15.16b, v15.16b, #8
+#endif
+
+ aese v1.16b, v18.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 0
+ ldr q13, [x3, #64] //load h2l | h2h
+#ifndef __AARCH64EB__
+ ext v13.16b, v13.16b, v13.16b, #8
+#endif
+
+ aese v2.16b, v18.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 0
+ ld1 {v27.4s}, [x8], #16 //load rk9
+
+ aese v0.16b, v19.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 1
+
+ aese v1.16b, v19.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 1
+ ld1 { v11.16b}, [x3]
+ ext v11.16b, v11.16b, v11.16b, #8
+ rev64 v11.16b, v11.16b
+
+ aese v2.16b, v19.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 1
+ ld1 {v28.4s}, [x8], #16 //load rk10
+
+ aese v3.16b, v19.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 1
+ ld1 {v29.4s}, [x8], #16 //load rk11
+
+ aese v0.16b, v20.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 2
+ ldr q12, [x3, #32] //load h1l | h1h
+#ifndef __AARCH64EB__
+ ext v12.16b, v12.16b, v12.16b, #8
+#endif
+ aese v2.16b, v20.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 2
+ ld1 {v30.4s}, [x8], #16 //load rk12
+
+ aese v3.16b, v20.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 2
+
+ aese v0.16b, v21.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 3
+
+ aese v1.16b, v20.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 2
+
+ aese v3.16b, v21.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 3
+
+ aese v0.16b, v22.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 4
+ cmp x0, x5 //check if we have <= 4 blocks
+
+ aese v2.16b, v21.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 3
+
+ aese v1.16b, v21.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 3
+
+ aese v3.16b, v22.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 4
+
+ aese v2.16b, v22.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 4
+
+ aese v1.16b, v22.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 4
+
+ aese v3.16b, v23.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 5
+
+ aese v0.16b, v23.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 5
+
+ aese v1.16b, v23.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 5
+
+ aese v2.16b, v23.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 5
+
+ aese v0.16b, v24.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 6
+
+ aese v3.16b, v24.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 6
+
+ aese v1.16b, v24.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 6
+
+ aese v2.16b, v24.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 6
+
+ aese v0.16b, v25.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 7
+
+ aese v1.16b, v25.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 7
+
+ aese v3.16b, v25.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 7
+
+ aese v0.16b, v26.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 8
+
+ aese v2.16b, v25.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 7
+
+ aese v3.16b, v26.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 8
+
+ aese v1.16b, v26.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 8
+
+ aese v0.16b, v27.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 9
+
+ aese v2.16b, v26.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 8
+ ld1 {v31.4s}, [x8], #16 //load rk13
+
+ aese v1.16b, v27.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 9
+
+ aese v0.16b, v28.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 10
+
+ aese v3.16b, v27.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 9
+
+ aese v1.16b, v28.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 10
+
+ aese v2.16b, v27.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 9
+
+ aese v3.16b, v28.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 10
+
+ aese v0.16b, v29.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 11
+
+ aese v2.16b, v28.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 10
+
+ aese v3.16b, v29.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 11
+
+ aese v1.16b, v29.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 11
+
+ aese v2.16b, v29.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 11
+
+ trn1 v9.2d, v14.2d, v15.2d //h4h | h3h
+
+ trn2 v17.2d, v14.2d, v15.2d //h4l | h3l
+
+ trn1 v8.2d, v12.2d, v13.2d //h2h | h1h
+ trn2 v16.2d, v12.2d, v13.2d //h2l | h1l
+
+ aese v1.16b, v30.16b
+ aesmc v1.16b, v1.16b //AES block 1 - round 12
+
+ aese v0.16b, v30.16b
+ aesmc v0.16b, v0.16b //AES block 0 - round 12
+
+ aese v2.16b, v30.16b
+ aesmc v2.16b, v2.16b //AES block 2 - round 12
+
+ aese v3.16b, v30.16b
+ aesmc v3.16b, v3.16b //AES block 3 - round 12
+ eor v17.16b, v17.16b, v9.16b //h4k | h3k
+
+ aese v1.16b, v31.16b //AES block 1 - round 13
+
+ aese v2.16b, v31.16b //AES block 2 - round 13
+ eor v16.16b, v16.16b, v8.16b //h2k | h1k
+
+ aese v3.16b, v31.16b //AES block 3 - round 13
+
+ aese v0.16b, v31.16b //AES block 0 - round 13
+ b.ge .L256_dec_tail //handle tail
+
+ ld1 {v4.16b, v5.16b}, [x0], #32 //AES block 0,1 - load ciphertext
+
+ rev w9, w12 //CTR block 4
+
+ eor v0.16b, v4.16b, v0.16b //AES block 0 - result
+
+ eor v1.16b, v5.16b, v1.16b //AES block 1 - result
+ rev64 v5.16b, v5.16b //GHASH block 1
+ ld1 {v6.16b}, [x0], #16 //AES block 2 - load ciphertext
+
+ mov x7, v0.d[1] //AES block 0 - mov high
+
+ mov x6, v0.d[0] //AES block 0 - mov low
+ rev64 v4.16b, v4.16b //GHASH block 0
+ add w12, w12, #1 //CTR block 4
+
+ fmov d0, x10 //CTR block 4
+ orr x9, x11, x9, lsl #32 //CTR block 4
+
+ fmov v0.d[1], x9 //CTR block 4
+ rev w9, w12 //CTR block 5
+ add w12, w12, #1 //CTR block 5
+
+ mov x19, v1.d[0] //AES block 1 - mov low
+
+ orr x9, x11, x9, lsl #32 //CTR block 5
+ mov x20, v1.d[1] //AES block 1 - mov high
+ eor x7, x7, x14 //AES block 0 - round 14 high
+#ifdef __AARCH64EB__
+ rev x7, x7
+#endif
+ eor x6, x6, x13 //AES block 0 - round 14 low
+#ifdef __AARCH64EB__
+ rev x6, x6
+#endif
+ stp x6, x7, [x2], #16 //AES block 0 - store result
+ fmov d1, x10 //CTR block 5
+
+ ld1 {v7.16b}, [x0], #16 //AES block 3 - load ciphertext
+
+ fmov v1.d[1], x9 //CTR block 5
+ rev w9, w12 //CTR block 6
+ add w12, w12, #1 //CTR block 6
+
+ eor x19, x19, x13 //AES block 1 - round 14 low
+#ifdef __AARCH64EB__
+ rev x19, x19
+#endif
+ orr x9, x11, x9, lsl #32 //CTR block 6
+
+ eor x20, x20, x14 //AES block 1 - round 14 high
+#ifdef __AARCH64EB__
+ rev x20, x20
+#endif
+ stp x19, x20, [x2], #16 //AES block 1 - store result
+
+ eor v2.16b, v6.16b, v2.16b //AES block 2 - result
+ cmp x0, x5 //check if we have <= 8 blocks
+ b.ge .L256_dec_prepretail //do prepretail
+
+.L256_dec_main_loop: //main loop start
+ mov x21, v2.d[0] //AES block 4k+2 - mov low
+ ext v11.16b, v11.16b, v11.16b, #8 //PRE 0
+ eor v3.16b, v7.16b, v3.16b //AES block 4k+3 - result
+
+ aese v0.16b, v18.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 0
+ mov x22, v2.d[1] //AES block 4k+2 - mov high
+
+ aese v1.16b, v18.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 0
+ fmov d2, x10 //CTR block 4k+6
+
+ fmov v2.d[1], x9 //CTR block 4k+6
+ eor v4.16b, v4.16b, v11.16b //PRE 1
+ rev w9, w12 //CTR block 4k+7
+
+ aese v0.16b, v19.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 1
+ mov x24, v3.d[1] //AES block 4k+3 - mov high
+
+ aese v1.16b, v19.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 1
+ mov x23, v3.d[0] //AES block 4k+3 - mov low
+
+ pmull2 v9.1q, v4.2d, v15.2d //GHASH block 4k - high
+ mov d8, v4.d[1] //GHASH block 4k - mid
+ fmov d3, x10 //CTR block 4k+7
+
+ aese v0.16b, v20.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 2
+ orr x9, x11, x9, lsl #32 //CTR block 4k+7
+
+ aese v2.16b, v18.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 0
+ fmov v3.d[1], x9 //CTR block 4k+7
+
+ aese v1.16b, v20.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 2
+ eor v8.8b, v8.8b, v4.8b //GHASH block 4k - mid
+
+ aese v0.16b, v21.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 3
+ eor x22, x22, x14 //AES block 4k+2 - round 14 high
+#ifdef __AARCH64EB__
+ rev x22, x22
+#endif
+ aese v2.16b, v19.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 1
+ mov d10, v17.d[1] //GHASH block 4k - mid
+
+ aese v1.16b, v21.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 3
+ rev64 v6.16b, v6.16b //GHASH block 4k+2
+
+ aese v3.16b, v18.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 0
+ eor x21, x21, x13 //AES block 4k+2 - round 14 low
+#ifdef __AARCH64EB__
+ rev x21, x21
+#endif
+ aese v2.16b, v20.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 2
+ stp x21, x22, [x2], #16 //AES block 4k+2 - store result
+
+ pmull v11.1q, v4.1d, v15.1d //GHASH block 4k - low
+
+ pmull2 v4.1q, v5.2d, v14.2d //GHASH block 4k+1 - high
+
+ aese v2.16b, v21.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 3
+ rev64 v7.16b, v7.16b //GHASH block 4k+3
+
+ pmull v10.1q, v8.1d, v10.1d //GHASH block 4k - mid
+ eor x23, x23, x13 //AES block 4k+3 - round 14 low
+#ifdef __AARCH64EB__
+ rev x23, x23
+#endif
+ pmull v8.1q, v5.1d, v14.1d //GHASH block 4k+1 - low
+ eor x24, x24, x14 //AES block 4k+3 - round 14 high
+#ifdef __AARCH64EB__
+ rev x24, x24
+#endif
+ eor v9.16b, v9.16b, v4.16b //GHASH block 4k+1 - high
+
+ aese v2.16b, v22.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 4
+
+ aese v3.16b, v19.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 1
+ mov d4, v5.d[1] //GHASH block 4k+1 - mid
+
+ aese v0.16b, v22.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 4
+ eor v11.16b, v11.16b, v8.16b //GHASH block 4k+1 - low
+
+ aese v2.16b, v23.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 5
+ add w12, w12, #1 //CTR block 4k+7
+
+ aese v3.16b, v20.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 2
+ mov d8, v6.d[1] //GHASH block 4k+2 - mid
+
+ aese v1.16b, v22.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 4
+ eor v4.8b, v4.8b, v5.8b //GHASH block 4k+1 - mid
+
+ pmull v5.1q, v6.1d, v13.1d //GHASH block 4k+2 - low
+
+ aese v3.16b, v21.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 3
+ eor v8.8b, v8.8b, v6.8b //GHASH block 4k+2 - mid
+
+ aese v1.16b, v23.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 5
+
+ aese v0.16b, v23.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 5
+ eor v11.16b, v11.16b, v5.16b //GHASH block 4k+2 - low
+
+ pmull v4.1q, v4.1d, v17.1d //GHASH block 4k+1 - mid
+ rev w9, w12 //CTR block 4k+8
+
+ aese v1.16b, v24.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 6
+ ins v8.d[1], v8.d[0] //GHASH block 4k+2 - mid
+
+ aese v0.16b, v24.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 6
+ add w12, w12, #1 //CTR block 4k+8
+
+ aese v3.16b, v22.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 4
+
+ aese v1.16b, v25.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 7
+ eor v10.16b, v10.16b, v4.16b //GHASH block 4k+1 - mid
+
+ aese v0.16b, v25.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 7
+
+ pmull2 v4.1q, v6.2d, v13.2d //GHASH block 4k+2 - high
+ mov d6, v7.d[1] //GHASH block 4k+3 - mid
+
+ aese v3.16b, v23.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 5
+
+ pmull2 v8.1q, v8.2d, v16.2d //GHASH block 4k+2 - mid
+
+ aese v0.16b, v26.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 8
+ eor v9.16b, v9.16b, v4.16b //GHASH block 4k+2 - high
+
+ aese v3.16b, v24.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 6
+
+ pmull v4.1q, v7.1d, v12.1d //GHASH block 4k+3 - low
+ orr x9, x11, x9, lsl #32 //CTR block 4k+8
+ eor v10.16b, v10.16b, v8.16b //GHASH block 4k+2 - mid
+
+ pmull2 v5.1q, v7.2d, v12.2d //GHASH block 4k+3 - high
+
+ aese v0.16b, v27.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 9
+ eor v6.8b, v6.8b, v7.8b //GHASH block 4k+3 - mid
+
+ aese v1.16b, v26.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 8
+
+ aese v2.16b, v24.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 6
+ eor v9.16b, v9.16b, v5.16b //GHASH block 4k+3 - high
+
+ aese v0.16b, v28.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 10
+
+ pmull v6.1q, v6.1d, v16.1d //GHASH block 4k+3 - mid
+ movi v8.8b, #0xc2
+
+ aese v2.16b, v25.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 7
+ eor v11.16b, v11.16b, v4.16b //GHASH block 4k+3 - low
+
+ aese v0.16b, v29.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 11
+
+ aese v3.16b, v25.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 7
+ shl d8, d8, #56 //mod_constant
+
+ aese v2.16b, v26.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 8
+ eor v10.16b, v10.16b, v6.16b //GHASH block 4k+3 - mid
+
+ aese v0.16b, v30.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 12
+
+ pmull v7.1q, v9.1d, v8.1d //MODULO - top 64b align with mid
+ eor v6.16b, v11.16b, v9.16b //MODULO - karatsuba tidy up
+
+ aese v1.16b, v27.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 9
+ ld1 {v4.16b}, [x0], #16 //AES block 4k+4 - load ciphertext
+
+ aese v0.16b, v31.16b //AES block 4k+4 - round 13
+ ext v9.16b, v9.16b, v9.16b, #8 //MODULO - other top alignment
+
+ aese v1.16b, v28.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 10
+ eor v10.16b, v10.16b, v6.16b //MODULO - karatsuba tidy up
+
+ aese v2.16b, v27.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 9
+ ld1 {v5.16b}, [x0], #16 //AES block 4k+5 - load ciphertext
+
+ aese v3.16b, v26.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 8
+ eor v0.16b, v4.16b, v0.16b //AES block 4k+4 - result
+
+ aese v1.16b, v29.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 11
+ stp x23, x24, [x2], #16 //AES block 4k+3 - store result
+
+ aese v2.16b, v28.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 10
+ eor v10.16b, v10.16b, v7.16b //MODULO - fold into mid
+
+ aese v3.16b, v27.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 9
+ ld1 {v6.16b}, [x0], #16 //AES block 4k+6 - load ciphertext
+
+ aese v1.16b, v30.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 12
+ ld1 {v7.16b}, [x0], #16 //AES block 4k+7 - load ciphertext
+
+ aese v2.16b, v29.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 11
+ mov x7, v0.d[1] //AES block 4k+4 - mov high
+
+ aese v3.16b, v28.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 10
+ eor v10.16b, v10.16b, v9.16b //MODULO - fold into mid
+
+ aese v1.16b, v31.16b //AES block 4k+5 - round 13
+ mov x6, v0.d[0] //AES block 4k+4 - mov low
+
+ aese v2.16b, v30.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 12
+ fmov d0, x10 //CTR block 4k+8
+
+ aese v3.16b, v29.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 11
+ fmov v0.d[1], x9 //CTR block 4k+8
+
+ pmull v8.1q, v10.1d, v8.1d //MODULO - mid 64b align with low
+ eor v1.16b, v5.16b, v1.16b //AES block 4k+5 - result
+ rev w9, w12 //CTR block 4k+9
+
+ aese v2.16b, v31.16b //AES block 4k+6 - round 13
+ orr x9, x11, x9, lsl #32 //CTR block 4k+9
+ cmp x0, x5 //.LOOP CONTROL
+
+ add w12, w12, #1 //CTR block 4k+9
+
+ eor x6, x6, x13 //AES block 4k+4 - round 14 low
+#ifdef __AARCH64EB__
+ rev x6, x6
+#endif
+ eor x7, x7, x14 //AES block 4k+4 - round 14 high
+#ifdef __AARCH64EB__
+ rev x7, x7
+#endif
+ mov x20, v1.d[1] //AES block 4k+5 - mov high
+ eor v2.16b, v6.16b, v2.16b //AES block 4k+6 - result
+ eor v11.16b, v11.16b, v8.16b //MODULO - fold into low
+
+ aese v3.16b, v30.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 12
+ mov x19, v1.d[0] //AES block 4k+5 - mov low
+
+ fmov d1, x10 //CTR block 4k+9
+ ext v10.16b, v10.16b, v10.16b, #8 //MODULO - other mid alignment
+
+ fmov v1.d[1], x9 //CTR block 4k+9
+ rev w9, w12 //CTR block 4k+10
+ add w12, w12, #1 //CTR block 4k+10
+
+ aese v3.16b, v31.16b //AES block 4k+7 - round 13
+ orr x9, x11, x9, lsl #32 //CTR block 4k+10
+
+ rev64 v5.16b, v5.16b //GHASH block 4k+5
+ eor x20, x20, x14 //AES block 4k+5 - round 14 high
+#ifdef __AARCH64EB__
+ rev x20, x20
+#endif
+ stp x6, x7, [x2], #16 //AES block 4k+4 - store result
+
+ eor x19, x19, x13 //AES block 4k+5 - round 14 low
+#ifdef __AARCH64EB__
+ rev x19, x19
+#endif
+ stp x19, x20, [x2], #16 //AES block 4k+5 - store result
+
+ rev64 v4.16b, v4.16b //GHASH block 4k+4
+ eor v11.16b, v11.16b, v10.16b //MODULO - fold into low
+ b.lt .L256_dec_main_loop
+
+
+.L256_dec_prepretail: //PREPRETAIL
+ ext v11.16b, v11.16b, v11.16b, #8 //PRE 0
+ mov x21, v2.d[0] //AES block 4k+2 - mov low
+ eor v3.16b, v7.16b, v3.16b //AES block 4k+3 - result
+
+ aese v0.16b, v18.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 0
+ mov x22, v2.d[1] //AES block 4k+2 - mov high
+
+ aese v1.16b, v18.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 0
+ fmov d2, x10 //CTR block 4k+6
+
+ fmov v2.d[1], x9 //CTR block 4k+6
+ rev w9, w12 //CTR block 4k+7
+ eor v4.16b, v4.16b, v11.16b //PRE 1
+
+ rev64 v6.16b, v6.16b //GHASH block 4k+2
+ orr x9, x11, x9, lsl #32 //CTR block 4k+7
+ mov x23, v3.d[0] //AES block 4k+3 - mov low
+
+ aese v1.16b, v19.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 1
+ mov x24, v3.d[1] //AES block 4k+3 - mov high
+
+ pmull v11.1q, v4.1d, v15.1d //GHASH block 4k - low
+ mov d8, v4.d[1] //GHASH block 4k - mid
+ fmov d3, x10 //CTR block 4k+7
+
+ pmull2 v9.1q, v4.2d, v15.2d //GHASH block 4k - high
+ fmov v3.d[1], x9 //CTR block 4k+7
+
+ aese v2.16b, v18.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 0
+ mov d10, v17.d[1] //GHASH block 4k - mid
+
+ aese v0.16b, v19.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 1
+ eor v8.8b, v8.8b, v4.8b //GHASH block 4k - mid
+
+ pmull2 v4.1q, v5.2d, v14.2d //GHASH block 4k+1 - high
+
+ aese v2.16b, v19.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 1
+ rev64 v7.16b, v7.16b //GHASH block 4k+3
+
+ aese v3.16b, v18.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 0
+
+ pmull v10.1q, v8.1d, v10.1d //GHASH block 4k - mid
+ eor v9.16b, v9.16b, v4.16b //GHASH block 4k+1 - high
+
+ pmull v8.1q, v5.1d, v14.1d //GHASH block 4k+1 - low
+
+ aese v3.16b, v19.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 1
+ mov d4, v5.d[1] //GHASH block 4k+1 - mid
+
+ aese v0.16b, v20.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 2
+
+ aese v1.16b, v20.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 2
+ eor v11.16b, v11.16b, v8.16b //GHASH block 4k+1 - low
+
+ aese v2.16b, v20.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 2
+
+ aese v0.16b, v21.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 3
+ mov d8, v6.d[1] //GHASH block 4k+2 - mid
+
+ aese v3.16b, v20.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 2
+ eor v4.8b, v4.8b, v5.8b //GHASH block 4k+1 - mid
+
+ pmull v5.1q, v6.1d, v13.1d //GHASH block 4k+2 - low
+
+ aese v0.16b, v22.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 4
+
+ aese v3.16b, v21.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 3
+ eor v8.8b, v8.8b, v6.8b //GHASH block 4k+2 - mid
+
+ pmull v4.1q, v4.1d, v17.1d //GHASH block 4k+1 - mid
+
+ aese v0.16b, v23.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 5
+ eor v11.16b, v11.16b, v5.16b //GHASH block 4k+2 - low
+
+ aese v3.16b, v22.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 4
+
+ pmull2 v5.1q, v7.2d, v12.2d //GHASH block 4k+3 - high
+ eor v10.16b, v10.16b, v4.16b //GHASH block 4k+1 - mid
+
+ pmull2 v4.1q, v6.2d, v13.2d //GHASH block 4k+2 - high
+
+ aese v3.16b, v23.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 5
+ ins v8.d[1], v8.d[0] //GHASH block 4k+2 - mid
+
+ aese v2.16b, v21.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 3
+
+ aese v1.16b, v21.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 3
+ eor v9.16b, v9.16b, v4.16b //GHASH block 4k+2 - high
+
+ pmull v4.1q, v7.1d, v12.1d //GHASH block 4k+3 - low
+
+ aese v2.16b, v22.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 4
+ mov d6, v7.d[1] //GHASH block 4k+3 - mid
+
+ aese v1.16b, v22.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 4
+
+ pmull2 v8.1q, v8.2d, v16.2d //GHASH block 4k+2 - mid
+
+ aese v2.16b, v23.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 5
+ eor v6.8b, v6.8b, v7.8b //GHASH block 4k+3 - mid
+
+ aese v1.16b, v23.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 5
+
+ aese v3.16b, v24.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 6
+ eor v10.16b, v10.16b, v8.16b //GHASH block 4k+2 - mid
+
+ aese v2.16b, v24.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 6
+
+ aese v0.16b, v24.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 6
+ movi v8.8b, #0xc2
+
+ aese v1.16b, v24.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 6
+ eor v11.16b, v11.16b, v4.16b //GHASH block 4k+3 - low
+
+ pmull v6.1q, v6.1d, v16.1d //GHASH block 4k+3 - mid
+
+ aese v3.16b, v25.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 7
+ eor v9.16b, v9.16b, v5.16b //GHASH block 4k+3 - high
+
+ aese v1.16b, v25.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 7
+
+ aese v0.16b, v25.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 7
+ eor v10.16b, v10.16b, v6.16b //GHASH block 4k+3 - mid
+
+ aese v3.16b, v26.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 8
+
+ aese v2.16b, v25.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 7
+ eor v6.16b, v11.16b, v9.16b //MODULO - karatsuba tidy up
+
+ aese v1.16b, v26.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 8
+
+ aese v0.16b, v26.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 8
+ shl d8, d8, #56 //mod_constant
+
+ aese v2.16b, v26.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 8
+
+ aese v1.16b, v27.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 9
+ eor v10.16b, v10.16b, v6.16b //MODULO - karatsuba tidy up
+
+ pmull v7.1q, v9.1d, v8.1d //MODULO - top 64b align with mid
+
+ aese v2.16b, v27.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 9
+ ext v9.16b, v9.16b, v9.16b, #8 //MODULO - other top alignment
+
+ aese v3.16b, v27.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 9
+
+ aese v0.16b, v27.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 9
+ eor v10.16b, v10.16b, v7.16b //MODULO - fold into mid
+
+ aese v2.16b, v28.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 10
+
+ aese v3.16b, v28.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 10
+
+ aese v0.16b, v28.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 10
+ eor x22, x22, x14 //AES block 4k+2 - round 14 high
+#ifdef __AARCH64EB__
+ rev x22, x22
+#endif
+ aese v1.16b, v28.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 10
+ eor x23, x23, x13 //AES block 4k+3 - round 14 low
+#ifdef __AARCH64EB__
+ rev x23, x23
+#endif
+ aese v2.16b, v29.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 11
+ eor v10.16b, v10.16b, v9.16b //MODULO - fold into mid
+
+ aese v0.16b, v29.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 11
+ add w12, w12, #1 //CTR block 4k+7
+
+ aese v1.16b, v29.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 11
+ eor x21, x21, x13 //AES block 4k+2 - round 14 low
+#ifdef __AARCH64EB__
+ rev x21, x21
+#endif
+
+ aese v2.16b, v30.16b
+ aesmc v2.16b, v2.16b //AES block 4k+6 - round 12
+
+ pmull v8.1q, v10.1d, v8.1d //MODULO - mid 64b align with low
+ eor x24, x24, x14 //AES block 4k+3 - round 14 high
+#ifdef __AARCH64EB__
+ rev x24, x24
+#endif
+
+ aese v3.16b, v29.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 11
+ stp x21, x22, [x2], #16 //AES block 4k+2 - store result
+
+ aese v1.16b, v30.16b
+ aesmc v1.16b, v1.16b //AES block 4k+5 - round 12
+ ext v10.16b, v10.16b, v10.16b, #8 //MODULO - other mid alignment
+
+ aese v0.16b, v30.16b
+ aesmc v0.16b, v0.16b //AES block 4k+4 - round 12
+ stp x23, x24, [x2], #16 //AES block 4k+3 - store result
+
+ aese v3.16b, v30.16b
+ aesmc v3.16b, v3.16b //AES block 4k+7 - round 12
+ eor v11.16b, v11.16b, v8.16b //MODULO - fold into low
+
+ aese v1.16b, v31.16b //AES block 4k+5 - round 13
+
+ aese v0.16b, v31.16b //AES block 4k+4 - round 13
+
+ aese v3.16b, v31.16b //AES block 4k+7 - round 13
+
+ aese v2.16b, v31.16b //AES block 4k+6 - round 13
+ eor v11.16b, v11.16b, v10.16b //MODULO - fold into low
+.L256_dec_tail: //TAIL
+
+ sub x5, x4, x0 //main_end_input_ptr is number of bytes left to process
+ ld1 { v5.16b}, [x0], #16 //AES block 4k+4 - load ciphertext
+
+ eor v0.16b, v5.16b, v0.16b //AES block 4k+4 - result
+
+ mov x6, v0.d[0] //AES block 4k+4 - mov low
+
+ mov x7, v0.d[1] //AES block 4k+4 - mov high
+ ext v8.16b, v11.16b, v11.16b, #8 //prepare final partial tag
+
+ cmp x5, #48
+
+ eor x6, x6, x13 //AES block 4k+4 - round 14 low
+#ifdef __AARCH64EB__
+ rev x6, x6
+#endif
+
+ eor x7, x7, x14 //AES block 4k+4 - round 14 high
+#ifdef __AARCH64EB__
+ rev x7, x7
+#endif
+ b.gt .L256_dec_blocks_more_than_3
+
+ sub w12, w12, #1
+ mov v3.16b, v2.16b
+ movi v10.8b, #0
+
+ movi v11.8b, #0
+ cmp x5, #32
+
+ movi v9.8b, #0
+ mov v2.16b, v1.16b
+ b.gt .L256_dec_blocks_more_than_2
+
+ sub w12, w12, #1
+
+ mov v3.16b, v1.16b
+ cmp x5, #16
+ b.gt .L256_dec_blocks_more_than_1
+
+ sub w12, w12, #1
+ b .L256_dec_blocks_less_than_1
+.L256_dec_blocks_more_than_3: //blocks left > 3
+ rev64 v4.16b, v5.16b //GHASH final-3 block
+ ld1 { v5.16b}, [x0], #16 //AES final-2 block - load ciphertext
+
+ stp x6, x7, [x2], #16 //AES final-3 block - store result
+
+ mov d10, v17.d[1] //GHASH final-3 block - mid
+
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+
+ eor v0.16b, v5.16b, v1.16b //AES final-2 block - result
+
+ mov d22, v4.d[1] //GHASH final-3 block - mid
+
+ mov x6, v0.d[0] //AES final-2 block - mov low
+
+ mov x7, v0.d[1] //AES final-2 block - mov high
+
+ eor v22.8b, v22.8b, v4.8b //GHASH final-3 block - mid
+
+ movi v8.8b, #0 //suppress further partial tag feed in
+
+ pmull2 v9.1q, v4.2d, v15.2d //GHASH final-3 block - high
+
+ pmull v10.1q, v22.1d, v10.1d //GHASH final-3 block - mid
+ eor x6, x6, x13 //AES final-2 block - round 14 low
+#ifdef __AARCH64EB__
+ rev x6, x6
+#endif
+
+ pmull v11.1q, v4.1d, v15.1d //GHASH final-3 block - low
+ eor x7, x7, x14 //AES final-2 block - round 14 high
+#ifdef __AARCH64EB__
+ rev x7, x7
+#endif
+.L256_dec_blocks_more_than_2: //blocks left > 2
+
+ rev64 v4.16b, v5.16b //GHASH final-2 block
+ ld1 { v5.16b}, [x0], #16 //AES final-1 block - load ciphertext
+
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+ stp x6, x7, [x2], #16 //AES final-2 block - store result
+
+ eor v0.16b, v5.16b, v2.16b //AES final-1 block - result
+
+ mov d22, v4.d[1] //GHASH final-2 block - mid
+
+ pmull v21.1q, v4.1d, v14.1d //GHASH final-2 block - low
+
+ pmull2 v20.1q, v4.2d, v14.2d //GHASH final-2 block - high
+
+ eor v22.8b, v22.8b, v4.8b //GHASH final-2 block - mid
+ mov x6, v0.d[0] //AES final-1 block - mov low
+
+ mov x7, v0.d[1] //AES final-1 block - mov high
+ eor v11.16b, v11.16b, v21.16b //GHASH final-2 block - low
+ movi v8.8b, #0 //suppress further partial tag feed in
+
+ pmull v22.1q, v22.1d, v17.1d //GHASH final-2 block - mid
+
+ eor v9.16b, v9.16b, v20.16b //GHASH final-2 block - high
+ eor x6, x6, x13 //AES final-1 block - round 14 low
+#ifdef __AARCH64EB__
+ rev x6, x6
+#endif
+
+ eor v10.16b, v10.16b, v22.16b //GHASH final-2 block - mid
+ eor x7, x7, x14 //AES final-1 block - round 14 high
+#ifdef __AARCH64EB__
+ rev x7, x7
+#endif
+.L256_dec_blocks_more_than_1: //blocks left > 1
+
+ stp x6, x7, [x2], #16 //AES final-1 block - store result
+ rev64 v4.16b, v5.16b //GHASH final-1 block
+
+ ld1 { v5.16b}, [x0], #16 //AES final block - load ciphertext
+
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+ movi v8.8b, #0 //suppress further partial tag feed in
+
+ mov d22, v4.d[1] //GHASH final-1 block - mid
+
+ eor v0.16b, v5.16b, v3.16b //AES final block - result
+
+ pmull2 v20.1q, v4.2d, v13.2d //GHASH final-1 block - high
+
+ eor v22.8b, v22.8b, v4.8b //GHASH final-1 block - mid
+
+ pmull v21.1q, v4.1d, v13.1d //GHASH final-1 block - low
+ mov x6, v0.d[0] //AES final block - mov low
+
+ ins v22.d[1], v22.d[0] //GHASH final-1 block - mid
+
+ mov x7, v0.d[1] //AES final block - mov high
+
+ pmull2 v22.1q, v22.2d, v16.2d //GHASH final-1 block - mid
+ eor x6, x6, x13 //AES final block - round 14 low
+#ifdef __AARCH64EB__
+ rev x6, x6
+#endif
+ eor v11.16b, v11.16b, v21.16b //GHASH final-1 block - low
+
+ eor v9.16b, v9.16b, v20.16b //GHASH final-1 block - high
+
+ eor v10.16b, v10.16b, v22.16b //GHASH final-1 block - mid
+ eor x7, x7, x14 //AES final block - round 14 high
+#ifdef __AARCH64EB__
+ rev x7, x7
+#endif
+.L256_dec_blocks_less_than_1: //blocks left <= 1
+
+ and x1, x1, #127 //bit_length %= 128
+ mvn x14, xzr //rk14_h = 0xffffffffffffffff
+
+ sub x1, x1, #128 //bit_length -= 128
+ mvn x13, xzr //rk14_l = 0xffffffffffffffff
+
+ ldp x4, x5, [x2] //load existing bytes we need to not overwrite
+ neg x1, x1 //bit_length = 128 - #bits in input (in range [1,128])
+
+ and x1, x1, #127 //bit_length %= 128
+
+ lsr x14, x14, x1 //rk14_h is mask for top 64b of last block
+ cmp x1, #64
+
+ csel x9, x13, x14, lt
+ csel x10, x14, xzr, lt
+
+ fmov d0, x9 //ctr0b is mask for last block
+ and x6, x6, x9
+
+ mov v0.d[1], x10
+ bic x4, x4, x9 //mask out low existing bytes
+
+#ifndef __AARCH64EB__
+ rev w9, w12
+#else
+ mov w9, w12
+#endif
+
+ bic x5, x5, x10 //mask out high existing bytes
+
+ orr x6, x6, x4
+
+ and x7, x7, x10
+
+ orr x7, x7, x5
+
+ and v5.16b, v5.16b, v0.16b //possibly partial last block has zeroes in highest bits
+
+ rev64 v4.16b, v5.16b //GHASH final block
+
+ eor v4.16b, v4.16b, v8.16b //feed in partial tag
+
+ pmull v21.1q, v4.1d, v12.1d //GHASH final block - low
+
+ mov d8, v4.d[1] //GHASH final block - mid
+
+ eor v8.8b, v8.8b, v4.8b //GHASH final block - mid
+
+ pmull2 v20.1q, v4.2d, v12.2d //GHASH final block - high
+
+ pmull v8.1q, v8.1d, v16.1d //GHASH final block - mid
+
+ eor v9.16b, v9.16b, v20.16b //GHASH final block - high
+
+ eor v11.16b, v11.16b, v21.16b //GHASH final block - low
+
+ eor v10.16b, v10.16b, v8.16b //GHASH final block - mid
+ movi v8.8b, #0xc2
+
+ eor v6.16b, v11.16b, v9.16b //MODULO - karatsuba tidy up
+
+ shl d8, d8, #56 //mod_constant
+
+ eor v10.16b, v10.16b, v6.16b //MODULO - karatsuba tidy up
+
+ pmull v7.1q, v9.1d, v8.1d //MODULO - top 64b align with mid
+
+ ext v9.16b, v9.16b, v9.16b, #8 //MODULO - other top alignment
+
+ eor v10.16b, v10.16b, v7.16b //MODULO - fold into mid
+
+ eor v10.16b, v10.16b, v9.16b //MODULO - fold into mid
+
+ pmull v8.1q, v10.1d, v8.1d //MODULO - mid 64b align with low
+
+ ext v10.16b, v10.16b, v10.16b, #8 //MODULO - other mid alignment
+
+ eor v11.16b, v11.16b, v8.16b //MODULO - fold into low
+
+ stp x6, x7, [x2]
+
+ str w9, [x16, #12] //store the updated counter
+
+ eor v11.16b, v11.16b, v10.16b //MODULO - fold into low
+ ext v11.16b, v11.16b, v11.16b, #8
+ rev64 v11.16b, v11.16b
+ mov x0, x15
+ st1 { v11.16b }, [x3]
+
+ ldp x21, x22, [sp, #16]
+ ldp x23, x24, [sp, #32]
+ ldp d8, d9, [sp, #48]
+ ldp d10, d11, [sp, #64]
+ ldp d12, d13, [sp, #80]
+ ldp d14, d15, [sp, #96]
+ ldp x19, x20, [sp], #112
+ ret
+
+.L256_dec_ret:
+ mov w0, #0x0
+ ret
+.size aes_gcm_dec_256_kernel,.-aes_gcm_dec_256_kernel
+.byte 71,72,65,83,72,32,102,111,114,32,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
+.align 2
+.align 2
+#endif
diff --git a/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/modes/ghashv8-armx.S b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/modes/ghashv8-armx.S
new file mode 100644
index 000000000000..ae1afff44127
--- /dev/null
+++ b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/modes/ghashv8-armx.S
@@ -0,0 +1,552 @@
+#include "arm_arch.h"
+
+#if __ARM_MAX_ARCH__>=7
+.arch armv8-a+crypto
+.text
+.globl gcm_init_v8
+.type gcm_init_v8,%function
+.align 4
+gcm_init_v8:
+ ld1 {v17.2d},[x1] //load input H
+ movi v19.16b,#0xe1
+ shl v19.2d,v19.2d,#57 //0xc2.0
+ ext v3.16b,v17.16b,v17.16b,#8
+ ushr v18.2d,v19.2d,#63
+ dup v17.4s,v17.s[1]
+ ext v16.16b,v18.16b,v19.16b,#8 //t0=0xc2....01
+ ushr v18.2d,v3.2d,#63
+ sshr v17.4s,v17.4s,#31 //broadcast carry bit
+ and v18.16b,v18.16b,v16.16b
+ shl v3.2d,v3.2d,#1
+ ext v18.16b,v18.16b,v18.16b,#8
+ and v16.16b,v16.16b,v17.16b
+ orr v3.16b,v3.16b,v18.16b //H<<<=1
+ eor v20.16b,v3.16b,v16.16b //twisted H
+ st1 {v20.2d},[x0],#16 //store Htable[0]
+
+ //calculate H^2
+ ext v16.16b,v20.16b,v20.16b,#8 //Karatsuba pre-processing
+ pmull v0.1q,v20.1d,v20.1d
+ eor v16.16b,v16.16b,v20.16b
+ pmull2 v2.1q,v20.2d,v20.2d
+ pmull v1.1q,v16.1d,v16.1d
+
+ ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
+ eor v18.16b,v0.16b,v2.16b
+ eor v1.16b,v1.16b,v17.16b
+ eor v1.16b,v1.16b,v18.16b
+ pmull v18.1q,v0.1d,v19.1d //1st phase
+
+ ins v2.d[0],v1.d[1]
+ ins v1.d[1],v0.d[0]
+ eor v0.16b,v1.16b,v18.16b
+
+ ext v18.16b,v0.16b,v0.16b,#8 //2nd phase
+ pmull v0.1q,v0.1d,v19.1d
+ eor v18.16b,v18.16b,v2.16b
+ eor v22.16b,v0.16b,v18.16b
+
+ ext v17.16b,v22.16b,v22.16b,#8 //Karatsuba pre-processing
+ eor v17.16b,v17.16b,v22.16b
+ ext v21.16b,v16.16b,v17.16b,#8 //pack Karatsuba pre-processed
+ st1 {v21.2d,v22.2d},[x0],#32 //store Htable[1..2]
+ //calculate H^3 and H^4
+ pmull v0.1q,v20.1d, v22.1d
+ pmull v5.1q,v22.1d,v22.1d
+ pmull2 v2.1q,v20.2d, v22.2d
+ pmull2 v7.1q,v22.2d,v22.2d
+ pmull v1.1q,v16.1d,v17.1d
+ pmull v6.1q,v17.1d,v17.1d
+
+ ext v16.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
+ ext v17.16b,v5.16b,v7.16b,#8
+ eor v18.16b,v0.16b,v2.16b
+ eor v1.16b,v1.16b,v16.16b
+ eor v4.16b,v5.16b,v7.16b
+ eor v6.16b,v6.16b,v17.16b
+ eor v1.16b,v1.16b,v18.16b
+ pmull v18.1q,v0.1d,v19.1d //1st phase
+ eor v6.16b,v6.16b,v4.16b
+ pmull v4.1q,v5.1d,v19.1d
+
+ ins v2.d[0],v1.d[1]
+ ins v7.d[0],v6.d[1]
+ ins v1.d[1],v0.d[0]
+ ins v6.d[1],v5.d[0]
+ eor v0.16b,v1.16b,v18.16b
+ eor v5.16b,v6.16b,v4.16b
+
+ ext v18.16b,v0.16b,v0.16b,#8 //2nd phase
+ ext v4.16b,v5.16b,v5.16b,#8
+ pmull v0.1q,v0.1d,v19.1d
+ pmull v5.1q,v5.1d,v19.1d
+ eor v18.16b,v18.16b,v2.16b
+ eor v4.16b,v4.16b,v7.16b
+ eor v20.16b, v0.16b,v18.16b //H^3
+ eor v22.16b,v5.16b,v4.16b //H^4
+
+ ext v16.16b,v20.16b, v20.16b,#8 //Karatsuba pre-processing
+ ext v17.16b,v22.16b,v22.16b,#8
+ eor v16.16b,v16.16b,v20.16b
+ eor v17.16b,v17.16b,v22.16b
+ ext v21.16b,v16.16b,v17.16b,#8 //pack Karatsuba pre-processed
+ st1 {v20.2d,v21.2d,v22.2d},[x0] //store Htable[3..5]
+ ret
+.size gcm_init_v8,.-gcm_init_v8
+.globl gcm_gmult_v8
+.type gcm_gmult_v8,%function
+.align 4
+gcm_gmult_v8:
+ ld1 {v17.2d},[x0] //load Xi
+ movi v19.16b,#0xe1
+ ld1 {v20.2d,v21.2d},[x1] //load twisted H, ...
+ shl v19.2d,v19.2d,#57
+#ifndef __ARMEB__
+ rev64 v17.16b,v17.16b
+#endif
+ ext v3.16b,v17.16b,v17.16b,#8
+
+ pmull v0.1q,v20.1d,v3.1d //H.lo·Xi.lo
+ eor v17.16b,v17.16b,v3.16b //Karatsuba pre-processing
+ pmull2 v2.1q,v20.2d,v3.2d //H.hi·Xi.hi
+ pmull v1.1q,v21.1d,v17.1d //(H.lo+H.hi)·(Xi.lo+Xi.hi)
+
+ ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
+ eor v18.16b,v0.16b,v2.16b
+ eor v1.16b,v1.16b,v17.16b
+ eor v1.16b,v1.16b,v18.16b
+ pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
+
+ ins v2.d[0],v1.d[1]
+ ins v1.d[1],v0.d[0]
+ eor v0.16b,v1.16b,v18.16b
+
+ ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
+ pmull v0.1q,v0.1d,v19.1d
+ eor v18.16b,v18.16b,v2.16b
+ eor v0.16b,v0.16b,v18.16b
+
+#ifndef __ARMEB__
+ rev64 v0.16b,v0.16b
+#endif
+ ext v0.16b,v0.16b,v0.16b,#8
+ st1 {v0.2d},[x0] //write out Xi
+
+ ret
+.size gcm_gmult_v8,.-gcm_gmult_v8
+.globl gcm_ghash_v8
+.type gcm_ghash_v8,%function
+.align 4
+gcm_ghash_v8:
+ cmp x3,#64
+ b.hs .Lgcm_ghash_v8_4x
+ ld1 {v0.2d},[x0] //load [rotated] Xi
+ //"[rotated]" means that
+ //loaded value would have
+ //to be rotated in order to
+ //make it appear as in
+ //algorithm specification
+ subs x3,x3,#32 //see if x3 is 32 or larger
+ mov x12,#16 //x12 is used as post-
+ //increment for input pointer;
+ //as loop is modulo-scheduled
+ //x12 is zeroed just in time
+ //to preclude overstepping
+ //inp[len], which means that
+ //last block[s] are actually
+ //loaded twice, but last
+ //copy is not processed
+ ld1 {v20.2d,v21.2d},[x1],#32 //load twisted H, ..., H^2
+ movi v19.16b,#0xe1
+ ld1 {v22.2d},[x1]
+ csel x12,xzr,x12,eq //is it time to zero x12?
+ ext v0.16b,v0.16b,v0.16b,#8 //rotate Xi
+ ld1 {v16.2d},[x2],#16 //load [rotated] I[0]
+ shl v19.2d,v19.2d,#57 //compose 0xc2.0 constant
+#ifndef __ARMEB__
+ rev64 v16.16b,v16.16b
+ rev64 v0.16b,v0.16b
+#endif
+ ext v3.16b,v16.16b,v16.16b,#8 //rotate I[0]
+ b.lo .Lodd_tail_v8 //x3 was less than 32
+ ld1 {v17.2d},[x2],x12 //load [rotated] I[1]
+#ifndef __ARMEB__
+ rev64 v17.16b,v17.16b
+#endif
+ ext v7.16b,v17.16b,v17.16b,#8
+ eor v3.16b,v3.16b,v0.16b //I[i]^=Xi
+ pmull v4.1q,v20.1d,v7.1d //H·Ii+1
+ eor v17.16b,v17.16b,v7.16b //Karatsuba pre-processing
+ pmull2 v6.1q,v20.2d,v7.2d
+ b .Loop_mod2x_v8
+
+.align 4
+.Loop_mod2x_v8:
+ ext v18.16b,v3.16b,v3.16b,#8
+ subs x3,x3,#32 //is there more data?
+ pmull v0.1q,v22.1d,v3.1d //H^2.lo·Xi.lo
+ csel x12,xzr,x12,lo //is it time to zero x12?
+
+ pmull v5.1q,v21.1d,v17.1d
+ eor v18.16b,v18.16b,v3.16b //Karatsuba pre-processing
+ pmull2 v2.1q,v22.2d,v3.2d //H^2.hi·Xi.hi
+ eor v0.16b,v0.16b,v4.16b //accumulate
+ pmull2 v1.1q,v21.2d,v18.2d //(H^2.lo+H^2.hi)·(Xi.lo+Xi.hi)
+ ld1 {v16.2d},[x2],x12 //load [rotated] I[i+2]
+
+ eor v2.16b,v2.16b,v6.16b
+ csel x12,xzr,x12,eq //is it time to zero x12?
+ eor v1.16b,v1.16b,v5.16b
+
+ ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
+ eor v18.16b,v0.16b,v2.16b
+ eor v1.16b,v1.16b,v17.16b
+ ld1 {v17.2d},[x2],x12 //load [rotated] I[i+3]
+#ifndef __ARMEB__
+ rev64 v16.16b,v16.16b
+#endif
+ eor v1.16b,v1.16b,v18.16b
+ pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
+
+#ifndef __ARMEB__
+ rev64 v17.16b,v17.16b
+#endif
+ ins v2.d[0],v1.d[1]
+ ins v1.d[1],v0.d[0]
+ ext v7.16b,v17.16b,v17.16b,#8
+ ext v3.16b,v16.16b,v16.16b,#8
+ eor v0.16b,v1.16b,v18.16b
+ pmull v4.1q,v20.1d,v7.1d //H·Ii+1
+ eor v3.16b,v3.16b,v2.16b //accumulate v3.16b early
+
+ ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
+ pmull v0.1q,v0.1d,v19.1d
+ eor v3.16b,v3.16b,v18.16b
+ eor v17.16b,v17.16b,v7.16b //Karatsuba pre-processing
+ eor v3.16b,v3.16b,v0.16b
+ pmull2 v6.1q,v20.2d,v7.2d
+ b.hs .Loop_mod2x_v8 //there was at least 32 more bytes
+
+ eor v2.16b,v2.16b,v18.16b
+ ext v3.16b,v16.16b,v16.16b,#8 //re-construct v3.16b
+ adds x3,x3,#32 //re-construct x3
+ eor v0.16b,v0.16b,v2.16b //re-construct v0.16b
+ b.eq .Ldone_v8 //is x3 zero?
+.Lodd_tail_v8:
+ ext v18.16b,v0.16b,v0.16b,#8
+ eor v3.16b,v3.16b,v0.16b //inp^=Xi
+ eor v17.16b,v16.16b,v18.16b //v17.16b is rotated inp^Xi
+
+ pmull v0.1q,v20.1d,v3.1d //H.lo·Xi.lo
+ eor v17.16b,v17.16b,v3.16b //Karatsuba pre-processing
+ pmull2 v2.1q,v20.2d,v3.2d //H.hi·Xi.hi
+ pmull v1.1q,v21.1d,v17.1d //(H.lo+H.hi)·(Xi.lo+Xi.hi)
+
+ ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
+ eor v18.16b,v0.16b,v2.16b
+ eor v1.16b,v1.16b,v17.16b
+ eor v1.16b,v1.16b,v18.16b
+ pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
+
+ ins v2.d[0],v1.d[1]
+ ins v1.d[1],v0.d[0]
+ eor v0.16b,v1.16b,v18.16b
+
+ ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
+ pmull v0.1q,v0.1d,v19.1d
+ eor v18.16b,v18.16b,v2.16b
+ eor v0.16b,v0.16b,v18.16b
+
+.Ldone_v8:
+#ifndef __ARMEB__
+ rev64 v0.16b,v0.16b
+#endif
+ ext v0.16b,v0.16b,v0.16b,#8
+ st1 {v0.2d},[x0] //write out Xi
+
+ ret
+.size gcm_ghash_v8,.-gcm_ghash_v8
+.type gcm_ghash_v8_4x,%function
+.align 4
+gcm_ghash_v8_4x:
+.Lgcm_ghash_v8_4x:
+ ld1 {v0.2d},[x0] //load [rotated] Xi
+ ld1 {v20.2d,v21.2d,v22.2d},[x1],#48 //load twisted H, ..., H^2
+ movi v19.16b,#0xe1
+ ld1 {v26.2d,v27.2d,v28.2d},[x1] //load twisted H^3, ..., H^4
+ shl v19.2d,v19.2d,#57 //compose 0xc2.0 constant
+
+ ld1 {v4.2d,v5.2d,v6.2d,v7.2d},[x2],#64
+#ifndef __ARMEB__
+ rev64 v0.16b,v0.16b
+ rev64 v5.16b,v5.16b
+ rev64 v6.16b,v6.16b
+ rev64 v7.16b,v7.16b
+ rev64 v4.16b,v4.16b
+#endif
+ ext v25.16b,v7.16b,v7.16b,#8
+ ext v24.16b,v6.16b,v6.16b,#8
+ ext v23.16b,v5.16b,v5.16b,#8
+
+ pmull v29.1q,v20.1d,v25.1d //H·Ii+3
+ eor v7.16b,v7.16b,v25.16b
+ pmull2 v31.1q,v20.2d,v25.2d
+ pmull v30.1q,v21.1d,v7.1d
+
+ pmull v16.1q,v22.1d,v24.1d //H^2·Ii+2
+ eor v6.16b,v6.16b,v24.16b
+ pmull2 v24.1q,v22.2d,v24.2d
+ pmull2 v6.1q,v21.2d,v6.2d
+
+ eor v29.16b,v29.16b,v16.16b
+ eor v31.16b,v31.16b,v24.16b
+ eor v30.16b,v30.16b,v6.16b
+
+ pmull v7.1q,v26.1d,v23.1d //H^3·Ii+1
+ eor v5.16b,v5.16b,v23.16b
+ pmull2 v23.1q,v26.2d,v23.2d
+ pmull v5.1q,v27.1d,v5.1d
+
+ eor v29.16b,v29.16b,v7.16b
+ eor v31.16b,v31.16b,v23.16b
+ eor v30.16b,v30.16b,v5.16b
+
+ subs x3,x3,#128
+ b.lo .Ltail4x
+
+ b .Loop4x
+
+.align 4
+.Loop4x:
+ eor v16.16b,v4.16b,v0.16b
+ ld1 {v4.2d,v5.2d,v6.2d,v7.2d},[x2],#64
+ ext v3.16b,v16.16b,v16.16b,#8
+#ifndef __ARMEB__
+ rev64 v5.16b,v5.16b
+ rev64 v6.16b,v6.16b
+ rev64 v7.16b,v7.16b
+ rev64 v4.16b,v4.16b
+#endif
+
+ pmull v0.1q,v28.1d,v3.1d //H^4·(Xi+Ii)
+ eor v16.16b,v16.16b,v3.16b
+ pmull2 v2.1q,v28.2d,v3.2d
+ ext v25.16b,v7.16b,v7.16b,#8
+ pmull2 v1.1q,v27.2d,v16.2d
+
+ eor v0.16b,v0.16b,v29.16b
+ eor v2.16b,v2.16b,v31.16b
+ ext v24.16b,v6.16b,v6.16b,#8
+ eor v1.16b,v1.16b,v30.16b
+ ext v23.16b,v5.16b,v5.16b,#8
+
+ ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
+ eor v18.16b,v0.16b,v2.16b
+ pmull v29.1q,v20.1d,v25.1d //H·Ii+3
+ eor v7.16b,v7.16b,v25.16b
+ eor v1.16b,v1.16b,v17.16b
+ pmull2 v31.1q,v20.2d,v25.2d
+ eor v1.16b,v1.16b,v18.16b
+ pmull v30.1q,v21.1d,v7.1d
+
+ pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
+ ins v2.d[0],v1.d[1]
+ ins v1.d[1],v0.d[0]
+ pmull v16.1q,v22.1d,v24.1d //H^2·Ii+2
+ eor v6.16b,v6.16b,v24.16b
+ pmull2 v24.1q,v22.2d,v24.2d
+ eor v0.16b,v1.16b,v18.16b
+ pmull2 v6.1q,v21.2d,v6.2d
+
+ eor v29.16b,v29.16b,v16.16b
+ eor v31.16b,v31.16b,v24.16b
+ eor v30.16b,v30.16b,v6.16b
+
+ ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
+ pmull v0.1q,v0.1d,v19.1d
+ pmull v7.1q,v26.1d,v23.1d //H^3·Ii+1
+ eor v5.16b,v5.16b,v23.16b
+ eor v18.16b,v18.16b,v2.16b
+ pmull2 v23.1q,v26.2d,v23.2d
+ pmull v5.1q,v27.1d,v5.1d
+
+ eor v0.16b,v0.16b,v18.16b
+ eor v29.16b,v29.16b,v7.16b
+ eor v31.16b,v31.16b,v23.16b
+ ext v0.16b,v0.16b,v0.16b,#8
+ eor v30.16b,v30.16b,v5.16b
+
+ subs x3,x3,#64
+ b.hs .Loop4x
+
+.Ltail4x:
+ eor v16.16b,v4.16b,v0.16b
+ ext v3.16b,v16.16b,v16.16b,#8
+
+ pmull v0.1q,v28.1d,v3.1d //H^4·(Xi+Ii)
+ eor v16.16b,v16.16b,v3.16b
+ pmull2 v2.1q,v28.2d,v3.2d
+ pmull2 v1.1q,v27.2d,v16.2d
+
+ eor v0.16b,v0.16b,v29.16b
+ eor v2.16b,v2.16b,v31.16b
+ eor v1.16b,v1.16b,v30.16b
+
+ adds x3,x3,#64
+ b.eq .Ldone4x
+
+ cmp x3,#32
+ b.lo .Lone
+ b.eq .Ltwo
+.Lthree:
+ ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
+ eor v18.16b,v0.16b,v2.16b
+ eor v1.16b,v1.16b,v17.16b
+ ld1 {v4.2d,v5.2d,v6.2d},[x2]
+ eor v1.16b,v1.16b,v18.16b
+#ifndef __ARMEB__
+ rev64 v5.16b,v5.16b
+ rev64 v6.16b,v6.16b
+ rev64 v4.16b,v4.16b
+#endif
+
+ pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
+ ins v2.d[0],v1.d[1]
+ ins v1.d[1],v0.d[0]
+ ext v24.16b,v6.16b,v6.16b,#8
+ ext v23.16b,v5.16b,v5.16b,#8
+ eor v0.16b,v1.16b,v18.16b
+
+ pmull v29.1q,v20.1d,v24.1d //H·Ii+2
+ eor v6.16b,v6.16b,v24.16b
+
+ ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
+ pmull v0.1q,v0.1d,v19.1d
+ eor v18.16b,v18.16b,v2.16b
+ pmull2 v31.1q,v20.2d,v24.2d
+ pmull v30.1q,v21.1d,v6.1d
+ eor v0.16b,v0.16b,v18.16b
+ pmull v7.1q,v22.1d,v23.1d //H^2·Ii+1
+ eor v5.16b,v5.16b,v23.16b
+ ext v0.16b,v0.16b,v0.16b,#8
+
+ pmull2 v23.1q,v22.2d,v23.2d
+ eor v16.16b,v4.16b,v0.16b
+ pmull2 v5.1q,v21.2d,v5.2d
+ ext v3.16b,v16.16b,v16.16b,#8
+
+ eor v29.16b,v29.16b,v7.16b
+ eor v31.16b,v31.16b,v23.16b
+ eor v30.16b,v30.16b,v5.16b
+
+ pmull v0.1q,v26.1d,v3.1d //H^3·(Xi+Ii)
+ eor v16.16b,v16.16b,v3.16b
+ pmull2 v2.1q,v26.2d,v3.2d
+ pmull v1.1q,v27.1d,v16.1d
+
+ eor v0.16b,v0.16b,v29.16b
+ eor v2.16b,v2.16b,v31.16b
+ eor v1.16b,v1.16b,v30.16b
+ b .Ldone4x
+
+.align 4
+.Ltwo:
+ ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
+ eor v18.16b,v0.16b,v2.16b
+ eor v1.16b,v1.16b,v17.16b
+ ld1 {v4.2d,v5.2d},[x2]
+ eor v1.16b,v1.16b,v18.16b
+#ifndef __ARMEB__
+ rev64 v5.16b,v5.16b
+ rev64 v4.16b,v4.16b
+#endif
+
+ pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
+ ins v2.d[0],v1.d[1]
+ ins v1.d[1],v0.d[0]
+ ext v23.16b,v5.16b,v5.16b,#8
+ eor v0.16b,v1.16b,v18.16b
+
+ ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
+ pmull v0.1q,v0.1d,v19.1d
+ eor v18.16b,v18.16b,v2.16b
+ eor v0.16b,v0.16b,v18.16b
+ ext v0.16b,v0.16b,v0.16b,#8
+
+ pmull v29.1q,v20.1d,v23.1d //H·Ii+1
+ eor v5.16b,v5.16b,v23.16b
+
+ eor v16.16b,v4.16b,v0.16b
+ ext v3.16b,v16.16b,v16.16b,#8
+
+ pmull2 v31.1q,v20.2d,v23.2d
+ pmull v30.1q,v21.1d,v5.1d
+
+ pmull v0.1q,v22.1d,v3.1d //H^2·(Xi+Ii)
+ eor v16.16b,v16.16b,v3.16b
+ pmull2 v2.1q,v22.2d,v3.2d
+ pmull2 v1.1q,v21.2d,v16.2d
+
+ eor v0.16b,v0.16b,v29.16b
+ eor v2.16b,v2.16b,v31.16b
+ eor v1.16b,v1.16b,v30.16b
+ b .Ldone4x
+
+.align 4
+.Lone:
+ ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
+ eor v18.16b,v0.16b,v2.16b
+ eor v1.16b,v1.16b,v17.16b
+ ld1 {v4.2d},[x2]
+ eor v1.16b,v1.16b,v18.16b
+#ifndef __ARMEB__
+ rev64 v4.16b,v4.16b
+#endif
+
+ pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
+ ins v2.d[0],v1.d[1]
+ ins v1.d[1],v0.d[0]
+ eor v0.16b,v1.16b,v18.16b
+
+ ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
+ pmull v0.1q,v0.1d,v19.1d
+ eor v18.16b,v18.16b,v2.16b
+ eor v0.16b,v0.16b,v18.16b
+ ext v0.16b,v0.16b,v0.16b,#8
+
+ eor v16.16b,v4.16b,v0.16b
+ ext v3.16b,v16.16b,v16.16b,#8
+
+ pmull v0.1q,v20.1d,v3.1d
+ eor v16.16b,v16.16b,v3.16b
+ pmull2 v2.1q,v20.2d,v3.2d
+ pmull v1.1q,v21.1d,v16.1d
+
+.Ldone4x:
+ ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
+ eor v18.16b,v0.16b,v2.16b
+ eor v1.16b,v1.16b,v17.16b
+ eor v1.16b,v1.16b,v18.16b
+
+ pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
+ ins v2.d[0],v1.d[1]
+ ins v1.d[1],v0.d[0]
+ eor v0.16b,v1.16b,v18.16b
+
+ ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
+ pmull v0.1q,v0.1d,v19.1d
+ eor v18.16b,v18.16b,v2.16b
+ eor v0.16b,v0.16b,v18.16b
+ ext v0.16b,v0.16b,v0.16b,#8
+
+#ifndef __ARMEB__
+ rev64 v0.16b,v0.16b
+#endif
+ st1 {v0.2d},[x0] //write out Xi
+
+ ret
+.size gcm_ghash_v8_4x,.-gcm_ghash_v8_4x
+.byte 71,72,65,83,72,32,102,111,114,32,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
+.align 2
+.align 2
+#endif
diff --git a/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/keccak1600-armv8.S b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/keccak1600-armv8.S
new file mode 100644
index 000000000000..67e553f97634
--- /dev/null
+++ b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/keccak1600-armv8.S
@@ -0,0 +1,1009 @@
+.text
+
+.align 8 // strategic alignment and padding that allows to use
+ // address value as loop termination condition...
+.quad 0,0,0,0,0,0,0,0
+.type iotas,%object
+iotas:
+.quad 0x0000000000000001
+.quad 0x0000000000008082
+.quad 0x800000000000808a
+.quad 0x8000000080008000
+.quad 0x000000000000808b
+.quad 0x0000000080000001
+.quad 0x8000000080008081
+.quad 0x8000000000008009
+.quad 0x000000000000008a
+.quad 0x0000000000000088
+.quad 0x0000000080008009
+.quad 0x000000008000000a
+.quad 0x000000008000808b
+.quad 0x800000000000008b
+.quad 0x8000000000008089
+.quad 0x8000000000008003
+.quad 0x8000000000008002
+.quad 0x8000000000000080
+.quad 0x000000000000800a
+.quad 0x800000008000000a
+.quad 0x8000000080008081
+.quad 0x8000000000008080
+.quad 0x0000000080000001
+.quad 0x8000000080008008
+.size iotas,.-iotas
+.type KeccakF1600_int,%function
+.align 5
+KeccakF1600_int:
+ adr x28,iotas
+.inst 0xd503233f // paciasp
+ stp x28,x30,[sp,#16] // 32 bytes on top are mine
+ b .Loop
+.align 4
+.Loop:
+ ////////////////////////////////////////// Theta
+ eor x26,x0,x5
+ stp x4,x9,[sp,#0] // offload pair...
+ eor x27,x1,x6
+ eor x28,x2,x7
+ eor x30,x3,x8
+ eor x4,x4,x9
+ eor x26,x26,x10
+ eor x27,x27,x11
+ eor x28,x28,x12
+ eor x30,x30,x13
+ eor x4,x4,x14
+ eor x26,x26,x15
+ eor x27,x27,x16
+ eor x28,x28,x17
+ eor x30,x30,x25
+ eor x4,x4,x19
+ eor x26,x26,x20
+ eor x28,x28,x22
+ eor x27,x27,x21
+ eor x30,x30,x23
+ eor x4,x4,x24
+
+ eor x9,x26,x28,ror#63
+
+ eor x1,x1,x9
+ eor x6,x6,x9
+ eor x11,x11,x9
+ eor x16,x16,x9
+ eor x21,x21,x9
+
+ eor x9,x27,x30,ror#63
+ eor x28,x28,x4,ror#63
+ eor x30,x30,x26,ror#63
+ eor x4,x4,x27,ror#63
+
+ eor x27, x2,x9 // mov x27,x2
+ eor x7,x7,x9
+ eor x12,x12,x9
+ eor x17,x17,x9
+ eor x22,x22,x9
+
+ eor x0,x0,x4
+ eor x5,x5,x4
+ eor x10,x10,x4
+ eor x15,x15,x4
+ eor x20,x20,x4
+ ldp x4,x9,[sp,#0] // re-load offloaded data
+ eor x26, x3,x28 // mov x26,x3
+ eor x8,x8,x28
+ eor x13,x13,x28
+ eor x25,x25,x28
+ eor x23,x23,x28
+
+ eor x28, x4,x30 // mov x28,x4
+ eor x9,x9,x30
+ eor x14,x14,x30
+ eor x19,x19,x30
+ eor x24,x24,x30
+
+ ////////////////////////////////////////// Rho+Pi
+ mov x30,x1
+ ror x1,x6,#64-44
+ //mov x27,x2
+ ror x2,x12,#64-43
+ //mov x26,x3
+ ror x3,x25,#64-21
+ //mov x28,x4
+ ror x4,x24,#64-14
+
+ ror x6,x9,#64-20
+ ror x12,x13,#64-25
+ ror x25,x17,#64-15
+ ror x24,x21,#64-2
+
+ ror x9,x22,#64-61
+ ror x13,x19,#64-8
+ ror x17,x11,#64-10
+ ror x21,x8,#64-55
+
+ ror x22,x14,#64-39
+ ror x19,x23,#64-56
+ ror x11,x7,#64-6
+ ror x8,x16,#64-45
+
+ ror x14,x20,#64-18
+ ror x23,x15,#64-41
+ ror x7,x10,#64-3
+ ror x16,x5,#64-36
+
+ ror x5,x26,#64-28
+ ror x10,x30,#64-1
+ ror x15,x28,#64-27
+ ror x20,x27,#64-62
+
+ ////////////////////////////////////////// Chi+Iota
+ bic x26,x2,x1
+ bic x27,x3,x2
+ bic x28,x0,x4
+ bic x30,x1,x0
+ eor x0,x0,x26
+ bic x26,x4,x3
+ eor x1,x1,x27
+ ldr x27,[sp,#16]
+ eor x3,x3,x28
+ eor x4,x4,x30
+ eor x2,x2,x26
+ ldr x30,[x27],#8 // Iota[i++]
+
+ bic x26,x7,x6
+ tst x27,#255 // are we done?
+ str x27,[sp,#16]
+ bic x27,x8,x7
+ bic x28,x5,x9
+ eor x0,x0,x30 // A[0][0] ^= Iota
+ bic x30,x6,x5
+ eor x5,x5,x26
+ bic x26,x9,x8
+ eor x6,x6,x27
+ eor x8,x8,x28
+ eor x9,x9,x30
+ eor x7,x7,x26
+
+ bic x26,x12,x11
+ bic x27,x13,x12
+ bic x28,x10,x14
+ bic x30,x11,x10
+ eor x10,x10,x26
+ bic x26,x14,x13
+ eor x11,x11,x27
+ eor x13,x13,x28
+ eor x14,x14,x30
+ eor x12,x12,x26
+
+ bic x26,x17,x16
+ bic x27,x25,x17
+ bic x28,x15,x19
+ bic x30,x16,x15
+ eor x15,x15,x26
+ bic x26,x19,x25
+ eor x16,x16,x27
+ eor x25,x25,x28
+ eor x19,x19,x30
+ eor x17,x17,x26
+
+ bic x26,x22,x21
+ bic x27,x23,x22
+ bic x28,x20,x24
+ bic x30,x21,x20
+ eor x20,x20,x26
+ bic x26,x24,x23
+ eor x21,x21,x27
+ eor x23,x23,x28
+ eor x24,x24,x30
+ eor x22,x22,x26
+
+ bne .Loop
+
+ ldr x30,[sp,#24]
+.inst 0xd50323bf // autiasp
+ ret
+.size KeccakF1600_int,.-KeccakF1600_int
+
+.type KeccakF1600,%function
+.align 5
+KeccakF1600:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-128]!
+ add x29,sp,#0
+ stp x19,x20,[sp,#16]
+ stp x21,x22,[sp,#32]
+ stp x23,x24,[sp,#48]
+ stp x25,x26,[sp,#64]
+ stp x27,x28,[sp,#80]
+ sub sp,sp,#48
+
+ str x0,[sp,#32] // offload argument
+ mov x26,x0
+ ldp x0,x1,[x0,#16*0]
+ ldp x2,x3,[x26,#16*1]
+ ldp x4,x5,[x26,#16*2]
+ ldp x6,x7,[x26,#16*3]
+ ldp x8,x9,[x26,#16*4]
+ ldp x10,x11,[x26,#16*5]
+ ldp x12,x13,[x26,#16*6]
+ ldp x14,x15,[x26,#16*7]
+ ldp x16,x17,[x26,#16*8]
+ ldp x25,x19,[x26,#16*9]
+ ldp x20,x21,[x26,#16*10]
+ ldp x22,x23,[x26,#16*11]
+ ldr x24,[x26,#16*12]
+
+ bl KeccakF1600_int
+
+ ldr x26,[sp,#32]
+ stp x0,x1,[x26,#16*0]
+ stp x2,x3,[x26,#16*1]
+ stp x4,x5,[x26,#16*2]
+ stp x6,x7,[x26,#16*3]
+ stp x8,x9,[x26,#16*4]
+ stp x10,x11,[x26,#16*5]
+ stp x12,x13,[x26,#16*6]
+ stp x14,x15,[x26,#16*7]
+ stp x16,x17,[x26,#16*8]
+ stp x25,x19,[x26,#16*9]
+ stp x20,x21,[x26,#16*10]
+ stp x22,x23,[x26,#16*11]
+ str x24,[x26,#16*12]
+
+ ldp x19,x20,[x29,#16]
+ add sp,sp,#48
+ ldp x21,x22,[x29,#32]
+ ldp x23,x24,[x29,#48]
+ ldp x25,x26,[x29,#64]
+ ldp x27,x28,[x29,#80]
+ ldp x29,x30,[sp],#128
+.inst 0xd50323bf // autiasp
+ ret
+.size KeccakF1600,.-KeccakF1600
+
+.globl SHA3_absorb
+.type SHA3_absorb,%function
+.align 5
+SHA3_absorb:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-128]!
+ add x29,sp,#0
+ stp x19,x20,[sp,#16]
+ stp x21,x22,[sp,#32]
+ stp x23,x24,[sp,#48]
+ stp x25,x26,[sp,#64]
+ stp x27,x28,[sp,#80]
+ sub sp,sp,#64
+
+ stp x0,x1,[sp,#32] // offload arguments
+ stp x2,x3,[sp,#48]
+
+ mov x26,x0 // uint64_t A[5][5]
+ mov x27,x1 // const void *inp
+ mov x28,x2 // size_t len
+ mov x30,x3 // size_t bsz
+ ldp x0,x1,[x26,#16*0]
+ ldp x2,x3,[x26,#16*1]
+ ldp x4,x5,[x26,#16*2]
+ ldp x6,x7,[x26,#16*3]
+ ldp x8,x9,[x26,#16*4]
+ ldp x10,x11,[x26,#16*5]
+ ldp x12,x13,[x26,#16*6]
+ ldp x14,x15,[x26,#16*7]
+ ldp x16,x17,[x26,#16*8]
+ ldp x25,x19,[x26,#16*9]
+ ldp x20,x21,[x26,#16*10]
+ ldp x22,x23,[x26,#16*11]
+ ldr x24,[x26,#16*12]
+ b .Loop_absorb
+
+.align 4
+.Loop_absorb:
+ subs x26,x28,x30 // len - bsz
+ blo .Labsorbed
+
+ str x26,[sp,#48] // save len - bsz
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x0,x0,x26
+ cmp x30,#8*(0+2)
+ blo .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x1,x1,x26
+ beq .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x2,x2,x26
+ cmp x30,#8*(2+2)
+ blo .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x3,x3,x26
+ beq .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x4,x4,x26
+ cmp x30,#8*(4+2)
+ blo .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x5,x5,x26
+ beq .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x6,x6,x26
+ cmp x30,#8*(6+2)
+ blo .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x7,x7,x26
+ beq .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x8,x8,x26
+ cmp x30,#8*(8+2)
+ blo .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x9,x9,x26
+ beq .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x10,x10,x26
+ cmp x30,#8*(10+2)
+ blo .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x11,x11,x26
+ beq .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x12,x12,x26
+ cmp x30,#8*(12+2)
+ blo .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x13,x13,x26
+ beq .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x14,x14,x26
+ cmp x30,#8*(14+2)
+ blo .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x15,x15,x26
+ beq .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x16,x16,x26
+ cmp x30,#8*(16+2)
+ blo .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x17,x17,x26
+ beq .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x25,x25,x26
+ cmp x30,#8*(18+2)
+ blo .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x19,x19,x26
+ beq .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x20,x20,x26
+ cmp x30,#8*(20+2)
+ blo .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x21,x21,x26
+ beq .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x22,x22,x26
+ cmp x30,#8*(22+2)
+ blo .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x23,x23,x26
+ beq .Lprocess_block
+ ldr x26,[x27],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev x26,x26
+#endif
+ eor x24,x24,x26
+
+.Lprocess_block:
+ str x27,[sp,#40] // save inp
+
+ bl KeccakF1600_int
+
+ ldr x27,[sp,#40] // restore arguments
+ ldp x28,x30,[sp,#48]
+ b .Loop_absorb
+
+.align 4
+.Labsorbed:
+ ldr x27,[sp,#32]
+ stp x0,x1,[x27,#16*0]
+ stp x2,x3,[x27,#16*1]
+ stp x4,x5,[x27,#16*2]
+ stp x6,x7,[x27,#16*3]
+ stp x8,x9,[x27,#16*4]
+ stp x10,x11,[x27,#16*5]
+ stp x12,x13,[x27,#16*6]
+ stp x14,x15,[x27,#16*7]
+ stp x16,x17,[x27,#16*8]
+ stp x25,x19,[x27,#16*9]
+ stp x20,x21,[x27,#16*10]
+ stp x22,x23,[x27,#16*11]
+ str x24,[x27,#16*12]
+
+ mov x0,x28 // return value
+ ldp x19,x20,[x29,#16]
+ add sp,sp,#64
+ ldp x21,x22,[x29,#32]
+ ldp x23,x24,[x29,#48]
+ ldp x25,x26,[x29,#64]
+ ldp x27,x28,[x29,#80]
+ ldp x29,x30,[sp],#128
+.inst 0xd50323bf // autiasp
+ ret
+.size SHA3_absorb,.-SHA3_absorb
+.globl SHA3_squeeze
+.type SHA3_squeeze,%function
+.align 5
+SHA3_squeeze:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-48]!
+ add x29,sp,#0
+ stp x19,x20,[sp,#16]
+ stp x21,x22,[sp,#32]
+
+ mov x19,x0 // put aside arguments
+ mov x20,x1
+ mov x21,x2
+ mov x22,x3
+
+.Loop_squeeze:
+ ldr x4,[x0],#8
+ cmp x21,#8
+ blo .Lsqueeze_tail
+#ifdef __AARCH64EB__
+ rev x4,x4
+#endif
+ str x4,[x20],#8
+ subs x21,x21,#8
+ beq .Lsqueeze_done
+
+ subs x3,x3,#8
+ bhi .Loop_squeeze
+
+ mov x0,x19
+ bl KeccakF1600
+ mov x0,x19
+ mov x3,x22
+ b .Loop_squeeze
+
+.align 4
+.Lsqueeze_tail:
+ strb w4,[x20],#1
+ lsr x4,x4,#8
+ subs x21,x21,#1
+ beq .Lsqueeze_done
+ strb w4,[x20],#1
+ lsr x4,x4,#8
+ subs x21,x21,#1
+ beq .Lsqueeze_done
+ strb w4,[x20],#1
+ lsr x4,x4,#8
+ subs x21,x21,#1
+ beq .Lsqueeze_done
+ strb w4,[x20],#1
+ lsr x4,x4,#8
+ subs x21,x21,#1
+ beq .Lsqueeze_done
+ strb w4,[x20],#1
+ lsr x4,x4,#8
+ subs x21,x21,#1
+ beq .Lsqueeze_done
+ strb w4,[x20],#1
+ lsr x4,x4,#8
+ subs x21,x21,#1
+ beq .Lsqueeze_done
+ strb w4,[x20],#1
+
+.Lsqueeze_done:
+ ldp x19,x20,[sp,#16]
+ ldp x21,x22,[sp,#32]
+ ldp x29,x30,[sp],#48
+.inst 0xd50323bf // autiasp
+ ret
+.size SHA3_squeeze,.-SHA3_squeeze
+.type KeccakF1600_ce,%function
+.align 5
+KeccakF1600_ce:
+ mov x9,#24
+ adr x10,iotas
+ b .Loop_ce
+.align 4
+.Loop_ce:
+ ////////////////////////////////////////////////// Theta
+.inst 0xce0f2a99 //eor3 v25.16b,v20.16b,v15.16b,v10.16b
+.inst 0xce102eba //eor3 v26.16b,v21.16b,v16.16b,v11.16b
+.inst 0xce1132db //eor3 v27.16b,v22.16b,v17.16b,v12.16b
+.inst 0xce1236fc //eor3 v28.16b,v23.16b,v18.16b,v13.16b
+.inst 0xce133b1d //eor3 v29.16b,v24.16b,v19.16b,v14.16b
+.inst 0xce050339 //eor3 v25.16b,v25.16b, v5.16b,v0.16b
+.inst 0xce06075a //eor3 v26.16b,v26.16b, v6.16b,v1.16b
+.inst 0xce070b7b //eor3 v27.16b,v27.16b, v7.16b,v2.16b
+.inst 0xce080f9c //eor3 v28.16b,v28.16b, v8.16b,v3.16b
+.inst 0xce0913bd //eor3 v29.16b,v29.16b, v9.16b,v4.16b
+
+.inst 0xce7b8f3e //rax1 v30.16b,v25.16b,v27.16b // D[1]
+.inst 0xce7c8f5f //rax1 v31.16b,v26.16b,v28.16b // D[2]
+.inst 0xce7d8f7b //rax1 v27.16b,v27.16b,v29.16b // D[3]
+.inst 0xce798f9c //rax1 v28.16b,v28.16b,v25.16b // D[4]
+.inst 0xce7a8fbd //rax1 v29.16b,v29.16b,v26.16b // D[0]
+
+ ////////////////////////////////////////////////// Theta+Rho+Pi
+.inst 0xce9efc39 //xar v25.16b, v1.16b,v30.16b,#64-1 // C[0]=A[2][0]
+
+.inst 0xce9e50c1 //xar v1.16b,v6.16b,v30.16b,#64-44
+.inst 0xce9cb126 //xar v6.16b,v9.16b,v28.16b,#64-20
+.inst 0xce9f0ec9 //xar v9.16b,v22.16b,v31.16b,#64-61
+.inst 0xce9c65d6 //xar v22.16b,v14.16b,v28.16b,#64-39
+.inst 0xce9dba8e //xar v14.16b,v20.16b,v29.16b,#64-18
+
+.inst 0xce9f085a //xar v26.16b, v2.16b,v31.16b,#64-62 // C[1]=A[4][0]
+
+.inst 0xce9f5582 //xar v2.16b,v12.16b,v31.16b,#64-43
+.inst 0xce9b9dac //xar v12.16b,v13.16b,v27.16b,#64-25
+.inst 0xce9ce26d //xar v13.16b,v19.16b,v28.16b,#64-8
+.inst 0xce9b22f3 //xar v19.16b,v23.16b,v27.16b,#64-56
+.inst 0xce9d5df7 //xar v23.16b,v15.16b,v29.16b,#64-41
+
+.inst 0xce9c948f //xar v15.16b,v4.16b,v28.16b,#64-27
+
+.inst 0xce9ccb1c //xar v28.16b, v24.16b,v28.16b,#64-14 // D[4]=A[0][4]
+.inst 0xce9efab8 //xar v24.16b,v21.16b,v30.16b,#64-2
+.inst 0xce9b2508 //xar v8.16b,v8.16b,v27.16b,#64-55 // A[1][3]=A[4][1]
+.inst 0xce9e4e04 //xar v4.16b,v16.16b,v30.16b,#64-45 // A[0][4]=A[1][3]
+.inst 0xce9d70b0 //xar v16.16b,v5.16b,v29.16b,#64-36
+
+.inst 0xce9b9065 //xar v5.16b,v3.16b,v27.16b,#64-28
+
+ eor v0.16b,v0.16b,v29.16b
+
+.inst 0xce9bae5b //xar v27.16b, v18.16b,v27.16b,#64-21 // D[3]=A[0][3]
+.inst 0xce9fc623 //xar v3.16b,v17.16b,v31.16b,#64-15 // A[0][3]=A[3][3]
+.inst 0xce9ed97e //xar v30.16b, v11.16b,v30.16b,#64-10 // D[1]=A[3][2]
+.inst 0xce9fe8ff //xar v31.16b, v7.16b,v31.16b,#64-6 // D[2]=A[2][1]
+.inst 0xce9df55d //xar v29.16b, v10.16b,v29.16b,#64-3 // D[0]=A[1][2]
+
+ ////////////////////////////////////////////////// Chi+Iota
+.inst 0xce362354 //bcax v20.16b,v26.16b, v22.16b,v8.16b // A[1][3]=A[4][1]
+.inst 0xce375915 //bcax v21.16b,v8.16b,v23.16b,v22.16b // A[1][3]=A[4][1]
+.inst 0xce385ed6 //bcax v22.16b,v22.16b,v24.16b,v23.16b
+.inst 0xce3a62f7 //bcax v23.16b,v23.16b,v26.16b, v24.16b
+.inst 0xce286b18 //bcax v24.16b,v24.16b,v8.16b,v26.16b // A[1][3]=A[4][1]
+
+ ld1r {v26.2d},[x10],#8
+
+.inst 0xce330fd1 //bcax v17.16b,v30.16b, v19.16b,v3.16b // A[0][3]=A[3][3]
+.inst 0xce2f4c72 //bcax v18.16b,v3.16b,v15.16b,v19.16b // A[0][3]=A[3][3]
+.inst 0xce303e73 //bcax v19.16b,v19.16b,v16.16b,v15.16b
+.inst 0xce3e41ef //bcax v15.16b,v15.16b,v30.16b, v16.16b
+.inst 0xce237a10 //bcax v16.16b,v16.16b,v3.16b,v30.16b // A[0][3]=A[3][3]
+
+.inst 0xce2c7f2a //bcax v10.16b,v25.16b, v12.16b,v31.16b
+.inst 0xce2d33eb //bcax v11.16b,v31.16b, v13.16b,v12.16b
+.inst 0xce2e358c //bcax v12.16b,v12.16b,v14.16b,v13.16b
+.inst 0xce3939ad //bcax v13.16b,v13.16b,v25.16b, v14.16b
+.inst 0xce3f65ce //bcax v14.16b,v14.16b,v31.16b, v25.16b
+
+.inst 0xce2913a7 //bcax v7.16b,v29.16b, v9.16b,v4.16b // A[0][4]=A[1][3]
+.inst 0xce252488 //bcax v8.16b,v4.16b,v5.16b,v9.16b // A[0][4]=A[1][3]
+.inst 0xce261529 //bcax v9.16b,v9.16b,v6.16b,v5.16b
+.inst 0xce3d18a5 //bcax v5.16b,v5.16b,v29.16b, v6.16b
+.inst 0xce2474c6 //bcax v6.16b,v6.16b,v4.16b,v29.16b // A[0][4]=A[1][3]
+
+.inst 0xce207363 //bcax v3.16b,v27.16b, v0.16b,v28.16b
+.inst 0xce210384 //bcax v4.16b,v28.16b, v1.16b,v0.16b
+.inst 0xce220400 //bcax v0.16b,v0.16b,v2.16b,v1.16b
+.inst 0xce3b0821 //bcax v1.16b,v1.16b,v27.16b, v2.16b
+.inst 0xce3c6c42 //bcax v2.16b,v2.16b,v28.16b, v27.16b
+
+ eor v0.16b,v0.16b,v26.16b
+
+ subs x9,x9,#1
+ bne .Loop_ce
+
+ ret
+.size KeccakF1600_ce,.-KeccakF1600_ce
+
+.type KeccakF1600_cext,%function
+.align 5
+KeccakF1600_cext:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-80]!
+ add x29,sp,#0
+ stp d8,d9,[sp,#16] // per ABI requirement
+ stp d10,d11,[sp,#32]
+ stp d12,d13,[sp,#48]
+ stp d14,d15,[sp,#64]
+ ldp d0,d1,[x0,#8*0]
+ ldp d2,d3,[x0,#8*2]
+ ldp d4,d5,[x0,#8*4]
+ ldp d6,d7,[x0,#8*6]
+ ldp d8,d9,[x0,#8*8]
+ ldp d10,d11,[x0,#8*10]
+ ldp d12,d13,[x0,#8*12]
+ ldp d14,d15,[x0,#8*14]
+ ldp d16,d17,[x0,#8*16]
+ ldp d18,d19,[x0,#8*18]
+ ldp d20,d21,[x0,#8*20]
+ ldp d22,d23,[x0,#8*22]
+ ldr d24,[x0,#8*24]
+ bl KeccakF1600_ce
+ ldr x30,[sp,#8]
+ stp d0,d1,[x0,#8*0]
+ stp d2,d3,[x0,#8*2]
+ stp d4,d5,[x0,#8*4]
+ stp d6,d7,[x0,#8*6]
+ stp d8,d9,[x0,#8*8]
+ stp d10,d11,[x0,#8*10]
+ stp d12,d13,[x0,#8*12]
+ stp d14,d15,[x0,#8*14]
+ stp d16,d17,[x0,#8*16]
+ stp d18,d19,[x0,#8*18]
+ stp d20,d21,[x0,#8*20]
+ stp d22,d23,[x0,#8*22]
+ str d24,[x0,#8*24]
+
+ ldp d8,d9,[sp,#16]
+ ldp d10,d11,[sp,#32]
+ ldp d12,d13,[sp,#48]
+ ldp d14,d15,[sp,#64]
+ ldr x29,[sp],#80
+.inst 0xd50323bf // autiasp
+ ret
+.size KeccakF1600_cext,.-KeccakF1600_cext
+.globl SHA3_absorb_cext
+.type SHA3_absorb_cext,%function
+.align 5
+SHA3_absorb_cext:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-80]!
+ add x29,sp,#0
+ stp d8,d9,[sp,#16] // per ABI requirement
+ stp d10,d11,[sp,#32]
+ stp d12,d13,[sp,#48]
+ stp d14,d15,[sp,#64]
+ ldp d0,d1,[x0,#8*0]
+ ldp d2,d3,[x0,#8*2]
+ ldp d4,d5,[x0,#8*4]
+ ldp d6,d7,[x0,#8*6]
+ ldp d8,d9,[x0,#8*8]
+ ldp d10,d11,[x0,#8*10]
+ ldp d12,d13,[x0,#8*12]
+ ldp d14,d15,[x0,#8*14]
+ ldp d16,d17,[x0,#8*16]
+ ldp d18,d19,[x0,#8*18]
+ ldp d20,d21,[x0,#8*20]
+ ldp d22,d23,[x0,#8*22]
+ ldr d24,[x0,#8*24]
+ b .Loop_absorb_ce
+
+.align 4
+.Loop_absorb_ce:
+ subs x2,x2,x3 // len - bsz
+ blo .Labsorbed_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v0.16b,v0.16b,v31.16b
+ cmp x3,#8*(0+2)
+ blo .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v1.16b,v1.16b,v31.16b
+ beq .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v2.16b,v2.16b,v31.16b
+ cmp x3,#8*(2+2)
+ blo .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v3.16b,v3.16b,v31.16b
+ beq .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v4.16b,v4.16b,v31.16b
+ cmp x3,#8*(4+2)
+ blo .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v5.16b,v5.16b,v31.16b
+ beq .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v6.16b,v6.16b,v31.16b
+ cmp x3,#8*(6+2)
+ blo .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v7.16b,v7.16b,v31.16b
+ beq .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v8.16b,v8.16b,v31.16b
+ cmp x3,#8*(8+2)
+ blo .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v9.16b,v9.16b,v31.16b
+ beq .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v10.16b,v10.16b,v31.16b
+ cmp x3,#8*(10+2)
+ blo .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v11.16b,v11.16b,v31.16b
+ beq .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v12.16b,v12.16b,v31.16b
+ cmp x3,#8*(12+2)
+ blo .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v13.16b,v13.16b,v31.16b
+ beq .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v14.16b,v14.16b,v31.16b
+ cmp x3,#8*(14+2)
+ blo .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v15.16b,v15.16b,v31.16b
+ beq .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v16.16b,v16.16b,v31.16b
+ cmp x3,#8*(16+2)
+ blo .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v17.16b,v17.16b,v31.16b
+ beq .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v18.16b,v18.16b,v31.16b
+ cmp x3,#8*(18+2)
+ blo .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v19.16b,v19.16b,v31.16b
+ beq .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v20.16b,v20.16b,v31.16b
+ cmp x3,#8*(20+2)
+ blo .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v21.16b,v21.16b,v31.16b
+ beq .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v22.16b,v22.16b,v31.16b
+ cmp x3,#8*(22+2)
+ blo .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v23.16b,v23.16b,v31.16b
+ beq .Lprocess_block_ce
+ ldr d31,[x1],#8 // *inp++
+#ifdef __AARCH64EB__
+ rev64 v31.16b,v31.16b
+#endif
+ eor v24.16b,v24.16b,v31.16b
+
+.Lprocess_block_ce:
+
+ bl KeccakF1600_ce
+
+ b .Loop_absorb_ce
+
+.align 4
+.Labsorbed_ce:
+ stp d0,d1,[x0,#8*0]
+ stp d2,d3,[x0,#8*2]
+ stp d4,d5,[x0,#8*4]
+ stp d6,d7,[x0,#8*6]
+ stp d8,d9,[x0,#8*8]
+ stp d10,d11,[x0,#8*10]
+ stp d12,d13,[x0,#8*12]
+ stp d14,d15,[x0,#8*14]
+ stp d16,d17,[x0,#8*16]
+ stp d18,d19,[x0,#8*18]
+ stp d20,d21,[x0,#8*20]
+ stp d22,d23,[x0,#8*22]
+ str d24,[x0,#8*24]
+ add x0,x2,x3 // return value
+
+ ldp d8,d9,[sp,#16]
+ ldp d10,d11,[sp,#32]
+ ldp d12,d13,[sp,#48]
+ ldp d14,d15,[sp,#64]
+ ldp x29,x30,[sp],#80
+.inst 0xd50323bf // autiasp
+ ret
+.size SHA3_absorb_cext,.-SHA3_absorb_cext
+.globl SHA3_squeeze_cext
+.type SHA3_squeeze_cext,%function
+.align 5
+SHA3_squeeze_cext:
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+ mov x9,x0
+ mov x10,x3
+
+.Loop_squeeze_ce:
+ ldr x4,[x9],#8
+ cmp x2,#8
+ blo .Lsqueeze_tail_ce
+#ifdef __AARCH64EB__
+ rev x4,x4
+#endif
+ str x4,[x1],#8
+ beq .Lsqueeze_done_ce
+
+ sub x2,x2,#8
+ subs x10,x10,#8
+ bhi .Loop_squeeze_ce
+
+ bl KeccakF1600_cext
+ ldr x30,[sp,#8]
+ mov x9,x0
+ mov x10,x3
+ b .Loop_squeeze_ce
+
+.align 4
+.Lsqueeze_tail_ce:
+ strb w4,[x1],#1
+ lsr x4,x4,#8
+ subs x2,x2,#1
+ beq .Lsqueeze_done_ce
+ strb w4,[x1],#1
+ lsr x4,x4,#8
+ subs x2,x2,#1
+ beq .Lsqueeze_done_ce
+ strb w4,[x1],#1
+ lsr x4,x4,#8
+ subs x2,x2,#1
+ beq .Lsqueeze_done_ce
+ strb w4,[x1],#1
+ lsr x4,x4,#8
+ subs x2,x2,#1
+ beq .Lsqueeze_done_ce
+ strb w4,[x1],#1
+ lsr x4,x4,#8
+ subs x2,x2,#1
+ beq .Lsqueeze_done_ce
+ strb w4,[x1],#1
+ lsr x4,x4,#8
+ subs x2,x2,#1
+ beq .Lsqueeze_done_ce
+ strb w4,[x1],#1
+
+.Lsqueeze_done_ce:
+ ldr x29,[sp],#16
+.inst 0xd50323bf // autiasp
+ ret
+.size SHA3_squeeze_cext,.-SHA3_squeeze_cext
+.byte 75,101,99,99,97,107,45,49,54,48,48,32,97,98,115,111,114,98,32,97,110,100,32,115,113,117,101,101,122,101,32,102,111,114,32,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
+.align 2
diff --git a/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/sha1-armv8.S b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/sha1-armv8.S
new file mode 100644
index 000000000000..7f6d5be9537f
--- /dev/null
+++ b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/sha1-armv8.S
@@ -0,0 +1,1211 @@
+#ifndef __KERNEL__
+# include "arm_arch.h"
+
+.hidden OPENSSL_armcap_P
+#endif
+
+.text
+
+.globl sha1_block_data_order
+.type sha1_block_data_order,%function
+.align 6
+sha1_block_data_order:
+ adrp x16,OPENSSL_armcap_P
+ ldr w16,[x16,#:lo12:OPENSSL_armcap_P]
+ tst w16,#ARMV8_SHA1
+ b.ne .Lv8_entry
+
+ stp x29,x30,[sp,#-96]!
+ add x29,sp,#0
+ stp x19,x20,[sp,#16]
+ stp x21,x22,[sp,#32]
+ stp x23,x24,[sp,#48]
+ stp x25,x26,[sp,#64]
+ stp x27,x28,[sp,#80]
+
+ ldp w20,w21,[x0]
+ ldp w22,w23,[x0,#8]
+ ldr w24,[x0,#16]
+
+.Loop:
+ ldr x3,[x1],#64
+ movz w28,#0x7999
+ sub x2,x2,#1
+ movk w28,#0x5a82,lsl#16
+#ifdef __AARCH64EB__
+ ror x3,x3,#32
+#else
+ rev32 x3,x3
+#endif
+ add w24,w24,w28 // warm it up
+ add w24,w24,w3
+ lsr x4,x3,#32
+ ldur x5,[x1,#-56]
+ bic w25,w23,w21
+ and w26,w22,w21
+ ror w27,w20,#27
+ add w23,w23,w28 // future e+=K
+ orr w25,w25,w26
+ add w24,w24,w27 // e+=rot(a,5)
+ ror w21,w21,#2
+ add w23,w23,w4 // future e+=X[i]
+ add w24,w24,w25 // e+=F(b,c,d)
+#ifdef __AARCH64EB__
+ ror x5,x5,#32
+#else
+ rev32 x5,x5
+#endif
+ bic w25,w22,w20
+ and w26,w21,w20
+ ror w27,w24,#27
+ add w22,w22,w28 // future e+=K
+ orr w25,w25,w26
+ add w23,w23,w27 // e+=rot(a,5)
+ ror w20,w20,#2
+ add w22,w22,w5 // future e+=X[i]
+ add w23,w23,w25 // e+=F(b,c,d)
+ lsr x6,x5,#32
+ ldur x7,[x1,#-48]
+ bic w25,w21,w24
+ and w26,w20,w24
+ ror w27,w23,#27
+ add w21,w21,w28 // future e+=K
+ orr w25,w25,w26
+ add w22,w22,w27 // e+=rot(a,5)
+ ror w24,w24,#2
+ add w21,w21,w6 // future e+=X[i]
+ add w22,w22,w25 // e+=F(b,c,d)
+#ifdef __AARCH64EB__
+ ror x7,x7,#32
+#else
+ rev32 x7,x7
+#endif
+ bic w25,w20,w23
+ and w26,w24,w23
+ ror w27,w22,#27
+ add w20,w20,w28 // future e+=K
+ orr w25,w25,w26
+ add w21,w21,w27 // e+=rot(a,5)
+ ror w23,w23,#2
+ add w20,w20,w7 // future e+=X[i]
+ add w21,w21,w25 // e+=F(b,c,d)
+ lsr x8,x7,#32
+ ldur x9,[x1,#-40]
+ bic w25,w24,w22
+ and w26,w23,w22
+ ror w27,w21,#27
+ add w24,w24,w28 // future e+=K
+ orr w25,w25,w26
+ add w20,w20,w27 // e+=rot(a,5)
+ ror w22,w22,#2
+ add w24,w24,w8 // future e+=X[i]
+ add w20,w20,w25 // e+=F(b,c,d)
+#ifdef __AARCH64EB__
+ ror x9,x9,#32
+#else
+ rev32 x9,x9
+#endif
+ bic w25,w23,w21
+ and w26,w22,w21
+ ror w27,w20,#27
+ add w23,w23,w28 // future e+=K
+ orr w25,w25,w26
+ add w24,w24,w27 // e+=rot(a,5)
+ ror w21,w21,#2
+ add w23,w23,w9 // future e+=X[i]
+ add w24,w24,w25 // e+=F(b,c,d)
+ lsr x10,x9,#32
+ ldur x11,[x1,#-32]
+ bic w25,w22,w20
+ and w26,w21,w20
+ ror w27,w24,#27
+ add w22,w22,w28 // future e+=K
+ orr w25,w25,w26
+ add w23,w23,w27 // e+=rot(a,5)
+ ror w20,w20,#2
+ add w22,w22,w10 // future e+=X[i]
+ add w23,w23,w25 // e+=F(b,c,d)
+#ifdef __AARCH64EB__
+ ror x11,x11,#32
+#else
+ rev32 x11,x11
+#endif
+ bic w25,w21,w24
+ and w26,w20,w24
+ ror w27,w23,#27
+ add w21,w21,w28 // future e+=K
+ orr w25,w25,w26
+ add w22,w22,w27 // e+=rot(a,5)
+ ror w24,w24,#2
+ add w21,w21,w11 // future e+=X[i]
+ add w22,w22,w25 // e+=F(b,c,d)
+ lsr x12,x11,#32
+ ldur x13,[x1,#-24]
+ bic w25,w20,w23
+ and w26,w24,w23
+ ror w27,w22,#27
+ add w20,w20,w28 // future e+=K
+ orr w25,w25,w26
+ add w21,w21,w27 // e+=rot(a,5)
+ ror w23,w23,#2
+ add w20,w20,w12 // future e+=X[i]
+ add w21,w21,w25 // e+=F(b,c,d)
+#ifdef __AARCH64EB__
+ ror x13,x13,#32
+#else
+ rev32 x13,x13
+#endif
+ bic w25,w24,w22
+ and w26,w23,w22
+ ror w27,w21,#27
+ add w24,w24,w28 // future e+=K
+ orr w25,w25,w26
+ add w20,w20,w27 // e+=rot(a,5)
+ ror w22,w22,#2
+ add w24,w24,w13 // future e+=X[i]
+ add w20,w20,w25 // e+=F(b,c,d)
+ lsr x14,x13,#32
+ ldur x15,[x1,#-16]
+ bic w25,w23,w21
+ and w26,w22,w21
+ ror w27,w20,#27
+ add w23,w23,w28 // future e+=K
+ orr w25,w25,w26
+ add w24,w24,w27 // e+=rot(a,5)
+ ror w21,w21,#2
+ add w23,w23,w14 // future e+=X[i]
+ add w24,w24,w25 // e+=F(b,c,d)
+#ifdef __AARCH64EB__
+ ror x15,x15,#32
+#else
+ rev32 x15,x15
+#endif
+ bic w25,w22,w20
+ and w26,w21,w20
+ ror w27,w24,#27
+ add w22,w22,w28 // future e+=K
+ orr w25,w25,w26
+ add w23,w23,w27 // e+=rot(a,5)
+ ror w20,w20,#2
+ add w22,w22,w15 // future e+=X[i]
+ add w23,w23,w25 // e+=F(b,c,d)
+ lsr x16,x15,#32
+ ldur x17,[x1,#-8]
+ bic w25,w21,w24
+ and w26,w20,w24
+ ror w27,w23,#27
+ add w21,w21,w28 // future e+=K
+ orr w25,w25,w26
+ add w22,w22,w27 // e+=rot(a,5)
+ ror w24,w24,#2
+ add w21,w21,w16 // future e+=X[i]
+ add w22,w22,w25 // e+=F(b,c,d)
+#ifdef __AARCH64EB__
+ ror x17,x17,#32
+#else
+ rev32 x17,x17
+#endif
+ bic w25,w20,w23
+ and w26,w24,w23
+ ror w27,w22,#27
+ add w20,w20,w28 // future e+=K
+ orr w25,w25,w26
+ add w21,w21,w27 // e+=rot(a,5)
+ ror w23,w23,#2
+ add w20,w20,w17 // future e+=X[i]
+ add w21,w21,w25 // e+=F(b,c,d)
+ lsr x19,x17,#32
+ eor w3,w3,w5
+ bic w25,w24,w22
+ and w26,w23,w22
+ ror w27,w21,#27
+ eor w3,w3,w11
+ add w24,w24,w28 // future e+=K
+ orr w25,w25,w26
+ add w20,w20,w27 // e+=rot(a,5)
+ eor w3,w3,w16
+ ror w22,w22,#2
+ add w24,w24,w19 // future e+=X[i]
+ add w20,w20,w25 // e+=F(b,c,d)
+ ror w3,w3,#31
+ eor w4,w4,w6
+ bic w25,w23,w21
+ and w26,w22,w21
+ ror w27,w20,#27
+ eor w4,w4,w12
+ add w23,w23,w28 // future e+=K
+ orr w25,w25,w26
+ add w24,w24,w27 // e+=rot(a,5)
+ eor w4,w4,w17
+ ror w21,w21,#2
+ add w23,w23,w3 // future e+=X[i]
+ add w24,w24,w25 // e+=F(b,c,d)
+ ror w4,w4,#31
+ eor w5,w5,w7
+ bic w25,w22,w20
+ and w26,w21,w20
+ ror w27,w24,#27
+ eor w5,w5,w13
+ add w22,w22,w28 // future e+=K
+ orr w25,w25,w26
+ add w23,w23,w27 // e+=rot(a,5)
+ eor w5,w5,w19
+ ror w20,w20,#2
+ add w22,w22,w4 // future e+=X[i]
+ add w23,w23,w25 // e+=F(b,c,d)
+ ror w5,w5,#31
+ eor w6,w6,w8
+ bic w25,w21,w24
+ and w26,w20,w24
+ ror w27,w23,#27
+ eor w6,w6,w14
+ add w21,w21,w28 // future e+=K
+ orr w25,w25,w26
+ add w22,w22,w27 // e+=rot(a,5)
+ eor w6,w6,w3
+ ror w24,w24,#2
+ add w21,w21,w5 // future e+=X[i]
+ add w22,w22,w25 // e+=F(b,c,d)
+ ror w6,w6,#31
+ eor w7,w7,w9
+ bic w25,w20,w23
+ and w26,w24,w23
+ ror w27,w22,#27
+ eor w7,w7,w15
+ add w20,w20,w28 // future e+=K
+ orr w25,w25,w26
+ add w21,w21,w27 // e+=rot(a,5)
+ eor w7,w7,w4
+ ror w23,w23,#2
+ add w20,w20,w6 // future e+=X[i]
+ add w21,w21,w25 // e+=F(b,c,d)
+ ror w7,w7,#31
+ movz w28,#0xeba1
+ movk w28,#0x6ed9,lsl#16
+ eor w8,w8,w10
+ bic w25,w24,w22
+ and w26,w23,w22
+ ror w27,w21,#27
+ eor w8,w8,w16
+ add w24,w24,w28 // future e+=K
+ orr w25,w25,w26
+ add w20,w20,w27 // e+=rot(a,5)
+ eor w8,w8,w5
+ ror w22,w22,#2
+ add w24,w24,w7 // future e+=X[i]
+ add w20,w20,w25 // e+=F(b,c,d)
+ ror w8,w8,#31
+ eor w9,w9,w11
+ eor w25,w23,w21
+ ror w27,w20,#27
+ add w23,w23,w28 // future e+=K
+ eor w9,w9,w17
+ eor w25,w25,w22
+ add w24,w24,w27 // e+=rot(a,5)
+ ror w21,w21,#2
+ eor w9,w9,w6
+ add w23,w23,w8 // future e+=X[i]
+ add w24,w24,w25 // e+=F(b,c,d)
+ ror w9,w9,#31
+ eor w10,w10,w12
+ eor w25,w22,w20
+ ror w27,w24,#27
+ add w22,w22,w28 // future e+=K
+ eor w10,w10,w19
+ eor w25,w25,w21
+ add w23,w23,w27 // e+=rot(a,5)
+ ror w20,w20,#2
+ eor w10,w10,w7
+ add w22,w22,w9 // future e+=X[i]
+ add w23,w23,w25 // e+=F(b,c,d)
+ ror w10,w10,#31
+ eor w11,w11,w13
+ eor w25,w21,w24
+ ror w27,w23,#27
+ add w21,w21,w28 // future e+=K
+ eor w11,w11,w3
+ eor w25,w25,w20
+ add w22,w22,w27 // e+=rot(a,5)
+ ror w24,w24,#2
+ eor w11,w11,w8
+ add w21,w21,w10 // future e+=X[i]
+ add w22,w22,w25 // e+=F(b,c,d)
+ ror w11,w11,#31
+ eor w12,w12,w14
+ eor w25,w20,w23
+ ror w27,w22,#27
+ add w20,w20,w28 // future e+=K
+ eor w12,w12,w4
+ eor w25,w25,w24
+ add w21,w21,w27 // e+=rot(a,5)
+ ror w23,w23,#2
+ eor w12,w12,w9
+ add w20,w20,w11 // future e+=X[i]
+ add w21,w21,w25 // e+=F(b,c,d)
+ ror w12,w12,#31
+ eor w13,w13,w15
+ eor w25,w24,w22
+ ror w27,w21,#27
+ add w24,w24,w28 // future e+=K
+ eor w13,w13,w5
+ eor w25,w25,w23
+ add w20,w20,w27 // e+=rot(a,5)
+ ror w22,w22,#2
+ eor w13,w13,w10
+ add w24,w24,w12 // future e+=X[i]
+ add w20,w20,w25 // e+=F(b,c,d)
+ ror w13,w13,#31
+ eor w14,w14,w16
+ eor w25,w23,w21
+ ror w27,w20,#27
+ add w23,w23,w28 // future e+=K
+ eor w14,w14,w6
+ eor w25,w25,w22
+ add w24,w24,w27 // e+=rot(a,5)
+ ror w21,w21,#2
+ eor w14,w14,w11
+ add w23,w23,w13 // future e+=X[i]
+ add w24,w24,w25 // e+=F(b,c,d)
+ ror w14,w14,#31
+ eor w15,w15,w17
+ eor w25,w22,w20
+ ror w27,w24,#27
+ add w22,w22,w28 // future e+=K
+ eor w15,w15,w7
+ eor w25,w25,w21
+ add w23,w23,w27 // e+=rot(a,5)
+ ror w20,w20,#2
+ eor w15,w15,w12
+ add w22,w22,w14 // future e+=X[i]
+ add w23,w23,w25 // e+=F(b,c,d)
+ ror w15,w15,#31
+ eor w16,w16,w19
+ eor w25,w21,w24
+ ror w27,w23,#27
+ add w21,w21,w28 // future e+=K
+ eor w16,w16,w8
+ eor w25,w25,w20
+ add w22,w22,w27 // e+=rot(a,5)
+ ror w24,w24,#2
+ eor w16,w16,w13
+ add w21,w21,w15 // future e+=X[i]
+ add w22,w22,w25 // e+=F(b,c,d)
+ ror w16,w16,#31
+ eor w17,w17,w3
+ eor w25,w20,w23
+ ror w27,w22,#27
+ add w20,w20,w28 // future e+=K
+ eor w17,w17,w9
+ eor w25,w25,w24
+ add w21,w21,w27 // e+=rot(a,5)
+ ror w23,w23,#2
+ eor w17,w17,w14
+ add w20,w20,w16 // future e+=X[i]
+ add w21,w21,w25 // e+=F(b,c,d)
+ ror w17,w17,#31
+ eor w19,w19,w4
+ eor w25,w24,w22
+ ror w27,w21,#27
+ add w24,w24,w28 // future e+=K
+ eor w19,w19,w10
+ eor w25,w25,w23
+ add w20,w20,w27 // e+=rot(a,5)
+ ror w22,w22,#2
+ eor w19,w19,w15
+ add w24,w24,w17 // future e+=X[i]
+ add w20,w20,w25 // e+=F(b,c,d)
+ ror w19,w19,#31
+ eor w3,w3,w5
+ eor w25,w23,w21
+ ror w27,w20,#27
+ add w23,w23,w28 // future e+=K
+ eor w3,w3,w11
+ eor w25,w25,w22
+ add w24,w24,w27 // e+=rot(a,5)
+ ror w21,w21,#2
+ eor w3,w3,w16
+ add w23,w23,w19 // future e+=X[i]
+ add w24,w24,w25 // e+=F(b,c,d)
+ ror w3,w3,#31
+ eor w4,w4,w6
+ eor w25,w22,w20
+ ror w27,w24,#27
+ add w22,w22,w28 // future e+=K
+ eor w4,w4,w12
+ eor w25,w25,w21
+ add w23,w23,w27 // e+=rot(a,5)
+ ror w20,w20,#2
+ eor w4,w4,w17
+ add w22,w22,w3 // future e+=X[i]
+ add w23,w23,w25 // e+=F(b,c,d)
+ ror w4,w4,#31
+ eor w5,w5,w7
+ eor w25,w21,w24
+ ror w27,w23,#27
+ add w21,w21,w28 // future e+=K
+ eor w5,w5,w13
+ eor w25,w25,w20
+ add w22,w22,w27 // e+=rot(a,5)
+ ror w24,w24,#2
+ eor w5,w5,w19
+ add w21,w21,w4 // future e+=X[i]
+ add w22,w22,w25 // e+=F(b,c,d)
+ ror w5,w5,#31
+ eor w6,w6,w8
+ eor w25,w20,w23
+ ror w27,w22,#27
+ add w20,w20,w28 // future e+=K
+ eor w6,w6,w14
+ eor w25,w25,w24
+ add w21,w21,w27 // e+=rot(a,5)
+ ror w23,w23,#2
+ eor w6,w6,w3
+ add w20,w20,w5 // future e+=X[i]
+ add w21,w21,w25 // e+=F(b,c,d)
+ ror w6,w6,#31
+ eor w7,w7,w9
+ eor w25,w24,w22
+ ror w27,w21,#27
+ add w24,w24,w28 // future e+=K
+ eor w7,w7,w15
+ eor w25,w25,w23
+ add w20,w20,w27 // e+=rot(a,5)
+ ror w22,w22,#2
+ eor w7,w7,w4
+ add w24,w24,w6 // future e+=X[i]
+ add w20,w20,w25 // e+=F(b,c,d)
+ ror w7,w7,#31
+ eor w8,w8,w10
+ eor w25,w23,w21
+ ror w27,w20,#27
+ add w23,w23,w28 // future e+=K
+ eor w8,w8,w16
+ eor w25,w25,w22
+ add w24,w24,w27 // e+=rot(a,5)
+ ror w21,w21,#2
+ eor w8,w8,w5
+ add w23,w23,w7 // future e+=X[i]
+ add w24,w24,w25 // e+=F(b,c,d)
+ ror w8,w8,#31
+ eor w9,w9,w11
+ eor w25,w22,w20
+ ror w27,w24,#27
+ add w22,w22,w28 // future e+=K
+ eor w9,w9,w17
+ eor w25,w25,w21
+ add w23,w23,w27 // e+=rot(a,5)
+ ror w20,w20,#2
+ eor w9,w9,w6
+ add w22,w22,w8 // future e+=X[i]
+ add w23,w23,w25 // e+=F(b,c,d)
+ ror w9,w9,#31
+ eor w10,w10,w12
+ eor w25,w21,w24
+ ror w27,w23,#27
+ add w21,w21,w28 // future e+=K
+ eor w10,w10,w19
+ eor w25,w25,w20
+ add w22,w22,w27 // e+=rot(a,5)
+ ror w24,w24,#2
+ eor w10,w10,w7
+ add w21,w21,w9 // future e+=X[i]
+ add w22,w22,w25 // e+=F(b,c,d)
+ ror w10,w10,#31
+ eor w11,w11,w13
+ eor w25,w20,w23
+ ror w27,w22,#27
+ add w20,w20,w28 // future e+=K
+ eor w11,w11,w3
+ eor w25,w25,w24
+ add w21,w21,w27 // e+=rot(a,5)
+ ror w23,w23,#2
+ eor w11,w11,w8
+ add w20,w20,w10 // future e+=X[i]
+ add w21,w21,w25 // e+=F(b,c,d)
+ ror w11,w11,#31
+ movz w28,#0xbcdc
+ movk w28,#0x8f1b,lsl#16
+ eor w12,w12,w14
+ eor w25,w24,w22
+ ror w27,w21,#27
+ add w24,w24,w28 // future e+=K
+ eor w12,w12,w4
+ eor w25,w25,w23
+ add w20,w20,w27 // e+=rot(a,5)
+ ror w22,w22,#2
+ eor w12,w12,w9
+ add w24,w24,w11 // future e+=X[i]
+ add w20,w20,w25 // e+=F(b,c,d)
+ ror w12,w12,#31
+ orr w25,w21,w22
+ and w26,w21,w22
+ eor w13,w13,w15
+ ror w27,w20,#27
+ and w25,w25,w23
+ add w23,w23,w28 // future e+=K
+ eor w13,w13,w5
+ add w24,w24,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w21,w21,#2
+ eor w13,w13,w10
+ add w23,w23,w12 // future e+=X[i]
+ add w24,w24,w25 // e+=F(b,c,d)
+ ror w13,w13,#31
+ orr w25,w20,w21
+ and w26,w20,w21
+ eor w14,w14,w16
+ ror w27,w24,#27
+ and w25,w25,w22
+ add w22,w22,w28 // future e+=K
+ eor w14,w14,w6
+ add w23,w23,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w20,w20,#2
+ eor w14,w14,w11
+ add w22,w22,w13 // future e+=X[i]
+ add w23,w23,w25 // e+=F(b,c,d)
+ ror w14,w14,#31
+ orr w25,w24,w20
+ and w26,w24,w20
+ eor w15,w15,w17
+ ror w27,w23,#27
+ and w25,w25,w21
+ add w21,w21,w28 // future e+=K
+ eor w15,w15,w7
+ add w22,w22,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w24,w24,#2
+ eor w15,w15,w12
+ add w21,w21,w14 // future e+=X[i]
+ add w22,w22,w25 // e+=F(b,c,d)
+ ror w15,w15,#31
+ orr w25,w23,w24
+ and w26,w23,w24
+ eor w16,w16,w19
+ ror w27,w22,#27
+ and w25,w25,w20
+ add w20,w20,w28 // future e+=K
+ eor w16,w16,w8
+ add w21,w21,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w23,w23,#2
+ eor w16,w16,w13
+ add w20,w20,w15 // future e+=X[i]
+ add w21,w21,w25 // e+=F(b,c,d)
+ ror w16,w16,#31
+ orr w25,w22,w23
+ and w26,w22,w23
+ eor w17,w17,w3
+ ror w27,w21,#27
+ and w25,w25,w24
+ add w24,w24,w28 // future e+=K
+ eor w17,w17,w9
+ add w20,w20,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w22,w22,#2
+ eor w17,w17,w14
+ add w24,w24,w16 // future e+=X[i]
+ add w20,w20,w25 // e+=F(b,c,d)
+ ror w17,w17,#31
+ orr w25,w21,w22
+ and w26,w21,w22
+ eor w19,w19,w4
+ ror w27,w20,#27
+ and w25,w25,w23
+ add w23,w23,w28 // future e+=K
+ eor w19,w19,w10
+ add w24,w24,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w21,w21,#2
+ eor w19,w19,w15
+ add w23,w23,w17 // future e+=X[i]
+ add w24,w24,w25 // e+=F(b,c,d)
+ ror w19,w19,#31
+ orr w25,w20,w21
+ and w26,w20,w21
+ eor w3,w3,w5
+ ror w27,w24,#27
+ and w25,w25,w22
+ add w22,w22,w28 // future e+=K
+ eor w3,w3,w11
+ add w23,w23,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w20,w20,#2
+ eor w3,w3,w16
+ add w22,w22,w19 // future e+=X[i]
+ add w23,w23,w25 // e+=F(b,c,d)
+ ror w3,w3,#31
+ orr w25,w24,w20
+ and w26,w24,w20
+ eor w4,w4,w6
+ ror w27,w23,#27
+ and w25,w25,w21
+ add w21,w21,w28 // future e+=K
+ eor w4,w4,w12
+ add w22,w22,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w24,w24,#2
+ eor w4,w4,w17
+ add w21,w21,w3 // future e+=X[i]
+ add w22,w22,w25 // e+=F(b,c,d)
+ ror w4,w4,#31
+ orr w25,w23,w24
+ and w26,w23,w24
+ eor w5,w5,w7
+ ror w27,w22,#27
+ and w25,w25,w20
+ add w20,w20,w28 // future e+=K
+ eor w5,w5,w13
+ add w21,w21,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w23,w23,#2
+ eor w5,w5,w19
+ add w20,w20,w4 // future e+=X[i]
+ add w21,w21,w25 // e+=F(b,c,d)
+ ror w5,w5,#31
+ orr w25,w22,w23
+ and w26,w22,w23
+ eor w6,w6,w8
+ ror w27,w21,#27
+ and w25,w25,w24
+ add w24,w24,w28 // future e+=K
+ eor w6,w6,w14
+ add w20,w20,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w22,w22,#2
+ eor w6,w6,w3
+ add w24,w24,w5 // future e+=X[i]
+ add w20,w20,w25 // e+=F(b,c,d)
+ ror w6,w6,#31
+ orr w25,w21,w22
+ and w26,w21,w22
+ eor w7,w7,w9
+ ror w27,w20,#27
+ and w25,w25,w23
+ add w23,w23,w28 // future e+=K
+ eor w7,w7,w15
+ add w24,w24,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w21,w21,#2
+ eor w7,w7,w4
+ add w23,w23,w6 // future e+=X[i]
+ add w24,w24,w25 // e+=F(b,c,d)
+ ror w7,w7,#31
+ orr w25,w20,w21
+ and w26,w20,w21
+ eor w8,w8,w10
+ ror w27,w24,#27
+ and w25,w25,w22
+ add w22,w22,w28 // future e+=K
+ eor w8,w8,w16
+ add w23,w23,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w20,w20,#2
+ eor w8,w8,w5
+ add w22,w22,w7 // future e+=X[i]
+ add w23,w23,w25 // e+=F(b,c,d)
+ ror w8,w8,#31
+ orr w25,w24,w20
+ and w26,w24,w20
+ eor w9,w9,w11
+ ror w27,w23,#27
+ and w25,w25,w21
+ add w21,w21,w28 // future e+=K
+ eor w9,w9,w17
+ add w22,w22,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w24,w24,#2
+ eor w9,w9,w6
+ add w21,w21,w8 // future e+=X[i]
+ add w22,w22,w25 // e+=F(b,c,d)
+ ror w9,w9,#31
+ orr w25,w23,w24
+ and w26,w23,w24
+ eor w10,w10,w12
+ ror w27,w22,#27
+ and w25,w25,w20
+ add w20,w20,w28 // future e+=K
+ eor w10,w10,w19
+ add w21,w21,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w23,w23,#2
+ eor w10,w10,w7
+ add w20,w20,w9 // future e+=X[i]
+ add w21,w21,w25 // e+=F(b,c,d)
+ ror w10,w10,#31
+ orr w25,w22,w23
+ and w26,w22,w23
+ eor w11,w11,w13
+ ror w27,w21,#27
+ and w25,w25,w24
+ add w24,w24,w28 // future e+=K
+ eor w11,w11,w3
+ add w20,w20,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w22,w22,#2
+ eor w11,w11,w8
+ add w24,w24,w10 // future e+=X[i]
+ add w20,w20,w25 // e+=F(b,c,d)
+ ror w11,w11,#31
+ orr w25,w21,w22
+ and w26,w21,w22
+ eor w12,w12,w14
+ ror w27,w20,#27
+ and w25,w25,w23
+ add w23,w23,w28 // future e+=K
+ eor w12,w12,w4
+ add w24,w24,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w21,w21,#2
+ eor w12,w12,w9
+ add w23,w23,w11 // future e+=X[i]
+ add w24,w24,w25 // e+=F(b,c,d)
+ ror w12,w12,#31
+ orr w25,w20,w21
+ and w26,w20,w21
+ eor w13,w13,w15
+ ror w27,w24,#27
+ and w25,w25,w22
+ add w22,w22,w28 // future e+=K
+ eor w13,w13,w5
+ add w23,w23,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w20,w20,#2
+ eor w13,w13,w10
+ add w22,w22,w12 // future e+=X[i]
+ add w23,w23,w25 // e+=F(b,c,d)
+ ror w13,w13,#31
+ orr w25,w24,w20
+ and w26,w24,w20
+ eor w14,w14,w16
+ ror w27,w23,#27
+ and w25,w25,w21
+ add w21,w21,w28 // future e+=K
+ eor w14,w14,w6
+ add w22,w22,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w24,w24,#2
+ eor w14,w14,w11
+ add w21,w21,w13 // future e+=X[i]
+ add w22,w22,w25 // e+=F(b,c,d)
+ ror w14,w14,#31
+ orr w25,w23,w24
+ and w26,w23,w24
+ eor w15,w15,w17
+ ror w27,w22,#27
+ and w25,w25,w20
+ add w20,w20,w28 // future e+=K
+ eor w15,w15,w7
+ add w21,w21,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w23,w23,#2
+ eor w15,w15,w12
+ add w20,w20,w14 // future e+=X[i]
+ add w21,w21,w25 // e+=F(b,c,d)
+ ror w15,w15,#31
+ movz w28,#0xc1d6
+ movk w28,#0xca62,lsl#16
+ orr w25,w22,w23
+ and w26,w22,w23
+ eor w16,w16,w19
+ ror w27,w21,#27
+ and w25,w25,w24
+ add w24,w24,w28 // future e+=K
+ eor w16,w16,w8
+ add w20,w20,w27 // e+=rot(a,5)
+ orr w25,w25,w26
+ ror w22,w22,#2
+ eor w16,w16,w13
+ add w24,w24,w15 // future e+=X[i]
+ add w20,w20,w25 // e+=F(b,c,d)
+ ror w16,w16,#31
+ eor w17,w17,w3
+ eor w25,w23,w21
+ ror w27,w20,#27
+ add w23,w23,w28 // future e+=K
+ eor w17,w17,w9
+ eor w25,w25,w22
+ add w24,w24,w27 // e+=rot(a,5)
+ ror w21,w21,#2
+ eor w17,w17,w14
+ add w23,w23,w16 // future e+=X[i]
+ add w24,w24,w25 // e+=F(b,c,d)
+ ror w17,w17,#31
+ eor w19,w19,w4
+ eor w25,w22,w20
+ ror w27,w24,#27
+ add w22,w22,w28 // future e+=K
+ eor w19,w19,w10
+ eor w25,w25,w21
+ add w23,w23,w27 // e+=rot(a,5)
+ ror w20,w20,#2
+ eor w19,w19,w15
+ add w22,w22,w17 // future e+=X[i]
+ add w23,w23,w25 // e+=F(b,c,d)
+ ror w19,w19,#31
+ eor w3,w3,w5
+ eor w25,w21,w24
+ ror w27,w23,#27
+ add w21,w21,w28 // future e+=K
+ eor w3,w3,w11
+ eor w25,w25,w20
+ add w22,w22,w27 // e+=rot(a,5)
+ ror w24,w24,#2
+ eor w3,w3,w16
+ add w21,w21,w19 // future e+=X[i]
+ add w22,w22,w25 // e+=F(b,c,d)
+ ror w3,w3,#31
+ eor w4,w4,w6
+ eor w25,w20,w23
+ ror w27,w22,#27
+ add w20,w20,w28 // future e+=K
+ eor w4,w4,w12
+ eor w25,w25,w24
+ add w21,w21,w27 // e+=rot(a,5)
+ ror w23,w23,#2
+ eor w4,w4,w17
+ add w20,w20,w3 // future e+=X[i]
+ add w21,w21,w25 // e+=F(b,c,d)
+ ror w4,w4,#31
+ eor w5,w5,w7
+ eor w25,w24,w22
+ ror w27,w21,#27
+ add w24,w24,w28 // future e+=K
+ eor w5,w5,w13
+ eor w25,w25,w23
+ add w20,w20,w27 // e+=rot(a,5)
+ ror w22,w22,#2
+ eor w5,w5,w19
+ add w24,w24,w4 // future e+=X[i]
+ add w20,w20,w25 // e+=F(b,c,d)
+ ror w5,w5,#31
+ eor w6,w6,w8
+ eor w25,w23,w21
+ ror w27,w20,#27
+ add w23,w23,w28 // future e+=K
+ eor w6,w6,w14
+ eor w25,w25,w22
+ add w24,w24,w27 // e+=rot(a,5)
+ ror w21,w21,#2
+ eor w6,w6,w3
+ add w23,w23,w5 // future e+=X[i]
+ add w24,w24,w25 // e+=F(b,c,d)
+ ror w6,w6,#31
+ eor w7,w7,w9
+ eor w25,w22,w20
+ ror w27,w24,#27
+ add w22,w22,w28 // future e+=K
+ eor w7,w7,w15
+ eor w25,w25,w21
+ add w23,w23,w27 // e+=rot(a,5)
+ ror w20,w20,#2
+ eor w7,w7,w4
+ add w22,w22,w6 // future e+=X[i]
+ add w23,w23,w25 // e+=F(b,c,d)
+ ror w7,w7,#31
+ eor w8,w8,w10
+ eor w25,w21,w24
+ ror w27,w23,#27
+ add w21,w21,w28 // future e+=K
+ eor w8,w8,w16
+ eor w25,w25,w20
+ add w22,w22,w27 // e+=rot(a,5)
+ ror w24,w24,#2
+ eor w8,w8,w5
+ add w21,w21,w7 // future e+=X[i]
+ add w22,w22,w25 // e+=F(b,c,d)
+ ror w8,w8,#31
+ eor w9,w9,w11
+ eor w25,w20,w23
+ ror w27,w22,#27
+ add w20,w20,w28 // future e+=K
+ eor w9,w9,w17
+ eor w25,w25,w24
+ add w21,w21,w27 // e+=rot(a,5)
+ ror w23,w23,#2
+ eor w9,w9,w6
+ add w20,w20,w8 // future e+=X[i]
+ add w21,w21,w25 // e+=F(b,c,d)
+ ror w9,w9,#31
+ eor w10,w10,w12
+ eor w25,w24,w22
+ ror w27,w21,#27
+ add w24,w24,w28 // future e+=K
+ eor w10,w10,w19
+ eor w25,w25,w23
+ add w20,w20,w27 // e+=rot(a,5)
+ ror w22,w22,#2
+ eor w10,w10,w7
+ add w24,w24,w9 // future e+=X[i]
+ add w20,w20,w25 // e+=F(b,c,d)
+ ror w10,w10,#31
+ eor w11,w11,w13
+ eor w25,w23,w21
+ ror w27,w20,#27
+ add w23,w23,w28 // future e+=K
+ eor w11,w11,w3
+ eor w25,w25,w22
+ add w24,w24,w27 // e+=rot(a,5)
+ ror w21,w21,#2
+ eor w11,w11,w8
+ add w23,w23,w10 // future e+=X[i]
+ add w24,w24,w25 // e+=F(b,c,d)
+ ror w11,w11,#31
+ eor w12,w12,w14
+ eor w25,w22,w20
+ ror w27,w24,#27
+ add w22,w22,w28 // future e+=K
+ eor w12,w12,w4
+ eor w25,w25,w21
+ add w23,w23,w27 // e+=rot(a,5)
+ ror w20,w20,#2
+ eor w12,w12,w9
+ add w22,w22,w11 // future e+=X[i]
+ add w23,w23,w25 // e+=F(b,c,d)
+ ror w12,w12,#31
+ eor w13,w13,w15
+ eor w25,w21,w24
+ ror w27,w23,#27
+ add w21,w21,w28 // future e+=K
+ eor w13,w13,w5
+ eor w25,w25,w20
+ add w22,w22,w27 // e+=rot(a,5)
+ ror w24,w24,#2
+ eor w13,w13,w10
+ add w21,w21,w12 // future e+=X[i]
+ add w22,w22,w25 // e+=F(b,c,d)
+ ror w13,w13,#31
+ eor w14,w14,w16
+ eor w25,w20,w23
+ ror w27,w22,#27
+ add w20,w20,w28 // future e+=K
+ eor w14,w14,w6
+ eor w25,w25,w24
+ add w21,w21,w27 // e+=rot(a,5)
+ ror w23,w23,#2
+ eor w14,w14,w11
+ add w20,w20,w13 // future e+=X[i]
+ add w21,w21,w25 // e+=F(b,c,d)
+ ror w14,w14,#31
+ eor w15,w15,w17
+ eor w25,w24,w22
+ ror w27,w21,#27
+ add w24,w24,w28 // future e+=K
+ eor w15,w15,w7
+ eor w25,w25,w23
+ add w20,w20,w27 // e+=rot(a,5)
+ ror w22,w22,#2
+ eor w15,w15,w12
+ add w24,w24,w14 // future e+=X[i]
+ add w20,w20,w25 // e+=F(b,c,d)
+ ror w15,w15,#31
+ eor w16,w16,w19
+ eor w25,w23,w21
+ ror w27,w20,#27
+ add w23,w23,w28 // future e+=K
+ eor w16,w16,w8
+ eor w25,w25,w22
+ add w24,w24,w27 // e+=rot(a,5)
+ ror w21,w21,#2
+ eor w16,w16,w13
+ add w23,w23,w15 // future e+=X[i]
+ add w24,w24,w25 // e+=F(b,c,d)
+ ror w16,w16,#31
+ eor w17,w17,w3
+ eor w25,w22,w20
+ ror w27,w24,#27
+ add w22,w22,w28 // future e+=K
+ eor w17,w17,w9
+ eor w25,w25,w21
+ add w23,w23,w27 // e+=rot(a,5)
+ ror w20,w20,#2
+ eor w17,w17,w14
+ add w22,w22,w16 // future e+=X[i]
+ add w23,w23,w25 // e+=F(b,c,d)
+ ror w17,w17,#31
+ eor w19,w19,w4
+ eor w25,w21,w24
+ ror w27,w23,#27
+ add w21,w21,w28 // future e+=K
+ eor w19,w19,w10
+ eor w25,w25,w20
+ add w22,w22,w27 // e+=rot(a,5)
+ ror w24,w24,#2
+ eor w19,w19,w15
+ add w21,w21,w17 // future e+=X[i]
+ add w22,w22,w25 // e+=F(b,c,d)
+ ror w19,w19,#31
+ ldp w4,w5,[x0]
+ eor w25,w20,w23
+ ror w27,w22,#27
+ add w20,w20,w28 // future e+=K
+ eor w25,w25,w24
+ add w21,w21,w27 // e+=rot(a,5)
+ ror w23,w23,#2
+ add w20,w20,w19 // future e+=X[i]
+ add w21,w21,w25 // e+=F(b,c,d)
+ ldp w6,w7,[x0,#8]
+ eor w25,w24,w22
+ ror w27,w21,#27
+ eor w25,w25,w23
+ add w20,w20,w27 // e+=rot(a,5)
+ ror w22,w22,#2
+ ldr w8,[x0,#16]
+ add w20,w20,w25 // e+=F(b,c,d)
+ add w21,w21,w5
+ add w22,w22,w6
+ add w20,w20,w4
+ add w23,w23,w7
+ add w24,w24,w8
+ stp w20,w21,[x0]
+ stp w22,w23,[x0,#8]
+ str w24,[x0,#16]
+ cbnz x2,.Loop
+
+ ldp x19,x20,[sp,#16]
+ ldp x21,x22,[sp,#32]
+ ldp x23,x24,[sp,#48]
+ ldp x25,x26,[sp,#64]
+ ldp x27,x28,[sp,#80]
+ ldr x29,[sp],#96
+ ret
+.size sha1_block_data_order,.-sha1_block_data_order
+.type sha1_block_armv8,%function
+.align 6
+sha1_block_armv8:
+.Lv8_entry:
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+
+ adr x4,.Lconst
+ eor v1.16b,v1.16b,v1.16b
+ ld1 {v0.4s},[x0],#16
+ ld1 {v1.s}[0],[x0]
+ sub x0,x0,#16
+ ld1 {v16.4s,v17.4s,v18.4s,v19.4s},[x4]
+
+.Loop_hw:
+ ld1 {v4.16b,v5.16b,v6.16b,v7.16b},[x1],#64
+ sub x2,x2,#1
+ rev32 v4.16b,v4.16b
+ rev32 v5.16b,v5.16b
+
+ add v20.4s,v16.4s,v4.4s
+ rev32 v6.16b,v6.16b
+ orr v22.16b,v0.16b,v0.16b // offload
+
+ add v21.4s,v16.4s,v5.4s
+ rev32 v7.16b,v7.16b
+.inst 0x5e280803 //sha1h v3.16b,v0.16b
+.inst 0x5e140020 //sha1c v0.16b,v1.16b,v20.4s // 0
+ add v20.4s,v16.4s,v6.4s
+.inst 0x5e0630a4 //sha1su0 v4.16b,v5.16b,v6.16b
+.inst 0x5e280802 //sha1h v2.16b,v0.16b // 1
+.inst 0x5e150060 //sha1c v0.16b,v3.16b,v21.4s
+ add v21.4s,v16.4s,v7.4s
+.inst 0x5e2818e4 //sha1su1 v4.16b,v7.16b
+.inst 0x5e0730c5 //sha1su0 v5.16b,v6.16b,v7.16b
+.inst 0x5e280803 //sha1h v3.16b,v0.16b // 2
+.inst 0x5e140040 //sha1c v0.16b,v2.16b,v20.4s
+ add v20.4s,v16.4s,v4.4s
+.inst 0x5e281885 //sha1su1 v5.16b,v4.16b
+.inst 0x5e0430e6 //sha1su0 v6.16b,v7.16b,v4.16b
+.inst 0x5e280802 //sha1h v2.16b,v0.16b // 3
+.inst 0x5e150060 //sha1c v0.16b,v3.16b,v21.4s
+ add v21.4s,v17.4s,v5.4s
+.inst 0x5e2818a6 //sha1su1 v6.16b,v5.16b
+.inst 0x5e053087 //sha1su0 v7.16b,v4.16b,v5.16b
+.inst 0x5e280803 //sha1h v3.16b,v0.16b // 4
+.inst 0x5e140040 //sha1c v0.16b,v2.16b,v20.4s
+ add v20.4s,v17.4s,v6.4s
+.inst 0x5e2818c7 //sha1su1 v7.16b,v6.16b
+.inst 0x5e0630a4 //sha1su0 v4.16b,v5.16b,v6.16b
+.inst 0x5e280802 //sha1h v2.16b,v0.16b // 5
+.inst 0x5e151060 //sha1p v0.16b,v3.16b,v21.4s
+ add v21.4s,v17.4s,v7.4s
+.inst 0x5e2818e4 //sha1su1 v4.16b,v7.16b
+.inst 0x5e0730c5 //sha1su0 v5.16b,v6.16b,v7.16b
+.inst 0x5e280803 //sha1h v3.16b,v0.16b // 6
+.inst 0x5e141040 //sha1p v0.16b,v2.16b,v20.4s
+ add v20.4s,v17.4s,v4.4s
+.inst 0x5e281885 //sha1su1 v5.16b,v4.16b
+.inst 0x5e0430e6 //sha1su0 v6.16b,v7.16b,v4.16b
+.inst 0x5e280802 //sha1h v2.16b,v0.16b // 7
+.inst 0x5e151060 //sha1p v0.16b,v3.16b,v21.4s
+ add v21.4s,v17.4s,v5.4s
+.inst 0x5e2818a6 //sha1su1 v6.16b,v5.16b
+.inst 0x5e053087 //sha1su0 v7.16b,v4.16b,v5.16b
+.inst 0x5e280803 //sha1h v3.16b,v0.16b // 8
+.inst 0x5e141040 //sha1p v0.16b,v2.16b,v20.4s
+ add v20.4s,v18.4s,v6.4s
+.inst 0x5e2818c7 //sha1su1 v7.16b,v6.16b
+.inst 0x5e0630a4 //sha1su0 v4.16b,v5.16b,v6.16b
+.inst 0x5e280802 //sha1h v2.16b,v0.16b // 9
+.inst 0x5e151060 //sha1p v0.16b,v3.16b,v21.4s
+ add v21.4s,v18.4s,v7.4s
+.inst 0x5e2818e4 //sha1su1 v4.16b,v7.16b
+.inst 0x5e0730c5 //sha1su0 v5.16b,v6.16b,v7.16b
+.inst 0x5e280803 //sha1h v3.16b,v0.16b // 10
+.inst 0x5e142040 //sha1m v0.16b,v2.16b,v20.4s
+ add v20.4s,v18.4s,v4.4s
+.inst 0x5e281885 //sha1su1 v5.16b,v4.16b
+.inst 0x5e0430e6 //sha1su0 v6.16b,v7.16b,v4.16b
+.inst 0x5e280802 //sha1h v2.16b,v0.16b // 11
+.inst 0x5e152060 //sha1m v0.16b,v3.16b,v21.4s
+ add v21.4s,v18.4s,v5.4s
+.inst 0x5e2818a6 //sha1su1 v6.16b,v5.16b
+.inst 0x5e053087 //sha1su0 v7.16b,v4.16b,v5.16b
+.inst 0x5e280803 //sha1h v3.16b,v0.16b // 12
+.inst 0x5e142040 //sha1m v0.16b,v2.16b,v20.4s
+ add v20.4s,v18.4s,v6.4s
+.inst 0x5e2818c7 //sha1su1 v7.16b,v6.16b
+.inst 0x5e0630a4 //sha1su0 v4.16b,v5.16b,v6.16b
+.inst 0x5e280802 //sha1h v2.16b,v0.16b // 13
+.inst 0x5e152060 //sha1m v0.16b,v3.16b,v21.4s
+ add v21.4s,v19.4s,v7.4s
+.inst 0x5e2818e4 //sha1su1 v4.16b,v7.16b
+.inst 0x5e0730c5 //sha1su0 v5.16b,v6.16b,v7.16b
+.inst 0x5e280803 //sha1h v3.16b,v0.16b // 14
+.inst 0x5e142040 //sha1m v0.16b,v2.16b,v20.4s
+ add v20.4s,v19.4s,v4.4s
+.inst 0x5e281885 //sha1su1 v5.16b,v4.16b
+.inst 0x5e0430e6 //sha1su0 v6.16b,v7.16b,v4.16b
+.inst 0x5e280802 //sha1h v2.16b,v0.16b // 15
+.inst 0x5e151060 //sha1p v0.16b,v3.16b,v21.4s
+ add v21.4s,v19.4s,v5.4s
+.inst 0x5e2818a6 //sha1su1 v6.16b,v5.16b
+.inst 0x5e053087 //sha1su0 v7.16b,v4.16b,v5.16b
+.inst 0x5e280803 //sha1h v3.16b,v0.16b // 16
+.inst 0x5e141040 //sha1p v0.16b,v2.16b,v20.4s
+ add v20.4s,v19.4s,v6.4s
+.inst 0x5e2818c7 //sha1su1 v7.16b,v6.16b
+.inst 0x5e280802 //sha1h v2.16b,v0.16b // 17
+.inst 0x5e151060 //sha1p v0.16b,v3.16b,v21.4s
+ add v21.4s,v19.4s,v7.4s
+
+.inst 0x5e280803 //sha1h v3.16b,v0.16b // 18
+.inst 0x5e141040 //sha1p v0.16b,v2.16b,v20.4s
+
+.inst 0x5e280802 //sha1h v2.16b,v0.16b // 19
+.inst 0x5e151060 //sha1p v0.16b,v3.16b,v21.4s
+
+ add v1.4s,v1.4s,v2.4s
+ add v0.4s,v0.4s,v22.4s
+
+ cbnz x2,.Loop_hw
+
+ st1 {v0.4s},[x0],#16
+ st1 {v1.s}[0],[x0]
+
+ ldr x29,[sp],#16
+ ret
+.size sha1_block_armv8,.-sha1_block_armv8
+.align 6
+.Lconst:
+.long 0x5a827999,0x5a827999,0x5a827999,0x5a827999 //K_00_19
+.long 0x6ed9eba1,0x6ed9eba1,0x6ed9eba1,0x6ed9eba1 //K_20_39
+.long 0x8f1bbcdc,0x8f1bbcdc,0x8f1bbcdc,0x8f1bbcdc //K_40_59
+.long 0xca62c1d6,0xca62c1d6,0xca62c1d6,0xca62c1d6 //K_60_79
+.byte 83,72,65,49,32,98,108,111,99,107,32,116,114,97,110,115,102,111,114,109,32,102,111,114,32,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
+.align 2
+.align 2
diff --git a/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/sha256-armv8.S b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/sha256-armv8.S
new file mode 100644
index 000000000000..f762580f0932
--- /dev/null
+++ b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/sha256-armv8.S
@@ -0,0 +1,2051 @@
+// Copyright 2014-2020 The OpenSSL Project Authors. All Rights Reserved.
+//
+// Licensed under the Apache License 2.0 (the "License"). You may not use
+// this file except in compliance with the License. You can obtain a copy
+// in the file LICENSE in the source distribution or at
+// https://www.openssl.org/source/license.html
+
+// ====================================================================
+// Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
+// project. The module is, however, dual licensed under OpenSSL and
+// CRYPTOGAMS licenses depending on where you obtain it. For further
+// details see http://www.openssl.org/~appro/cryptogams/.
+//
+// Permission to use under GPLv2 terms is granted.
+// ====================================================================
+//
+// SHA256/512 for ARMv8.
+//
+// Performance in cycles per processed byte and improvement coefficient
+// over code generated with "default" compiler:
+//
+// SHA256-hw SHA256(*) SHA512
+// Apple A7 1.97 10.5 (+33%) 6.73 (-1%(**))
+// Cortex-A53 2.38 15.5 (+115%) 10.0 (+150%(***))
+// Cortex-A57 2.31 11.6 (+86%) 7.51 (+260%(***))
+// Denver 2.01 10.5 (+26%) 6.70 (+8%)
+// X-Gene 20.0 (+100%) 12.8 (+300%(***))
+// Mongoose 2.36 13.0 (+50%) 8.36 (+33%)
+// Kryo 1.92 17.4 (+30%) 11.2 (+8%)
+// ThunderX2 2.54 13.2 (+40%) 8.40 (+18%)
+//
+// (*) Software SHA256 results are of lesser relevance, presented
+// mostly for informational purposes.
+// (**) The result is a trade-off: it's possible to improve it by
+// 10% (or by 1 cycle per round), but at the cost of 20% loss
+// on Cortex-A53 (or by 4 cycles per round).
+// (***) Super-impressive coefficients over gcc-generated code are
+// indication of some compiler "pathology", most notably code
+// generated with -mgeneral-regs-only is significantly faster
+// and the gap is only 40-90%.
+//
+// October 2016.
+//
+// Originally it was reckoned that it makes no sense to implement NEON
+// version of SHA256 for 64-bit processors. This is because performance
+// improvement on most wide-spread Cortex-A5x processors was observed
+// to be marginal, same on Cortex-A53 and ~10% on A57. But then it was
+// observed that 32-bit NEON SHA256 performs significantly better than
+// 64-bit scalar version on *some* of the more recent processors. As
+// result 64-bit NEON version of SHA256 was added to provide best
+// all-round performance. For example it executes ~30% faster on X-Gene
+// and Mongoose. [For reference, NEON version of SHA512 is bound to
+// deliver much less improvement, likely *negative* on Cortex-A5x.
+// Which is why NEON support is limited to SHA256.]
+
+// $output is the last argument if it looks like a file (it has an extension)
+// $flavour is the first argument if it doesn't look like a file
+#ifndef __KERNEL__
+# include "arm_arch.h"
+
+.hidden OPENSSL_armcap_P
+#endif
+
+.text
+
+.globl sha256_block_data_order
+.type sha256_block_data_order,%function
+.align 6
+sha256_block_data_order:
+#ifndef __KERNEL__
+ adrp x16,OPENSSL_armcap_P
+ ldr w16,[x16,#:lo12:OPENSSL_armcap_P]
+ tst w16,#ARMV8_SHA256
+ b.ne .Lv8_entry
+ tst w16,#ARMV7_NEON
+ b.ne .Lneon_entry
+#endif
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-128]!
+ add x29,sp,#0
+
+ stp x19,x20,[sp,#16]
+ stp x21,x22,[sp,#32]
+ stp x23,x24,[sp,#48]
+ stp x25,x26,[sp,#64]
+ stp x27,x28,[sp,#80]
+ sub sp,sp,#4*4
+
+ ldp w20,w21,[x0] // load context
+ ldp w22,w23,[x0,#2*4]
+ ldp w24,w25,[x0,#4*4]
+ add x2,x1,x2,lsl#6 // end of input
+ ldp w26,w27,[x0,#6*4]
+ adr x30,.LK256
+ stp x0,x2,[x29,#96]
+
+.Loop:
+ ldp w3,w4,[x1],#2*4
+ ldr w19,[x30],#4 // *K++
+ eor w28,w21,w22 // magic seed
+ str x1,[x29,#112]
+#ifndef __AARCH64EB__
+ rev w3,w3 // 0
+#endif
+ ror w16,w24,#6
+ add w27,w27,w19 // h+=K[i]
+ eor w6,w24,w24,ror#14
+ and w17,w25,w24
+ bic w19,w26,w24
+ add w27,w27,w3 // h+=X[i]
+ orr w17,w17,w19 // Ch(e,f,g)
+ eor w19,w20,w21 // a^b, b^c in next round
+ eor w16,w16,w6,ror#11 // Sigma1(e)
+ ror w6,w20,#2
+ add w27,w27,w17 // h+=Ch(e,f,g)
+ eor w17,w20,w20,ror#9
+ add w27,w27,w16 // h+=Sigma1(e)
+ and w28,w28,w19 // (b^c)&=(a^b)
+ add w23,w23,w27 // d+=h
+ eor w28,w28,w21 // Maj(a,b,c)
+ eor w17,w6,w17,ror#13 // Sigma0(a)
+ add w27,w27,w28 // h+=Maj(a,b,c)
+ ldr w28,[x30],#4 // *K++, w19 in next round
+ //add w27,w27,w17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev w4,w4 // 1
+#endif
+ ldp w5,w6,[x1],#2*4
+ add w27,w27,w17 // h+=Sigma0(a)
+ ror w16,w23,#6
+ add w26,w26,w28 // h+=K[i]
+ eor w7,w23,w23,ror#14
+ and w17,w24,w23
+ bic w28,w25,w23
+ add w26,w26,w4 // h+=X[i]
+ orr w17,w17,w28 // Ch(e,f,g)
+ eor w28,w27,w20 // a^b, b^c in next round
+ eor w16,w16,w7,ror#11 // Sigma1(e)
+ ror w7,w27,#2
+ add w26,w26,w17 // h+=Ch(e,f,g)
+ eor w17,w27,w27,ror#9
+ add w26,w26,w16 // h+=Sigma1(e)
+ and w19,w19,w28 // (b^c)&=(a^b)
+ add w22,w22,w26 // d+=h
+ eor w19,w19,w20 // Maj(a,b,c)
+ eor w17,w7,w17,ror#13 // Sigma0(a)
+ add w26,w26,w19 // h+=Maj(a,b,c)
+ ldr w19,[x30],#4 // *K++, w28 in next round
+ //add w26,w26,w17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev w5,w5 // 2
+#endif
+ add w26,w26,w17 // h+=Sigma0(a)
+ ror w16,w22,#6
+ add w25,w25,w19 // h+=K[i]
+ eor w8,w22,w22,ror#14
+ and w17,w23,w22
+ bic w19,w24,w22
+ add w25,w25,w5 // h+=X[i]
+ orr w17,w17,w19 // Ch(e,f,g)
+ eor w19,w26,w27 // a^b, b^c in next round
+ eor w16,w16,w8,ror#11 // Sigma1(e)
+ ror w8,w26,#2
+ add w25,w25,w17 // h+=Ch(e,f,g)
+ eor w17,w26,w26,ror#9
+ add w25,w25,w16 // h+=Sigma1(e)
+ and w28,w28,w19 // (b^c)&=(a^b)
+ add w21,w21,w25 // d+=h
+ eor w28,w28,w27 // Maj(a,b,c)
+ eor w17,w8,w17,ror#13 // Sigma0(a)
+ add w25,w25,w28 // h+=Maj(a,b,c)
+ ldr w28,[x30],#4 // *K++, w19 in next round
+ //add w25,w25,w17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev w6,w6 // 3
+#endif
+ ldp w7,w8,[x1],#2*4
+ add w25,w25,w17 // h+=Sigma0(a)
+ ror w16,w21,#6
+ add w24,w24,w28 // h+=K[i]
+ eor w9,w21,w21,ror#14
+ and w17,w22,w21
+ bic w28,w23,w21
+ add w24,w24,w6 // h+=X[i]
+ orr w17,w17,w28 // Ch(e,f,g)
+ eor w28,w25,w26 // a^b, b^c in next round
+ eor w16,w16,w9,ror#11 // Sigma1(e)
+ ror w9,w25,#2
+ add w24,w24,w17 // h+=Ch(e,f,g)
+ eor w17,w25,w25,ror#9
+ add w24,w24,w16 // h+=Sigma1(e)
+ and w19,w19,w28 // (b^c)&=(a^b)
+ add w20,w20,w24 // d+=h
+ eor w19,w19,w26 // Maj(a,b,c)
+ eor w17,w9,w17,ror#13 // Sigma0(a)
+ add w24,w24,w19 // h+=Maj(a,b,c)
+ ldr w19,[x30],#4 // *K++, w28 in next round
+ //add w24,w24,w17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev w7,w7 // 4
+#endif
+ add w24,w24,w17 // h+=Sigma0(a)
+ ror w16,w20,#6
+ add w23,w23,w19 // h+=K[i]
+ eor w10,w20,w20,ror#14
+ and w17,w21,w20
+ bic w19,w22,w20
+ add w23,w23,w7 // h+=X[i]
+ orr w17,w17,w19 // Ch(e,f,g)
+ eor w19,w24,w25 // a^b, b^c in next round
+ eor w16,w16,w10,ror#11 // Sigma1(e)
+ ror w10,w24,#2
+ add w23,w23,w17 // h+=Ch(e,f,g)
+ eor w17,w24,w24,ror#9
+ add w23,w23,w16 // h+=Sigma1(e)
+ and w28,w28,w19 // (b^c)&=(a^b)
+ add w27,w27,w23 // d+=h
+ eor w28,w28,w25 // Maj(a,b,c)
+ eor w17,w10,w17,ror#13 // Sigma0(a)
+ add w23,w23,w28 // h+=Maj(a,b,c)
+ ldr w28,[x30],#4 // *K++, w19 in next round
+ //add w23,w23,w17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev w8,w8 // 5
+#endif
+ ldp w9,w10,[x1],#2*4
+ add w23,w23,w17 // h+=Sigma0(a)
+ ror w16,w27,#6
+ add w22,w22,w28 // h+=K[i]
+ eor w11,w27,w27,ror#14
+ and w17,w20,w27
+ bic w28,w21,w27
+ add w22,w22,w8 // h+=X[i]
+ orr w17,w17,w28 // Ch(e,f,g)
+ eor w28,w23,w24 // a^b, b^c in next round
+ eor w16,w16,w11,ror#11 // Sigma1(e)
+ ror w11,w23,#2
+ add w22,w22,w17 // h+=Ch(e,f,g)
+ eor w17,w23,w23,ror#9
+ add w22,w22,w16 // h+=Sigma1(e)
+ and w19,w19,w28 // (b^c)&=(a^b)
+ add w26,w26,w22 // d+=h
+ eor w19,w19,w24 // Maj(a,b,c)
+ eor w17,w11,w17,ror#13 // Sigma0(a)
+ add w22,w22,w19 // h+=Maj(a,b,c)
+ ldr w19,[x30],#4 // *K++, w28 in next round
+ //add w22,w22,w17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev w9,w9 // 6
+#endif
+ add w22,w22,w17 // h+=Sigma0(a)
+ ror w16,w26,#6
+ add w21,w21,w19 // h+=K[i]
+ eor w12,w26,w26,ror#14
+ and w17,w27,w26
+ bic w19,w20,w26
+ add w21,w21,w9 // h+=X[i]
+ orr w17,w17,w19 // Ch(e,f,g)
+ eor w19,w22,w23 // a^b, b^c in next round
+ eor w16,w16,w12,ror#11 // Sigma1(e)
+ ror w12,w22,#2
+ add w21,w21,w17 // h+=Ch(e,f,g)
+ eor w17,w22,w22,ror#9
+ add w21,w21,w16 // h+=Sigma1(e)
+ and w28,w28,w19 // (b^c)&=(a^b)
+ add w25,w25,w21 // d+=h
+ eor w28,w28,w23 // Maj(a,b,c)
+ eor w17,w12,w17,ror#13 // Sigma0(a)
+ add w21,w21,w28 // h+=Maj(a,b,c)
+ ldr w28,[x30],#4 // *K++, w19 in next round
+ //add w21,w21,w17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev w10,w10 // 7
+#endif
+ ldp w11,w12,[x1],#2*4
+ add w21,w21,w17 // h+=Sigma0(a)
+ ror w16,w25,#6
+ add w20,w20,w28 // h+=K[i]
+ eor w13,w25,w25,ror#14
+ and w17,w26,w25
+ bic w28,w27,w25
+ add w20,w20,w10 // h+=X[i]
+ orr w17,w17,w28 // Ch(e,f,g)
+ eor w28,w21,w22 // a^b, b^c in next round
+ eor w16,w16,w13,ror#11 // Sigma1(e)
+ ror w13,w21,#2
+ add w20,w20,w17 // h+=Ch(e,f,g)
+ eor w17,w21,w21,ror#9
+ add w20,w20,w16 // h+=Sigma1(e)
+ and w19,w19,w28 // (b^c)&=(a^b)
+ add w24,w24,w20 // d+=h
+ eor w19,w19,w22 // Maj(a,b,c)
+ eor w17,w13,w17,ror#13 // Sigma0(a)
+ add w20,w20,w19 // h+=Maj(a,b,c)
+ ldr w19,[x30],#4 // *K++, w28 in next round
+ //add w20,w20,w17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev w11,w11 // 8
+#endif
+ add w20,w20,w17 // h+=Sigma0(a)
+ ror w16,w24,#6
+ add w27,w27,w19 // h+=K[i]
+ eor w14,w24,w24,ror#14
+ and w17,w25,w24
+ bic w19,w26,w24
+ add w27,w27,w11 // h+=X[i]
+ orr w17,w17,w19 // Ch(e,f,g)
+ eor w19,w20,w21 // a^b, b^c in next round
+ eor w16,w16,w14,ror#11 // Sigma1(e)
+ ror w14,w20,#2
+ add w27,w27,w17 // h+=Ch(e,f,g)
+ eor w17,w20,w20,ror#9
+ add w27,w27,w16 // h+=Sigma1(e)
+ and w28,w28,w19 // (b^c)&=(a^b)
+ add w23,w23,w27 // d+=h
+ eor w28,w28,w21 // Maj(a,b,c)
+ eor w17,w14,w17,ror#13 // Sigma0(a)
+ add w27,w27,w28 // h+=Maj(a,b,c)
+ ldr w28,[x30],#4 // *K++, w19 in next round
+ //add w27,w27,w17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev w12,w12 // 9
+#endif
+ ldp w13,w14,[x1],#2*4
+ add w27,w27,w17 // h+=Sigma0(a)
+ ror w16,w23,#6
+ add w26,w26,w28 // h+=K[i]
+ eor w15,w23,w23,ror#14
+ and w17,w24,w23
+ bic w28,w25,w23
+ add w26,w26,w12 // h+=X[i]
+ orr w17,w17,w28 // Ch(e,f,g)
+ eor w28,w27,w20 // a^b, b^c in next round
+ eor w16,w16,w15,ror#11 // Sigma1(e)
+ ror w15,w27,#2
+ add w26,w26,w17 // h+=Ch(e,f,g)
+ eor w17,w27,w27,ror#9
+ add w26,w26,w16 // h+=Sigma1(e)
+ and w19,w19,w28 // (b^c)&=(a^b)
+ add w22,w22,w26 // d+=h
+ eor w19,w19,w20 // Maj(a,b,c)
+ eor w17,w15,w17,ror#13 // Sigma0(a)
+ add w26,w26,w19 // h+=Maj(a,b,c)
+ ldr w19,[x30],#4 // *K++, w28 in next round
+ //add w26,w26,w17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev w13,w13 // 10
+#endif
+ add w26,w26,w17 // h+=Sigma0(a)
+ ror w16,w22,#6
+ add w25,w25,w19 // h+=K[i]
+ eor w0,w22,w22,ror#14
+ and w17,w23,w22
+ bic w19,w24,w22
+ add w25,w25,w13 // h+=X[i]
+ orr w17,w17,w19 // Ch(e,f,g)
+ eor w19,w26,w27 // a^b, b^c in next round
+ eor w16,w16,w0,ror#11 // Sigma1(e)
+ ror w0,w26,#2
+ add w25,w25,w17 // h+=Ch(e,f,g)
+ eor w17,w26,w26,ror#9
+ add w25,w25,w16 // h+=Sigma1(e)
+ and w28,w28,w19 // (b^c)&=(a^b)
+ add w21,w21,w25 // d+=h
+ eor w28,w28,w27 // Maj(a,b,c)
+ eor w17,w0,w17,ror#13 // Sigma0(a)
+ add w25,w25,w28 // h+=Maj(a,b,c)
+ ldr w28,[x30],#4 // *K++, w19 in next round
+ //add w25,w25,w17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev w14,w14 // 11
+#endif
+ ldp w15,w0,[x1],#2*4
+ add w25,w25,w17 // h+=Sigma0(a)
+ str w6,[sp,#12]
+ ror w16,w21,#6
+ add w24,w24,w28 // h+=K[i]
+ eor w6,w21,w21,ror#14
+ and w17,w22,w21
+ bic w28,w23,w21
+ add w24,w24,w14 // h+=X[i]
+ orr w17,w17,w28 // Ch(e,f,g)
+ eor w28,w25,w26 // a^b, b^c in next round
+ eor w16,w16,w6,ror#11 // Sigma1(e)
+ ror w6,w25,#2
+ add w24,w24,w17 // h+=Ch(e,f,g)
+ eor w17,w25,w25,ror#9
+ add w24,w24,w16 // h+=Sigma1(e)
+ and w19,w19,w28 // (b^c)&=(a^b)
+ add w20,w20,w24 // d+=h
+ eor w19,w19,w26 // Maj(a,b,c)
+ eor w17,w6,w17,ror#13 // Sigma0(a)
+ add w24,w24,w19 // h+=Maj(a,b,c)
+ ldr w19,[x30],#4 // *K++, w28 in next round
+ //add w24,w24,w17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev w15,w15 // 12
+#endif
+ add w24,w24,w17 // h+=Sigma0(a)
+ str w7,[sp,#0]
+ ror w16,w20,#6
+ add w23,w23,w19 // h+=K[i]
+ eor w7,w20,w20,ror#14
+ and w17,w21,w20
+ bic w19,w22,w20
+ add w23,w23,w15 // h+=X[i]
+ orr w17,w17,w19 // Ch(e,f,g)
+ eor w19,w24,w25 // a^b, b^c in next round
+ eor w16,w16,w7,ror#11 // Sigma1(e)
+ ror w7,w24,#2
+ add w23,w23,w17 // h+=Ch(e,f,g)
+ eor w17,w24,w24,ror#9
+ add w23,w23,w16 // h+=Sigma1(e)
+ and w28,w28,w19 // (b^c)&=(a^b)
+ add w27,w27,w23 // d+=h
+ eor w28,w28,w25 // Maj(a,b,c)
+ eor w17,w7,w17,ror#13 // Sigma0(a)
+ add w23,w23,w28 // h+=Maj(a,b,c)
+ ldr w28,[x30],#4 // *K++, w19 in next round
+ //add w23,w23,w17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev w0,w0 // 13
+#endif
+ ldp w1,w2,[x1]
+ add w23,w23,w17 // h+=Sigma0(a)
+ str w8,[sp,#4]
+ ror w16,w27,#6
+ add w22,w22,w28 // h+=K[i]
+ eor w8,w27,w27,ror#14
+ and w17,w20,w27
+ bic w28,w21,w27
+ add w22,w22,w0 // h+=X[i]
+ orr w17,w17,w28 // Ch(e,f,g)
+ eor w28,w23,w24 // a^b, b^c in next round
+ eor w16,w16,w8,ror#11 // Sigma1(e)
+ ror w8,w23,#2
+ add w22,w22,w17 // h+=Ch(e,f,g)
+ eor w17,w23,w23,ror#9
+ add w22,w22,w16 // h+=Sigma1(e)
+ and w19,w19,w28 // (b^c)&=(a^b)
+ add w26,w26,w22 // d+=h
+ eor w19,w19,w24 // Maj(a,b,c)
+ eor w17,w8,w17,ror#13 // Sigma0(a)
+ add w22,w22,w19 // h+=Maj(a,b,c)
+ ldr w19,[x30],#4 // *K++, w28 in next round
+ //add w22,w22,w17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev w1,w1 // 14
+#endif
+ ldr w6,[sp,#12]
+ add w22,w22,w17 // h+=Sigma0(a)
+ str w9,[sp,#8]
+ ror w16,w26,#6
+ add w21,w21,w19 // h+=K[i]
+ eor w9,w26,w26,ror#14
+ and w17,w27,w26
+ bic w19,w20,w26
+ add w21,w21,w1 // h+=X[i]
+ orr w17,w17,w19 // Ch(e,f,g)
+ eor w19,w22,w23 // a^b, b^c in next round
+ eor w16,w16,w9,ror#11 // Sigma1(e)
+ ror w9,w22,#2
+ add w21,w21,w17 // h+=Ch(e,f,g)
+ eor w17,w22,w22,ror#9
+ add w21,w21,w16 // h+=Sigma1(e)
+ and w28,w28,w19 // (b^c)&=(a^b)
+ add w25,w25,w21 // d+=h
+ eor w28,w28,w23 // Maj(a,b,c)
+ eor w17,w9,w17,ror#13 // Sigma0(a)
+ add w21,w21,w28 // h+=Maj(a,b,c)
+ ldr w28,[x30],#4 // *K++, w19 in next round
+ //add w21,w21,w17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev w2,w2 // 15
+#endif
+ ldr w7,[sp,#0]
+ add w21,w21,w17 // h+=Sigma0(a)
+ str w10,[sp,#12]
+ ror w16,w25,#6
+ add w20,w20,w28 // h+=K[i]
+ ror w9,w4,#7
+ and w17,w26,w25
+ ror w8,w1,#17
+ bic w28,w27,w25
+ ror w10,w21,#2
+ add w20,w20,w2 // h+=X[i]
+ eor w16,w16,w25,ror#11
+ eor w9,w9,w4,ror#18
+ orr w17,w17,w28 // Ch(e,f,g)
+ eor w28,w21,w22 // a^b, b^c in next round
+ eor w16,w16,w25,ror#25 // Sigma1(e)
+ eor w10,w10,w21,ror#13
+ add w20,w20,w17 // h+=Ch(e,f,g)
+ and w19,w19,w28 // (b^c)&=(a^b)
+ eor w8,w8,w1,ror#19
+ eor w9,w9,w4,lsr#3 // sigma0(X[i+1])
+ add w20,w20,w16 // h+=Sigma1(e)
+ eor w19,w19,w22 // Maj(a,b,c)
+ eor w17,w10,w21,ror#22 // Sigma0(a)
+ eor w8,w8,w1,lsr#10 // sigma1(X[i+14])
+ add w3,w3,w12
+ add w24,w24,w20 // d+=h
+ add w20,w20,w19 // h+=Maj(a,b,c)
+ ldr w19,[x30],#4 // *K++, w28 in next round
+ add w3,w3,w9
+ add w20,w20,w17 // h+=Sigma0(a)
+ add w3,w3,w8
+.Loop_16_xx:
+ ldr w8,[sp,#4]
+ str w11,[sp,#0]
+ ror w16,w24,#6
+ add w27,w27,w19 // h+=K[i]
+ ror w10,w5,#7
+ and w17,w25,w24
+ ror w9,w2,#17
+ bic w19,w26,w24
+ ror w11,w20,#2
+ add w27,w27,w3 // h+=X[i]
+ eor w16,w16,w24,ror#11
+ eor w10,w10,w5,ror#18
+ orr w17,w17,w19 // Ch(e,f,g)
+ eor w19,w20,w21 // a^b, b^c in next round
+ eor w16,w16,w24,ror#25 // Sigma1(e)
+ eor w11,w11,w20,ror#13
+ add w27,w27,w17 // h+=Ch(e,f,g)
+ and w28,w28,w19 // (b^c)&=(a^b)
+ eor w9,w9,w2,ror#19
+ eor w10,w10,w5,lsr#3 // sigma0(X[i+1])
+ add w27,w27,w16 // h+=Sigma1(e)
+ eor w28,w28,w21 // Maj(a,b,c)
+ eor w17,w11,w20,ror#22 // Sigma0(a)
+ eor w9,w9,w2,lsr#10 // sigma1(X[i+14])
+ add w4,w4,w13
+ add w23,w23,w27 // d+=h
+ add w27,w27,w28 // h+=Maj(a,b,c)
+ ldr w28,[x30],#4 // *K++, w19 in next round
+ add w4,w4,w10
+ add w27,w27,w17 // h+=Sigma0(a)
+ add w4,w4,w9
+ ldr w9,[sp,#8]
+ str w12,[sp,#4]
+ ror w16,w23,#6
+ add w26,w26,w28 // h+=K[i]
+ ror w11,w6,#7
+ and w17,w24,w23
+ ror w10,w3,#17
+ bic w28,w25,w23
+ ror w12,w27,#2
+ add w26,w26,w4 // h+=X[i]
+ eor w16,w16,w23,ror#11
+ eor w11,w11,w6,ror#18
+ orr w17,w17,w28 // Ch(e,f,g)
+ eor w28,w27,w20 // a^b, b^c in next round
+ eor w16,w16,w23,ror#25 // Sigma1(e)
+ eor w12,w12,w27,ror#13
+ add w26,w26,w17 // h+=Ch(e,f,g)
+ and w19,w19,w28 // (b^c)&=(a^b)
+ eor w10,w10,w3,ror#19
+ eor w11,w11,w6,lsr#3 // sigma0(X[i+1])
+ add w26,w26,w16 // h+=Sigma1(e)
+ eor w19,w19,w20 // Maj(a,b,c)
+ eor w17,w12,w27,ror#22 // Sigma0(a)
+ eor w10,w10,w3,lsr#10 // sigma1(X[i+14])
+ add w5,w5,w14
+ add w22,w22,w26 // d+=h
+ add w26,w26,w19 // h+=Maj(a,b,c)
+ ldr w19,[x30],#4 // *K++, w28 in next round
+ add w5,w5,w11
+ add w26,w26,w17 // h+=Sigma0(a)
+ add w5,w5,w10
+ ldr w10,[sp,#12]
+ str w13,[sp,#8]
+ ror w16,w22,#6
+ add w25,w25,w19 // h+=K[i]
+ ror w12,w7,#7
+ and w17,w23,w22
+ ror w11,w4,#17
+ bic w19,w24,w22
+ ror w13,w26,#2
+ add w25,w25,w5 // h+=X[i]
+ eor w16,w16,w22,ror#11
+ eor w12,w12,w7,ror#18
+ orr w17,w17,w19 // Ch(e,f,g)
+ eor w19,w26,w27 // a^b, b^c in next round
+ eor w16,w16,w22,ror#25 // Sigma1(e)
+ eor w13,w13,w26,ror#13
+ add w25,w25,w17 // h+=Ch(e,f,g)
+ and w28,w28,w19 // (b^c)&=(a^b)
+ eor w11,w11,w4,ror#19
+ eor w12,w12,w7,lsr#3 // sigma0(X[i+1])
+ add w25,w25,w16 // h+=Sigma1(e)
+ eor w28,w28,w27 // Maj(a,b,c)
+ eor w17,w13,w26,ror#22 // Sigma0(a)
+ eor w11,w11,w4,lsr#10 // sigma1(X[i+14])
+ add w6,w6,w15
+ add w21,w21,w25 // d+=h
+ add w25,w25,w28 // h+=Maj(a,b,c)
+ ldr w28,[x30],#4 // *K++, w19 in next round
+ add w6,w6,w12
+ add w25,w25,w17 // h+=Sigma0(a)
+ add w6,w6,w11
+ ldr w11,[sp,#0]
+ str w14,[sp,#12]
+ ror w16,w21,#6
+ add w24,w24,w28 // h+=K[i]
+ ror w13,w8,#7
+ and w17,w22,w21
+ ror w12,w5,#17
+ bic w28,w23,w21
+ ror w14,w25,#2
+ add w24,w24,w6 // h+=X[i]
+ eor w16,w16,w21,ror#11
+ eor w13,w13,w8,ror#18
+ orr w17,w17,w28 // Ch(e,f,g)
+ eor w28,w25,w26 // a^b, b^c in next round
+ eor w16,w16,w21,ror#25 // Sigma1(e)
+ eor w14,w14,w25,ror#13
+ add w24,w24,w17 // h+=Ch(e,f,g)
+ and w19,w19,w28 // (b^c)&=(a^b)
+ eor w12,w12,w5,ror#19
+ eor w13,w13,w8,lsr#3 // sigma0(X[i+1])
+ add w24,w24,w16 // h+=Sigma1(e)
+ eor w19,w19,w26 // Maj(a,b,c)
+ eor w17,w14,w25,ror#22 // Sigma0(a)
+ eor w12,w12,w5,lsr#10 // sigma1(X[i+14])
+ add w7,w7,w0
+ add w20,w20,w24 // d+=h
+ add w24,w24,w19 // h+=Maj(a,b,c)
+ ldr w19,[x30],#4 // *K++, w28 in next round
+ add w7,w7,w13
+ add w24,w24,w17 // h+=Sigma0(a)
+ add w7,w7,w12
+ ldr w12,[sp,#4]
+ str w15,[sp,#0]
+ ror w16,w20,#6
+ add w23,w23,w19 // h+=K[i]
+ ror w14,w9,#7
+ and w17,w21,w20
+ ror w13,w6,#17
+ bic w19,w22,w20
+ ror w15,w24,#2
+ add w23,w23,w7 // h+=X[i]
+ eor w16,w16,w20,ror#11
+ eor w14,w14,w9,ror#18
+ orr w17,w17,w19 // Ch(e,f,g)
+ eor w19,w24,w25 // a^b, b^c in next round
+ eor w16,w16,w20,ror#25 // Sigma1(e)
+ eor w15,w15,w24,ror#13
+ add w23,w23,w17 // h+=Ch(e,f,g)
+ and w28,w28,w19 // (b^c)&=(a^b)
+ eor w13,w13,w6,ror#19
+ eor w14,w14,w9,lsr#3 // sigma0(X[i+1])
+ add w23,w23,w16 // h+=Sigma1(e)
+ eor w28,w28,w25 // Maj(a,b,c)
+ eor w17,w15,w24,ror#22 // Sigma0(a)
+ eor w13,w13,w6,lsr#10 // sigma1(X[i+14])
+ add w8,w8,w1
+ add w27,w27,w23 // d+=h
+ add w23,w23,w28 // h+=Maj(a,b,c)
+ ldr w28,[x30],#4 // *K++, w19 in next round
+ add w8,w8,w14
+ add w23,w23,w17 // h+=Sigma0(a)
+ add w8,w8,w13
+ ldr w13,[sp,#8]
+ str w0,[sp,#4]
+ ror w16,w27,#6
+ add w22,w22,w28 // h+=K[i]
+ ror w15,w10,#7
+ and w17,w20,w27
+ ror w14,w7,#17
+ bic w28,w21,w27
+ ror w0,w23,#2
+ add w22,w22,w8 // h+=X[i]
+ eor w16,w16,w27,ror#11
+ eor w15,w15,w10,ror#18
+ orr w17,w17,w28 // Ch(e,f,g)
+ eor w28,w23,w24 // a^b, b^c in next round
+ eor w16,w16,w27,ror#25 // Sigma1(e)
+ eor w0,w0,w23,ror#13
+ add w22,w22,w17 // h+=Ch(e,f,g)
+ and w19,w19,w28 // (b^c)&=(a^b)
+ eor w14,w14,w7,ror#19
+ eor w15,w15,w10,lsr#3 // sigma0(X[i+1])
+ add w22,w22,w16 // h+=Sigma1(e)
+ eor w19,w19,w24 // Maj(a,b,c)
+ eor w17,w0,w23,ror#22 // Sigma0(a)
+ eor w14,w14,w7,lsr#10 // sigma1(X[i+14])
+ add w9,w9,w2
+ add w26,w26,w22 // d+=h
+ add w22,w22,w19 // h+=Maj(a,b,c)
+ ldr w19,[x30],#4 // *K++, w28 in next round
+ add w9,w9,w15
+ add w22,w22,w17 // h+=Sigma0(a)
+ add w9,w9,w14
+ ldr w14,[sp,#12]
+ str w1,[sp,#8]
+ ror w16,w26,#6
+ add w21,w21,w19 // h+=K[i]
+ ror w0,w11,#7
+ and w17,w27,w26
+ ror w15,w8,#17
+ bic w19,w20,w26
+ ror w1,w22,#2
+ add w21,w21,w9 // h+=X[i]
+ eor w16,w16,w26,ror#11
+ eor w0,w0,w11,ror#18
+ orr w17,w17,w19 // Ch(e,f,g)
+ eor w19,w22,w23 // a^b, b^c in next round
+ eor w16,w16,w26,ror#25 // Sigma1(e)
+ eor w1,w1,w22,ror#13
+ add w21,w21,w17 // h+=Ch(e,f,g)
+ and w28,w28,w19 // (b^c)&=(a^b)
+ eor w15,w15,w8,ror#19
+ eor w0,w0,w11,lsr#3 // sigma0(X[i+1])
+ add w21,w21,w16 // h+=Sigma1(e)
+ eor w28,w28,w23 // Maj(a,b,c)
+ eor w17,w1,w22,ror#22 // Sigma0(a)
+ eor w15,w15,w8,lsr#10 // sigma1(X[i+14])
+ add w10,w10,w3
+ add w25,w25,w21 // d+=h
+ add w21,w21,w28 // h+=Maj(a,b,c)
+ ldr w28,[x30],#4 // *K++, w19 in next round
+ add w10,w10,w0
+ add w21,w21,w17 // h+=Sigma0(a)
+ add w10,w10,w15
+ ldr w15,[sp,#0]
+ str w2,[sp,#12]
+ ror w16,w25,#6
+ add w20,w20,w28 // h+=K[i]
+ ror w1,w12,#7
+ and w17,w26,w25
+ ror w0,w9,#17
+ bic w28,w27,w25
+ ror w2,w21,#2
+ add w20,w20,w10 // h+=X[i]
+ eor w16,w16,w25,ror#11
+ eor w1,w1,w12,ror#18
+ orr w17,w17,w28 // Ch(e,f,g)
+ eor w28,w21,w22 // a^b, b^c in next round
+ eor w16,w16,w25,ror#25 // Sigma1(e)
+ eor w2,w2,w21,ror#13
+ add w20,w20,w17 // h+=Ch(e,f,g)
+ and w19,w19,w28 // (b^c)&=(a^b)
+ eor w0,w0,w9,ror#19
+ eor w1,w1,w12,lsr#3 // sigma0(X[i+1])
+ add w20,w20,w16 // h+=Sigma1(e)
+ eor w19,w19,w22 // Maj(a,b,c)
+ eor w17,w2,w21,ror#22 // Sigma0(a)
+ eor w0,w0,w9,lsr#10 // sigma1(X[i+14])
+ add w11,w11,w4
+ add w24,w24,w20 // d+=h
+ add w20,w20,w19 // h+=Maj(a,b,c)
+ ldr w19,[x30],#4 // *K++, w28 in next round
+ add w11,w11,w1
+ add w20,w20,w17 // h+=Sigma0(a)
+ add w11,w11,w0
+ ldr w0,[sp,#4]
+ str w3,[sp,#0]
+ ror w16,w24,#6
+ add w27,w27,w19 // h+=K[i]
+ ror w2,w13,#7
+ and w17,w25,w24
+ ror w1,w10,#17
+ bic w19,w26,w24
+ ror w3,w20,#2
+ add w27,w27,w11 // h+=X[i]
+ eor w16,w16,w24,ror#11
+ eor w2,w2,w13,ror#18
+ orr w17,w17,w19 // Ch(e,f,g)
+ eor w19,w20,w21 // a^b, b^c in next round
+ eor w16,w16,w24,ror#25 // Sigma1(e)
+ eor w3,w3,w20,ror#13
+ add w27,w27,w17 // h+=Ch(e,f,g)
+ and w28,w28,w19 // (b^c)&=(a^b)
+ eor w1,w1,w10,ror#19
+ eor w2,w2,w13,lsr#3 // sigma0(X[i+1])
+ add w27,w27,w16 // h+=Sigma1(e)
+ eor w28,w28,w21 // Maj(a,b,c)
+ eor w17,w3,w20,ror#22 // Sigma0(a)
+ eor w1,w1,w10,lsr#10 // sigma1(X[i+14])
+ add w12,w12,w5
+ add w23,w23,w27 // d+=h
+ add w27,w27,w28 // h+=Maj(a,b,c)
+ ldr w28,[x30],#4 // *K++, w19 in next round
+ add w12,w12,w2
+ add w27,w27,w17 // h+=Sigma0(a)
+ add w12,w12,w1
+ ldr w1,[sp,#8]
+ str w4,[sp,#4]
+ ror w16,w23,#6
+ add w26,w26,w28 // h+=K[i]
+ ror w3,w14,#7
+ and w17,w24,w23
+ ror w2,w11,#17
+ bic w28,w25,w23
+ ror w4,w27,#2
+ add w26,w26,w12 // h+=X[i]
+ eor w16,w16,w23,ror#11
+ eor w3,w3,w14,ror#18
+ orr w17,w17,w28 // Ch(e,f,g)
+ eor w28,w27,w20 // a^b, b^c in next round
+ eor w16,w16,w23,ror#25 // Sigma1(e)
+ eor w4,w4,w27,ror#13
+ add w26,w26,w17 // h+=Ch(e,f,g)
+ and w19,w19,w28 // (b^c)&=(a^b)
+ eor w2,w2,w11,ror#19
+ eor w3,w3,w14,lsr#3 // sigma0(X[i+1])
+ add w26,w26,w16 // h+=Sigma1(e)
+ eor w19,w19,w20 // Maj(a,b,c)
+ eor w17,w4,w27,ror#22 // Sigma0(a)
+ eor w2,w2,w11,lsr#10 // sigma1(X[i+14])
+ add w13,w13,w6
+ add w22,w22,w26 // d+=h
+ add w26,w26,w19 // h+=Maj(a,b,c)
+ ldr w19,[x30],#4 // *K++, w28 in next round
+ add w13,w13,w3
+ add w26,w26,w17 // h+=Sigma0(a)
+ add w13,w13,w2
+ ldr w2,[sp,#12]
+ str w5,[sp,#8]
+ ror w16,w22,#6
+ add w25,w25,w19 // h+=K[i]
+ ror w4,w15,#7
+ and w17,w23,w22
+ ror w3,w12,#17
+ bic w19,w24,w22
+ ror w5,w26,#2
+ add w25,w25,w13 // h+=X[i]
+ eor w16,w16,w22,ror#11
+ eor w4,w4,w15,ror#18
+ orr w17,w17,w19 // Ch(e,f,g)
+ eor w19,w26,w27 // a^b, b^c in next round
+ eor w16,w16,w22,ror#25 // Sigma1(e)
+ eor w5,w5,w26,ror#13
+ add w25,w25,w17 // h+=Ch(e,f,g)
+ and w28,w28,w19 // (b^c)&=(a^b)
+ eor w3,w3,w12,ror#19
+ eor w4,w4,w15,lsr#3 // sigma0(X[i+1])
+ add w25,w25,w16 // h+=Sigma1(e)
+ eor w28,w28,w27 // Maj(a,b,c)
+ eor w17,w5,w26,ror#22 // Sigma0(a)
+ eor w3,w3,w12,lsr#10 // sigma1(X[i+14])
+ add w14,w14,w7
+ add w21,w21,w25 // d+=h
+ add w25,w25,w28 // h+=Maj(a,b,c)
+ ldr w28,[x30],#4 // *K++, w19 in next round
+ add w14,w14,w4
+ add w25,w25,w17 // h+=Sigma0(a)
+ add w14,w14,w3
+ ldr w3,[sp,#0]
+ str w6,[sp,#12]
+ ror w16,w21,#6
+ add w24,w24,w28 // h+=K[i]
+ ror w5,w0,#7
+ and w17,w22,w21
+ ror w4,w13,#17
+ bic w28,w23,w21
+ ror w6,w25,#2
+ add w24,w24,w14 // h+=X[i]
+ eor w16,w16,w21,ror#11
+ eor w5,w5,w0,ror#18
+ orr w17,w17,w28 // Ch(e,f,g)
+ eor w28,w25,w26 // a^b, b^c in next round
+ eor w16,w16,w21,ror#25 // Sigma1(e)
+ eor w6,w6,w25,ror#13
+ add w24,w24,w17 // h+=Ch(e,f,g)
+ and w19,w19,w28 // (b^c)&=(a^b)
+ eor w4,w4,w13,ror#19
+ eor w5,w5,w0,lsr#3 // sigma0(X[i+1])
+ add w24,w24,w16 // h+=Sigma1(e)
+ eor w19,w19,w26 // Maj(a,b,c)
+ eor w17,w6,w25,ror#22 // Sigma0(a)
+ eor w4,w4,w13,lsr#10 // sigma1(X[i+14])
+ add w15,w15,w8
+ add w20,w20,w24 // d+=h
+ add w24,w24,w19 // h+=Maj(a,b,c)
+ ldr w19,[x30],#4 // *K++, w28 in next round
+ add w15,w15,w5
+ add w24,w24,w17 // h+=Sigma0(a)
+ add w15,w15,w4
+ ldr w4,[sp,#4]
+ str w7,[sp,#0]
+ ror w16,w20,#6
+ add w23,w23,w19 // h+=K[i]
+ ror w6,w1,#7
+ and w17,w21,w20
+ ror w5,w14,#17
+ bic w19,w22,w20
+ ror w7,w24,#2
+ add w23,w23,w15 // h+=X[i]
+ eor w16,w16,w20,ror#11
+ eor w6,w6,w1,ror#18
+ orr w17,w17,w19 // Ch(e,f,g)
+ eor w19,w24,w25 // a^b, b^c in next round
+ eor w16,w16,w20,ror#25 // Sigma1(e)
+ eor w7,w7,w24,ror#13
+ add w23,w23,w17 // h+=Ch(e,f,g)
+ and w28,w28,w19 // (b^c)&=(a^b)
+ eor w5,w5,w14,ror#19
+ eor w6,w6,w1,lsr#3 // sigma0(X[i+1])
+ add w23,w23,w16 // h+=Sigma1(e)
+ eor w28,w28,w25 // Maj(a,b,c)
+ eor w17,w7,w24,ror#22 // Sigma0(a)
+ eor w5,w5,w14,lsr#10 // sigma1(X[i+14])
+ add w0,w0,w9
+ add w27,w27,w23 // d+=h
+ add w23,w23,w28 // h+=Maj(a,b,c)
+ ldr w28,[x30],#4 // *K++, w19 in next round
+ add w0,w0,w6
+ add w23,w23,w17 // h+=Sigma0(a)
+ add w0,w0,w5
+ ldr w5,[sp,#8]
+ str w8,[sp,#4]
+ ror w16,w27,#6
+ add w22,w22,w28 // h+=K[i]
+ ror w7,w2,#7
+ and w17,w20,w27
+ ror w6,w15,#17
+ bic w28,w21,w27
+ ror w8,w23,#2
+ add w22,w22,w0 // h+=X[i]
+ eor w16,w16,w27,ror#11
+ eor w7,w7,w2,ror#18
+ orr w17,w17,w28 // Ch(e,f,g)
+ eor w28,w23,w24 // a^b, b^c in next round
+ eor w16,w16,w27,ror#25 // Sigma1(e)
+ eor w8,w8,w23,ror#13
+ add w22,w22,w17 // h+=Ch(e,f,g)
+ and w19,w19,w28 // (b^c)&=(a^b)
+ eor w6,w6,w15,ror#19
+ eor w7,w7,w2,lsr#3 // sigma0(X[i+1])
+ add w22,w22,w16 // h+=Sigma1(e)
+ eor w19,w19,w24 // Maj(a,b,c)
+ eor w17,w8,w23,ror#22 // Sigma0(a)
+ eor w6,w6,w15,lsr#10 // sigma1(X[i+14])
+ add w1,w1,w10
+ add w26,w26,w22 // d+=h
+ add w22,w22,w19 // h+=Maj(a,b,c)
+ ldr w19,[x30],#4 // *K++, w28 in next round
+ add w1,w1,w7
+ add w22,w22,w17 // h+=Sigma0(a)
+ add w1,w1,w6
+ ldr w6,[sp,#12]
+ str w9,[sp,#8]
+ ror w16,w26,#6
+ add w21,w21,w19 // h+=K[i]
+ ror w8,w3,#7
+ and w17,w27,w26
+ ror w7,w0,#17
+ bic w19,w20,w26
+ ror w9,w22,#2
+ add w21,w21,w1 // h+=X[i]
+ eor w16,w16,w26,ror#11
+ eor w8,w8,w3,ror#18
+ orr w17,w17,w19 // Ch(e,f,g)
+ eor w19,w22,w23 // a^b, b^c in next round
+ eor w16,w16,w26,ror#25 // Sigma1(e)
+ eor w9,w9,w22,ror#13
+ add w21,w21,w17 // h+=Ch(e,f,g)
+ and w28,w28,w19 // (b^c)&=(a^b)
+ eor w7,w7,w0,ror#19
+ eor w8,w8,w3,lsr#3 // sigma0(X[i+1])
+ add w21,w21,w16 // h+=Sigma1(e)
+ eor w28,w28,w23 // Maj(a,b,c)
+ eor w17,w9,w22,ror#22 // Sigma0(a)
+ eor w7,w7,w0,lsr#10 // sigma1(X[i+14])
+ add w2,w2,w11
+ add w25,w25,w21 // d+=h
+ add w21,w21,w28 // h+=Maj(a,b,c)
+ ldr w28,[x30],#4 // *K++, w19 in next round
+ add w2,w2,w8
+ add w21,w21,w17 // h+=Sigma0(a)
+ add w2,w2,w7
+ ldr w7,[sp,#0]
+ str w10,[sp,#12]
+ ror w16,w25,#6
+ add w20,w20,w28 // h+=K[i]
+ ror w9,w4,#7
+ and w17,w26,w25
+ ror w8,w1,#17
+ bic w28,w27,w25
+ ror w10,w21,#2
+ add w20,w20,w2 // h+=X[i]
+ eor w16,w16,w25,ror#11
+ eor w9,w9,w4,ror#18
+ orr w17,w17,w28 // Ch(e,f,g)
+ eor w28,w21,w22 // a^b, b^c in next round
+ eor w16,w16,w25,ror#25 // Sigma1(e)
+ eor w10,w10,w21,ror#13
+ add w20,w20,w17 // h+=Ch(e,f,g)
+ and w19,w19,w28 // (b^c)&=(a^b)
+ eor w8,w8,w1,ror#19
+ eor w9,w9,w4,lsr#3 // sigma0(X[i+1])
+ add w20,w20,w16 // h+=Sigma1(e)
+ eor w19,w19,w22 // Maj(a,b,c)
+ eor w17,w10,w21,ror#22 // Sigma0(a)
+ eor w8,w8,w1,lsr#10 // sigma1(X[i+14])
+ add w3,w3,w12
+ add w24,w24,w20 // d+=h
+ add w20,w20,w19 // h+=Maj(a,b,c)
+ ldr w19,[x30],#4 // *K++, w28 in next round
+ add w3,w3,w9
+ add w20,w20,w17 // h+=Sigma0(a)
+ add w3,w3,w8
+ cbnz w19,.Loop_16_xx
+
+ ldp x0,x2,[x29,#96]
+ ldr x1,[x29,#112]
+ sub x30,x30,#260 // rewind
+
+ ldp w3,w4,[x0]
+ ldp w5,w6,[x0,#2*4]
+ add x1,x1,#14*4 // advance input pointer
+ ldp w7,w8,[x0,#4*4]
+ add w20,w20,w3
+ ldp w9,w10,[x0,#6*4]
+ add w21,w21,w4
+ add w22,w22,w5
+ add w23,w23,w6
+ stp w20,w21,[x0]
+ add w24,w24,w7
+ add w25,w25,w8
+ stp w22,w23,[x0,#2*4]
+ add w26,w26,w9
+ add w27,w27,w10
+ cmp x1,x2
+ stp w24,w25,[x0,#4*4]
+ stp w26,w27,[x0,#6*4]
+ b.ne .Loop
+
+ ldp x19,x20,[x29,#16]
+ add sp,sp,#4*4
+ ldp x21,x22,[x29,#32]
+ ldp x23,x24,[x29,#48]
+ ldp x25,x26,[x29,#64]
+ ldp x27,x28,[x29,#80]
+ ldp x29,x30,[sp],#128
+.inst 0xd50323bf // autiasp
+ ret
+.size sha256_block_data_order,.-sha256_block_data_order
+
+.align 6
+.type .LK256,%object
+.LK256:
+.long 0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5
+.long 0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5
+.long 0xd807aa98,0x12835b01,0x243185be,0x550c7dc3
+.long 0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174
+.long 0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc
+.long 0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da
+.long 0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7
+.long 0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967
+.long 0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13
+.long 0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85
+.long 0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3
+.long 0xd192e819,0xd6990624,0xf40e3585,0x106aa070
+.long 0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5
+.long 0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3
+.long 0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208
+.long 0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
+.long 0 //terminator
+.size .LK256,.-.LK256
+.byte 83,72,65,50,53,54,32,98,108,111,99,107,32,116,114,97,110,115,102,111,114,109,32,102,111,114,32,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
+.align 2
+.align 2
+#ifndef __KERNEL__
+.type sha256_block_armv8,%function
+.align 6
+sha256_block_armv8:
+.Lv8_entry:
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+
+ ld1 {v0.4s,v1.4s},[x0]
+ adr x3,.LK256
+
+.Loop_hw:
+ ld1 {v4.16b,v5.16b,v6.16b,v7.16b},[x1],#64
+ sub x2,x2,#1
+ ld1 {v16.4s},[x3],#16
+ rev32 v4.16b,v4.16b
+ rev32 v5.16b,v5.16b
+ rev32 v6.16b,v6.16b
+ rev32 v7.16b,v7.16b
+ orr v18.16b,v0.16b,v0.16b // offload
+ orr v19.16b,v1.16b,v1.16b
+ ld1 {v17.4s},[x3],#16
+ add v16.4s,v16.4s,v4.4s
+.inst 0x5e2828a4 //sha256su0 v4.16b,v5.16b
+ orr v2.16b,v0.16b,v0.16b
+.inst 0x5e104020 //sha256h v0.16b,v1.16b,v16.4s
+.inst 0x5e105041 //sha256h2 v1.16b,v2.16b,v16.4s
+.inst 0x5e0760c4 //sha256su1 v4.16b,v6.16b,v7.16b
+ ld1 {v16.4s},[x3],#16
+ add v17.4s,v17.4s,v5.4s
+.inst 0x5e2828c5 //sha256su0 v5.16b,v6.16b
+ orr v2.16b,v0.16b,v0.16b
+.inst 0x5e114020 //sha256h v0.16b,v1.16b,v17.4s
+.inst 0x5e115041 //sha256h2 v1.16b,v2.16b,v17.4s
+.inst 0x5e0460e5 //sha256su1 v5.16b,v7.16b,v4.16b
+ ld1 {v17.4s},[x3],#16
+ add v16.4s,v16.4s,v6.4s
+.inst 0x5e2828e6 //sha256su0 v6.16b,v7.16b
+ orr v2.16b,v0.16b,v0.16b
+.inst 0x5e104020 //sha256h v0.16b,v1.16b,v16.4s
+.inst 0x5e105041 //sha256h2 v1.16b,v2.16b,v16.4s
+.inst 0x5e056086 //sha256su1 v6.16b,v4.16b,v5.16b
+ ld1 {v16.4s},[x3],#16
+ add v17.4s,v17.4s,v7.4s
+.inst 0x5e282887 //sha256su0 v7.16b,v4.16b
+ orr v2.16b,v0.16b,v0.16b
+.inst 0x5e114020 //sha256h v0.16b,v1.16b,v17.4s
+.inst 0x5e115041 //sha256h2 v1.16b,v2.16b,v17.4s
+.inst 0x5e0660a7 //sha256su1 v7.16b,v5.16b,v6.16b
+ ld1 {v17.4s},[x3],#16
+ add v16.4s,v16.4s,v4.4s
+.inst 0x5e2828a4 //sha256su0 v4.16b,v5.16b
+ orr v2.16b,v0.16b,v0.16b
+.inst 0x5e104020 //sha256h v0.16b,v1.16b,v16.4s
+.inst 0x5e105041 //sha256h2 v1.16b,v2.16b,v16.4s
+.inst 0x5e0760c4 //sha256su1 v4.16b,v6.16b,v7.16b
+ ld1 {v16.4s},[x3],#16
+ add v17.4s,v17.4s,v5.4s
+.inst 0x5e2828c5 //sha256su0 v5.16b,v6.16b
+ orr v2.16b,v0.16b,v0.16b
+.inst 0x5e114020 //sha256h v0.16b,v1.16b,v17.4s
+.inst 0x5e115041 //sha256h2 v1.16b,v2.16b,v17.4s
+.inst 0x5e0460e5 //sha256su1 v5.16b,v7.16b,v4.16b
+ ld1 {v17.4s},[x3],#16
+ add v16.4s,v16.4s,v6.4s
+.inst 0x5e2828e6 //sha256su0 v6.16b,v7.16b
+ orr v2.16b,v0.16b,v0.16b
+.inst 0x5e104020 //sha256h v0.16b,v1.16b,v16.4s
+.inst 0x5e105041 //sha256h2 v1.16b,v2.16b,v16.4s
+.inst 0x5e056086 //sha256su1 v6.16b,v4.16b,v5.16b
+ ld1 {v16.4s},[x3],#16
+ add v17.4s,v17.4s,v7.4s
+.inst 0x5e282887 //sha256su0 v7.16b,v4.16b
+ orr v2.16b,v0.16b,v0.16b
+.inst 0x5e114020 //sha256h v0.16b,v1.16b,v17.4s
+.inst 0x5e115041 //sha256h2 v1.16b,v2.16b,v17.4s
+.inst 0x5e0660a7 //sha256su1 v7.16b,v5.16b,v6.16b
+ ld1 {v17.4s},[x3],#16
+ add v16.4s,v16.4s,v4.4s
+.inst 0x5e2828a4 //sha256su0 v4.16b,v5.16b
+ orr v2.16b,v0.16b,v0.16b
+.inst 0x5e104020 //sha256h v0.16b,v1.16b,v16.4s
+.inst 0x5e105041 //sha256h2 v1.16b,v2.16b,v16.4s
+.inst 0x5e0760c4 //sha256su1 v4.16b,v6.16b,v7.16b
+ ld1 {v16.4s},[x3],#16
+ add v17.4s,v17.4s,v5.4s
+.inst 0x5e2828c5 //sha256su0 v5.16b,v6.16b
+ orr v2.16b,v0.16b,v0.16b
+.inst 0x5e114020 //sha256h v0.16b,v1.16b,v17.4s
+.inst 0x5e115041 //sha256h2 v1.16b,v2.16b,v17.4s
+.inst 0x5e0460e5 //sha256su1 v5.16b,v7.16b,v4.16b
+ ld1 {v17.4s},[x3],#16
+ add v16.4s,v16.4s,v6.4s
+.inst 0x5e2828e6 //sha256su0 v6.16b,v7.16b
+ orr v2.16b,v0.16b,v0.16b
+.inst 0x5e104020 //sha256h v0.16b,v1.16b,v16.4s
+.inst 0x5e105041 //sha256h2 v1.16b,v2.16b,v16.4s
+.inst 0x5e056086 //sha256su1 v6.16b,v4.16b,v5.16b
+ ld1 {v16.4s},[x3],#16
+ add v17.4s,v17.4s,v7.4s
+.inst 0x5e282887 //sha256su0 v7.16b,v4.16b
+ orr v2.16b,v0.16b,v0.16b
+.inst 0x5e114020 //sha256h v0.16b,v1.16b,v17.4s
+.inst 0x5e115041 //sha256h2 v1.16b,v2.16b,v17.4s
+.inst 0x5e0660a7 //sha256su1 v7.16b,v5.16b,v6.16b
+ ld1 {v17.4s},[x3],#16
+ add v16.4s,v16.4s,v4.4s
+ orr v2.16b,v0.16b,v0.16b
+.inst 0x5e104020 //sha256h v0.16b,v1.16b,v16.4s
+.inst 0x5e105041 //sha256h2 v1.16b,v2.16b,v16.4s
+
+ ld1 {v16.4s},[x3],#16
+ add v17.4s,v17.4s,v5.4s
+ orr v2.16b,v0.16b,v0.16b
+.inst 0x5e114020 //sha256h v0.16b,v1.16b,v17.4s
+.inst 0x5e115041 //sha256h2 v1.16b,v2.16b,v17.4s
+
+ ld1 {v17.4s},[x3]
+ add v16.4s,v16.4s,v6.4s
+ sub x3,x3,#64*4-16 // rewind
+ orr v2.16b,v0.16b,v0.16b
+.inst 0x5e104020 //sha256h v0.16b,v1.16b,v16.4s
+.inst 0x5e105041 //sha256h2 v1.16b,v2.16b,v16.4s
+
+ add v17.4s,v17.4s,v7.4s
+ orr v2.16b,v0.16b,v0.16b
+.inst 0x5e114020 //sha256h v0.16b,v1.16b,v17.4s
+.inst 0x5e115041 //sha256h2 v1.16b,v2.16b,v17.4s
+
+ add v0.4s,v0.4s,v18.4s
+ add v1.4s,v1.4s,v19.4s
+
+ cbnz x2,.Loop_hw
+
+ st1 {v0.4s,v1.4s},[x0]
+
+ ldr x29,[sp],#16
+ ret
+.size sha256_block_armv8,.-sha256_block_armv8
+#endif
+#ifdef __KERNEL__
+.globl sha256_block_neon
+#endif
+.type sha256_block_neon,%function
+.align 4
+sha256_block_neon:
+.Lneon_entry:
+ stp x29, x30, [sp, #-16]!
+ mov x29, sp
+ sub sp,sp,#16*4
+
+ adr x16,.LK256
+ add x2,x1,x2,lsl#6 // len to point at the end of inp
+
+ ld1 {v0.16b},[x1], #16
+ ld1 {v1.16b},[x1], #16
+ ld1 {v2.16b},[x1], #16
+ ld1 {v3.16b},[x1], #16
+ ld1 {v4.4s},[x16], #16
+ ld1 {v5.4s},[x16], #16
+ ld1 {v6.4s},[x16], #16
+ ld1 {v7.4s},[x16], #16
+ rev32 v0.16b,v0.16b // yes, even on
+ rev32 v1.16b,v1.16b // big-endian
+ rev32 v2.16b,v2.16b
+ rev32 v3.16b,v3.16b
+ mov x17,sp
+ add v4.4s,v4.4s,v0.4s
+ add v5.4s,v5.4s,v1.4s
+ add v6.4s,v6.4s,v2.4s
+ st1 {v4.4s,v5.4s},[x17], #32
+ add v7.4s,v7.4s,v3.4s
+ st1 {v6.4s,v7.4s},[x17]
+ sub x17,x17,#32
+
+ ldp w3,w4,[x0]
+ ldp w5,w6,[x0,#8]
+ ldp w7,w8,[x0,#16]
+ ldp w9,w10,[x0,#24]
+ ldr w12,[sp,#0]
+ mov w13,wzr
+ eor w14,w4,w5
+ mov w15,wzr
+ b .L_00_48
+
+.align 4
+.L_00_48:
+ ext v4.16b,v0.16b,v1.16b,#4
+ add w10,w10,w12
+ add w3,w3,w15
+ and w12,w8,w7
+ bic w15,w9,w7
+ ext v7.16b,v2.16b,v3.16b,#4
+ eor w11,w7,w7,ror#5
+ add w3,w3,w13
+ mov d19,v3.d[1]
+ orr w12,w12,w15
+ eor w11,w11,w7,ror#19
+ ushr v6.4s,v4.4s,#7
+ eor w15,w3,w3,ror#11
+ ushr v5.4s,v4.4s,#3
+ add w10,w10,w12
+ add v0.4s,v0.4s,v7.4s
+ ror w11,w11,#6
+ sli v6.4s,v4.4s,#25
+ eor w13,w3,w4
+ eor w15,w15,w3,ror#20
+ ushr v7.4s,v4.4s,#18
+ add w10,w10,w11
+ ldr w12,[sp,#4]
+ and w14,w14,w13
+ eor v5.16b,v5.16b,v6.16b
+ ror w15,w15,#2
+ add w6,w6,w10
+ sli v7.4s,v4.4s,#14
+ eor w14,w14,w4
+ ushr v16.4s,v19.4s,#17
+ add w9,w9,w12
+ add w10,w10,w15
+ and w12,w7,w6
+ eor v5.16b,v5.16b,v7.16b
+ bic w15,w8,w6
+ eor w11,w6,w6,ror#5
+ sli v16.4s,v19.4s,#15
+ add w10,w10,w14
+ orr w12,w12,w15
+ ushr v17.4s,v19.4s,#10
+ eor w11,w11,w6,ror#19
+ eor w15,w10,w10,ror#11
+ ushr v7.4s,v19.4s,#19
+ add w9,w9,w12
+ ror w11,w11,#6
+ add v0.4s,v0.4s,v5.4s
+ eor w14,w10,w3
+ eor w15,w15,w10,ror#20
+ sli v7.4s,v19.4s,#13
+ add w9,w9,w11
+ ldr w12,[sp,#8]
+ and w13,w13,w14
+ eor v17.16b,v17.16b,v16.16b
+ ror w15,w15,#2
+ add w5,w5,w9
+ eor w13,w13,w3
+ eor v17.16b,v17.16b,v7.16b
+ add w8,w8,w12
+ add w9,w9,w15
+ and w12,w6,w5
+ add v0.4s,v0.4s,v17.4s
+ bic w15,w7,w5
+ eor w11,w5,w5,ror#5
+ add w9,w9,w13
+ ushr v18.4s,v0.4s,#17
+ orr w12,w12,w15
+ ushr v19.4s,v0.4s,#10
+ eor w11,w11,w5,ror#19
+ eor w15,w9,w9,ror#11
+ sli v18.4s,v0.4s,#15
+ add w8,w8,w12
+ ushr v17.4s,v0.4s,#19
+ ror w11,w11,#6
+ eor w13,w9,w10
+ eor v19.16b,v19.16b,v18.16b
+ eor w15,w15,w9,ror#20
+ add w8,w8,w11
+ sli v17.4s,v0.4s,#13
+ ldr w12,[sp,#12]
+ and w14,w14,w13
+ ror w15,w15,#2
+ ld1 {v4.4s},[x16], #16
+ add w4,w4,w8
+ eor v19.16b,v19.16b,v17.16b
+ eor w14,w14,w10
+ eor v17.16b,v17.16b,v17.16b
+ add w7,w7,w12
+ add w8,w8,w15
+ and w12,w5,w4
+ mov v17.d[1],v19.d[0]
+ bic w15,w6,w4
+ eor w11,w4,w4,ror#5
+ add w8,w8,w14
+ add v0.4s,v0.4s,v17.4s
+ orr w12,w12,w15
+ eor w11,w11,w4,ror#19
+ eor w15,w8,w8,ror#11
+ add v4.4s,v4.4s,v0.4s
+ add w7,w7,w12
+ ror w11,w11,#6
+ eor w14,w8,w9
+ eor w15,w15,w8,ror#20
+ add w7,w7,w11
+ ldr w12,[sp,#16]
+ and w13,w13,w14
+ ror w15,w15,#2
+ add w3,w3,w7
+ eor w13,w13,w9
+ st1 {v4.4s},[x17], #16
+ ext v4.16b,v1.16b,v2.16b,#4
+ add w6,w6,w12
+ add w7,w7,w15
+ and w12,w4,w3
+ bic w15,w5,w3
+ ext v7.16b,v3.16b,v0.16b,#4
+ eor w11,w3,w3,ror#5
+ add w7,w7,w13
+ mov d19,v0.d[1]
+ orr w12,w12,w15
+ eor w11,w11,w3,ror#19
+ ushr v6.4s,v4.4s,#7
+ eor w15,w7,w7,ror#11
+ ushr v5.4s,v4.4s,#3
+ add w6,w6,w12
+ add v1.4s,v1.4s,v7.4s
+ ror w11,w11,#6
+ sli v6.4s,v4.4s,#25
+ eor w13,w7,w8
+ eor w15,w15,w7,ror#20
+ ushr v7.4s,v4.4s,#18
+ add w6,w6,w11
+ ldr w12,[sp,#20]
+ and w14,w14,w13
+ eor v5.16b,v5.16b,v6.16b
+ ror w15,w15,#2
+ add w10,w10,w6
+ sli v7.4s,v4.4s,#14
+ eor w14,w14,w8
+ ushr v16.4s,v19.4s,#17
+ add w5,w5,w12
+ add w6,w6,w15
+ and w12,w3,w10
+ eor v5.16b,v5.16b,v7.16b
+ bic w15,w4,w10
+ eor w11,w10,w10,ror#5
+ sli v16.4s,v19.4s,#15
+ add w6,w6,w14
+ orr w12,w12,w15
+ ushr v17.4s,v19.4s,#10
+ eor w11,w11,w10,ror#19
+ eor w15,w6,w6,ror#11
+ ushr v7.4s,v19.4s,#19
+ add w5,w5,w12
+ ror w11,w11,#6
+ add v1.4s,v1.4s,v5.4s
+ eor w14,w6,w7
+ eor w15,w15,w6,ror#20
+ sli v7.4s,v19.4s,#13
+ add w5,w5,w11
+ ldr w12,[sp,#24]
+ and w13,w13,w14
+ eor v17.16b,v17.16b,v16.16b
+ ror w15,w15,#2
+ add w9,w9,w5
+ eor w13,w13,w7
+ eor v17.16b,v17.16b,v7.16b
+ add w4,w4,w12
+ add w5,w5,w15
+ and w12,w10,w9
+ add v1.4s,v1.4s,v17.4s
+ bic w15,w3,w9
+ eor w11,w9,w9,ror#5
+ add w5,w5,w13
+ ushr v18.4s,v1.4s,#17
+ orr w12,w12,w15
+ ushr v19.4s,v1.4s,#10
+ eor w11,w11,w9,ror#19
+ eor w15,w5,w5,ror#11
+ sli v18.4s,v1.4s,#15
+ add w4,w4,w12
+ ushr v17.4s,v1.4s,#19
+ ror w11,w11,#6
+ eor w13,w5,w6
+ eor v19.16b,v19.16b,v18.16b
+ eor w15,w15,w5,ror#20
+ add w4,w4,w11
+ sli v17.4s,v1.4s,#13
+ ldr w12,[sp,#28]
+ and w14,w14,w13
+ ror w15,w15,#2
+ ld1 {v4.4s},[x16], #16
+ add w8,w8,w4
+ eor v19.16b,v19.16b,v17.16b
+ eor w14,w14,w6
+ eor v17.16b,v17.16b,v17.16b
+ add w3,w3,w12
+ add w4,w4,w15
+ and w12,w9,w8
+ mov v17.d[1],v19.d[0]
+ bic w15,w10,w8
+ eor w11,w8,w8,ror#5
+ add w4,w4,w14
+ add v1.4s,v1.4s,v17.4s
+ orr w12,w12,w15
+ eor w11,w11,w8,ror#19
+ eor w15,w4,w4,ror#11
+ add v4.4s,v4.4s,v1.4s
+ add w3,w3,w12
+ ror w11,w11,#6
+ eor w14,w4,w5
+ eor w15,w15,w4,ror#20
+ add w3,w3,w11
+ ldr w12,[sp,#32]
+ and w13,w13,w14
+ ror w15,w15,#2
+ add w7,w7,w3
+ eor w13,w13,w5
+ st1 {v4.4s},[x17], #16
+ ext v4.16b,v2.16b,v3.16b,#4
+ add w10,w10,w12
+ add w3,w3,w15
+ and w12,w8,w7
+ bic w15,w9,w7
+ ext v7.16b,v0.16b,v1.16b,#4
+ eor w11,w7,w7,ror#5
+ add w3,w3,w13
+ mov d19,v1.d[1]
+ orr w12,w12,w15
+ eor w11,w11,w7,ror#19
+ ushr v6.4s,v4.4s,#7
+ eor w15,w3,w3,ror#11
+ ushr v5.4s,v4.4s,#3
+ add w10,w10,w12
+ add v2.4s,v2.4s,v7.4s
+ ror w11,w11,#6
+ sli v6.4s,v4.4s,#25
+ eor w13,w3,w4
+ eor w15,w15,w3,ror#20
+ ushr v7.4s,v4.4s,#18
+ add w10,w10,w11
+ ldr w12,[sp,#36]
+ and w14,w14,w13
+ eor v5.16b,v5.16b,v6.16b
+ ror w15,w15,#2
+ add w6,w6,w10
+ sli v7.4s,v4.4s,#14
+ eor w14,w14,w4
+ ushr v16.4s,v19.4s,#17
+ add w9,w9,w12
+ add w10,w10,w15
+ and w12,w7,w6
+ eor v5.16b,v5.16b,v7.16b
+ bic w15,w8,w6
+ eor w11,w6,w6,ror#5
+ sli v16.4s,v19.4s,#15
+ add w10,w10,w14
+ orr w12,w12,w15
+ ushr v17.4s,v19.4s,#10
+ eor w11,w11,w6,ror#19
+ eor w15,w10,w10,ror#11
+ ushr v7.4s,v19.4s,#19
+ add w9,w9,w12
+ ror w11,w11,#6
+ add v2.4s,v2.4s,v5.4s
+ eor w14,w10,w3
+ eor w15,w15,w10,ror#20
+ sli v7.4s,v19.4s,#13
+ add w9,w9,w11
+ ldr w12,[sp,#40]
+ and w13,w13,w14
+ eor v17.16b,v17.16b,v16.16b
+ ror w15,w15,#2
+ add w5,w5,w9
+ eor w13,w13,w3
+ eor v17.16b,v17.16b,v7.16b
+ add w8,w8,w12
+ add w9,w9,w15
+ and w12,w6,w5
+ add v2.4s,v2.4s,v17.4s
+ bic w15,w7,w5
+ eor w11,w5,w5,ror#5
+ add w9,w9,w13
+ ushr v18.4s,v2.4s,#17
+ orr w12,w12,w15
+ ushr v19.4s,v2.4s,#10
+ eor w11,w11,w5,ror#19
+ eor w15,w9,w9,ror#11
+ sli v18.4s,v2.4s,#15
+ add w8,w8,w12
+ ushr v17.4s,v2.4s,#19
+ ror w11,w11,#6
+ eor w13,w9,w10
+ eor v19.16b,v19.16b,v18.16b
+ eor w15,w15,w9,ror#20
+ add w8,w8,w11
+ sli v17.4s,v2.4s,#13
+ ldr w12,[sp,#44]
+ and w14,w14,w13
+ ror w15,w15,#2
+ ld1 {v4.4s},[x16], #16
+ add w4,w4,w8
+ eor v19.16b,v19.16b,v17.16b
+ eor w14,w14,w10
+ eor v17.16b,v17.16b,v17.16b
+ add w7,w7,w12
+ add w8,w8,w15
+ and w12,w5,w4
+ mov v17.d[1],v19.d[0]
+ bic w15,w6,w4
+ eor w11,w4,w4,ror#5
+ add w8,w8,w14
+ add v2.4s,v2.4s,v17.4s
+ orr w12,w12,w15
+ eor w11,w11,w4,ror#19
+ eor w15,w8,w8,ror#11
+ add v4.4s,v4.4s,v2.4s
+ add w7,w7,w12
+ ror w11,w11,#6
+ eor w14,w8,w9
+ eor w15,w15,w8,ror#20
+ add w7,w7,w11
+ ldr w12,[sp,#48]
+ and w13,w13,w14
+ ror w15,w15,#2
+ add w3,w3,w7
+ eor w13,w13,w9
+ st1 {v4.4s},[x17], #16
+ ext v4.16b,v3.16b,v0.16b,#4
+ add w6,w6,w12
+ add w7,w7,w15
+ and w12,w4,w3
+ bic w15,w5,w3
+ ext v7.16b,v1.16b,v2.16b,#4
+ eor w11,w3,w3,ror#5
+ add w7,w7,w13
+ mov d19,v2.d[1]
+ orr w12,w12,w15
+ eor w11,w11,w3,ror#19
+ ushr v6.4s,v4.4s,#7
+ eor w15,w7,w7,ror#11
+ ushr v5.4s,v4.4s,#3
+ add w6,w6,w12
+ add v3.4s,v3.4s,v7.4s
+ ror w11,w11,#6
+ sli v6.4s,v4.4s,#25
+ eor w13,w7,w8
+ eor w15,w15,w7,ror#20
+ ushr v7.4s,v4.4s,#18
+ add w6,w6,w11
+ ldr w12,[sp,#52]
+ and w14,w14,w13
+ eor v5.16b,v5.16b,v6.16b
+ ror w15,w15,#2
+ add w10,w10,w6
+ sli v7.4s,v4.4s,#14
+ eor w14,w14,w8
+ ushr v16.4s,v19.4s,#17
+ add w5,w5,w12
+ add w6,w6,w15
+ and w12,w3,w10
+ eor v5.16b,v5.16b,v7.16b
+ bic w15,w4,w10
+ eor w11,w10,w10,ror#5
+ sli v16.4s,v19.4s,#15
+ add w6,w6,w14
+ orr w12,w12,w15
+ ushr v17.4s,v19.4s,#10
+ eor w11,w11,w10,ror#19
+ eor w15,w6,w6,ror#11
+ ushr v7.4s,v19.4s,#19
+ add w5,w5,w12
+ ror w11,w11,#6
+ add v3.4s,v3.4s,v5.4s
+ eor w14,w6,w7
+ eor w15,w15,w6,ror#20
+ sli v7.4s,v19.4s,#13
+ add w5,w5,w11
+ ldr w12,[sp,#56]
+ and w13,w13,w14
+ eor v17.16b,v17.16b,v16.16b
+ ror w15,w15,#2
+ add w9,w9,w5
+ eor w13,w13,w7
+ eor v17.16b,v17.16b,v7.16b
+ add w4,w4,w12
+ add w5,w5,w15
+ and w12,w10,w9
+ add v3.4s,v3.4s,v17.4s
+ bic w15,w3,w9
+ eor w11,w9,w9,ror#5
+ add w5,w5,w13
+ ushr v18.4s,v3.4s,#17
+ orr w12,w12,w15
+ ushr v19.4s,v3.4s,#10
+ eor w11,w11,w9,ror#19
+ eor w15,w5,w5,ror#11
+ sli v18.4s,v3.4s,#15
+ add w4,w4,w12
+ ushr v17.4s,v3.4s,#19
+ ror w11,w11,#6
+ eor w13,w5,w6
+ eor v19.16b,v19.16b,v18.16b
+ eor w15,w15,w5,ror#20
+ add w4,w4,w11
+ sli v17.4s,v3.4s,#13
+ ldr w12,[sp,#60]
+ and w14,w14,w13
+ ror w15,w15,#2
+ ld1 {v4.4s},[x16], #16
+ add w8,w8,w4
+ eor v19.16b,v19.16b,v17.16b
+ eor w14,w14,w6
+ eor v17.16b,v17.16b,v17.16b
+ add w3,w3,w12
+ add w4,w4,w15
+ and w12,w9,w8
+ mov v17.d[1],v19.d[0]
+ bic w15,w10,w8
+ eor w11,w8,w8,ror#5
+ add w4,w4,w14
+ add v3.4s,v3.4s,v17.4s
+ orr w12,w12,w15
+ eor w11,w11,w8,ror#19
+ eor w15,w4,w4,ror#11
+ add v4.4s,v4.4s,v3.4s
+ add w3,w3,w12
+ ror w11,w11,#6
+ eor w14,w4,w5
+ eor w15,w15,w4,ror#20
+ add w3,w3,w11
+ ldr w12,[x16]
+ and w13,w13,w14
+ ror w15,w15,#2
+ add w7,w7,w3
+ eor w13,w13,w5
+ st1 {v4.4s},[x17], #16
+ cmp w12,#0 // check for K256 terminator
+ ldr w12,[sp,#0]
+ sub x17,x17,#64
+ bne .L_00_48
+
+ sub x16,x16,#256 // rewind x16
+ cmp x1,x2
+ mov x17, #64
+ csel x17, x17, xzr, eq
+ sub x1,x1,x17 // avoid SEGV
+ mov x17,sp
+ add w10,w10,w12
+ add w3,w3,w15
+ and w12,w8,w7
+ ld1 {v0.16b},[x1],#16
+ bic w15,w9,w7
+ eor w11,w7,w7,ror#5
+ ld1 {v4.4s},[x16],#16
+ add w3,w3,w13
+ orr w12,w12,w15
+ eor w11,w11,w7,ror#19
+ eor w15,w3,w3,ror#11
+ rev32 v0.16b,v0.16b
+ add w10,w10,w12
+ ror w11,w11,#6
+ eor w13,w3,w4
+ eor w15,w15,w3,ror#20
+ add v4.4s,v4.4s,v0.4s
+ add w10,w10,w11
+ ldr w12,[sp,#4]
+ and w14,w14,w13
+ ror w15,w15,#2
+ add w6,w6,w10
+ eor w14,w14,w4
+ add w9,w9,w12
+ add w10,w10,w15
+ and w12,w7,w6
+ bic w15,w8,w6
+ eor w11,w6,w6,ror#5
+ add w10,w10,w14
+ orr w12,w12,w15
+ eor w11,w11,w6,ror#19
+ eor w15,w10,w10,ror#11
+ add w9,w9,w12
+ ror w11,w11,#6
+ eor w14,w10,w3
+ eor w15,w15,w10,ror#20
+ add w9,w9,w11
+ ldr w12,[sp,#8]
+ and w13,w13,w14
+ ror w15,w15,#2
+ add w5,w5,w9
+ eor w13,w13,w3
+ add w8,w8,w12
+ add w9,w9,w15
+ and w12,w6,w5
+ bic w15,w7,w5
+ eor w11,w5,w5,ror#5
+ add w9,w9,w13
+ orr w12,w12,w15
+ eor w11,w11,w5,ror#19
+ eor w15,w9,w9,ror#11
+ add w8,w8,w12
+ ror w11,w11,#6
+ eor w13,w9,w10
+ eor w15,w15,w9,ror#20
+ add w8,w8,w11
+ ldr w12,[sp,#12]
+ and w14,w14,w13
+ ror w15,w15,#2
+ add w4,w4,w8
+ eor w14,w14,w10
+ add w7,w7,w12
+ add w8,w8,w15
+ and w12,w5,w4
+ bic w15,w6,w4
+ eor w11,w4,w4,ror#5
+ add w8,w8,w14
+ orr w12,w12,w15
+ eor w11,w11,w4,ror#19
+ eor w15,w8,w8,ror#11
+ add w7,w7,w12
+ ror w11,w11,#6
+ eor w14,w8,w9
+ eor w15,w15,w8,ror#20
+ add w7,w7,w11
+ ldr w12,[sp,#16]
+ and w13,w13,w14
+ ror w15,w15,#2
+ add w3,w3,w7
+ eor w13,w13,w9
+ st1 {v4.4s},[x17], #16
+ add w6,w6,w12
+ add w7,w7,w15
+ and w12,w4,w3
+ ld1 {v1.16b},[x1],#16
+ bic w15,w5,w3
+ eor w11,w3,w3,ror#5
+ ld1 {v4.4s},[x16],#16
+ add w7,w7,w13
+ orr w12,w12,w15
+ eor w11,w11,w3,ror#19
+ eor w15,w7,w7,ror#11
+ rev32 v1.16b,v1.16b
+ add w6,w6,w12
+ ror w11,w11,#6
+ eor w13,w7,w8
+ eor w15,w15,w7,ror#20
+ add v4.4s,v4.4s,v1.4s
+ add w6,w6,w11
+ ldr w12,[sp,#20]
+ and w14,w14,w13
+ ror w15,w15,#2
+ add w10,w10,w6
+ eor w14,w14,w8
+ add w5,w5,w12
+ add w6,w6,w15
+ and w12,w3,w10
+ bic w15,w4,w10
+ eor w11,w10,w10,ror#5
+ add w6,w6,w14
+ orr w12,w12,w15
+ eor w11,w11,w10,ror#19
+ eor w15,w6,w6,ror#11
+ add w5,w5,w12
+ ror w11,w11,#6
+ eor w14,w6,w7
+ eor w15,w15,w6,ror#20
+ add w5,w5,w11
+ ldr w12,[sp,#24]
+ and w13,w13,w14
+ ror w15,w15,#2
+ add w9,w9,w5
+ eor w13,w13,w7
+ add w4,w4,w12
+ add w5,w5,w15
+ and w12,w10,w9
+ bic w15,w3,w9
+ eor w11,w9,w9,ror#5
+ add w5,w5,w13
+ orr w12,w12,w15
+ eor w11,w11,w9,ror#19
+ eor w15,w5,w5,ror#11
+ add w4,w4,w12
+ ror w11,w11,#6
+ eor w13,w5,w6
+ eor w15,w15,w5,ror#20
+ add w4,w4,w11
+ ldr w12,[sp,#28]
+ and w14,w14,w13
+ ror w15,w15,#2
+ add w8,w8,w4
+ eor w14,w14,w6
+ add w3,w3,w12
+ add w4,w4,w15
+ and w12,w9,w8
+ bic w15,w10,w8
+ eor w11,w8,w8,ror#5
+ add w4,w4,w14
+ orr w12,w12,w15
+ eor w11,w11,w8,ror#19
+ eor w15,w4,w4,ror#11
+ add w3,w3,w12
+ ror w11,w11,#6
+ eor w14,w4,w5
+ eor w15,w15,w4,ror#20
+ add w3,w3,w11
+ ldr w12,[sp,#32]
+ and w13,w13,w14
+ ror w15,w15,#2
+ add w7,w7,w3
+ eor w13,w13,w5
+ st1 {v4.4s},[x17], #16
+ add w10,w10,w12
+ add w3,w3,w15
+ and w12,w8,w7
+ ld1 {v2.16b},[x1],#16
+ bic w15,w9,w7
+ eor w11,w7,w7,ror#5
+ ld1 {v4.4s},[x16],#16
+ add w3,w3,w13
+ orr w12,w12,w15
+ eor w11,w11,w7,ror#19
+ eor w15,w3,w3,ror#11
+ rev32 v2.16b,v2.16b
+ add w10,w10,w12
+ ror w11,w11,#6
+ eor w13,w3,w4
+ eor w15,w15,w3,ror#20
+ add v4.4s,v4.4s,v2.4s
+ add w10,w10,w11
+ ldr w12,[sp,#36]
+ and w14,w14,w13
+ ror w15,w15,#2
+ add w6,w6,w10
+ eor w14,w14,w4
+ add w9,w9,w12
+ add w10,w10,w15
+ and w12,w7,w6
+ bic w15,w8,w6
+ eor w11,w6,w6,ror#5
+ add w10,w10,w14
+ orr w12,w12,w15
+ eor w11,w11,w6,ror#19
+ eor w15,w10,w10,ror#11
+ add w9,w9,w12
+ ror w11,w11,#6
+ eor w14,w10,w3
+ eor w15,w15,w10,ror#20
+ add w9,w9,w11
+ ldr w12,[sp,#40]
+ and w13,w13,w14
+ ror w15,w15,#2
+ add w5,w5,w9
+ eor w13,w13,w3
+ add w8,w8,w12
+ add w9,w9,w15
+ and w12,w6,w5
+ bic w15,w7,w5
+ eor w11,w5,w5,ror#5
+ add w9,w9,w13
+ orr w12,w12,w15
+ eor w11,w11,w5,ror#19
+ eor w15,w9,w9,ror#11
+ add w8,w8,w12
+ ror w11,w11,#6
+ eor w13,w9,w10
+ eor w15,w15,w9,ror#20
+ add w8,w8,w11
+ ldr w12,[sp,#44]
+ and w14,w14,w13
+ ror w15,w15,#2
+ add w4,w4,w8
+ eor w14,w14,w10
+ add w7,w7,w12
+ add w8,w8,w15
+ and w12,w5,w4
+ bic w15,w6,w4
+ eor w11,w4,w4,ror#5
+ add w8,w8,w14
+ orr w12,w12,w15
+ eor w11,w11,w4,ror#19
+ eor w15,w8,w8,ror#11
+ add w7,w7,w12
+ ror w11,w11,#6
+ eor w14,w8,w9
+ eor w15,w15,w8,ror#20
+ add w7,w7,w11
+ ldr w12,[sp,#48]
+ and w13,w13,w14
+ ror w15,w15,#2
+ add w3,w3,w7
+ eor w13,w13,w9
+ st1 {v4.4s},[x17], #16
+ add w6,w6,w12
+ add w7,w7,w15
+ and w12,w4,w3
+ ld1 {v3.16b},[x1],#16
+ bic w15,w5,w3
+ eor w11,w3,w3,ror#5
+ ld1 {v4.4s},[x16],#16
+ add w7,w7,w13
+ orr w12,w12,w15
+ eor w11,w11,w3,ror#19
+ eor w15,w7,w7,ror#11
+ rev32 v3.16b,v3.16b
+ add w6,w6,w12
+ ror w11,w11,#6
+ eor w13,w7,w8
+ eor w15,w15,w7,ror#20
+ add v4.4s,v4.4s,v3.4s
+ add w6,w6,w11
+ ldr w12,[sp,#52]
+ and w14,w14,w13
+ ror w15,w15,#2
+ add w10,w10,w6
+ eor w14,w14,w8
+ add w5,w5,w12
+ add w6,w6,w15
+ and w12,w3,w10
+ bic w15,w4,w10
+ eor w11,w10,w10,ror#5
+ add w6,w6,w14
+ orr w12,w12,w15
+ eor w11,w11,w10,ror#19
+ eor w15,w6,w6,ror#11
+ add w5,w5,w12
+ ror w11,w11,#6
+ eor w14,w6,w7
+ eor w15,w15,w6,ror#20
+ add w5,w5,w11
+ ldr w12,[sp,#56]
+ and w13,w13,w14
+ ror w15,w15,#2
+ add w9,w9,w5
+ eor w13,w13,w7
+ add w4,w4,w12
+ add w5,w5,w15
+ and w12,w10,w9
+ bic w15,w3,w9
+ eor w11,w9,w9,ror#5
+ add w5,w5,w13
+ orr w12,w12,w15
+ eor w11,w11,w9,ror#19
+ eor w15,w5,w5,ror#11
+ add w4,w4,w12
+ ror w11,w11,#6
+ eor w13,w5,w6
+ eor w15,w15,w5,ror#20
+ add w4,w4,w11
+ ldr w12,[sp,#60]
+ and w14,w14,w13
+ ror w15,w15,#2
+ add w8,w8,w4
+ eor w14,w14,w6
+ add w3,w3,w12
+ add w4,w4,w15
+ and w12,w9,w8
+ bic w15,w10,w8
+ eor w11,w8,w8,ror#5
+ add w4,w4,w14
+ orr w12,w12,w15
+ eor w11,w11,w8,ror#19
+ eor w15,w4,w4,ror#11
+ add w3,w3,w12
+ ror w11,w11,#6
+ eor w14,w4,w5
+ eor w15,w15,w4,ror#20
+ add w3,w3,w11
+ and w13,w13,w14
+ ror w15,w15,#2
+ add w7,w7,w3
+ eor w13,w13,w5
+ st1 {v4.4s},[x17], #16
+ add w3,w3,w15 // h+=Sigma0(a) from the past
+ ldp w11,w12,[x0,#0]
+ add w3,w3,w13 // h+=Maj(a,b,c) from the past
+ ldp w13,w14,[x0,#8]
+ add w3,w3,w11 // accumulate
+ add w4,w4,w12
+ ldp w11,w12,[x0,#16]
+ add w5,w5,w13
+ add w6,w6,w14
+ ldp w13,w14,[x0,#24]
+ add w7,w7,w11
+ add w8,w8,w12
+ ldr w12,[sp,#0]
+ stp w3,w4,[x0,#0]
+ add w9,w9,w13
+ mov w13,wzr
+ stp w5,w6,[x0,#8]
+ add w10,w10,w14
+ stp w7,w8,[x0,#16]
+ eor w14,w4,w5
+ stp w9,w10,[x0,#24]
+ mov w15,wzr
+ mov x17,sp
+ b.ne .L_00_48
+
+ ldr x29,[x29]
+ add sp,sp,#16*4+16
+ ret
+.size sha256_block_neon,.-sha256_block_neon
diff --git a/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/sha512-armv8.S b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/sha512-armv8.S
new file mode 100644
index 000000000000..00269c027b3e
--- /dev/null
+++ b/CryptoPkg/Library/OpensslLib/OpensslGen/AARCH64-GCC/crypto/sha/sha512-armv8.S
@@ -0,0 +1,1606 @@
+// Copyright 2014-2020 The OpenSSL Project Authors. All Rights Reserved.
+//
+// Licensed under the Apache License 2.0 (the "License"). You may not use
+// this file except in compliance with the License. You can obtain a copy
+// in the file LICENSE in the source distribution or at
+// https://www.openssl.org/source/license.html
+
+// ====================================================================
+// Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
+// project. The module is, however, dual licensed under OpenSSL and
+// CRYPTOGAMS licenses depending on where you obtain it. For further
+// details see http://www.openssl.org/~appro/cryptogams/.
+//
+// Permission to use under GPLv2 terms is granted.
+// ====================================================================
+//
+// SHA256/512 for ARMv8.
+//
+// Performance in cycles per processed byte and improvement coefficient
+// over code generated with "default" compiler:
+//
+// SHA256-hw SHA256(*) SHA512
+// Apple A7 1.97 10.5 (+33%) 6.73 (-1%(**))
+// Cortex-A53 2.38 15.5 (+115%) 10.0 (+150%(***))
+// Cortex-A57 2.31 11.6 (+86%) 7.51 (+260%(***))
+// Denver 2.01 10.5 (+26%) 6.70 (+8%)
+// X-Gene 20.0 (+100%) 12.8 (+300%(***))
+// Mongoose 2.36 13.0 (+50%) 8.36 (+33%)
+// Kryo 1.92 17.4 (+30%) 11.2 (+8%)
+// ThunderX2 2.54 13.2 (+40%) 8.40 (+18%)
+//
+// (*) Software SHA256 results are of lesser relevance, presented
+// mostly for informational purposes.
+// (**) The result is a trade-off: it's possible to improve it by
+// 10% (or by 1 cycle per round), but at the cost of 20% loss
+// on Cortex-A53 (or by 4 cycles per round).
+// (***) Super-impressive coefficients over gcc-generated code are
+// indication of some compiler "pathology", most notably code
+// generated with -mgeneral-regs-only is significantly faster
+// and the gap is only 40-90%.
+//
+// October 2016.
+//
+// Originally it was reckoned that it makes no sense to implement NEON
+// version of SHA256 for 64-bit processors. This is because performance
+// improvement on most wide-spread Cortex-A5x processors was observed
+// to be marginal, same on Cortex-A53 and ~10% on A57. But then it was
+// observed that 32-bit NEON SHA256 performs significantly better than
+// 64-bit scalar version on *some* of the more recent processors. As
+// result 64-bit NEON version of SHA256 was added to provide best
+// all-round performance. For example it executes ~30% faster on X-Gene
+// and Mongoose. [For reference, NEON version of SHA512 is bound to
+// deliver much less improvement, likely *negative* on Cortex-A5x.
+// Which is why NEON support is limited to SHA256.]
+
+// $output is the last argument if it looks like a file (it has an extension)
+// $flavour is the first argument if it doesn't look like a file
+#ifndef __KERNEL__
+# include "arm_arch.h"
+
+.hidden OPENSSL_armcap_P
+#endif
+
+.text
+
+.globl sha512_block_data_order
+.type sha512_block_data_order,%function
+.align 6
+sha512_block_data_order:
+#ifndef __KERNEL__
+ adrp x16,OPENSSL_armcap_P
+ ldr w16,[x16,#:lo12:OPENSSL_armcap_P]
+ tst w16,#ARMV8_SHA512
+ b.ne .Lv8_entry
+#endif
+.inst 0xd503233f // paciasp
+ stp x29,x30,[sp,#-128]!
+ add x29,sp,#0
+
+ stp x19,x20,[sp,#16]
+ stp x21,x22,[sp,#32]
+ stp x23,x24,[sp,#48]
+ stp x25,x26,[sp,#64]
+ stp x27,x28,[sp,#80]
+ sub sp,sp,#4*8
+
+ ldp x20,x21,[x0] // load context
+ ldp x22,x23,[x0,#2*8]
+ ldp x24,x25,[x0,#4*8]
+ add x2,x1,x2,lsl#7 // end of input
+ ldp x26,x27,[x0,#6*8]
+ adr x30,.LK512
+ stp x0,x2,[x29,#96]
+
+.Loop:
+ ldp x3,x4,[x1],#2*8
+ ldr x19,[x30],#8 // *K++
+ eor x28,x21,x22 // magic seed
+ str x1,[x29,#112]
+#ifndef __AARCH64EB__
+ rev x3,x3 // 0
+#endif
+ ror x16,x24,#14
+ add x27,x27,x19 // h+=K[i]
+ eor x6,x24,x24,ror#23
+ and x17,x25,x24
+ bic x19,x26,x24
+ add x27,x27,x3 // h+=X[i]
+ orr x17,x17,x19 // Ch(e,f,g)
+ eor x19,x20,x21 // a^b, b^c in next round
+ eor x16,x16,x6,ror#18 // Sigma1(e)
+ ror x6,x20,#28
+ add x27,x27,x17 // h+=Ch(e,f,g)
+ eor x17,x20,x20,ror#5
+ add x27,x27,x16 // h+=Sigma1(e)
+ and x28,x28,x19 // (b^c)&=(a^b)
+ add x23,x23,x27 // d+=h
+ eor x28,x28,x21 // Maj(a,b,c)
+ eor x17,x6,x17,ror#34 // Sigma0(a)
+ add x27,x27,x28 // h+=Maj(a,b,c)
+ ldr x28,[x30],#8 // *K++, x19 in next round
+ //add x27,x27,x17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev x4,x4 // 1
+#endif
+ ldp x5,x6,[x1],#2*8
+ add x27,x27,x17 // h+=Sigma0(a)
+ ror x16,x23,#14
+ add x26,x26,x28 // h+=K[i]
+ eor x7,x23,x23,ror#23
+ and x17,x24,x23
+ bic x28,x25,x23
+ add x26,x26,x4 // h+=X[i]
+ orr x17,x17,x28 // Ch(e,f,g)
+ eor x28,x27,x20 // a^b, b^c in next round
+ eor x16,x16,x7,ror#18 // Sigma1(e)
+ ror x7,x27,#28
+ add x26,x26,x17 // h+=Ch(e,f,g)
+ eor x17,x27,x27,ror#5
+ add x26,x26,x16 // h+=Sigma1(e)
+ and x19,x19,x28 // (b^c)&=(a^b)
+ add x22,x22,x26 // d+=h
+ eor x19,x19,x20 // Maj(a,b,c)
+ eor x17,x7,x17,ror#34 // Sigma0(a)
+ add x26,x26,x19 // h+=Maj(a,b,c)
+ ldr x19,[x30],#8 // *K++, x28 in next round
+ //add x26,x26,x17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev x5,x5 // 2
+#endif
+ add x26,x26,x17 // h+=Sigma0(a)
+ ror x16,x22,#14
+ add x25,x25,x19 // h+=K[i]
+ eor x8,x22,x22,ror#23
+ and x17,x23,x22
+ bic x19,x24,x22
+ add x25,x25,x5 // h+=X[i]
+ orr x17,x17,x19 // Ch(e,f,g)
+ eor x19,x26,x27 // a^b, b^c in next round
+ eor x16,x16,x8,ror#18 // Sigma1(e)
+ ror x8,x26,#28
+ add x25,x25,x17 // h+=Ch(e,f,g)
+ eor x17,x26,x26,ror#5
+ add x25,x25,x16 // h+=Sigma1(e)
+ and x28,x28,x19 // (b^c)&=(a^b)
+ add x21,x21,x25 // d+=h
+ eor x28,x28,x27 // Maj(a,b,c)
+ eor x17,x8,x17,ror#34 // Sigma0(a)
+ add x25,x25,x28 // h+=Maj(a,b,c)
+ ldr x28,[x30],#8 // *K++, x19 in next round
+ //add x25,x25,x17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev x6,x6 // 3
+#endif
+ ldp x7,x8,[x1],#2*8
+ add x25,x25,x17 // h+=Sigma0(a)
+ ror x16,x21,#14
+ add x24,x24,x28 // h+=K[i]
+ eor x9,x21,x21,ror#23
+ and x17,x22,x21
+ bic x28,x23,x21
+ add x24,x24,x6 // h+=X[i]
+ orr x17,x17,x28 // Ch(e,f,g)
+ eor x28,x25,x26 // a^b, b^c in next round
+ eor x16,x16,x9,ror#18 // Sigma1(e)
+ ror x9,x25,#28
+ add x24,x24,x17 // h+=Ch(e,f,g)
+ eor x17,x25,x25,ror#5
+ add x24,x24,x16 // h+=Sigma1(e)
+ and x19,x19,x28 // (b^c)&=(a^b)
+ add x20,x20,x24 // d+=h
+ eor x19,x19,x26 // Maj(a,b,c)
+ eor x17,x9,x17,ror#34 // Sigma0(a)
+ add x24,x24,x19 // h+=Maj(a,b,c)
+ ldr x19,[x30],#8 // *K++, x28 in next round
+ //add x24,x24,x17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev x7,x7 // 4
+#endif
+ add x24,x24,x17 // h+=Sigma0(a)
+ ror x16,x20,#14
+ add x23,x23,x19 // h+=K[i]
+ eor x10,x20,x20,ror#23
+ and x17,x21,x20
+ bic x19,x22,x20
+ add x23,x23,x7 // h+=X[i]
+ orr x17,x17,x19 // Ch(e,f,g)
+ eor x19,x24,x25 // a^b, b^c in next round
+ eor x16,x16,x10,ror#18 // Sigma1(e)
+ ror x10,x24,#28
+ add x23,x23,x17 // h+=Ch(e,f,g)
+ eor x17,x24,x24,ror#5
+ add x23,x23,x16 // h+=Sigma1(e)
+ and x28,x28,x19 // (b^c)&=(a^b)
+ add x27,x27,x23 // d+=h
+ eor x28,x28,x25 // Maj(a,b,c)
+ eor x17,x10,x17,ror#34 // Sigma0(a)
+ add x23,x23,x28 // h+=Maj(a,b,c)
+ ldr x28,[x30],#8 // *K++, x19 in next round
+ //add x23,x23,x17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev x8,x8 // 5
+#endif
+ ldp x9,x10,[x1],#2*8
+ add x23,x23,x17 // h+=Sigma0(a)
+ ror x16,x27,#14
+ add x22,x22,x28 // h+=K[i]
+ eor x11,x27,x27,ror#23
+ and x17,x20,x27
+ bic x28,x21,x27
+ add x22,x22,x8 // h+=X[i]
+ orr x17,x17,x28 // Ch(e,f,g)
+ eor x28,x23,x24 // a^b, b^c in next round
+ eor x16,x16,x11,ror#18 // Sigma1(e)
+ ror x11,x23,#28
+ add x22,x22,x17 // h+=Ch(e,f,g)
+ eor x17,x23,x23,ror#5
+ add x22,x22,x16 // h+=Sigma1(e)
+ and x19,x19,x28 // (b^c)&=(a^b)
+ add x26,x26,x22 // d+=h
+ eor x19,x19,x24 // Maj(a,b,c)
+ eor x17,x11,x17,ror#34 // Sigma0(a)
+ add x22,x22,x19 // h+=Maj(a,b,c)
+ ldr x19,[x30],#8 // *K++, x28 in next round
+ //add x22,x22,x17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev x9,x9 // 6
+#endif
+ add x22,x22,x17 // h+=Sigma0(a)
+ ror x16,x26,#14
+ add x21,x21,x19 // h+=K[i]
+ eor x12,x26,x26,ror#23
+ and x17,x27,x26
+ bic x19,x20,x26
+ add x21,x21,x9 // h+=X[i]
+ orr x17,x17,x19 // Ch(e,f,g)
+ eor x19,x22,x23 // a^b, b^c in next round
+ eor x16,x16,x12,ror#18 // Sigma1(e)
+ ror x12,x22,#28
+ add x21,x21,x17 // h+=Ch(e,f,g)
+ eor x17,x22,x22,ror#5
+ add x21,x21,x16 // h+=Sigma1(e)
+ and x28,x28,x19 // (b^c)&=(a^b)
+ add x25,x25,x21 // d+=h
+ eor x28,x28,x23 // Maj(a,b,c)
+ eor x17,x12,x17,ror#34 // Sigma0(a)
+ add x21,x21,x28 // h+=Maj(a,b,c)
+ ldr x28,[x30],#8 // *K++, x19 in next round
+ //add x21,x21,x17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev x10,x10 // 7
+#endif
+ ldp x11,x12,[x1],#2*8
+ add x21,x21,x17 // h+=Sigma0(a)
+ ror x16,x25,#14
+ add x20,x20,x28 // h+=K[i]
+ eor x13,x25,x25,ror#23
+ and x17,x26,x25
+ bic x28,x27,x25
+ add x20,x20,x10 // h+=X[i]
+ orr x17,x17,x28 // Ch(e,f,g)
+ eor x28,x21,x22 // a^b, b^c in next round
+ eor x16,x16,x13,ror#18 // Sigma1(e)
+ ror x13,x21,#28
+ add x20,x20,x17 // h+=Ch(e,f,g)
+ eor x17,x21,x21,ror#5
+ add x20,x20,x16 // h+=Sigma1(e)
+ and x19,x19,x28 // (b^c)&=(a^b)
+ add x24,x24,x20 // d+=h
+ eor x19,x19,x22 // Maj(a,b,c)
+ eor x17,x13,x17,ror#34 // Sigma0(a)
+ add x20,x20,x19 // h+=Maj(a,b,c)
+ ldr x19,[x30],#8 // *K++, x28 in next round
+ //add x20,x20,x17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev x11,x11 // 8
+#endif
+ add x20,x20,x17 // h+=Sigma0(a)
+ ror x16,x24,#14
+ add x27,x27,x19 // h+=K[i]
+ eor x14,x24,x24,ror#23
+ and x17,x25,x24
+ bic x19,x26,x24
+ add x27,x27,x11 // h+=X[i]
+ orr x17,x17,x19 // Ch(e,f,g)
+ eor x19,x20,x21 // a^b, b^c in next round
+ eor x16,x16,x14,ror#18 // Sigma1(e)
+ ror x14,x20,#28
+ add x27,x27,x17 // h+=Ch(e,f,g)
+ eor x17,x20,x20,ror#5
+ add x27,x27,x16 // h+=Sigma1(e)
+ and x28,x28,x19 // (b^c)&=(a^b)
+ add x23,x23,x27 // d+=h
+ eor x28,x28,x21 // Maj(a,b,c)
+ eor x17,x14,x17,ror#34 // Sigma0(a)
+ add x27,x27,x28 // h+=Maj(a,b,c)
+ ldr x28,[x30],#8 // *K++, x19 in next round
+ //add x27,x27,x17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev x12,x12 // 9
+#endif
+ ldp x13,x14,[x1],#2*8
+ add x27,x27,x17 // h+=Sigma0(a)
+ ror x16,x23,#14
+ add x26,x26,x28 // h+=K[i]
+ eor x15,x23,x23,ror#23
+ and x17,x24,x23
+ bic x28,x25,x23
+ add x26,x26,x12 // h+=X[i]
+ orr x17,x17,x28 // Ch(e,f,g)
+ eor x28,x27,x20 // a^b, b^c in next round
+ eor x16,x16,x15,ror#18 // Sigma1(e)
+ ror x15,x27,#28
+ add x26,x26,x17 // h+=Ch(e,f,g)
+ eor x17,x27,x27,ror#5
+ add x26,x26,x16 // h+=Sigma1(e)
+ and x19,x19,x28 // (b^c)&=(a^b)
+ add x22,x22,x26 // d+=h
+ eor x19,x19,x20 // Maj(a,b,c)
+ eor x17,x15,x17,ror#34 // Sigma0(a)
+ add x26,x26,x19 // h+=Maj(a,b,c)
+ ldr x19,[x30],#8 // *K++, x28 in next round
+ //add x26,x26,x17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev x13,x13 // 10
+#endif
+ add x26,x26,x17 // h+=Sigma0(a)
+ ror x16,x22,#14
+ add x25,x25,x19 // h+=K[i]
+ eor x0,x22,x22,ror#23
+ and x17,x23,x22
+ bic x19,x24,x22
+ add x25,x25,x13 // h+=X[i]
+ orr x17,x17,x19 // Ch(e,f,g)
+ eor x19,x26,x27 // a^b, b^c in next round
+ eor x16,x16,x0,ror#18 // Sigma1(e)
+ ror x0,x26,#28
+ add x25,x25,x17 // h+=Ch(e,f,g)
+ eor x17,x26,x26,ror#5
+ add x25,x25,x16 // h+=Sigma1(e)
+ and x28,x28,x19 // (b^c)&=(a^b)
+ add x21,x21,x25 // d+=h
+ eor x28,x28,x27 // Maj(a,b,c)
+ eor x17,x0,x17,ror#34 // Sigma0(a)
+ add x25,x25,x28 // h+=Maj(a,b,c)
+ ldr x28,[x30],#8 // *K++, x19 in next round
+ //add x25,x25,x17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev x14,x14 // 11
+#endif
+ ldp x15,x0,[x1],#2*8
+ add x25,x25,x17 // h+=Sigma0(a)
+ str x6,[sp,#24]
+ ror x16,x21,#14
+ add x24,x24,x28 // h+=K[i]
+ eor x6,x21,x21,ror#23
+ and x17,x22,x21
+ bic x28,x23,x21
+ add x24,x24,x14 // h+=X[i]
+ orr x17,x17,x28 // Ch(e,f,g)
+ eor x28,x25,x26 // a^b, b^c in next round
+ eor x16,x16,x6,ror#18 // Sigma1(e)
+ ror x6,x25,#28
+ add x24,x24,x17 // h+=Ch(e,f,g)
+ eor x17,x25,x25,ror#5
+ add x24,x24,x16 // h+=Sigma1(e)
+ and x19,x19,x28 // (b^c)&=(a^b)
+ add x20,x20,x24 // d+=h
+ eor x19,x19,x26 // Maj(a,b,c)
+ eor x17,x6,x17,ror#34 // Sigma0(a)
+ add x24,x24,x19 // h+=Maj(a,b,c)
+ ldr x19,[x30],#8 // *K++, x28 in next round
+ //add x24,x24,x17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev x15,x15 // 12
+#endif
+ add x24,x24,x17 // h+=Sigma0(a)
+ str x7,[sp,#0]
+ ror x16,x20,#14
+ add x23,x23,x19 // h+=K[i]
+ eor x7,x20,x20,ror#23
+ and x17,x21,x20
+ bic x19,x22,x20
+ add x23,x23,x15 // h+=X[i]
+ orr x17,x17,x19 // Ch(e,f,g)
+ eor x19,x24,x25 // a^b, b^c in next round
+ eor x16,x16,x7,ror#18 // Sigma1(e)
+ ror x7,x24,#28
+ add x23,x23,x17 // h+=Ch(e,f,g)
+ eor x17,x24,x24,ror#5
+ add x23,x23,x16 // h+=Sigma1(e)
+ and x28,x28,x19 // (b^c)&=(a^b)
+ add x27,x27,x23 // d+=h
+ eor x28,x28,x25 // Maj(a,b,c)
+ eor x17,x7,x17,ror#34 // Sigma0(a)
+ add x23,x23,x28 // h+=Maj(a,b,c)
+ ldr x28,[x30],#8 // *K++, x19 in next round
+ //add x23,x23,x17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev x0,x0 // 13
+#endif
+ ldp x1,x2,[x1]
+ add x23,x23,x17 // h+=Sigma0(a)
+ str x8,[sp,#8]
+ ror x16,x27,#14
+ add x22,x22,x28 // h+=K[i]
+ eor x8,x27,x27,ror#23
+ and x17,x20,x27
+ bic x28,x21,x27
+ add x22,x22,x0 // h+=X[i]
+ orr x17,x17,x28 // Ch(e,f,g)
+ eor x28,x23,x24 // a^b, b^c in next round
+ eor x16,x16,x8,ror#18 // Sigma1(e)
+ ror x8,x23,#28
+ add x22,x22,x17 // h+=Ch(e,f,g)
+ eor x17,x23,x23,ror#5
+ add x22,x22,x16 // h+=Sigma1(e)
+ and x19,x19,x28 // (b^c)&=(a^b)
+ add x26,x26,x22 // d+=h
+ eor x19,x19,x24 // Maj(a,b,c)
+ eor x17,x8,x17,ror#34 // Sigma0(a)
+ add x22,x22,x19 // h+=Maj(a,b,c)
+ ldr x19,[x30],#8 // *K++, x28 in next round
+ //add x22,x22,x17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev x1,x1 // 14
+#endif
+ ldr x6,[sp,#24]
+ add x22,x22,x17 // h+=Sigma0(a)
+ str x9,[sp,#16]
+ ror x16,x26,#14
+ add x21,x21,x19 // h+=K[i]
+ eor x9,x26,x26,ror#23
+ and x17,x27,x26
+ bic x19,x20,x26
+ add x21,x21,x1 // h+=X[i]
+ orr x17,x17,x19 // Ch(e,f,g)
+ eor x19,x22,x23 // a^b, b^c in next round
+ eor x16,x16,x9,ror#18 // Sigma1(e)
+ ror x9,x22,#28
+ add x21,x21,x17 // h+=Ch(e,f,g)
+ eor x17,x22,x22,ror#5
+ add x21,x21,x16 // h+=Sigma1(e)
+ and x28,x28,x19 // (b^c)&=(a^b)
+ add x25,x25,x21 // d+=h
+ eor x28,x28,x23 // Maj(a,b,c)
+ eor x17,x9,x17,ror#34 // Sigma0(a)
+ add x21,x21,x28 // h+=Maj(a,b,c)
+ ldr x28,[x30],#8 // *K++, x19 in next round
+ //add x21,x21,x17 // h+=Sigma0(a)
+#ifndef __AARCH64EB__
+ rev x2,x2 // 15
+#endif
+ ldr x7,[sp,#0]
+ add x21,x21,x17 // h+=Sigma0(a)
+ str x10,[sp,#24]
+ ror x16,x25,#14
+ add x20,x20,x28 // h+=K[i]
+ ror x9,x4,#1
+ and x17,x26,x25
+ ror x8,x1,#19
+ bic x28,x27,x25
+ ror x10,x21,#28
+ add x20,x20,x2 // h+=X[i]
+ eor x16,x16,x25,ror#18
+ eor x9,x9,x4,ror#8
+ orr x17,x17,x28 // Ch(e,f,g)
+ eor x28,x21,x22 // a^b, b^c in next round
+ eor x16,x16,x25,ror#41 // Sigma1(e)
+ eor x10,x10,x21,ror#34
+ add x20,x20,x17 // h+=Ch(e,f,g)
+ and x19,x19,x28 // (b^c)&=(a^b)
+ eor x8,x8,x1,ror#61
+ eor x9,x9,x4,lsr#7 // sigma0(X[i+1])
+ add x20,x20,x16 // h+=Sigma1(e)
+ eor x19,x19,x22 // Maj(a,b,c)
+ eor x17,x10,x21,ror#39 // Sigma0(a)
+ eor x8,x8,x1,lsr#6 // sigma1(X[i+14])
+ add x3,x3,x12
+ add x24,x24,x20 // d+=h
+ add x20,x20,x19 // h+=Maj(a,b,c)
+ ldr x19,[x30],#8 // *K++, x28 in next round
+ add x3,x3,x9
+ add x20,x20,x17 // h+=Sigma0(a)
+ add x3,x3,x8
+.Loop_16_xx:
+ ldr x8,[sp,#8]
+ str x11,[sp,#0]
+ ror x16,x24,#14
+ add x27,x27,x19 // h+=K[i]
+ ror x10,x5,#1
+ and x17,x25,x24
+ ror x9,x2,#19
+ bic x19,x26,x24
+ ror x11,x20,#28
+ add x27,x27,x3 // h+=X[i]
+ eor x16,x16,x24,ror#18
+ eor x10,x10,x5,ror#8
+ orr x17,x17,x19 // Ch(e,f,g)
+ eor x19,x20,x21 // a^b, b^c in next round
+ eor x16,x16,x24,ror#41 // Sigma1(e)
+ eor x11,x11,x20,ror#34
+ add x27,x27,x17 // h+=Ch(e,f,g)
+ and x28,x28,x19 // (b^c)&=(a^b)
+ eor x9,x9,x2,ror#61
+ eor x10,x10,x5,lsr#7 // sigma0(X[i+1])
+ add x27,x27,x16 // h+=Sigma1(e)
+ eor x28,x28,x21 // Maj(a,b,c)
+ eor x17,x11,x20,ror#39 // Sigma0(a)
+ eor x9,x9,x2,lsr#6 // sigma1(X[i+14])
+ add x4,x4,x13
+ add x23,x23,x27 // d+=h
+ add x27,x27,x28 // h+=Maj(a,b,c)
+ ldr x28,[x30],#8 // *K++, x19 in next round
+ add x4,x4,x10
+ add x27,x27,x17 // h+=Sigma0(a)
+ add x4,x4,x9
+ ldr x9,[sp,#16]
+ str x12,[sp,#8]
+ ror x16,x23,#14
+ add x26,x26,x28 // h+=K[i]
+ ror x11,x6,#1
+ and x17,x24,x23
+ ror x10,x3,#19
+ bic x28,x25,x23
+ ror x12,x27,#28
+ add x26,x26,x4 // h+=X[i]
+ eor x16,x16,x23,ror#18
+ eor x11,x11,x6,ror#8
+ orr x17,x17,x28 // Ch(e,f,g)
+ eor x28,x27,x20 // a^b, b^c in next round
+ eor x16,x16,x23,ror#41 // Sigma1(e)
+ eor x12,x12,x27,ror#34
+ add x26,x26,x17 // h+=Ch(e,f,g)
+ and x19,x19,x28 // (b^c)&=(a^b)
+ eor x10,x10,x3,ror#61
+ eor x11,x11,x6,lsr#7 // sigma0(X[i+1])
+ add x26,x26,x16 // h+=Sigma1(e)
+ eor x19,x19,x20 // Maj(a,b,c)
+ eor x17,x12,x27,ror#39 // Sigma0(a)
+ eor x10,x10,x3,lsr#6 // sigma1(X[i+14])
+ add x5,x5,x14
+ add x22,x22,x26 // d+=h
+ add x26,x26,x19 // h+=Maj(a,b,c)
+ ldr x19,[x30],#8 // *K++, x28 in next round
+ add x5,x5,x11
+ add x26,x26,x17 // h+=Sigma0(a)
+ add x5,x5,x10
+ ldr x10,[sp,#24]
+ str x13,[sp,#16]
+ ror x16,x22,#14
+ add x25,x25,x19 // h+=K[i]
+ ror x12,x7,#1
+ and x17,x23,x22
+ ror x11,x4,#19
+ bic x19,x24,x22
+ ror x13,x26,#28
+ add x25,x25,x5 // h+=X[i]
+ eor x16,x16,x22,ror#18
+ eor x12,x12,x7,ror#8
+ orr x17,x17,x19 // Ch(e,f,g)
+ eor x19,x26,x27 // a^b, b^c in next round
+ eor x16,x16,x22,ror#41 // Sigma1(e)
+ eor x13,x13,x26,ror#34
+ add x25,x25,x17 // h+=Ch(e,f,g)
+ and x28,x28,x19 // (b^c)&=(a^b)
+ eor x11,x11,x4,ror#61
+ eor x12,x12,x7,lsr#7 // sigma0(X[i+1])
+ add x25,x25,x16 // h+=Sigma1(e)
+ eor x28,x28,x27 // Maj(a,b,c)
+ eor x17,x13,x26,ror#39 // Sigma0(a)
+ eor x11,x11,x4,lsr#6 // sigma1(X[i+14])
+ add x6,x6,x15
+ add x21,x21,x25 // d+=h
+ add x25,x25,x28 // h+=Maj(a,b,c)
+ ldr x28,[x30],#8 // *K++, x19 in next round
+ add x6,x6,x12
+ add x25,x25,x17 // h+=Sigma0(a)
+ add x6,x6,x11
+ ldr x11,[sp,#0]
+ str x14,[sp,#24]
+ ror x16,x21,#14
+ add x24,x24,x28 // h+=K[i]
+ ror x13,x8,#1
+ and x17,x22,x21
+ ror x12,x5,#19
+ bic x28,x23,x21
+ ror x14,x25,#28
+ add x24,x24,x6 // h+=X[i]
+ eor x16,x16,x21,ror#18
+ eor x13,x13,x8,ror#8
+ orr x17,x17,x28 // Ch(e,f,g)
+ eor x28,x25,x26 // a^b, b^c in next round
+ eor x16,x16,x21,ror#41 // Sigma1(e)
+ eor x14,x14,x25,ror#34
+ add x24,x24,x17 // h+=Ch(e,f,g)
+ and x19,x19,x28 // (b^c)&=(a^b)
+ eor x12,x12,x5,ror#61
+ eor x13,x13,x8,lsr#7 // sigma0(X[i+1])
+ add x24,x24,x16 // h+=Sigma1(e)
+ eor x19,x19,x26 // Maj(a,b,c)
+ eor x17,x14,x25,ror#39 // Sigma0(a)
+ eor x12,x12,x5,lsr#6 // sigma1(X[i+14])
+ add x7,x7,x0
+ add x20,x20,x24 // d+=h
+ add x24,x24,x19 // h+=Maj(a,b,c)
+ ldr x19,[x30],#8 // *K++, x28 in next round
+ add x7,x7,x13
+ add x24,x24,x17 // h+=Sigma0(a)
+ add x7,x7,x12
+ ldr x12,[sp,#8]
+ str x15,[sp,#0]
+ ror x16,x20,#14
+ add x23,x23,x19 // h+=K[i]
+ ror x14,x9,#1
+ and x17,x21,x20
+ ror x13,x6,#19
+ bic x19,x22,x20
+ ror x15,x24,#28
+ add x23,x23,x7 // h+=X[i]
+ eor x16,x16,x20,ror#18
+ eor x14,x14,x9,ror#8
+ orr x17,x17,x19 // Ch(e,f,g)
+ eor x19,x24,x25 // a^b, b^c in next round
+ eor x16,x16,x20,ror#41 // Sigma1(e)
+ eor x15,x15,x24,ror#34
+ add x23,x23,x17 // h+=Ch(e,f,g)
+ and x28,x28,x19 // (b^c)&=(a^b)
+ eor x13,x13,x6,ror#61
+ eor x14,x14,x9,lsr#7 // sigma0(X[i+1])
+ add x23,x23,x16 // h+=Sigma1(e)
+ eor x28,x28,x25 // Maj(a,b,c)
+ eor x17,x15,x24,ror#39 // Sigma0(a)
+ eor x13,x13,x6,lsr#6 // sigma1(X[i+14])
+ add x8,x8,x1
+ add x27,x27,x23 // d+=h
+ add x23,x23,x28 // h+=Maj(a,b,c)
+ ldr x28,[x30],#8 // *K++, x19 in next round
+ add x8,x8,x14
+ add x23,x23,x17 // h+=Sigma0(a)
+ add x8,x8,x13
+ ldr x13,[sp,#16]
+ str x0,[sp,#8]
+ ror x16,x27,#14
+ add x22,x22,x28 // h+=K[i]
+ ror x15,x10,#1
+ and x17,x20,x27
+ ror x14,x7,#19
+ bic x28,x21,x27
+ ror x0,x23,#28
+ add x22,x22,x8 // h+=X[i]
+ eor x16,x16,x27,ror#18
+ eor x15,x15,x10,ror#8
+ orr x17,x17,x28 // Ch(e,f,g)
+ eor x28,x23,x24 // a^b, b^c in next round
+ eor x16,x16,x27,ror#41 // Sigma1(e)
+ eor x0,x0,x23,ror#34
+ add x22,x22,x17 // h+=Ch(e,f,g)
+ and x19,x19,x28 // (b^c)&=(a^b)
+ eor x14,x14,x7,ror#61
+ eor x15,x15,x10,lsr#7 // sigma0(X[i+1])
+ add x22,x22,x16 // h+=Sigma1(e)
+ eor x19,x19,x24 // Maj(a,b,c)
+ eor x17,x0,x23,ror#39 // Sigma0(a)
+ eor x14,x14,x7,lsr#6 // sigma1(X[i+14])
+ add x9,x9,x2
+ add x26,x26,x22 // d+=h
+ add x22,x22,x19 // h+=Maj(a,b,c)
+ ldr x19,[x30],#8 // *K++, x28 in next round
+ add x9,x9,x15
+ add x22,x22,x17 // h+=Sigma0(a)
+ add x9,x9,x14
+ ldr x14,[sp,#24]
+ str x1,[sp,#16]
+ ror x16,x26,#14
+ add x21,x21,x19 // h+=K[i]
+ ror x0,x11,#1
+ and x17,x27,x26
+ ror x15,x8,#19
+ bic x19,x20,x26
+ ror x1,x22,#28
+ add x21,x21,x9 // h+=X[i]
+ eor x16,x16,x26,ror#18
+ eor x0,x0,x11,ror#8
+ orr x17,x17,x19 // Ch(e,f,g)
+ eor x19,x22,x23 // a^b, b^c in next round
+ eor x16,x16,x26,ror#41 // Sigma1(e)
+ eor x1,x1,x22,ror#34
+ add x21,x21,x17 // h+=Ch(e,f,g)
+ and x28,x28,x19 // (b^c)&=(a^b)
+ eor x15,x15,x8,ror#61
+ eor x0,x0,x11,lsr#7 // sigma0(X[i+1])
+ add x21,x21,x16 // h+=Sigma1(e)
+ eor x28,x28,x23 // Maj(a,b,c)
+ eor x17,x1,x22,ror#39 // Sigma0(a)
+ eor x15,x15,x8,lsr#6 // sigma1(X[i+14])
+ add x10,x10,x3
+ add x25,x25,x21 // d+=h
+ add x21,x21,x28 // h+=Maj(a,b,c)
+ ldr x28,[x30],#8 // *K++, x19 in next round
+ add x10,x10,x0
+ add x21,x21,x17 // h+=Sigma0(a)
+ add x10,x10,x15
+ ldr x15,[sp,#0]
+ str x2,[sp,#24]
+ ror x16,x25,#14
+ add x20,x20,x28 // h+=K[i]
+ ror x1,x12,#1
+ and x17,x26,x25
+ ror x0,x9,#19
+ bic x28,x27,x25
+ ror x2,x21,#28
+ add x20,x20,x10 // h+=X[i]
+ eor x16,x16,x25,ror#18
+ eor x1,x1,x12,ror#8
+ orr x17,x17,x28 // Ch(e,f,g)
+ eor x28,x21,x22 // a^b, b^c in next round
+ eor x16,x16,x25,ror#41 // Sigma1(e)
+ eor x2,x2,x21,ror#34
+ add x20,x20,x17 // h+=Ch(e,f,g)
+ and x19,x19,x28 // (b^c)&=(a^b)
+ eor x0,x0,x9,ror#61
+ eor x1,x1,x12,lsr#7 // sigma0(X[i+1])
+ add x20,x20,x16 // h+=Sigma1(e)
+ eor x19,x19,x22 // Maj(a,b,c)
+ eor x17,x2,x21,ror#39 // Sigma0(a)
+ eor x0,x0,x9,lsr#6 // sigma1(X[i+14])
+ add x11,x11,x4
+ add x24,x24,x20 // d+=h
+ add x20,x20,x19 // h+=Maj(a,b,c)
+ ldr x19,[x30],#8 // *K++, x28 in next round
+ add x11,x11,x1
+ add x20,x20,x17 // h+=Sigma0(a)
+ add x11,x11,x0
+ ldr x0,[sp,#8]
+ str x3,[sp,#0]
+ ror x16,x24,#14
+ add x27,x27,x19 // h+=K[i]
+ ror x2,x13,#1
+ and x17,x25,x24
+ ror x1,x10,#19
+ bic x19,x26,x24
+ ror x3,x20,#28
+ add x27,x27,x11 // h+=X[i]
+ eor x16,x16,x24,ror#18
+ eor x2,x2,x13,ror#8
+ orr x17,x17,x19 // Ch(e,f,g)
+ eor x19,x20,x21 // a^b, b^c in next round
+ eor x16,x16,x24,ror#41 // Sigma1(e)
+ eor x3,x3,x20,ror#34
+ add x27,x27,x17 // h+=Ch(e,f,g)
+ and x28,x28,x19 // (b^c)&=(a^b)
+ eor x1,x1,x10,ror#61
+ eor x2,x2,x13,lsr#7 // sigma0(X[i+1])
+ add x27,x27,x16 // h+=Sigma1(e)
+ eor x28,x28,x21 // Maj(a,b,c)
+ eor x17,x3,x20,ror#39 // Sigma0(a)
+ eor x1,x1,x10,lsr#6 // sigma1(X[i+14])
+ add x12,x12,x5
+ add x23,x23,x27 // d+=h
+ add x27,x27,x28 // h+=Maj(a,b,c)
+ ldr x28,[x30],#8 // *K++, x19 in next round
+ add x12,x12,x2
+ add x27,x27,x17 // h+=Sigma0(a)
+ add x12,x12,x1
+ ldr x1,[sp,#16]
+ str x4,[sp,#8]
+ ror x16,x23,#14
+ add x26,x26,x28 // h+=K[i]
+ ror x3,x14,#1
+ and x17,x24,x23
+ ror x2,x11,#19
+ bic x28,x25,x23
+ ror x4,x27,#28
+ add x26,x26,x12 // h+=X[i]
+ eor x16,x16,x23,ror#18
+ eor x3,x3,x14,ror#8
+ orr x17,x17,x28 // Ch(e,f,g)
+ eor x28,x27,x20 // a^b, b^c in next round
+ eor x16,x16,x23,ror#41 // Sigma1(e)
+ eor x4,x4,x27,ror#34
+ add x26,x26,x17 // h+=Ch(e,f,g)
+ and x19,x19,x28 // (b^c)&=(a^b)
+ eor x2,x2,x11,ror#61
+ eor x3,x3,x14,lsr#7 // sigma0(X[i+1])
+ add x26,x26,x16 // h+=Sigma1(e)
+ eor x19,x19,x20 // Maj(a,b,c)
+ eor x17,x4,x27,ror#39 // Sigma0(a)
+ eor x2,x2,x11,lsr#6 // sigma1(X[i+14])
+ add x13,x13,x6
+ add x22,x22,x26 // d+=h
+ add x26,x26,x19 // h+=Maj(a,b,c)
+ ldr x19,[x30],#8 // *K++, x28 in next round
+ add x13,x13,x3
+ add x26,x26,x17 // h+=Sigma0(a)
+ add x13,x13,x2
+ ldr x2,[sp,#24]
+ str x5,[sp,#16]
+ ror x16,x22,#14
+ add x25,x25,x19 // h+=K[i]
+ ror x4,x15,#1
+ and x17,x23,x22
+ ror x3,x12,#19
+ bic x19,x24,x22
+ ror x5,x26,#28
+ add x25,x25,x13 // h+=X[i]
+ eor x16,x16,x22,ror#18
+ eor x4,x4,x15,ror#8
+ orr x17,x17,x19 // Ch(e,f,g)
+ eor x19,x26,x27 // a^b, b^c in next round
+ eor x16,x16,x22,ror#41 // Sigma1(e)
+ eor x5,x5,x26,ror#34
+ add x25,x25,x17 // h+=Ch(e,f,g)
+ and x28,x28,x19 // (b^c)&=(a^b)
+ eor x3,x3,x12,ror#61
+ eor x4,x4,x15,lsr#7 // sigma0(X[i+1])
+ add x25,x25,x16 // h+=Sigma1(e)
+ eor x28,x28,x27 // Maj(a,b,c)
+ eor x17,x5,x26,ror#39 // Sigma0(a)
+ eor x3,x3,x12,lsr#6 // sigma1(X[i+14])
+ add x14,x14,x7
+ add x21,x21,x25 // d+=h
+ add x25,x25,x28 // h+=Maj(a,b,c)
+ ldr x28,[x30],#8 // *K++, x19 in next round
+ add x14,x14,x4
+ add x25,x25,x17 // h+=Sigma0(a)
+ add x14,x14,x3
+ ldr x3,[sp,#0]
+ str x6,[sp,#24]
+ ror x16,x21,#14
+ add x24,x24,x28 // h+=K[i]
+ ror x5,x0,#1
+ and x17,x22,x21
+ ror x4,x13,#19
+ bic x28,x23,x21
+ ror x6,x25,#28
+ add x24,x24,x14 // h+=X[i]
+ eor x16,x16,x21,ror#18
+ eor x5,x5,x0,ror#8
+ orr x17,x17,x28 // Ch(e,f,g)
+ eor x28,x25,x26 // a^b, b^c in next round
+ eor x16,x16,x21,ror#41 // Sigma1(e)
+ eor x6,x6,x25,ror#34
+ add x24,x24,x17 // h+=Ch(e,f,g)
+ and x19,x19,x28 // (b^c)&=(a^b)
+ eor x4,x4,x13,ror#61
+ eor x5,x5,x0,lsr#7 // sigma0(X[i+1])
+ add x24,x24,x16 // h+=Sigma1(e)
+ eor x19,x19,x26 // Maj(a,b,c)
+ eor x17,x6,x25,ror#39 // Sigma0(a)
+ eor x4,x4,x13,lsr#6 // sigma1(X[i+14])
+ add x15,x15,x8
+ add x20,x20,x24 // d+=h
+ add x24,x24,x19 // h+=Maj(a,b,c)
+ ldr x19,[x30],#8 // *K++, x28 in next round
+ add x15,x15,x5
+ add x24,x24,x17 // h+=Sigma0(a)
+ add x15,x15,x4
+ ldr x4,[sp,#8]
+ str x7,[sp,#0]
+ ror x16,x20,#14
+ add x23,x23,x19 // h+=K[i]
+ ror x6,x1,#1
+ and x17,x21,x20
+ ror x5,x14,#19
+ bic x19,x22,x20
+ ror x7,x24,#28
+ add x23,x23,x15 // h+=X[i]
+ eor x16,x16,x20,ror#18
+ eor x6,x6,x1,ror#8
+ orr x17,x17,x19 // Ch(e,f,g)
+ eor x19,x24,x25 // a^b, b^c in next round
+ eor x16,x16,x20,ror#41 // Sigma1(e)
+ eor x7,x7,x24,ror#34
+ add x23,x23,x17 // h+=Ch(e,f,g)
+ and x28,x28,x19 // (b^c)&=(a^b)
+ eor x5,x5,x14,ror#61
+ eor x6,x6,x1,lsr#7 // sigma0(X[i+1])
+ add x23,x23,x16 // h+=Sigma1(e)
+ eor x28,x28,x25 // Maj(a,b,c)
+ eor x17,x7,x24,ror#39 // Sigma0(a)
+ eor x5,x5,x14,lsr#6 // sigma1(X[i+14])
+ add x0,x0,x9
+ add x27,x27,x23 // d+=h
+ add x23,x23,x28 // h+=Maj(a,b,c)
+ ldr x28,[x30],#8 // *K++, x19 in next round
+ add x0,x0,x6
+ add x23,x23,x17 // h+=Sigma0(a)
+ add x0,x0,x5
+ ldr x5,[sp,#16]
+ str x8,[sp,#8]
+ ror x16,x27,#14
+ add x22,x22,x28 // h+=K[i]
+ ror x7,x2,#1
+ and x17,x20,x27
+ ror x6,x15,#19
+ bic x28,x21,x27
+ ror x8,x23,#28
+ add x22,x22,x0 // h+=X[i]
+ eor x16,x16,x27,ror#18
+ eor x7,x7,x2,ror#8
+ orr x17,x17,x28 // Ch(e,f,g)
+ eor x28,x23,x24 // a^b, b^c in next round
+ eor x16,x16,x27,ror#41 // Sigma1(e)
+ eor x8,x8,x23,ror#34
+ add x22,x22,x17 // h+=Ch(e,f,g)
+ and x19,x19,x28 // (b^c)&=(a^b)
+ eor x6,x6,x15,ror#61
+ eor x7,x7,x2,lsr#7 // sigma0(X[i+1])
+ add x22,x22,x16 // h+=Sigma1(e)
+ eor x19,x19,x24 // Maj(a,b,c)
+ eor x17,x8,x23,ror#39 // Sigma0(a)
+ eor x6,x6,x15,lsr#6 // sigma1(X[i+14])
+ add x1,x1,x10
+ add x26,x26,x22 // d+=h
+ add x22,x22,x19 // h+=Maj(a,b,c)
+ ldr x19,[x30],#8 // *K++, x28 in next round
+ add x1,x1,x7
+ add x22,x22,x17 // h+=Sigma0(a)
+ add x1,x1,x6
+ ldr x6,[sp,#24]
+ str x9,[sp,#16]
+ ror x16,x26,#14
+ add x21,x21,x19 // h+=K[i]
+ ror x8,x3,#1
+ and x17,x27,x26
+ ror x7,x0,#19
+ bic x19,x20,x26
+ ror x9,x22,#28
+ add x21,x21,x1 // h+=X[i]
+ eor x16,x16,x26,ror#18
+ eor x8,x8,x3,ror#8
+ orr x17,x17,x19 // Ch(e,f,g)
+ eor x19,x22,x23 // a^b, b^c in next round
+ eor x16,x16,x26,ror#41 // Sigma1(e)
+ eor x9,x9,x22,ror#34
+ add x21,x21,x17 // h+=Ch(e,f,g)
+ and x28,x28,x19 // (b^c)&=(a^b)
+ eor x7,x7,x0,ror#61
+ eor x8,x8,x3,lsr#7 // sigma0(X[i+1])
+ add x21,x21,x16 // h+=Sigma1(e)
+ eor x28,x28,x23 // Maj(a,b,c)
+ eor x17,x9,x22,ror#39 // Sigma0(a)
+ eor x7,x7,x0,lsr#6 // sigma1(X[i+14])
+ add x2,x2,x11
+ add x25,x25,x21 // d+=h
+ add x21,x21,x28 // h+=Maj(a,b,c)
+ ldr x28,[x30],#8 // *K++, x19 in next round
+ add x2,x2,x8
+ add x21,x21,x17 // h+=Sigma0(a)
+ add x2,x2,x7
+ ldr x7,[sp,#0]
+ str x10,[sp,#24]
+ ror x16,x25,#14
+ add x20,x20,x28 // h+=K[i]
+ ror x9,x4,#1
+ and x17,x26,x25
+ ror x8,x1,#19
+ bic x28,x27,x25
+ ror x10,x21,#28
+ add x20,x20,x2 // h+=X[i]
+ eor x16,x16,x25,ror#18
+ eor x9,x9,x4,ror#8
+ orr x17,x17,x28 // Ch(e,f,g)
+ eor x28,x21,x22 // a^b, b^c in next round
+ eor x16,x16,x25,ror#41 // Sigma1(e)
+ eor x10,x10,x21,ror#34
+ add x20,x20,x17 // h+=Ch(e,f,g)
+ and x19,x19,x28 // (b^c)&=(a^b)
+ eor x8,x8,x1,ror#61
+ eor x9,x9,x4,lsr#7 // sigma0(X[i+1])
+ add x20,x20,x16 // h+=Sigma1(e)
+ eor x19,x19,x22 // Maj(a,b,c)
+ eor x17,x10,x21,ror#39 // Sigma0(a)
+ eor x8,x8,x1,lsr#6 // sigma1(X[i+14])
+ add x3,x3,x12
+ add x24,x24,x20 // d+=h
+ add x20,x20,x19 // h+=Maj(a,b,c)
+ ldr x19,[x30],#8 // *K++, x28 in next round
+ add x3,x3,x9
+ add x20,x20,x17 // h+=Sigma0(a)
+ add x3,x3,x8
+ cbnz x19,.Loop_16_xx
+
+ ldp x0,x2,[x29,#96]
+ ldr x1,[x29,#112]
+ sub x30,x30,#648 // rewind
+
+ ldp x3,x4,[x0]
+ ldp x5,x6,[x0,#2*8]
+ add x1,x1,#14*8 // advance input pointer
+ ldp x7,x8,[x0,#4*8]
+ add x20,x20,x3
+ ldp x9,x10,[x0,#6*8]
+ add x21,x21,x4
+ add x22,x22,x5
+ add x23,x23,x6
+ stp x20,x21,[x0]
+ add x24,x24,x7
+ add x25,x25,x8
+ stp x22,x23,[x0,#2*8]
+ add x26,x26,x9
+ add x27,x27,x10
+ cmp x1,x2
+ stp x24,x25,[x0,#4*8]
+ stp x26,x27,[x0,#6*8]
+ b.ne .Loop
+
+ ldp x19,x20,[x29,#16]
+ add sp,sp,#4*8
+ ldp x21,x22,[x29,#32]
+ ldp x23,x24,[x29,#48]
+ ldp x25,x26,[x29,#64]
+ ldp x27,x28,[x29,#80]
+ ldp x29,x30,[sp],#128
+.inst 0xd50323bf // autiasp
+ ret
+.size sha512_block_data_order,.-sha512_block_data_order
+
+.align 6
+.type .LK512,%object
+.LK512:
+.quad 0x428a2f98d728ae22,0x7137449123ef65cd
+.quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
+.quad 0x3956c25bf348b538,0x59f111f1b605d019
+.quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118
+.quad 0xd807aa98a3030242,0x12835b0145706fbe
+.quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
+.quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1
+.quad 0x9bdc06a725c71235,0xc19bf174cf692694
+.quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3
+.quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
+.quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483
+.quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5
+.quad 0x983e5152ee66dfab,0xa831c66d2db43210
+.quad 0xb00327c898fb213f,0xbf597fc7beef0ee4
+.quad 0xc6e00bf33da88fc2,0xd5a79147930aa725
+.quad 0x06ca6351e003826f,0x142929670a0e6e70
+.quad 0x27b70a8546d22ffc,0x2e1b21385c26c926
+.quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df
+.quad 0x650a73548baf63de,0x766a0abb3c77b2a8
+.quad 0x81c2c92e47edaee6,0x92722c851482353b
+.quad 0xa2bfe8a14cf10364,0xa81a664bbc423001
+.quad 0xc24b8b70d0f89791,0xc76c51a30654be30
+.quad 0xd192e819d6ef5218,0xd69906245565a910
+.quad 0xf40e35855771202a,0x106aa07032bbd1b8
+.quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53
+.quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8
+.quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb
+.quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3
+.quad 0x748f82ee5defb2fc,0x78a5636f43172f60
+.quad 0x84c87814a1f0ab72,0x8cc702081a6439ec
+.quad 0x90befffa23631e28,0xa4506cebde82bde9
+.quad 0xbef9a3f7b2c67915,0xc67178f2e372532b
+.quad 0xca273eceea26619c,0xd186b8c721c0c207
+.quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178
+.quad 0x06f067aa72176fba,0x0a637dc5a2c898a6
+.quad 0x113f9804bef90dae,0x1b710b35131c471b
+.quad 0x28db77f523047d84,0x32caab7b40c72493
+.quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c
+.quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a
+.quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817
+.quad 0 // terminator
+.size .LK512,.-.LK512
+.byte 83,72,65,53,49,50,32,98,108,111,99,107,32,116,114,97,110,115,102,111,114,109,32,102,111,114,32,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
+.align 2
+.align 2
+#ifndef __KERNEL__
+.type sha512_block_armv8,%function
+.align 6
+sha512_block_armv8:
+.Lv8_entry:
+ stp x29,x30,[sp,#-16]!
+ add x29,sp,#0
+
+ ld1 {v16.16b,v17.16b,v18.16b,v19.16b},[x1],#64 // load input
+ ld1 {v20.16b,v21.16b,v22.16b,v23.16b},[x1],#64
+
+ ld1 {v0.2d,v1.2d,v2.2d,v3.2d},[x0] // load context
+ adr x3,.LK512
+
+ rev64 v16.16b,v16.16b
+ rev64 v17.16b,v17.16b
+ rev64 v18.16b,v18.16b
+ rev64 v19.16b,v19.16b
+ rev64 v20.16b,v20.16b
+ rev64 v21.16b,v21.16b
+ rev64 v22.16b,v22.16b
+ rev64 v23.16b,v23.16b
+ b .Loop_hw
+
+.align 4
+.Loop_hw:
+ ld1 {v24.2d},[x3],#16
+ subs x2,x2,#1
+ sub x4,x1,#128
+ orr v26.16b,v0.16b,v0.16b // offload
+ orr v27.16b,v1.16b,v1.16b
+ orr v28.16b,v2.16b,v2.16b
+ orr v29.16b,v3.16b,v3.16b
+ csel x1,x1,x4,ne // conditional rewind
+ add v24.2d,v24.2d,v16.2d
+ ld1 {v25.2d},[x3],#16
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v2.16b,v3.16b,#8
+ ext v6.16b,v1.16b,v2.16b,#8
+ add v3.2d,v3.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xcec08230 //sha512su0 v16.16b,v17.16b
+ ext v7.16b,v20.16b,v21.16b,#8
+.inst 0xce6680a3 //sha512h v3.16b,v5.16b,v6.16b
+.inst 0xce678af0 //sha512su1 v16.16b,v23.16b,v7.16b
+ add v4.2d,v1.2d,v3.2d // "D + T1"
+.inst 0xce608423 //sha512h2 v3.16b,v1.16b,v0.16b
+ add v25.2d,v25.2d,v17.2d
+ ld1 {v24.2d},[x3],#16
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v4.16b,v2.16b,#8
+ ext v6.16b,v0.16b,v4.16b,#8
+ add v2.2d,v2.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xcec08251 //sha512su0 v17.16b,v18.16b
+ ext v7.16b,v21.16b,v22.16b,#8
+.inst 0xce6680a2 //sha512h v2.16b,v5.16b,v6.16b
+.inst 0xce678a11 //sha512su1 v17.16b,v16.16b,v7.16b
+ add v1.2d,v0.2d,v2.2d // "D + T1"
+.inst 0xce638402 //sha512h2 v2.16b,v0.16b,v3.16b
+ add v24.2d,v24.2d,v18.2d
+ ld1 {v25.2d},[x3],#16
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v1.16b,v4.16b,#8
+ ext v6.16b,v3.16b,v1.16b,#8
+ add v4.2d,v4.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xcec08272 //sha512su0 v18.16b,v19.16b
+ ext v7.16b,v22.16b,v23.16b,#8
+.inst 0xce6680a4 //sha512h v4.16b,v5.16b,v6.16b
+.inst 0xce678a32 //sha512su1 v18.16b,v17.16b,v7.16b
+ add v0.2d,v3.2d,v4.2d // "D + T1"
+.inst 0xce628464 //sha512h2 v4.16b,v3.16b,v2.16b
+ add v25.2d,v25.2d,v19.2d
+ ld1 {v24.2d},[x3],#16
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v0.16b,v1.16b,#8
+ ext v6.16b,v2.16b,v0.16b,#8
+ add v1.2d,v1.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xcec08293 //sha512su0 v19.16b,v20.16b
+ ext v7.16b,v23.16b,v16.16b,#8
+.inst 0xce6680a1 //sha512h v1.16b,v5.16b,v6.16b
+.inst 0xce678a53 //sha512su1 v19.16b,v18.16b,v7.16b
+ add v3.2d,v2.2d,v1.2d // "D + T1"
+.inst 0xce648441 //sha512h2 v1.16b,v2.16b,v4.16b
+ add v24.2d,v24.2d,v20.2d
+ ld1 {v25.2d},[x3],#16
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v3.16b,v0.16b,#8
+ ext v6.16b,v4.16b,v3.16b,#8
+ add v0.2d,v0.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xcec082b4 //sha512su0 v20.16b,v21.16b
+ ext v7.16b,v16.16b,v17.16b,#8
+.inst 0xce6680a0 //sha512h v0.16b,v5.16b,v6.16b
+.inst 0xce678a74 //sha512su1 v20.16b,v19.16b,v7.16b
+ add v2.2d,v4.2d,v0.2d // "D + T1"
+.inst 0xce618480 //sha512h2 v0.16b,v4.16b,v1.16b
+ add v25.2d,v25.2d,v21.2d
+ ld1 {v24.2d},[x3],#16
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v2.16b,v3.16b,#8
+ ext v6.16b,v1.16b,v2.16b,#8
+ add v3.2d,v3.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xcec082d5 //sha512su0 v21.16b,v22.16b
+ ext v7.16b,v17.16b,v18.16b,#8
+.inst 0xce6680a3 //sha512h v3.16b,v5.16b,v6.16b
+.inst 0xce678a95 //sha512su1 v21.16b,v20.16b,v7.16b
+ add v4.2d,v1.2d,v3.2d // "D + T1"
+.inst 0xce608423 //sha512h2 v3.16b,v1.16b,v0.16b
+ add v24.2d,v24.2d,v22.2d
+ ld1 {v25.2d},[x3],#16
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v4.16b,v2.16b,#8
+ ext v6.16b,v0.16b,v4.16b,#8
+ add v2.2d,v2.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xcec082f6 //sha512su0 v22.16b,v23.16b
+ ext v7.16b,v18.16b,v19.16b,#8
+.inst 0xce6680a2 //sha512h v2.16b,v5.16b,v6.16b
+.inst 0xce678ab6 //sha512su1 v22.16b,v21.16b,v7.16b
+ add v1.2d,v0.2d,v2.2d // "D + T1"
+.inst 0xce638402 //sha512h2 v2.16b,v0.16b,v3.16b
+ add v25.2d,v25.2d,v23.2d
+ ld1 {v24.2d},[x3],#16
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v1.16b,v4.16b,#8
+ ext v6.16b,v3.16b,v1.16b,#8
+ add v4.2d,v4.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xcec08217 //sha512su0 v23.16b,v16.16b
+ ext v7.16b,v19.16b,v20.16b,#8
+.inst 0xce6680a4 //sha512h v4.16b,v5.16b,v6.16b
+.inst 0xce678ad7 //sha512su1 v23.16b,v22.16b,v7.16b
+ add v0.2d,v3.2d,v4.2d // "D + T1"
+.inst 0xce628464 //sha512h2 v4.16b,v3.16b,v2.16b
+ add v24.2d,v24.2d,v16.2d
+ ld1 {v25.2d},[x3],#16
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v0.16b,v1.16b,#8
+ ext v6.16b,v2.16b,v0.16b,#8
+ add v1.2d,v1.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xcec08230 //sha512su0 v16.16b,v17.16b
+ ext v7.16b,v20.16b,v21.16b,#8
+.inst 0xce6680a1 //sha512h v1.16b,v5.16b,v6.16b
+.inst 0xce678af0 //sha512su1 v16.16b,v23.16b,v7.16b
+ add v3.2d,v2.2d,v1.2d // "D + T1"
+.inst 0xce648441 //sha512h2 v1.16b,v2.16b,v4.16b
+ add v25.2d,v25.2d,v17.2d
+ ld1 {v24.2d},[x3],#16
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v3.16b,v0.16b,#8
+ ext v6.16b,v4.16b,v3.16b,#8
+ add v0.2d,v0.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xcec08251 //sha512su0 v17.16b,v18.16b
+ ext v7.16b,v21.16b,v22.16b,#8
+.inst 0xce6680a0 //sha512h v0.16b,v5.16b,v6.16b
+.inst 0xce678a11 //sha512su1 v17.16b,v16.16b,v7.16b
+ add v2.2d,v4.2d,v0.2d // "D + T1"
+.inst 0xce618480 //sha512h2 v0.16b,v4.16b,v1.16b
+ add v24.2d,v24.2d,v18.2d
+ ld1 {v25.2d},[x3],#16
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v2.16b,v3.16b,#8
+ ext v6.16b,v1.16b,v2.16b,#8
+ add v3.2d,v3.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xcec08272 //sha512su0 v18.16b,v19.16b
+ ext v7.16b,v22.16b,v23.16b,#8
+.inst 0xce6680a3 //sha512h v3.16b,v5.16b,v6.16b
+.inst 0xce678a32 //sha512su1 v18.16b,v17.16b,v7.16b
+ add v4.2d,v1.2d,v3.2d // "D + T1"
+.inst 0xce608423 //sha512h2 v3.16b,v1.16b,v0.16b
+ add v25.2d,v25.2d,v19.2d
+ ld1 {v24.2d},[x3],#16
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v4.16b,v2.16b,#8
+ ext v6.16b,v0.16b,v4.16b,#8
+ add v2.2d,v2.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xcec08293 //sha512su0 v19.16b,v20.16b
+ ext v7.16b,v23.16b,v16.16b,#8
+.inst 0xce6680a2 //sha512h v2.16b,v5.16b,v6.16b
+.inst 0xce678a53 //sha512su1 v19.16b,v18.16b,v7.16b
+ add v1.2d,v0.2d,v2.2d // "D + T1"
+.inst 0xce638402 //sha512h2 v2.16b,v0.16b,v3.16b
+ add v24.2d,v24.2d,v20.2d
+ ld1 {v25.2d},[x3],#16
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v1.16b,v4.16b,#8
+ ext v6.16b,v3.16b,v1.16b,#8
+ add v4.2d,v4.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xcec082b4 //sha512su0 v20.16b,v21.16b
+ ext v7.16b,v16.16b,v17.16b,#8
+.inst 0xce6680a4 //sha512h v4.16b,v5.16b,v6.16b
+.inst 0xce678a74 //sha512su1 v20.16b,v19.16b,v7.16b
+ add v0.2d,v3.2d,v4.2d // "D + T1"
+.inst 0xce628464 //sha512h2 v4.16b,v3.16b,v2.16b
+ add v25.2d,v25.2d,v21.2d
+ ld1 {v24.2d},[x3],#16
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v0.16b,v1.16b,#8
+ ext v6.16b,v2.16b,v0.16b,#8
+ add v1.2d,v1.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xcec082d5 //sha512su0 v21.16b,v22.16b
+ ext v7.16b,v17.16b,v18.16b,#8
+.inst 0xce6680a1 //sha512h v1.16b,v5.16b,v6.16b
+.inst 0xce678a95 //sha512su1 v21.16b,v20.16b,v7.16b
+ add v3.2d,v2.2d,v1.2d // "D + T1"
+.inst 0xce648441 //sha512h2 v1.16b,v2.16b,v4.16b
+ add v24.2d,v24.2d,v22.2d
+ ld1 {v25.2d},[x3],#16
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v3.16b,v0.16b,#8
+ ext v6.16b,v4.16b,v3.16b,#8
+ add v0.2d,v0.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xcec082f6 //sha512su0 v22.16b,v23.16b
+ ext v7.16b,v18.16b,v19.16b,#8
+.inst 0xce6680a0 //sha512h v0.16b,v5.16b,v6.16b
+.inst 0xce678ab6 //sha512su1 v22.16b,v21.16b,v7.16b
+ add v2.2d,v4.2d,v0.2d // "D + T1"
+.inst 0xce618480 //sha512h2 v0.16b,v4.16b,v1.16b
+ add v25.2d,v25.2d,v23.2d
+ ld1 {v24.2d},[x3],#16
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v2.16b,v3.16b,#8
+ ext v6.16b,v1.16b,v2.16b,#8
+ add v3.2d,v3.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xcec08217 //sha512su0 v23.16b,v16.16b
+ ext v7.16b,v19.16b,v20.16b,#8
+.inst 0xce6680a3 //sha512h v3.16b,v5.16b,v6.16b
+.inst 0xce678ad7 //sha512su1 v23.16b,v22.16b,v7.16b
+ add v4.2d,v1.2d,v3.2d // "D + T1"
+.inst 0xce608423 //sha512h2 v3.16b,v1.16b,v0.16b
+ add v24.2d,v24.2d,v16.2d
+ ld1 {v25.2d},[x3],#16
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v4.16b,v2.16b,#8
+ ext v6.16b,v0.16b,v4.16b,#8
+ add v2.2d,v2.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xcec08230 //sha512su0 v16.16b,v17.16b
+ ext v7.16b,v20.16b,v21.16b,#8
+.inst 0xce6680a2 //sha512h v2.16b,v5.16b,v6.16b
+.inst 0xce678af0 //sha512su1 v16.16b,v23.16b,v7.16b
+ add v1.2d,v0.2d,v2.2d // "D + T1"
+.inst 0xce638402 //sha512h2 v2.16b,v0.16b,v3.16b
+ add v25.2d,v25.2d,v17.2d
+ ld1 {v24.2d},[x3],#16
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v1.16b,v4.16b,#8
+ ext v6.16b,v3.16b,v1.16b,#8
+ add v4.2d,v4.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xcec08251 //sha512su0 v17.16b,v18.16b
+ ext v7.16b,v21.16b,v22.16b,#8
+.inst 0xce6680a4 //sha512h v4.16b,v5.16b,v6.16b
+.inst 0xce678a11 //sha512su1 v17.16b,v16.16b,v7.16b
+ add v0.2d,v3.2d,v4.2d // "D + T1"
+.inst 0xce628464 //sha512h2 v4.16b,v3.16b,v2.16b
+ add v24.2d,v24.2d,v18.2d
+ ld1 {v25.2d},[x3],#16
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v0.16b,v1.16b,#8
+ ext v6.16b,v2.16b,v0.16b,#8
+ add v1.2d,v1.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xcec08272 //sha512su0 v18.16b,v19.16b
+ ext v7.16b,v22.16b,v23.16b,#8
+.inst 0xce6680a1 //sha512h v1.16b,v5.16b,v6.16b
+.inst 0xce678a32 //sha512su1 v18.16b,v17.16b,v7.16b
+ add v3.2d,v2.2d,v1.2d // "D + T1"
+.inst 0xce648441 //sha512h2 v1.16b,v2.16b,v4.16b
+ add v25.2d,v25.2d,v19.2d
+ ld1 {v24.2d},[x3],#16
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v3.16b,v0.16b,#8
+ ext v6.16b,v4.16b,v3.16b,#8
+ add v0.2d,v0.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xcec08293 //sha512su0 v19.16b,v20.16b
+ ext v7.16b,v23.16b,v16.16b,#8
+.inst 0xce6680a0 //sha512h v0.16b,v5.16b,v6.16b
+.inst 0xce678a53 //sha512su1 v19.16b,v18.16b,v7.16b
+ add v2.2d,v4.2d,v0.2d // "D + T1"
+.inst 0xce618480 //sha512h2 v0.16b,v4.16b,v1.16b
+ add v24.2d,v24.2d,v20.2d
+ ld1 {v25.2d},[x3],#16
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v2.16b,v3.16b,#8
+ ext v6.16b,v1.16b,v2.16b,#8
+ add v3.2d,v3.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xcec082b4 //sha512su0 v20.16b,v21.16b
+ ext v7.16b,v16.16b,v17.16b,#8
+.inst 0xce6680a3 //sha512h v3.16b,v5.16b,v6.16b
+.inst 0xce678a74 //sha512su1 v20.16b,v19.16b,v7.16b
+ add v4.2d,v1.2d,v3.2d // "D + T1"
+.inst 0xce608423 //sha512h2 v3.16b,v1.16b,v0.16b
+ add v25.2d,v25.2d,v21.2d
+ ld1 {v24.2d},[x3],#16
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v4.16b,v2.16b,#8
+ ext v6.16b,v0.16b,v4.16b,#8
+ add v2.2d,v2.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xcec082d5 //sha512su0 v21.16b,v22.16b
+ ext v7.16b,v17.16b,v18.16b,#8
+.inst 0xce6680a2 //sha512h v2.16b,v5.16b,v6.16b
+.inst 0xce678a95 //sha512su1 v21.16b,v20.16b,v7.16b
+ add v1.2d,v0.2d,v2.2d // "D + T1"
+.inst 0xce638402 //sha512h2 v2.16b,v0.16b,v3.16b
+ add v24.2d,v24.2d,v22.2d
+ ld1 {v25.2d},[x3],#16
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v1.16b,v4.16b,#8
+ ext v6.16b,v3.16b,v1.16b,#8
+ add v4.2d,v4.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xcec082f6 //sha512su0 v22.16b,v23.16b
+ ext v7.16b,v18.16b,v19.16b,#8
+.inst 0xce6680a4 //sha512h v4.16b,v5.16b,v6.16b
+.inst 0xce678ab6 //sha512su1 v22.16b,v21.16b,v7.16b
+ add v0.2d,v3.2d,v4.2d // "D + T1"
+.inst 0xce628464 //sha512h2 v4.16b,v3.16b,v2.16b
+ add v25.2d,v25.2d,v23.2d
+ ld1 {v24.2d},[x3],#16
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v0.16b,v1.16b,#8
+ ext v6.16b,v2.16b,v0.16b,#8
+ add v1.2d,v1.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xcec08217 //sha512su0 v23.16b,v16.16b
+ ext v7.16b,v19.16b,v20.16b,#8
+.inst 0xce6680a1 //sha512h v1.16b,v5.16b,v6.16b
+.inst 0xce678ad7 //sha512su1 v23.16b,v22.16b,v7.16b
+ add v3.2d,v2.2d,v1.2d // "D + T1"
+.inst 0xce648441 //sha512h2 v1.16b,v2.16b,v4.16b
+ add v24.2d,v24.2d,v16.2d
+ ld1 {v25.2d},[x3],#16
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v3.16b,v0.16b,#8
+ ext v6.16b,v4.16b,v3.16b,#8
+ add v0.2d,v0.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xcec08230 //sha512su0 v16.16b,v17.16b
+ ext v7.16b,v20.16b,v21.16b,#8
+.inst 0xce6680a0 //sha512h v0.16b,v5.16b,v6.16b
+.inst 0xce678af0 //sha512su1 v16.16b,v23.16b,v7.16b
+ add v2.2d,v4.2d,v0.2d // "D + T1"
+.inst 0xce618480 //sha512h2 v0.16b,v4.16b,v1.16b
+ add v25.2d,v25.2d,v17.2d
+ ld1 {v24.2d},[x3],#16
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v2.16b,v3.16b,#8
+ ext v6.16b,v1.16b,v2.16b,#8
+ add v3.2d,v3.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xcec08251 //sha512su0 v17.16b,v18.16b
+ ext v7.16b,v21.16b,v22.16b,#8
+.inst 0xce6680a3 //sha512h v3.16b,v5.16b,v6.16b
+.inst 0xce678a11 //sha512su1 v17.16b,v16.16b,v7.16b
+ add v4.2d,v1.2d,v3.2d // "D + T1"
+.inst 0xce608423 //sha512h2 v3.16b,v1.16b,v0.16b
+ add v24.2d,v24.2d,v18.2d
+ ld1 {v25.2d},[x3],#16
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v4.16b,v2.16b,#8
+ ext v6.16b,v0.16b,v4.16b,#8
+ add v2.2d,v2.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xcec08272 //sha512su0 v18.16b,v19.16b
+ ext v7.16b,v22.16b,v23.16b,#8
+.inst 0xce6680a2 //sha512h v2.16b,v5.16b,v6.16b
+.inst 0xce678a32 //sha512su1 v18.16b,v17.16b,v7.16b
+ add v1.2d,v0.2d,v2.2d // "D + T1"
+.inst 0xce638402 //sha512h2 v2.16b,v0.16b,v3.16b
+ add v25.2d,v25.2d,v19.2d
+ ld1 {v24.2d},[x3],#16
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v1.16b,v4.16b,#8
+ ext v6.16b,v3.16b,v1.16b,#8
+ add v4.2d,v4.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xcec08293 //sha512su0 v19.16b,v20.16b
+ ext v7.16b,v23.16b,v16.16b,#8
+.inst 0xce6680a4 //sha512h v4.16b,v5.16b,v6.16b
+.inst 0xce678a53 //sha512su1 v19.16b,v18.16b,v7.16b
+ add v0.2d,v3.2d,v4.2d // "D + T1"
+.inst 0xce628464 //sha512h2 v4.16b,v3.16b,v2.16b
+ add v24.2d,v24.2d,v20.2d
+ ld1 {v25.2d},[x3],#16
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v0.16b,v1.16b,#8
+ ext v6.16b,v2.16b,v0.16b,#8
+ add v1.2d,v1.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xcec082b4 //sha512su0 v20.16b,v21.16b
+ ext v7.16b,v16.16b,v17.16b,#8
+.inst 0xce6680a1 //sha512h v1.16b,v5.16b,v6.16b
+.inst 0xce678a74 //sha512su1 v20.16b,v19.16b,v7.16b
+ add v3.2d,v2.2d,v1.2d // "D + T1"
+.inst 0xce648441 //sha512h2 v1.16b,v2.16b,v4.16b
+ add v25.2d,v25.2d,v21.2d
+ ld1 {v24.2d},[x3],#16
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v3.16b,v0.16b,#8
+ ext v6.16b,v4.16b,v3.16b,#8
+ add v0.2d,v0.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xcec082d5 //sha512su0 v21.16b,v22.16b
+ ext v7.16b,v17.16b,v18.16b,#8
+.inst 0xce6680a0 //sha512h v0.16b,v5.16b,v6.16b
+.inst 0xce678a95 //sha512su1 v21.16b,v20.16b,v7.16b
+ add v2.2d,v4.2d,v0.2d // "D + T1"
+.inst 0xce618480 //sha512h2 v0.16b,v4.16b,v1.16b
+ add v24.2d,v24.2d,v22.2d
+ ld1 {v25.2d},[x3],#16
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v2.16b,v3.16b,#8
+ ext v6.16b,v1.16b,v2.16b,#8
+ add v3.2d,v3.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xcec082f6 //sha512su0 v22.16b,v23.16b
+ ext v7.16b,v18.16b,v19.16b,#8
+.inst 0xce6680a3 //sha512h v3.16b,v5.16b,v6.16b
+.inst 0xce678ab6 //sha512su1 v22.16b,v21.16b,v7.16b
+ add v4.2d,v1.2d,v3.2d // "D + T1"
+.inst 0xce608423 //sha512h2 v3.16b,v1.16b,v0.16b
+ add v25.2d,v25.2d,v23.2d
+ ld1 {v24.2d},[x3],#16
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v4.16b,v2.16b,#8
+ ext v6.16b,v0.16b,v4.16b,#8
+ add v2.2d,v2.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xcec08217 //sha512su0 v23.16b,v16.16b
+ ext v7.16b,v19.16b,v20.16b,#8
+.inst 0xce6680a2 //sha512h v2.16b,v5.16b,v6.16b
+.inst 0xce678ad7 //sha512su1 v23.16b,v22.16b,v7.16b
+ add v1.2d,v0.2d,v2.2d // "D + T1"
+.inst 0xce638402 //sha512h2 v2.16b,v0.16b,v3.16b
+ ld1 {v25.2d},[x3],#16
+ add v24.2d,v24.2d,v16.2d
+ ld1 {v16.16b},[x1],#16 // load next input
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v1.16b,v4.16b,#8
+ ext v6.16b,v3.16b,v1.16b,#8
+ add v4.2d,v4.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xce6680a4 //sha512h v4.16b,v5.16b,v6.16b
+ rev64 v16.16b,v16.16b
+ add v0.2d,v3.2d,v4.2d // "D + T1"
+.inst 0xce628464 //sha512h2 v4.16b,v3.16b,v2.16b
+ ld1 {v24.2d},[x3],#16
+ add v25.2d,v25.2d,v17.2d
+ ld1 {v17.16b},[x1],#16 // load next input
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v0.16b,v1.16b,#8
+ ext v6.16b,v2.16b,v0.16b,#8
+ add v1.2d,v1.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xce6680a1 //sha512h v1.16b,v5.16b,v6.16b
+ rev64 v17.16b,v17.16b
+ add v3.2d,v2.2d,v1.2d // "D + T1"
+.inst 0xce648441 //sha512h2 v1.16b,v2.16b,v4.16b
+ ld1 {v25.2d},[x3],#16
+ add v24.2d,v24.2d,v18.2d
+ ld1 {v18.16b},[x1],#16 // load next input
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v3.16b,v0.16b,#8
+ ext v6.16b,v4.16b,v3.16b,#8
+ add v0.2d,v0.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xce6680a0 //sha512h v0.16b,v5.16b,v6.16b
+ rev64 v18.16b,v18.16b
+ add v2.2d,v4.2d,v0.2d // "D + T1"
+.inst 0xce618480 //sha512h2 v0.16b,v4.16b,v1.16b
+ ld1 {v24.2d},[x3],#16
+ add v25.2d,v25.2d,v19.2d
+ ld1 {v19.16b},[x1],#16 // load next input
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v2.16b,v3.16b,#8
+ ext v6.16b,v1.16b,v2.16b,#8
+ add v3.2d,v3.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xce6680a3 //sha512h v3.16b,v5.16b,v6.16b
+ rev64 v19.16b,v19.16b
+ add v4.2d,v1.2d,v3.2d // "D + T1"
+.inst 0xce608423 //sha512h2 v3.16b,v1.16b,v0.16b
+ ld1 {v25.2d},[x3],#16
+ add v24.2d,v24.2d,v20.2d
+ ld1 {v20.16b},[x1],#16 // load next input
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v4.16b,v2.16b,#8
+ ext v6.16b,v0.16b,v4.16b,#8
+ add v2.2d,v2.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xce6680a2 //sha512h v2.16b,v5.16b,v6.16b
+ rev64 v20.16b,v20.16b
+ add v1.2d,v0.2d,v2.2d // "D + T1"
+.inst 0xce638402 //sha512h2 v2.16b,v0.16b,v3.16b
+ ld1 {v24.2d},[x3],#16
+ add v25.2d,v25.2d,v21.2d
+ ld1 {v21.16b},[x1],#16 // load next input
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v1.16b,v4.16b,#8
+ ext v6.16b,v3.16b,v1.16b,#8
+ add v4.2d,v4.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xce6680a4 //sha512h v4.16b,v5.16b,v6.16b
+ rev64 v21.16b,v21.16b
+ add v0.2d,v3.2d,v4.2d // "D + T1"
+.inst 0xce628464 //sha512h2 v4.16b,v3.16b,v2.16b
+ ld1 {v25.2d},[x3],#16
+ add v24.2d,v24.2d,v22.2d
+ ld1 {v22.16b},[x1],#16 // load next input
+ ext v24.16b,v24.16b,v24.16b,#8
+ ext v5.16b,v0.16b,v1.16b,#8
+ ext v6.16b,v2.16b,v0.16b,#8
+ add v1.2d,v1.2d,v24.2d // "T1 + H + K512[i]"
+.inst 0xce6680a1 //sha512h v1.16b,v5.16b,v6.16b
+ rev64 v22.16b,v22.16b
+ add v3.2d,v2.2d,v1.2d // "D + T1"
+.inst 0xce648441 //sha512h2 v1.16b,v2.16b,v4.16b
+ sub x3,x3,#80*8 // rewind
+ add v25.2d,v25.2d,v23.2d
+ ld1 {v23.16b},[x1],#16 // load next input
+ ext v25.16b,v25.16b,v25.16b,#8
+ ext v5.16b,v3.16b,v0.16b,#8
+ ext v6.16b,v4.16b,v3.16b,#8
+ add v0.2d,v0.2d,v25.2d // "T1 + H + K512[i]"
+.inst 0xce6680a0 //sha512h v0.16b,v5.16b,v6.16b
+ rev64 v23.16b,v23.16b
+ add v2.2d,v4.2d,v0.2d // "D + T1"
+.inst 0xce618480 //sha512h2 v0.16b,v4.16b,v1.16b
+ add v0.2d,v0.2d,v26.2d // accumulate
+ add v1.2d,v1.2d,v27.2d
+ add v2.2d,v2.2d,v28.2d
+ add v3.2d,v3.2d,v29.2d
+
+ cbnz x2,.Loop_hw
+
+ st1 {v0.2d,v1.2d,v2.2d,v3.2d},[x0] // store context
+
+ ldr x29,[sp],#16
+ ret
+.size sha512_block_armv8,.-sha512_block_armv8
+#endif
diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf b/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf
index a47e9087133b..3d1a9638b1c1 100644
--- a/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf
+++ b/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf
@@ -25,7 +25,7 @@ [Defines]
DEFINE OPENSSL_FLAGS = -DL_ENDIAN -DOPENSSL_SMALL_FOOTPRINT -D_CRT_SECURE_NO_DEPRECATE -D_CRT_NONSTDC_NO_DEPRECATE -DEDK2_OPENSSL_NOEC=1
DEFINE OPENSSL_FLAGS_IA32 = -DAES_ASM -DGHASH_ASM -DMD5_ASM -DOPENSSL_CPUID_OBJ -DSHA1_ASM -DSHA256_ASM -DSHA512_ASM -DVPAES_ASM
DEFINE OPENSSL_FLAGS_X64 = -DAES_ASM -DBSAES_ASM -DGHASH_ASM -DKECCAK1600_ASM -DMD5_ASM -DOPENSSL_CPUID_OBJ -DSHA1_ASM -DSHA256_ASM -DSHA512_ASM -DVPAES_ASM
- DEFINE OPENSSL_FLAGS_AARCH64 =
+ DEFINE OPENSSL_FLAGS_AARCH64 = -DKECCAK1600_ASM -DOPENSSL_CPUID_OBJ -DSHA1_ASM -DSHA256_ASM -DSHA512_ASM -DVPAES_ASM
#
# VALID_ARCHITECTURES = IA32 X64 AARCH64
@@ -1330,6 +1330,625 @@ [Sources.X64]
[Sources.AARCH64]
# Autogenerated files list starts here
+ $(OPENSSL_PATH)/crypto/aes/aes_cbc.c
+ $(OPENSSL_PATH)/crypto/aes/aes_cfb.c
+ $(OPENSSL_PATH)/crypto/aes/aes_core.c
+ $(OPENSSL_PATH)/crypto/aes/aes_ecb.c
+ $(OPENSSL_PATH)/crypto/aes/aes_ige.c
+ $(OPENSSL_PATH)/crypto/aes/aes_misc.c
+ $(OPENSSL_PATH)/crypto/aes/aes_ofb.c
+ $(OPENSSL_PATH)/crypto/aes/aes_wrap.c
+ $(OPENSSL_PATH)/crypto/asn1/a_bitstr.c
+ $(OPENSSL_PATH)/crypto/asn1/a_d2i_fp.c
+ $(OPENSSL_PATH)/crypto/asn1/a_digest.c
+ $(OPENSSL_PATH)/crypto/asn1/a_dup.c
+ $(OPENSSL_PATH)/crypto/asn1/a_gentm.c
+ $(OPENSSL_PATH)/crypto/asn1/a_i2d_fp.c
+ $(OPENSSL_PATH)/crypto/asn1/a_int.c
+ $(OPENSSL_PATH)/crypto/asn1/a_mbstr.c
+ $(OPENSSL_PATH)/crypto/asn1/a_object.c
+ $(OPENSSL_PATH)/crypto/asn1/a_octet.c
+ $(OPENSSL_PATH)/crypto/asn1/a_print.c
+ $(OPENSSL_PATH)/crypto/asn1/a_sign.c
+ $(OPENSSL_PATH)/crypto/asn1/a_strex.c
+ $(OPENSSL_PATH)/crypto/asn1/a_strnid.c
+ $(OPENSSL_PATH)/crypto/asn1/a_time.c
+ $(OPENSSL_PATH)/crypto/asn1/a_type.c
+ $(OPENSSL_PATH)/crypto/asn1/a_utctm.c
+ $(OPENSSL_PATH)/crypto/asn1/a_utf8.c
+ $(OPENSSL_PATH)/crypto/asn1/a_verify.c
+ $(OPENSSL_PATH)/crypto/asn1/ameth_lib.c
+ $(OPENSSL_PATH)/crypto/asn1/asn1_err.c
+ $(OPENSSL_PATH)/crypto/asn1/asn1_gen.c
+ $(OPENSSL_PATH)/crypto/asn1/asn1_item_list.c
+ $(OPENSSL_PATH)/crypto/asn1/asn1_lib.c
+ $(OPENSSL_PATH)/crypto/asn1/asn1_parse.c
+ $(OPENSSL_PATH)/crypto/asn1/asn_mime.c
+ $(OPENSSL_PATH)/crypto/asn1/asn_moid.c
+ $(OPENSSL_PATH)/crypto/asn1/asn_mstbl.c
+ $(OPENSSL_PATH)/crypto/asn1/asn_pack.c
+ $(OPENSSL_PATH)/crypto/asn1/bio_asn1.c
+ $(OPENSSL_PATH)/crypto/asn1/bio_ndef.c
+ $(OPENSSL_PATH)/crypto/asn1/d2i_param.c
+ $(OPENSSL_PATH)/crypto/asn1/d2i_pr.c
+ $(OPENSSL_PATH)/crypto/asn1/d2i_pu.c
+ $(OPENSSL_PATH)/crypto/asn1/evp_asn1.c
+ $(OPENSSL_PATH)/crypto/asn1/f_int.c
+ $(OPENSSL_PATH)/crypto/asn1/f_string.c
+ $(OPENSSL_PATH)/crypto/asn1/i2d_evp.c
+ $(OPENSSL_PATH)/crypto/asn1/nsseq.c
+ $(OPENSSL_PATH)/crypto/asn1/p5_pbe.c
+ $(OPENSSL_PATH)/crypto/asn1/p5_pbev2.c
+ $(OPENSSL_PATH)/crypto/asn1/p5_scrypt.c
+ $(OPENSSL_PATH)/crypto/asn1/p8_pkey.c
+ $(OPENSSL_PATH)/crypto/asn1/t_bitst.c
+ $(OPENSSL_PATH)/crypto/asn1/t_pkey.c
+ $(OPENSSL_PATH)/crypto/asn1/t_spki.c
+ $(OPENSSL_PATH)/crypto/asn1/tasn_dec.c
+ $(OPENSSL_PATH)/crypto/asn1/tasn_enc.c
+ $(OPENSSL_PATH)/crypto/asn1/tasn_fre.c
+ $(OPENSSL_PATH)/crypto/asn1/tasn_new.c
+ $(OPENSSL_PATH)/crypto/asn1/tasn_prn.c
+ $(OPENSSL_PATH)/crypto/asn1/tasn_scn.c
+ $(OPENSSL_PATH)/crypto/asn1/tasn_typ.c
+ $(OPENSSL_PATH)/crypto/asn1/tasn_utl.c
+ $(OPENSSL_PATH)/crypto/asn1/x_algor.c
+ $(OPENSSL_PATH)/crypto/asn1/x_bignum.c
+ $(OPENSSL_PATH)/crypto/asn1/x_info.c
+ $(OPENSSL_PATH)/crypto/asn1/x_int64.c
+ $(OPENSSL_PATH)/crypto/asn1/x_long.c
+ $(OPENSSL_PATH)/crypto/asn1/x_pkey.c
+ $(OPENSSL_PATH)/crypto/asn1/x_sig.c
+ $(OPENSSL_PATH)/crypto/asn1/x_spki.c
+ $(OPENSSL_PATH)/crypto/asn1/x_val.c
+ $(OPENSSL_PATH)/crypto/async/arch/async_null.c
+ $(OPENSSL_PATH)/crypto/async/arch/async_posix.c
+ $(OPENSSL_PATH)/crypto/async/arch/async_win.c
+ $(OPENSSL_PATH)/crypto/async/async.c
+ $(OPENSSL_PATH)/crypto/async/async_err.c
+ $(OPENSSL_PATH)/crypto/async/async_wait.c
+ $(OPENSSL_PATH)/crypto/bio/bf_buff.c
+ $(OPENSSL_PATH)/crypto/bio/bf_lbuf.c
+ $(OPENSSL_PATH)/crypto/bio/bf_nbio.c
+ $(OPENSSL_PATH)/crypto/bio/bf_null.c
+ $(OPENSSL_PATH)/crypto/bio/bf_prefix.c
+ $(OPENSSL_PATH)/crypto/bio/bf_readbuff.c
+ $(OPENSSL_PATH)/crypto/bio/bio_addr.c
+ $(OPENSSL_PATH)/crypto/bio/bio_cb.c
+ $(OPENSSL_PATH)/crypto/bio/bio_dump.c
+ $(OPENSSL_PATH)/crypto/bio/bio_err.c
+ $(OPENSSL_PATH)/crypto/bio/bio_lib.c
+ $(OPENSSL_PATH)/crypto/bio/bio_meth.c
+ $(OPENSSL_PATH)/crypto/bio/bio_print.c
+ $(OPENSSL_PATH)/crypto/bio/bio_sock.c
+ $(OPENSSL_PATH)/crypto/bio/bio_sock2.c
+ $(OPENSSL_PATH)/crypto/bio/bss_acpt.c
+ $(OPENSSL_PATH)/crypto/bio/bss_bio.c
+ $(OPENSSL_PATH)/crypto/bio/bss_conn.c
+ $(OPENSSL_PATH)/crypto/bio/bss_core.c
+ $(OPENSSL_PATH)/crypto/bio/bss_dgram.c
+ $(OPENSSL_PATH)/crypto/bio/bss_fd.c
+ $(OPENSSL_PATH)/crypto/bio/bss_file.c
+ $(OPENSSL_PATH)/crypto/bio/bss_log.c
+ $(OPENSSL_PATH)/crypto/bio/bss_mem.c
+ $(OPENSSL_PATH)/crypto/bio/bss_null.c
+ $(OPENSSL_PATH)/crypto/bio/bss_sock.c
+ $(OPENSSL_PATH)/crypto/bio/ossl_core_bio.c
+ $(OPENSSL_PATH)/crypto/bn/bn_add.c
+ $(OPENSSL_PATH)/crypto/bn/bn_asm.c
+ $(OPENSSL_PATH)/crypto/bn/bn_blind.c
+ $(OPENSSL_PATH)/crypto/bn/bn_const.c
+ $(OPENSSL_PATH)/crypto/bn/bn_conv.c
+ $(OPENSSL_PATH)/crypto/bn/bn_ctx.c
+ $(OPENSSL_PATH)/crypto/bn/bn_dh.c
+ $(OPENSSL_PATH)/crypto/bn/bn_div.c
+ $(OPENSSL_PATH)/crypto/bn/bn_err.c
+ $(OPENSSL_PATH)/crypto/bn/bn_exp.c
+ $(OPENSSL_PATH)/crypto/bn/bn_exp2.c
+ $(OPENSSL_PATH)/crypto/bn/bn_gcd.c
+ $(OPENSSL_PATH)/crypto/bn/bn_gf2m.c
+ $(OPENSSL_PATH)/crypto/bn/bn_intern.c
+ $(OPENSSL_PATH)/crypto/bn/bn_kron.c
+ $(OPENSSL_PATH)/crypto/bn/bn_lib.c
+ $(OPENSSL_PATH)/crypto/bn/bn_mod.c
+ $(OPENSSL_PATH)/crypto/bn/bn_mont.c
+ $(OPENSSL_PATH)/crypto/bn/bn_mpi.c
+ $(OPENSSL_PATH)/crypto/bn/bn_mul.c
+ $(OPENSSL_PATH)/crypto/bn/bn_nist.c
+ $(OPENSSL_PATH)/crypto/bn/bn_prime.c
+ $(OPENSSL_PATH)/crypto/bn/bn_print.c
+ $(OPENSSL_PATH)/crypto/bn/bn_rand.c
+ $(OPENSSL_PATH)/crypto/bn/bn_recp.c
+ $(OPENSSL_PATH)/crypto/bn/bn_rsa_fips186_4.c
+ $(OPENSSL_PATH)/crypto/bn/bn_shift.c
+ $(OPENSSL_PATH)/crypto/bn/bn_sqr.c
+ $(OPENSSL_PATH)/crypto/bn/bn_sqrt.c
+ $(OPENSSL_PATH)/crypto/bn/bn_srp.c
+ $(OPENSSL_PATH)/crypto/bn/bn_word.c
+ $(OPENSSL_PATH)/crypto/bn/bn_x931p.c
+ $(OPENSSL_PATH)/crypto/buffer/buf_err.c
+ $(OPENSSL_PATH)/crypto/buffer/buffer.c
+ $(OPENSSL_PATH)/crypto/comp/c_zlib.c
+ $(OPENSSL_PATH)/crypto/comp/comp_err.c
+ $(OPENSSL_PATH)/crypto/comp/comp_lib.c
+ $(OPENSSL_PATH)/crypto/conf/conf_api.c
+ $(OPENSSL_PATH)/crypto/conf/conf_def.c
+ $(OPENSSL_PATH)/crypto/conf/conf_err.c
+ $(OPENSSL_PATH)/crypto/conf/conf_lib.c
+ $(OPENSSL_PATH)/crypto/conf/conf_mall.c
+ $(OPENSSL_PATH)/crypto/conf/conf_mod.c
+ $(OPENSSL_PATH)/crypto/conf/conf_sap.c
+ $(OPENSSL_PATH)/crypto/conf/conf_ssl.c
+ $(OPENSSL_PATH)/crypto/dh/dh_ameth.c
+ $(OPENSSL_PATH)/crypto/dh/dh_asn1.c
+ $(OPENSSL_PATH)/crypto/dh/dh_backend.c
+ $(OPENSSL_PATH)/crypto/dh/dh_check.c
+ $(OPENSSL_PATH)/crypto/dh/dh_err.c
+ $(OPENSSL_PATH)/crypto/dh/dh_gen.c
+ $(OPENSSL_PATH)/crypto/dh/dh_group_params.c
+ $(OPENSSL_PATH)/crypto/dh/dh_kdf.c
+ $(OPENSSL_PATH)/crypto/dh/dh_key.c
+ $(OPENSSL_PATH)/crypto/dh/dh_lib.c
+ $(OPENSSL_PATH)/crypto/dh/dh_meth.c
+ $(OPENSSL_PATH)/crypto/dh/dh_pmeth.c
+ $(OPENSSL_PATH)/crypto/dh/dh_prn.c
+ $(OPENSSL_PATH)/crypto/dh/dh_rfc5114.c
+ $(OPENSSL_PATH)/crypto/dso/dso_dl.c
+ $(OPENSSL_PATH)/crypto/dso/dso_dlfcn.c
+ $(OPENSSL_PATH)/crypto/dso/dso_err.c
+ $(OPENSSL_PATH)/crypto/dso/dso_lib.c
+ $(OPENSSL_PATH)/crypto/dso/dso_openssl.c
+ $(OPENSSL_PATH)/crypto/dso/dso_vms.c
+ $(OPENSSL_PATH)/crypto/dso/dso_win32.c
+ $(OPENSSL_PATH)/crypto/encode_decode/decoder_err.c
+ $(OPENSSL_PATH)/crypto/encode_decode/decoder_lib.c
+ $(OPENSSL_PATH)/crypto/encode_decode/decoder_meth.c
+ $(OPENSSL_PATH)/crypto/encode_decode/decoder_pkey.c
+ $(OPENSSL_PATH)/crypto/err/err.c
+ $(OPENSSL_PATH)/crypto/err/err_all.c
+ $(OPENSSL_PATH)/crypto/err/err_all_legacy.c
+ $(OPENSSL_PATH)/crypto/err/err_blocks.c
+ $(OPENSSL_PATH)/crypto/err/err_prn.c
+ $(OPENSSL_PATH)/crypto/ess/ess_asn1.c
+ $(OPENSSL_PATH)/crypto/ess/ess_err.c
+ $(OPENSSL_PATH)/crypto/ess/ess_lib.c
+ $(OPENSSL_PATH)/crypto/evp/asymcipher.c
+ $(OPENSSL_PATH)/crypto/evp/bio_b64.c
+ $(OPENSSL_PATH)/crypto/evp/bio_enc.c
+ $(OPENSSL_PATH)/crypto/evp/bio_md.c
+ $(OPENSSL_PATH)/crypto/evp/bio_ok.c
+ $(OPENSSL_PATH)/crypto/evp/c_allc.c
+ $(OPENSSL_PATH)/crypto/evp/c_alld.c
+ $(OPENSSL_PATH)/crypto/evp/cmeth_lib.c
+ $(OPENSSL_PATH)/crypto/evp/ctrl_params_translate.c
+ $(OPENSSL_PATH)/crypto/evp/dh_ctrl.c
+ $(OPENSSL_PATH)/crypto/evp/dh_support.c
+ $(OPENSSL_PATH)/crypto/evp/digest.c
+ $(OPENSSL_PATH)/crypto/evp/dsa_ctrl.c
+ $(OPENSSL_PATH)/crypto/evp/e_aes.c
+ $(OPENSSL_PATH)/crypto/evp/e_aes_cbc_hmac_sha1.c
+ $(OPENSSL_PATH)/crypto/evp/e_aes_cbc_hmac_sha256.c
+ $(OPENSSL_PATH)/crypto/evp/e_aria.c
+ $(OPENSSL_PATH)/crypto/evp/e_bf.c
+ $(OPENSSL_PATH)/crypto/evp/e_cast.c
+ $(OPENSSL_PATH)/crypto/evp/e_chacha20_poly1305.c
+ $(OPENSSL_PATH)/crypto/evp/e_des.c
+ $(OPENSSL_PATH)/crypto/evp/e_des3.c
+ $(OPENSSL_PATH)/crypto/evp/e_idea.c
+ $(OPENSSL_PATH)/crypto/evp/e_null.c
+ $(OPENSSL_PATH)/crypto/evp/e_rc2.c
+ $(OPENSSL_PATH)/crypto/evp/e_rc4.c
+ $(OPENSSL_PATH)/crypto/evp/e_rc4_hmac_md5.c
+ $(OPENSSL_PATH)/crypto/evp/e_rc5.c
+ $(OPENSSL_PATH)/crypto/evp/e_sm4.c
+ $(OPENSSL_PATH)/crypto/evp/e_xcbc_d.c
+ $(OPENSSL_PATH)/crypto/evp/ec_ctrl.c
+ $(OPENSSL_PATH)/crypto/evp/ec_support.c
+ $(OPENSSL_PATH)/crypto/evp/encode.c
+ $(OPENSSL_PATH)/crypto/evp/evp_cnf.c
+ $(OPENSSL_PATH)/crypto/evp/evp_enc.c
+ $(OPENSSL_PATH)/crypto/evp/evp_err.c
+ $(OPENSSL_PATH)/crypto/evp/evp_fetch.c
+ $(OPENSSL_PATH)/crypto/evp/evp_key.c
+ $(OPENSSL_PATH)/crypto/evp/evp_lib.c
+ $(OPENSSL_PATH)/crypto/evp/evp_pbe.c
+ $(OPENSSL_PATH)/crypto/evp/evp_pkey.c
+ $(OPENSSL_PATH)/crypto/evp/evp_rand.c
+ $(OPENSSL_PATH)/crypto/evp/evp_utils.c
+ $(OPENSSL_PATH)/crypto/evp/exchange.c
+ $(OPENSSL_PATH)/crypto/evp/kdf_lib.c
+ $(OPENSSL_PATH)/crypto/evp/kdf_meth.c
+ $(OPENSSL_PATH)/crypto/evp/kem.c
+ $(OPENSSL_PATH)/crypto/evp/keymgmt_lib.c
+ $(OPENSSL_PATH)/crypto/evp/keymgmt_meth.c
+ $(OPENSSL_PATH)/crypto/evp/legacy_md5.c
+ $(OPENSSL_PATH)/crypto/evp/legacy_md5_sha1.c
+ $(OPENSSL_PATH)/crypto/evp/legacy_sha.c
+ $(OPENSSL_PATH)/crypto/evp/m_null.c
+ $(OPENSSL_PATH)/crypto/evp/m_sigver.c
+ $(OPENSSL_PATH)/crypto/evp/mac_lib.c
+ $(OPENSSL_PATH)/crypto/evp/mac_meth.c
+ $(OPENSSL_PATH)/crypto/evp/names.c
+ $(OPENSSL_PATH)/crypto/evp/p5_crpt.c
+ $(OPENSSL_PATH)/crypto/evp/p5_crpt2.c
+ $(OPENSSL_PATH)/crypto/evp/p_dec.c
+ $(OPENSSL_PATH)/crypto/evp/p_enc.c
+ $(OPENSSL_PATH)/crypto/evp/p_legacy.c
+ $(OPENSSL_PATH)/crypto/evp/p_lib.c
+ $(OPENSSL_PATH)/crypto/evp/p_open.c
+ $(OPENSSL_PATH)/crypto/evp/p_seal.c
+ $(OPENSSL_PATH)/crypto/evp/p_sign.c
+ $(OPENSSL_PATH)/crypto/evp/p_verify.c
+ $(OPENSSL_PATH)/crypto/evp/pbe_scrypt.c
+ $(OPENSSL_PATH)/crypto/evp/pmeth_check.c
+ $(OPENSSL_PATH)/crypto/evp/pmeth_gn.c
+ $(OPENSSL_PATH)/crypto/evp/pmeth_lib.c
+ $(OPENSSL_PATH)/crypto/evp/signature.c
+ $(OPENSSL_PATH)/crypto/ffc/ffc_backend.c
+ $(OPENSSL_PATH)/crypto/ffc/ffc_dh.c
+ $(OPENSSL_PATH)/crypto/ffc/ffc_key_generate.c
+ $(OPENSSL_PATH)/crypto/ffc/ffc_key_validate.c
+ $(OPENSSL_PATH)/crypto/ffc/ffc_params.c
+ $(OPENSSL_PATH)/crypto/ffc/ffc_params_generate.c
+ $(OPENSSL_PATH)/crypto/ffc/ffc_params_validate.c
+ $(OPENSSL_PATH)/crypto/hmac/hmac.c
+ $(OPENSSL_PATH)/crypto/http/http_client.c
+ $(OPENSSL_PATH)/crypto/http/http_err.c
+ $(OPENSSL_PATH)/crypto/http/http_lib.c
+ $(OPENSSL_PATH)/crypto/kdf/kdf_err.c
+ $(OPENSSL_PATH)/crypto/lhash/lh_stats.c
+ $(OPENSSL_PATH)/crypto/lhash/lhash.c
+ $(OPENSSL_PATH)/crypto/asn1_dsa.c
+ $(OPENSSL_PATH)/crypto/bsearch.c
+ $(OPENSSL_PATH)/crypto/context.c
+ $(OPENSSL_PATH)/crypto/core_algorithm.c
+ $(OPENSSL_PATH)/crypto/core_fetch.c
+ $(OPENSSL_PATH)/crypto/core_namemap.c
+ $(OPENSSL_PATH)/crypto/cpt_err.c
+ $(OPENSSL_PATH)/crypto/cpuid.c
+ $(OPENSSL_PATH)/crypto/cryptlib.c
+ $(OPENSSL_PATH)/crypto/ctype.c
+ $(OPENSSL_PATH)/crypto/cversion.c
+ $(OPENSSL_PATH)/crypto/der_writer.c
+ $(OPENSSL_PATH)/crypto/ebcdic.c
+ $(OPENSSL_PATH)/crypto/ex_data.c
+ $(OPENSSL_PATH)/crypto/getenv.c
+ $(OPENSSL_PATH)/crypto/info.c
+ $(OPENSSL_PATH)/crypto/init.c
+ $(OPENSSL_PATH)/crypto/initthread.c
+ $(OPENSSL_PATH)/crypto/mem.c
+ $(OPENSSL_PATH)/crypto/mem_sec.c
+ $(OPENSSL_PATH)/crypto/o_dir.c
+ $(OPENSSL_PATH)/crypto/o_fopen.c
+ $(OPENSSL_PATH)/crypto/o_init.c
+ $(OPENSSL_PATH)/crypto/o_str.c
+ $(OPENSSL_PATH)/crypto/o_time.c
+ $(OPENSSL_PATH)/crypto/packet.c
+ $(OPENSSL_PATH)/crypto/param_build.c
+ $(OPENSSL_PATH)/crypto/param_build_set.c
+ $(OPENSSL_PATH)/crypto/params.c
+ $(OPENSSL_PATH)/crypto/params_dup.c
+ $(OPENSSL_PATH)/crypto/params_from_text.c
+ $(OPENSSL_PATH)/crypto/passphrase.c
+ $(OPENSSL_PATH)/crypto/provider.c
+ $(OPENSSL_PATH)/crypto/provider_child.c
+ $(OPENSSL_PATH)/crypto/provider_conf.c
+ $(OPENSSL_PATH)/crypto/provider_core.c
+ $(OPENSSL_PATH)/crypto/punycode.c
+ $(OPENSSL_PATH)/crypto/self_test_core.c
+ $(OPENSSL_PATH)/crypto/sparse_array.c
+ $(OPENSSL_PATH)/crypto/threads_lib.c
+ $(OPENSSL_PATH)/crypto/threads_none.c
+ $(OPENSSL_PATH)/crypto/threads_pthread.c
+ $(OPENSSL_PATH)/crypto/threads_win.c
+ $(OPENSSL_PATH)/crypto/trace.c
+ $(OPENSSL_PATH)/crypto/uid.c
+ $(OPENSSL_PATH)/crypto/md5/md5_dgst.c
+ $(OPENSSL_PATH)/crypto/md5/md5_one.c
+ $(OPENSSL_PATH)/crypto/md5/md5_sha1.c
+ $(OPENSSL_PATH)/crypto/modes/cbc128.c
+ $(OPENSSL_PATH)/crypto/modes/ccm128.c
+ $(OPENSSL_PATH)/crypto/modes/cfb128.c
+ $(OPENSSL_PATH)/crypto/modes/ctr128.c
+ $(OPENSSL_PATH)/crypto/modes/cts128.c
+ $(OPENSSL_PATH)/crypto/modes/gcm128.c
+ $(OPENSSL_PATH)/crypto/modes/ocb128.c
+ $(OPENSSL_PATH)/crypto/modes/ofb128.c
+ $(OPENSSL_PATH)/crypto/modes/siv128.c
+ $(OPENSSL_PATH)/crypto/modes/wrap128.c
+ $(OPENSSL_PATH)/crypto/modes/xts128.c
+ $(OPENSSL_PATH)/crypto/objects/o_names.c
+ $(OPENSSL_PATH)/crypto/objects/obj_dat.c
+ $(OPENSSL_PATH)/crypto/objects/obj_err.c
+ $(OPENSSL_PATH)/crypto/objects/obj_lib.c
+ $(OPENSSL_PATH)/crypto/objects/obj_xref.c
+ $(OPENSSL_PATH)/crypto/pem/pem_all.c
+ $(OPENSSL_PATH)/crypto/pem/pem_err.c
+ $(OPENSSL_PATH)/crypto/pem/pem_info.c
+ $(OPENSSL_PATH)/crypto/pem/pem_lib.c
+ $(OPENSSL_PATH)/crypto/pem/pem_oth.c
+ $(OPENSSL_PATH)/crypto/pem/pem_pk8.c
+ $(OPENSSL_PATH)/crypto/pem/pem_pkey.c
+ $(OPENSSL_PATH)/crypto/pem/pem_sign.c
+ $(OPENSSL_PATH)/crypto/pem/pem_x509.c
+ $(OPENSSL_PATH)/crypto/pem/pem_xaux.c
+ $(OPENSSL_PATH)/crypto/pem/pvkfmt.c
+ $(OPENSSL_PATH)/crypto/pkcs7/bio_pk7.c
+ $(OPENSSL_PATH)/crypto/pkcs7/pk7_asn1.c
+ $(OPENSSL_PATH)/crypto/pkcs7/pk7_attr.c
+ $(OPENSSL_PATH)/crypto/pkcs7/pk7_doit.c
+ $(OPENSSL_PATH)/crypto/pkcs7/pk7_lib.c
+ $(OPENSSL_PATH)/crypto/pkcs7/pk7_mime.c
+ $(OPENSSL_PATH)/crypto/pkcs7/pk7_smime.c
+ $(OPENSSL_PATH)/crypto/pkcs7/pkcs7err.c
+ $(OPENSSL_PATH)/crypto/property/defn_cache.c
+ $(OPENSSL_PATH)/crypto/property/property.c
+ $(OPENSSL_PATH)/crypto/property/property_err.c
+ $(OPENSSL_PATH)/crypto/property/property_parse.c
+ $(OPENSSL_PATH)/crypto/property/property_query.c
+ $(OPENSSL_PATH)/crypto/property/property_string.c
+ $(OPENSSL_PATH)/crypto/rand/prov_seed.c
+ $(OPENSSL_PATH)/crypto/rand/rand_deprecated.c
+ $(OPENSSL_PATH)/crypto/rand/rand_err.c
+ $(OPENSSL_PATH)/crypto/rand/rand_lib.c
+ $(OPENSSL_PATH)/crypto/rand/rand_meth.c
+ $(OPENSSL_PATH)/crypto/rand/rand_pool.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_ameth.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_asn1.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_backend.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_chk.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_crpt.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_err.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_gen.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_lib.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_meth.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_mp.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_mp_names.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_none.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_oaep.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_ossl.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_pk1.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_pmeth.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_prn.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_pss.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_saos.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_schemes.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_sign.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_sp800_56b_check.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_sp800_56b_gen.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_x931.c
+ $(OPENSSL_PATH)/crypto/rsa/rsa_x931g.c
+ $(OPENSSL_PATH)/crypto/sha/sha1_one.c
+ $(OPENSSL_PATH)/crypto/sha/sha1dgst.c
+ $(OPENSSL_PATH)/crypto/sha/sha256.c
+ $(OPENSSL_PATH)/crypto/sha/sha3.c
+ $(OPENSSL_PATH)/crypto/sha/sha512.c
+ $(OPENSSL_PATH)/crypto/sm3/legacy_sm3.c
+ $(OPENSSL_PATH)/crypto/sm3/sm3.c
+ $(OPENSSL_PATH)/crypto/stack/stack.c
+ $(OPENSSL_PATH)/crypto/txt_db/txt_db.c
+ $(OPENSSL_PATH)/crypto/ui/ui_err.c
+ $(OPENSSL_PATH)/crypto/ui/ui_lib.c
+ $(OPENSSL_PATH)/crypto/ui/ui_null.c
+ $(OPENSSL_PATH)/crypto/ui/ui_openssl.c
+ $(OPENSSL_PATH)/crypto/ui/ui_util.c
+ $(OPENSSL_PATH)/crypto/x509/by_dir.c
+ $(OPENSSL_PATH)/crypto/x509/by_file.c
+ $(OPENSSL_PATH)/crypto/x509/by_store.c
+ $(OPENSSL_PATH)/crypto/x509/pcy_cache.c
+ $(OPENSSL_PATH)/crypto/x509/pcy_data.c
+ $(OPENSSL_PATH)/crypto/x509/pcy_lib.c
+ $(OPENSSL_PATH)/crypto/x509/pcy_map.c
+ $(OPENSSL_PATH)/crypto/x509/pcy_node.c
+ $(OPENSSL_PATH)/crypto/x509/pcy_tree.c
+ $(OPENSSL_PATH)/crypto/x509/t_crl.c
+ $(OPENSSL_PATH)/crypto/x509/t_req.c
+ $(OPENSSL_PATH)/crypto/x509/t_x509.c
+ $(OPENSSL_PATH)/crypto/x509/v3_addr.c
+ $(OPENSSL_PATH)/crypto/x509/v3_admis.c
+ $(OPENSSL_PATH)/crypto/x509/v3_akeya.c
+ $(OPENSSL_PATH)/crypto/x509/v3_akid.c
+ $(OPENSSL_PATH)/crypto/x509/v3_asid.c
+ $(OPENSSL_PATH)/crypto/x509/v3_bcons.c
+ $(OPENSSL_PATH)/crypto/x509/v3_bitst.c
+ $(OPENSSL_PATH)/crypto/x509/v3_conf.c
+ $(OPENSSL_PATH)/crypto/x509/v3_cpols.c
+ $(OPENSSL_PATH)/crypto/x509/v3_crld.c
+ $(OPENSSL_PATH)/crypto/x509/v3_enum.c
+ $(OPENSSL_PATH)/crypto/x509/v3_extku.c
+ $(OPENSSL_PATH)/crypto/x509/v3_genn.c
+ $(OPENSSL_PATH)/crypto/x509/v3_ia5.c
+ $(OPENSSL_PATH)/crypto/x509/v3_info.c
+ $(OPENSSL_PATH)/crypto/x509/v3_int.c
+ $(OPENSSL_PATH)/crypto/x509/v3_ist.c
+ $(OPENSSL_PATH)/crypto/x509/v3_lib.c
+ $(OPENSSL_PATH)/crypto/x509/v3_ncons.c
+ $(OPENSSL_PATH)/crypto/x509/v3_pci.c
+ $(OPENSSL_PATH)/crypto/x509/v3_pcia.c
+ $(OPENSSL_PATH)/crypto/x509/v3_pcons.c
+ $(OPENSSL_PATH)/crypto/x509/v3_pku.c
+ $(OPENSSL_PATH)/crypto/x509/v3_pmaps.c
+ $(OPENSSL_PATH)/crypto/x509/v3_prn.c
+ $(OPENSSL_PATH)/crypto/x509/v3_purp.c
+ $(OPENSSL_PATH)/crypto/x509/v3_san.c
+ $(OPENSSL_PATH)/crypto/x509/v3_skid.c
+ $(OPENSSL_PATH)/crypto/x509/v3_sxnet.c
+ $(OPENSSL_PATH)/crypto/x509/v3_tlsf.c
+ $(OPENSSL_PATH)/crypto/x509/v3_utf8.c
+ $(OPENSSL_PATH)/crypto/x509/v3_utl.c
+ $(OPENSSL_PATH)/crypto/x509/v3err.c
+ $(OPENSSL_PATH)/crypto/x509/x509_att.c
+ $(OPENSSL_PATH)/crypto/x509/x509_cmp.c
+ $(OPENSSL_PATH)/crypto/x509/x509_d2.c
+ $(OPENSSL_PATH)/crypto/x509/x509_def.c
+ $(OPENSSL_PATH)/crypto/x509/x509_err.c
+ $(OPENSSL_PATH)/crypto/x509/x509_ext.c
+ $(OPENSSL_PATH)/crypto/x509/x509_lu.c
+ $(OPENSSL_PATH)/crypto/x509/x509_meth.c
+ $(OPENSSL_PATH)/crypto/x509/x509_obj.c
+ $(OPENSSL_PATH)/crypto/x509/x509_r2x.c
+ $(OPENSSL_PATH)/crypto/x509/x509_req.c
+ $(OPENSSL_PATH)/crypto/x509/x509_set.c
+ $(OPENSSL_PATH)/crypto/x509/x509_trust.c
+ $(OPENSSL_PATH)/crypto/x509/x509_txt.c
+ $(OPENSSL_PATH)/crypto/x509/x509_v3.c
+ $(OPENSSL_PATH)/crypto/x509/x509_vfy.c
+ $(OPENSSL_PATH)/crypto/x509/x509_vpm.c
+ $(OPENSSL_PATH)/crypto/x509/x509cset.c
+ $(OPENSSL_PATH)/crypto/x509/x509name.c
+ $(OPENSSL_PATH)/crypto/x509/x509rset.c
+ $(OPENSSL_PATH)/crypto/x509/x509spki.c
+ $(OPENSSL_PATH)/crypto/x509/x509type.c
+ $(OPENSSL_PATH)/crypto/x509/x_all.c
+ $(OPENSSL_PATH)/crypto/x509/x_attrib.c
+ $(OPENSSL_PATH)/crypto/x509/x_crl.c
+ $(OPENSSL_PATH)/crypto/x509/x_exten.c
+ $(OPENSSL_PATH)/crypto/x509/x_name.c
+ $(OPENSSL_PATH)/crypto/x509/x_pubkey.c
+ $(OPENSSL_PATH)/crypto/x509/x_req.c
+ $(OPENSSL_PATH)/crypto/x509/x_x509.c
+ $(OPENSSL_PATH)/crypto/x509/x_x509a.c
+ $(OPENSSL_PATH)/providers/nullprov.c
+ $(OPENSSL_PATH)/providers/prov_running.c
+ $(OPENSSL_PATH)/providers/common/der/der_rsa_sig.c
+ $(OPENSSL_PATH)/providers/common/bio_prov.c
+ $(OPENSSL_PATH)/providers/common/capabilities.c
+ $(OPENSSL_PATH)/providers/common/digest_to_nid.c
+ $(OPENSSL_PATH)/providers/common/provider_seeding.c
+ $(OPENSSL_PATH)/providers/common/provider_util.c
+ $(OPENSSL_PATH)/providers/common/securitycheck.c
+ $(OPENSSL_PATH)/providers/common/securitycheck_default.c
+ $(OPENSSL_PATH)/providers/implementations/asymciphers/rsa_enc.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_cbc_hmac_sha.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_cbc_hmac_sha1_hw.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_cbc_hmac_sha256_hw.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_ccm.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_ccm_hw.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_gcm.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_gcm_hw.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_hw.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_wrp.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_xts.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_xts_fips.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_xts_hw.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_cts.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_null.c
+ $(OPENSSL_PATH)/providers/implementations/digests/md5_prov.c
+ $(OPENSSL_PATH)/providers/implementations/digests/md5_sha1_prov.c
+ $(OPENSSL_PATH)/providers/implementations/digests/null_prov.c
+ $(OPENSSL_PATH)/providers/implementations/digests/sha2_prov.c
+ $(OPENSSL_PATH)/providers/implementations/digests/sha3_prov.c
+ $(OPENSSL_PATH)/providers/implementations/digests/sm3_prov.c
+ $(OPENSSL_PATH)/providers/implementations/encode_decode/decode_der2key.c
+ $(OPENSSL_PATH)/providers/implementations/encode_decode/decode_epki2pki.c
+ $(OPENSSL_PATH)/providers/implementations/encode_decode/decode_msblob2key.c
+ $(OPENSSL_PATH)/providers/implementations/encode_decode/decode_pem2der.c
+ $(OPENSSL_PATH)/providers/implementations/encode_decode/decode_pvk2key.c
+ $(OPENSSL_PATH)/providers/implementations/encode_decode/decode_spki2typespki.c
+ $(OPENSSL_PATH)/providers/implementations/encode_decode/endecoder_common.c
+ $(OPENSSL_PATH)/providers/implementations/exchange/dh_exch.c
+ $(OPENSSL_PATH)/providers/implementations/exchange/kdf_exch.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/hkdf.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/kbkdf.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/krb5kdf.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/pbkdf2.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/pbkdf2_fips.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/pkcs12kdf.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/scrypt.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/sshkdf.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/sskdf.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/tls1_prf.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/x942kdf.c
+ $(OPENSSL_PATH)/providers/implementations/kem/rsa_kem.c
+ $(OPENSSL_PATH)/providers/implementations/keymgmt/dh_kmgmt.c
+ $(OPENSSL_PATH)/providers/implementations/keymgmt/kdf_legacy_kmgmt.c
+ $(OPENSSL_PATH)/providers/implementations/keymgmt/mac_legacy_kmgmt.c
+ $(OPENSSL_PATH)/providers/implementations/keymgmt/rsa_kmgmt.c
+ $(OPENSSL_PATH)/providers/implementations/macs/gmac_prov.c
+ $(OPENSSL_PATH)/providers/implementations/macs/hmac_prov.c
+ $(OPENSSL_PATH)/providers/implementations/macs/kmac_prov.c
+ $(OPENSSL_PATH)/providers/implementations/rands/crngt.c
+ $(OPENSSL_PATH)/providers/implementations/rands/drbg.c
+ $(OPENSSL_PATH)/providers/implementations/rands/drbg_ctr.c
+ $(OPENSSL_PATH)/providers/implementations/rands/drbg_hash.c
+ $(OPENSSL_PATH)/providers/implementations/rands/drbg_hmac.c
+ $(OPENSSL_PATH)/providers/implementations/rands/seed_src.c
+ $(OPENSSL_PATH)/providers/implementations/rands/test_rng.c
+ $(OPENSSL_PATH)/providers/implementations/rands/seeding/rand_cpu_x86.c
+ $(OPENSSL_PATH)/providers/implementations/rands/seeding/rand_tsc.c
+ $(OPENSSL_PATH)/providers/implementations/rands/seeding/rand_unix.c
+ $(OPENSSL_PATH)/providers/implementations/rands/seeding/rand_win.c
+ $(OPENSSL_PATH)/providers/implementations/signature/mac_legacy_sig.c
+ $(OPENSSL_PATH)/providers/implementations/signature/rsa_sig.c
+ $(OPENSSL_PATH)/ssl/s3_cbc.c
+ $(OPENSSL_PATH)/providers/common/der/der_rsa_key.c
+ $(OPENSSL_PATH)/providers/common/provider_ctx.c
+ $(OPENSSL_PATH)/providers/common/provider_err.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/ciphercommon.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/ciphercommon_block.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/ciphercommon_ccm.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/ciphercommon_ccm_hw.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/ciphercommon_gcm.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/ciphercommon_gcm_hw.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/ciphercommon_hw.c
+ $(OPENSSL_PATH)/providers/implementations/digests/digestcommon.c
+ $(OPENSSL_PATH)/ssl/record/tls_pad.c
+ $(OPENSSL_GEN_PATH)/providers/common/der/der_digests_gen.c
+ $(OPENSSL_GEN_PATH)/providers/common/der/der_rsa_gen.c
+ $(OPENSSL_GEN_PATH)/providers/common/der/der_wrap_gen.c
+ $(OPENSSL_PATH)/ssl/bio_ssl.c
+ $(OPENSSL_PATH)/ssl/d1_lib.c
+ $(OPENSSL_PATH)/ssl/d1_msg.c
+ $(OPENSSL_PATH)/ssl/d1_srtp.c
+ $(OPENSSL_PATH)/ssl/methods.c
+ $(OPENSSL_PATH)/ssl/pqueue.c
+ $(OPENSSL_PATH)/ssl/s3_enc.c
+ $(OPENSSL_PATH)/ssl/s3_lib.c
+ $(OPENSSL_PATH)/ssl/s3_msg.c
+ $(OPENSSL_PATH)/ssl/ssl_asn1.c
+ $(OPENSSL_PATH)/ssl/ssl_cert.c
+ $(OPENSSL_PATH)/ssl/ssl_ciph.c
+ $(OPENSSL_PATH)/ssl/ssl_conf.c
+ $(OPENSSL_PATH)/ssl/ssl_err.c
+ $(OPENSSL_PATH)/ssl/ssl_err_legacy.c
+ $(OPENSSL_PATH)/ssl/ssl_init.c
+ $(OPENSSL_PATH)/ssl/ssl_lib.c
+ $(OPENSSL_PATH)/ssl/ssl_mcnf.c
+ $(OPENSSL_PATH)/ssl/ssl_rsa.c
+ $(OPENSSL_PATH)/ssl/ssl_rsa_legacy.c
+ $(OPENSSL_PATH)/ssl/ssl_sess.c
+ $(OPENSSL_PATH)/ssl/ssl_stat.c
+ $(OPENSSL_PATH)/ssl/ssl_txt.c
+ $(OPENSSL_PATH)/ssl/ssl_utst.c
+ $(OPENSSL_PATH)/ssl/t1_enc.c
+ $(OPENSSL_PATH)/ssl/t1_lib.c
+ $(OPENSSL_PATH)/ssl/t1_trce.c
+ $(OPENSSL_PATH)/ssl/tls13_enc.c
+ $(OPENSSL_PATH)/ssl/tls_depr.c
+ $(OPENSSL_PATH)/ssl/tls_srp.c
+ $(OPENSSL_PATH)/ssl/record/dtls1_bitmap.c
+ $(OPENSSL_PATH)/ssl/record/rec_layer_d1.c
+ $(OPENSSL_PATH)/ssl/record/rec_layer_s3.c
+ $(OPENSSL_PATH)/ssl/record/ssl3_buffer.c
+ $(OPENSSL_PATH)/ssl/record/ssl3_record.c
+ $(OPENSSL_PATH)/ssl/record/ssl3_record_tls13.c
+ $(OPENSSL_PATH)/ssl/statem/extensions.c
+ $(OPENSSL_PATH)/ssl/statem/extensions_clnt.c
+ $(OPENSSL_PATH)/ssl/statem/extensions_cust.c
+ $(OPENSSL_PATH)/ssl/statem/statem.c
+ $(OPENSSL_PATH)/ssl/statem/statem_clnt.c
+ $(OPENSSL_PATH)/ssl/statem/statem_dtls.c
+ $(OPENSSL_PATH)/ssl/statem/statem_lib.c
+ $(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/aes/aesv8-armx.S | GCC
+ $(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/aes/vpaes-armv8.S | GCC
+ $(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/arm64cpuid.S | GCC
+ $(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/modes/aes-gcm-armv8_64.S | GCC
+ $(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/modes/ghashv8-armx.S | GCC
+ $(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/sha/keccak1600-armv8.S | GCC
+ $(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/sha/sha1-armv8.S | GCC
+ $(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/sha/sha256-armv8.S | GCC
+ $(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/sha/sha512-armv8.S | GCC
# Autogenerated files list ends here
[Packages]
diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf b/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf
index 45a58c7d382e..e7e83d419f4b 100644
--- a/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf
+++ b/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf
@@ -30,7 +30,7 @@ [Defines]
DEFINE OPENSSL_FLAGS = -DL_ENDIAN -DOPENSSL_SMALL_FOOTPRINT -D_CRT_SECURE_NO_DEPRECATE -D_CRT_NONSTDC_NO_DEPRECATE
DEFINE OPENSSL_FLAGS_IA32 = -DAES_ASM -DGHASH_ASM -DMD5_ASM -DOPENSSL_CPUID_OBJ -DSHA1_ASM -DSHA256_ASM -DSHA512_ASM -DVPAES_ASM
DEFINE OPENSSL_FLAGS_X64 = -DAES_ASM -DBSAES_ASM -DGHASH_ASM -DKECCAK1600_ASM -DMD5_ASM -DOPENSSL_CPUID_OBJ -DSHA1_ASM -DSHA256_ASM -DSHA512_ASM -DVPAES_ASM
- DEFINE OPENSSL_FLAGS_AARCH64 =
+ DEFINE OPENSSL_FLAGS_AARCH64 = -DKECCAK1600_ASM -DOPENSSL_CPUID_OBJ -DSHA1_ASM -DSHA256_ASM -DSHA512_ASM -DVPAES_ASM
#
# VALID_ARCHITECTURES = IA32 X64 AARCH64
@@ -1433,6 +1433,674 @@ [Sources.X64]
[Sources.AARCH64]
# Autogenerated files list starts here
+ $(OPENSSL_PATH)/crypto/aes/aes_cbc.c
+ $(OPENSSL_PATH)/crypto/aes/aes_cfb.c
+ $(OPENSSL_PATH)/crypto/aes/aes_core.c
+ $(OPENSSL_PATH)/crypto/aes/aes_ecb.c
+ $(OPENSSL_PATH)/crypto/aes/aes_ige.c
+ $(OPENSSL_PATH)/crypto/aes/aes_misc.c
+ $(OPENSSL_PATH)/crypto/aes/aes_ofb.c
+ $(OPENSSL_PATH)/crypto/aes/aes_wrap.c
+ $(OPENSSL_PATH)/crypto/asn1/a_bitstr.c
+ $(OPENSSL_PATH)/crypto/asn1/a_d2i_fp.c
+ $(OPENSSL_PATH)/crypto/asn1/a_digest.c
+ $(OPENSSL_PATH)/crypto/asn1/a_dup.c
+ $(OPENSSL_PATH)/crypto/asn1/a_gentm.c
+ $(OPENSSL_PATH)/crypto/asn1/a_i2d_fp.c
+ $(OPENSSL_PATH)/crypto/asn1/a_int.c
+ $(OPENSSL_PATH)/crypto/asn1/a_mbstr.c
+ $(OPENSSL_PATH)/crypto/asn1/a_object.c
+ $(OPENSSL_PATH)/crypto/asn1/a_octet.c
+ $(OPENSSL_PATH)/crypto/asn1/a_print.c
+ $(OPENSSL_PATH)/crypto/asn1/a_sign.c
+ $(OPENSSL_PATH)/crypto/asn1/a_strex.c
+ $(OPENSSL_PATH)/crypto/asn1/a_strnid.c
+ $(OPENSSL_PATH)/crypto/asn1/a_time.c
+ $(OPENSSL_PATH)/crypto/asn1/a_type.c
+ $(OPENSSL_PATH)/crypto/asn1/a_utctm.c
+ $(OPENSSL_PATH)/crypto/asn1/a_utf8.c
+ $(OPENSSL_PATH)/crypto/asn1/a_verify.c
+ $(OPENSSL_PATH)/crypto/asn1/ameth_lib.c
+ $(OPENSSL_PATH)/crypto/asn1/asn1_err.c
+ $(OPENSSL_PATH)/crypto/asn1/asn1_gen.c
+ $(OPENSSL_PATH)/crypto/asn1/asn1_item_list.c
+ $(OPENSSL_PATH)/crypto/asn1/asn1_lib.c
+ $(OPENSSL_PATH)/crypto/asn1/asn1_parse.c
+ $(OPENSSL_PATH)/crypto/asn1/asn_mime.c
+ $(OPENSSL_PATH)/crypto/asn1/asn_moid.c
+ $(OPENSSL_PATH)/crypto/asn1/asn_mstbl.c
+ $(OPENSSL_PATH)/crypto/asn1/asn_pack.c
+ $(OPENSSL_PATH)/crypto/asn1/bio_asn1.c
+ $(OPENSSL_PATH)/crypto/asn1/bio_ndef.c
+ $(OPENSSL_PATH)/crypto/asn1/d2i_param.c
+ $(OPENSSL_PATH)/crypto/asn1/d2i_pr.c
+ $(OPENSSL_PATH)/crypto/asn1/d2i_pu.c
+ $(OPENSSL_PATH)/crypto/asn1/evp_asn1.c
+ $(OPENSSL_PATH)/crypto/asn1/f_int.c
+ $(OPENSSL_PATH)/crypto/asn1/f_string.c
+ $(OPENSSL_PATH)/crypto/asn1/i2d_evp.c
+ $(OPENSSL_PATH)/crypto/asn1/nsseq.c
+ $(OPENSSL_PATH)/crypto/asn1/p5_pbe.c
+ $(OPENSSL_PATH)/crypto/asn1/p5_pbev2.c
+ $(OPENSSL_PATH)/crypto/asn1/p5_scrypt.c
+ $(OPENSSL_PATH)/crypto/asn1/p8_pkey.c
+ $(OPENSSL_PATH)/crypto/asn1/t_bitst.c
+ $(OPENSSL_PATH)/crypto/asn1/t_pkey.c
+ $(OPENSSL_PATH)/crypto/asn1/t_spki.c
+ $(OPENSSL_PATH)/crypto/asn1/tasn_dec.c
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+ $(OPENSSL_PATH)/crypto/x509/v3_purp.c
+ $(OPENSSL_PATH)/crypto/x509/v3_san.c
+ $(OPENSSL_PATH)/crypto/x509/v3_skid.c
+ $(OPENSSL_PATH)/crypto/x509/v3_sxnet.c
+ $(OPENSSL_PATH)/crypto/x509/v3_tlsf.c
+ $(OPENSSL_PATH)/crypto/x509/v3_utf8.c
+ $(OPENSSL_PATH)/crypto/x509/v3_utl.c
+ $(OPENSSL_PATH)/crypto/x509/v3err.c
+ $(OPENSSL_PATH)/crypto/x509/x509_att.c
+ $(OPENSSL_PATH)/crypto/x509/x509_cmp.c
+ $(OPENSSL_PATH)/crypto/x509/x509_d2.c
+ $(OPENSSL_PATH)/crypto/x509/x509_def.c
+ $(OPENSSL_PATH)/crypto/x509/x509_err.c
+ $(OPENSSL_PATH)/crypto/x509/x509_ext.c
+ $(OPENSSL_PATH)/crypto/x509/x509_lu.c
+ $(OPENSSL_PATH)/crypto/x509/x509_meth.c
+ $(OPENSSL_PATH)/crypto/x509/x509_obj.c
+ $(OPENSSL_PATH)/crypto/x509/x509_r2x.c
+ $(OPENSSL_PATH)/crypto/x509/x509_req.c
+ $(OPENSSL_PATH)/crypto/x509/x509_set.c
+ $(OPENSSL_PATH)/crypto/x509/x509_trust.c
+ $(OPENSSL_PATH)/crypto/x509/x509_txt.c
+ $(OPENSSL_PATH)/crypto/x509/x509_v3.c
+ $(OPENSSL_PATH)/crypto/x509/x509_vfy.c
+ $(OPENSSL_PATH)/crypto/x509/x509_vpm.c
+ $(OPENSSL_PATH)/crypto/x509/x509cset.c
+ $(OPENSSL_PATH)/crypto/x509/x509name.c
+ $(OPENSSL_PATH)/crypto/x509/x509rset.c
+ $(OPENSSL_PATH)/crypto/x509/x509spki.c
+ $(OPENSSL_PATH)/crypto/x509/x509type.c
+ $(OPENSSL_PATH)/crypto/x509/x_all.c
+ $(OPENSSL_PATH)/crypto/x509/x_attrib.c
+ $(OPENSSL_PATH)/crypto/x509/x_crl.c
+ $(OPENSSL_PATH)/crypto/x509/x_exten.c
+ $(OPENSSL_PATH)/crypto/x509/x_name.c
+ $(OPENSSL_PATH)/crypto/x509/x_pubkey.c
+ $(OPENSSL_PATH)/crypto/x509/x_req.c
+ $(OPENSSL_PATH)/crypto/x509/x_x509.c
+ $(OPENSSL_PATH)/crypto/x509/x_x509a.c
+ $(OPENSSL_PATH)/providers/nullprov.c
+ $(OPENSSL_PATH)/providers/prov_running.c
+ $(OPENSSL_PATH)/providers/common/der/der_rsa_sig.c
+ $(OPENSSL_PATH)/providers/common/bio_prov.c
+ $(OPENSSL_PATH)/providers/common/capabilities.c
+ $(OPENSSL_PATH)/providers/common/digest_to_nid.c
+ $(OPENSSL_PATH)/providers/common/provider_seeding.c
+ $(OPENSSL_PATH)/providers/common/provider_util.c
+ $(OPENSSL_PATH)/providers/common/securitycheck.c
+ $(OPENSSL_PATH)/providers/common/securitycheck_default.c
+ $(OPENSSL_PATH)/providers/implementations/asymciphers/rsa_enc.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_cbc_hmac_sha.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_cbc_hmac_sha1_hw.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_cbc_hmac_sha256_hw.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_ccm.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_ccm_hw.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_gcm.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_gcm_hw.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_hw.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_wrp.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_xts.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_xts_fips.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_aes_xts_hw.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_cts.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/cipher_null.c
+ $(OPENSSL_PATH)/providers/implementations/digests/md5_prov.c
+ $(OPENSSL_PATH)/providers/implementations/digests/md5_sha1_prov.c
+ $(OPENSSL_PATH)/providers/implementations/digests/null_prov.c
+ $(OPENSSL_PATH)/providers/implementations/digests/sha2_prov.c
+ $(OPENSSL_PATH)/providers/implementations/digests/sha3_prov.c
+ $(OPENSSL_PATH)/providers/implementations/digests/sm3_prov.c
+ $(OPENSSL_PATH)/providers/implementations/encode_decode/decode_der2key.c
+ $(OPENSSL_PATH)/providers/implementations/encode_decode/decode_epki2pki.c
+ $(OPENSSL_PATH)/providers/implementations/encode_decode/decode_msblob2key.c
+ $(OPENSSL_PATH)/providers/implementations/encode_decode/decode_pem2der.c
+ $(OPENSSL_PATH)/providers/implementations/encode_decode/decode_pvk2key.c
+ $(OPENSSL_PATH)/providers/implementations/encode_decode/decode_spki2typespki.c
+ $(OPENSSL_PATH)/providers/implementations/encode_decode/endecoder_common.c
+ $(OPENSSL_PATH)/providers/implementations/exchange/dh_exch.c
+ $(OPENSSL_PATH)/providers/implementations/exchange/ecdh_exch.c
+ $(OPENSSL_PATH)/providers/implementations/exchange/ecx_exch.c
+ $(OPENSSL_PATH)/providers/implementations/exchange/kdf_exch.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/hkdf.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/kbkdf.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/krb5kdf.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/pbkdf2.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/pbkdf2_fips.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/pkcs12kdf.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/scrypt.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/sshkdf.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/sskdf.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/tls1_prf.c
+ $(OPENSSL_PATH)/providers/implementations/kdfs/x942kdf.c
+ $(OPENSSL_PATH)/providers/implementations/kem/rsa_kem.c
+ $(OPENSSL_PATH)/providers/implementations/keymgmt/dh_kmgmt.c
+ $(OPENSSL_PATH)/providers/implementations/keymgmt/ec_kmgmt.c
+ $(OPENSSL_PATH)/providers/implementations/keymgmt/ecx_kmgmt.c
+ $(OPENSSL_PATH)/providers/implementations/keymgmt/kdf_legacy_kmgmt.c
+ $(OPENSSL_PATH)/providers/implementations/keymgmt/mac_legacy_kmgmt.c
+ $(OPENSSL_PATH)/providers/implementations/keymgmt/rsa_kmgmt.c
+ $(OPENSSL_PATH)/providers/implementations/macs/gmac_prov.c
+ $(OPENSSL_PATH)/providers/implementations/macs/hmac_prov.c
+ $(OPENSSL_PATH)/providers/implementations/macs/kmac_prov.c
+ $(OPENSSL_PATH)/providers/implementations/rands/crngt.c
+ $(OPENSSL_PATH)/providers/implementations/rands/drbg.c
+ $(OPENSSL_PATH)/providers/implementations/rands/drbg_ctr.c
+ $(OPENSSL_PATH)/providers/implementations/rands/drbg_hash.c
+ $(OPENSSL_PATH)/providers/implementations/rands/drbg_hmac.c
+ $(OPENSSL_PATH)/providers/implementations/rands/seed_src.c
+ $(OPENSSL_PATH)/providers/implementations/rands/test_rng.c
+ $(OPENSSL_PATH)/providers/implementations/rands/seeding/rand_cpu_x86.c
+ $(OPENSSL_PATH)/providers/implementations/rands/seeding/rand_tsc.c
+ $(OPENSSL_PATH)/providers/implementations/rands/seeding/rand_unix.c
+ $(OPENSSL_PATH)/providers/implementations/rands/seeding/rand_win.c
+ $(OPENSSL_PATH)/providers/implementations/signature/ecdsa_sig.c
+ $(OPENSSL_PATH)/providers/implementations/signature/eddsa_sig.c
+ $(OPENSSL_PATH)/providers/implementations/signature/mac_legacy_sig.c
+ $(OPENSSL_PATH)/providers/implementations/signature/rsa_sig.c
+ $(OPENSSL_PATH)/ssl/s3_cbc.c
+ $(OPENSSL_PATH)/providers/common/der/der_ec_key.c
+ $(OPENSSL_PATH)/providers/common/der/der_ec_sig.c
+ $(OPENSSL_PATH)/providers/common/der/der_ecx_key.c
+ $(OPENSSL_PATH)/providers/common/der/der_rsa_key.c
+ $(OPENSSL_PATH)/providers/common/provider_ctx.c
+ $(OPENSSL_PATH)/providers/common/provider_err.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/ciphercommon.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/ciphercommon_block.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/ciphercommon_ccm.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/ciphercommon_ccm_hw.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/ciphercommon_gcm.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/ciphercommon_gcm_hw.c
+ $(OPENSSL_PATH)/providers/implementations/ciphers/ciphercommon_hw.c
+ $(OPENSSL_PATH)/providers/implementations/digests/digestcommon.c
+ $(OPENSSL_PATH)/ssl/record/tls_pad.c
+ $(OPENSSL_GEN_PATH)/providers/common/der/der_digests_gen.c
+ $(OPENSSL_GEN_PATH)/providers/common/der/der_ec_gen.c
+ $(OPENSSL_GEN_PATH)/providers/common/der/der_ecx_gen.c
+ $(OPENSSL_GEN_PATH)/providers/common/der/der_rsa_gen.c
+ $(OPENSSL_GEN_PATH)/providers/common/der/der_wrap_gen.c
+ $(OPENSSL_PATH)/ssl/bio_ssl.c
+ $(OPENSSL_PATH)/ssl/d1_lib.c
+ $(OPENSSL_PATH)/ssl/d1_msg.c
+ $(OPENSSL_PATH)/ssl/d1_srtp.c
+ $(OPENSSL_PATH)/ssl/methods.c
+ $(OPENSSL_PATH)/ssl/pqueue.c
+ $(OPENSSL_PATH)/ssl/s3_enc.c
+ $(OPENSSL_PATH)/ssl/s3_lib.c
+ $(OPENSSL_PATH)/ssl/s3_msg.c
+ $(OPENSSL_PATH)/ssl/ssl_asn1.c
+ $(OPENSSL_PATH)/ssl/ssl_cert.c
+ $(OPENSSL_PATH)/ssl/ssl_ciph.c
+ $(OPENSSL_PATH)/ssl/ssl_conf.c
+ $(OPENSSL_PATH)/ssl/ssl_err.c
+ $(OPENSSL_PATH)/ssl/ssl_err_legacy.c
+ $(OPENSSL_PATH)/ssl/ssl_init.c
+ $(OPENSSL_PATH)/ssl/ssl_lib.c
+ $(OPENSSL_PATH)/ssl/ssl_mcnf.c
+ $(OPENSSL_PATH)/ssl/ssl_rsa.c
+ $(OPENSSL_PATH)/ssl/ssl_rsa_legacy.c
+ $(OPENSSL_PATH)/ssl/ssl_sess.c
+ $(OPENSSL_PATH)/ssl/ssl_stat.c
+ $(OPENSSL_PATH)/ssl/ssl_txt.c
+ $(OPENSSL_PATH)/ssl/ssl_utst.c
+ $(OPENSSL_PATH)/ssl/t1_enc.c
+ $(OPENSSL_PATH)/ssl/t1_lib.c
+ $(OPENSSL_PATH)/ssl/t1_trce.c
+ $(OPENSSL_PATH)/ssl/tls13_enc.c
+ $(OPENSSL_PATH)/ssl/tls_depr.c
+ $(OPENSSL_PATH)/ssl/tls_srp.c
+ $(OPENSSL_PATH)/ssl/record/dtls1_bitmap.c
+ $(OPENSSL_PATH)/ssl/record/rec_layer_d1.c
+ $(OPENSSL_PATH)/ssl/record/rec_layer_s3.c
+ $(OPENSSL_PATH)/ssl/record/ssl3_buffer.c
+ $(OPENSSL_PATH)/ssl/record/ssl3_record.c
+ $(OPENSSL_PATH)/ssl/record/ssl3_record_tls13.c
+ $(OPENSSL_PATH)/ssl/statem/extensions.c
+ $(OPENSSL_PATH)/ssl/statem/extensions_clnt.c
+ $(OPENSSL_PATH)/ssl/statem/extensions_cust.c
+ $(OPENSSL_PATH)/ssl/statem/statem.c
+ $(OPENSSL_PATH)/ssl/statem/statem_clnt.c
+ $(OPENSSL_PATH)/ssl/statem/statem_dtls.c
+ $(OPENSSL_PATH)/ssl/statem/statem_lib.c
+ $(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/aes/aesv8-armx.S | GCC
+ $(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/aes/vpaes-armv8.S | GCC
+ $(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/arm64cpuid.S | GCC
+ $(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/modes/aes-gcm-armv8_64.S | GCC
+ $(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/modes/ghashv8-armx.S | GCC
+ $(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/sha/keccak1600-armv8.S | GCC
+ $(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/sha/sha1-armv8.S | GCC
+ $(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/sha/sha256-armv8.S | GCC
+ $(OPENSSL_GEN_PATH)/AARCH64-GCC/crypto/sha/sha512-armv8.S | GCC
# Autogenerated files list ends here
[Packages]
--
2.25.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#111477): https://edk2.groups.io/g/devel/message/111477
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* [edk2-devel] [PATCH v4 5/6] CryptoPkg/OpensslLib: Add AArch64Cap for arch specific hooks
2023-11-20 13:48 [edk2-devel] [PATCH v4 0/6] CryptoPkg: Enable Openssl native instruction support for AARCH64 PierreGondois
` (3 preceding siblings ...)
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 4/6] CryptoPkg/OpensslLib: Generate files for AARCH64 native support PierreGondois
@ 2023-11-20 13:48 ` PierreGondois
2023-11-20 18:39 ` Leif Lindholm
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 6/6] CryptoPkg: Enable Openssl Accel builds for AARCH64 PierreGondois
5 siblings, 1 reply; 10+ messages in thread
From: PierreGondois @ 2023-11-20 13:48 UTC (permalink / raw)
To: devel
Cc: Jiewen Yao, Yi Li, Xiaoyu Lu, Guomin Jiang, Leif Lindholm,
Ard Biesheuvel, Sami Mujawar, Gerd Hoffmann
Add AARCH64 specific implementations of:
- OPENSSL_cpuid_setup(), probing hardware capabilitie
(presence of FEAT_AES, etc.)
- OPENSSL_rdtsc(), returning non-trusted entropy by accessing
system counter.
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
.../Library/OpensslLib/OpensslLibAccel.inf | 7 ++
.../OpensslLib/OpensslLibFullAccel.inf | 7 ++
.../OpensslLib/OpensslStub/AArch64Cap.c | 84 +++++++++++++++++++
3 files changed, 98 insertions(+)
create mode 100644 CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c
diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf b/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf
index 3d1a9638b1c1..08e8be6ea9e1 100644
--- a/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf
+++ b/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf
@@ -1329,6 +1329,7 @@ [Sources.X64]
# Autogenerated files list ends here
[Sources.AARCH64]
+ OpensslStub/AArch64Cap.c
# Autogenerated files list starts here
$(OPENSSL_PATH)/crypto/aes/aes_cbc.c
$(OPENSSL_PATH)/crypto/aes/aes_cfb.c
@@ -1955,11 +1956,17 @@ [Packages]
MdePkg/MdePkg.dec
CryptoPkg/CryptoPkg.dec
+[Packages.AARCH64]
+ ArmPkg/ArmPkg.dec
+
[LibraryClasses]
BaseLib
DebugLib
RngLib
+[LibraryClasses.AARCH64]
+ ArmLib
+
[BuildOptions]
#
# Disables the following Visual Studio compiler warnings brought by openssl source,
diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf b/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf
index e7e83d419f4b..2a01ffe06bd7 100644
--- a/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf
+++ b/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf
@@ -1432,6 +1432,7 @@ [Sources.X64]
# Autogenerated files list ends here
[Sources.AARCH64]
+ OpensslStub/AArch64Cap.c
# Autogenerated files list starts here
$(OPENSSL_PATH)/crypto/aes/aes_cbc.c
$(OPENSSL_PATH)/crypto/aes/aes_cfb.c
@@ -2107,11 +2108,17 @@ [Packages]
MdePkg/MdePkg.dec
CryptoPkg/CryptoPkg.dec
+[Packages.AARCH64]
+ ArmPkg/ArmPkg.dec
+
[LibraryClasses]
BaseLib
DebugLib
RngLib
+[LibraryClasses.AARCH64]
+ ArmLib
+
[BuildOptions]
#
# Disables the following Visual Studio compiler warnings brought by openssl source,
diff --git a/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c b/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c
new file mode 100644
index 000000000000..7468ef3ab54e
--- /dev/null
+++ b/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c
@@ -0,0 +1,84 @@
+/** @file
+ Arm capabilities probing.
+
+ Copyright (c) 2023, Arm Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <openssl/types.h>
+#include "crypto/arm_arch.h"
+
+#include <Library/ArmLib.h>
+
+/** Get bits from a value.
+
+ Shift the input value from 'shift' bits and apply 'mask'.
+
+ @param value The value to get the bits from.
+ @param shift Index of the bits to read.
+ @param mask Mask to apply to the value once shifted.
+
+ @return The desired bitfield from the value.
+**/
+#define GET_BITFIELD(value, shift, mask) \
+ ((value >> shift) & mask)
+
+UINT32 OPENSSL_armcap_P = 0;
+
+void
+OPENSSL_cpuid_setup (
+ void
+ )
+{
+ OPENSSL_armcap_P = 0;
+
+ /* Access to EL0 registers is possible from higher ELx. */
+ OPENSSL_armcap_P |= ARMV8_CPUID;
+ /* Access to Physical timer is possible. */
+ OPENSSL_armcap_P |= ARMV7_TICK;
+
+ /* Neon support is not guaranteed, but it is assumed to be present.
+ Arm ARM for Armv8, sA1.5 Advanced SIMD and floating-point support
+ */
+ OPENSSL_armcap_P |= ARMV7_NEON;
+
+ if (ArmHasAes ())
+ {
+ OPENSSL_armcap_P |= ARMV8_AES;
+ }
+
+ if (ArmHasSha1 ())
+ {
+ OPENSSL_armcap_P |= ARMV8_SHA1;
+ }
+
+ if (ArmHasSha256 ())
+ {
+ OPENSSL_armcap_P |= ARMV8_SHA256;
+ }
+
+ if (ArmHasPmull ())
+ {
+ OPENSSL_armcap_P |= ARMV8_PMULL;
+ }
+
+ if (ArmHasSha512 ())
+ {
+ OPENSSL_armcap_P |= ARMV8_SHA512;
+ }
+}
+
+/** Read system counter value.
+
+ Used to get some non-trusted entropy.
+
+ @return Lower bits of the physical counter.
+**/
+uint32_t
+OPENSSL_rdtsc (
+ void
+ )
+{
+ return (UINT32)ArmReadCntPct ();
+}
--
2.25.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* [edk2-devel] [PATCH v4 6/6] CryptoPkg: Enable Openssl Accel builds for AARCH64
2023-11-20 13:48 [edk2-devel] [PATCH v4 0/6] CryptoPkg: Enable Openssl native instruction support for AARCH64 PierreGondois
` (4 preceding siblings ...)
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 5/6] CryptoPkg/OpensslLib: Add AArch64Cap for arch specific hooks PierreGondois
@ 2023-11-20 13:48 ` PierreGondois
5 siblings, 0 replies; 10+ messages in thread
From: PierreGondois @ 2023-11-20 13:48 UTC (permalink / raw)
To: devel
Cc: Jiewen Yao, Yi Li, Xiaoyu Lu, Guomin Jiang, Leif Lindholm,
Ard Biesheuvel, Sami Mujawar, Gerd Hoffmann
Enable the following modules builds for AARCH64:
- OpensslLibAccel.inf
- OpensslLibFullAccel.inf
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
CryptoPkg/CryptoPkg.dsc | 23 ++++++++++---------
.../OpensslLib/OpensslStub/AArch64Cap.c | 15 ++++--------
CryptoPkg/Readme.md | 14 +++++------
3 files changed, 24 insertions(+), 28 deletions(-)
diff --git a/CryptoPkg/CryptoPkg.dsc b/CryptoPkg/CryptoPkg.dsc
index 6a0104a3bb68..f08808d5d18e 100644
--- a/CryptoPkg/CryptoPkg.dsc
+++ b/CryptoPkg/CryptoPkg.dsc
@@ -5,6 +5,7 @@
# Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+# Copyright (c) 2023, Arm Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -327,7 +328,7 @@ [Components.IA32, Components.X64, Components.ARM, Components.AARCH64]
MSFT:NOOPT_*_*_DLINK_FLAGS = /EXPORT:InitializeDriver=$(IMAGE_ENTRY_POINT) /BASE:0x10000
}
-[Components.IA32, Components.X64]
+[Components.IA32, Components.X64, Components.AARCH64]
CryptoPkg/Test/UnitTest/Library/BaseCryptLib/TestBaseCryptLibShell.inf {
<Defines>
FILE_GUID = B91B9A95-4D52-4501-A98F-A1711C14ED93
@@ -396,9 +397,9 @@ [Components]
TlsLib|CryptoPkg/Library/TlsLib/TlsLib.inf
}
-[Components.IA32, Components.X64]
+[Components.IA32, Components.X64, Components.AARCH64]
#
- # Build verification of IA32/X64 specific libraries
+ # Build verification of IA32/X64/AARCH64 specific libraries
#
CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf
CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf
@@ -439,9 +440,9 @@ [Components.IA32, Components.X64, Components.ARM, Components.AARCH64]
OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLibFull.inf
}
-[Components.IA32, Components.X64]
+[Components.IA32, Components.X64, Components.AARCH64]
#
- # CryptoPei with IA32/X64 performance optimized OpensslLib instance without EC services
+ # CryptoPei with IA32/X64/AARCH64 performance optimized OpensslLib instance without EC services
# IA32/X64 assembly optimizations required larger alignments
#
CryptoPkg/Driver/CryptoPei.inf {
@@ -455,7 +456,7 @@ [Components.IA32, Components.X64]
}
#
- # CryptoPei with IA32/X64 performance optimized OpensslLib instance all services
+ # CryptoPei with IA32/X64/AARCH64 performance optimized OpensslLib instance all services
# IA32/X64 assembly optimizations required larger alignments
#
CryptoPkg/Driver/CryptoPei.inf {
@@ -505,9 +506,9 @@ [Components.IA32, Components.X64, Components.ARM, Components.AARCH64]
OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLibFull.inf
}
-[Components.IA32, Components.X64]
+[Components.IA32, Components.X64, Components.AARCH64]
#
- # CryptoDxe with IA32/X64 performance optimized OpensslLib instance with no EC services
+ # CryptoDxe with IA32/X64/AARCH64 performance optimized OpensslLib instance with no EC services
# with TLS feature enabled.
# IA32/X64 assembly optimizations required larger alignments
#
@@ -521,7 +522,7 @@ [Components.IA32, Components.X64]
MSFT:*_*_X64_DLINK_FLAGS = /ALIGN:256
}
#
- # CryptoDxe with IA32/X64 performance optimized OpensslLib instance with all services.
+ # CryptoDxe with IA32/X64/AARCH64 performance optimized OpensslLib instance with all services.
# IA32/X64 assembly optimizations required larger alignments
#
CryptoPkg/Driver/CryptoDxe.inf {
@@ -561,7 +562,7 @@ [Components.IA32, Components.X64]
OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLibFull.inf
}
#
- # CryptoSmm with IA32/X64 performance optimized OpensslLib instance with no EC services
+ # CryptoSmm with IA32/X64/AARCH64 performance optimized OpensslLib instance with no EC services
# IA32/X64 assembly optimizations required larger alignments
#
CryptoPkg/Driver/CryptoSmm.inf {
@@ -574,7 +575,7 @@ [Components.IA32, Components.X64]
MSFT:*_*_X64_DLINK_FLAGS = /ALIGN:256
}
#
- # CryptoSmm with IA32/X64 performance optimized OpensslLib instance with all services
+ # CryptoSmm with IA32/X64/AARCH64 performance optimized OpensslLib instance with all services
# IA32/X64 assembly optimizations required larger alignments
#
CryptoPkg/Driver/CryptoSmm.inf {
diff --git a/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c b/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c
index 7468ef3ab54e..faee753b0fdf 100644
--- a/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c
+++ b/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c
@@ -43,28 +43,23 @@ OPENSSL_cpuid_setup (
*/
OPENSSL_armcap_P |= ARMV7_NEON;
- if (ArmHasAes ())
- {
+ if (ArmHasAes ()) {
OPENSSL_armcap_P |= ARMV8_AES;
}
- if (ArmHasSha1 ())
- {
+ if (ArmHasSha1 ()) {
OPENSSL_armcap_P |= ARMV8_SHA1;
}
- if (ArmHasSha256 ())
- {
+ if (ArmHasSha256 ()) {
OPENSSL_armcap_P |= ARMV8_SHA256;
}
- if (ArmHasPmull ())
- {
+ if (ArmHasPmull ()) {
OPENSSL_armcap_P |= ARMV8_PMULL;
}
- if (ArmHasSha512 ())
- {
+ if (ArmHasSha512 ()) {
OPENSSL_armcap_P |= ARMV8_SHA512;
}
}
diff --git a/CryptoPkg/Readme.md b/CryptoPkg/Readme.md
index 5a68dfb6abd4..cb2228b6b898 100644
--- a/CryptoPkg/Readme.md
+++ b/CryptoPkg/Readme.md
@@ -246,13 +246,13 @@ specific set of enabled cryptographic services. If ECC services are not
required, then the size can be reduced by using OpensslLib.inf instead of
`OpensslLibFull.inf`. Performance optimization requires a size increase.
-| OpensslLib Instance | SSL | ECC | Perf Opt | CPU Arch | Size |
-|:------------------------|:---:|:---:|:--------:|:--------:|:-----:|
-| OpensslLibCrypto.inf | N | N | N | All | +0K |
-| OpensslLib.inf | Y | N | N | All | +0K |
-| OpensslLibAccel.inf | Y | N | Y | IA32/X64 | +20K |
-| OpensslLibFull.inf | Y | Y | N | All | +115K |
-| OpensslLibFullAccel.inf | Y | Y | Y | IA32/X64 | +135K |
+| OpensslLib Instance | SSL | ECC | Perf Opt | CPU Arch | Size |
+|:------------------------|:---:|:---:|:--------:|:----------------:|:-----:|
+| OpensslLibCrypto.inf | N | N | N | All | +0K |
+| OpensslLib.inf | Y | N | N | All | +0K |
+| OpensslLibAccel.inf | Y | N | Y | IA32/X64/AARCH64 | +20K |
+| OpensslLibFull.inf | Y | Y | N | All | +115K |
+| OpensslLibFullAccel.inf | Y | Y | Y | IA32/X64/AARCH64 | +135K |
### SEC Phase Library Mappings
--
2.25.1
-=-=-=-=-=-=-=-=-=-=-=-
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View/Reply Online (#111479): https://edk2.groups.io/g/devel/message/111479
Mute This Topic: https://groups.io/mt/102707268/7686176
Group Owner: devel+owner@edk2.groups.io
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [edk2-devel] [PATCH v4 1/6] ArmPkg/ArmLib: Add macros/helper functions around AA64Isar0 register
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 1/6] ArmPkg/ArmLib: Add macros/helper functions around AA64Isar0 register PierreGondois
@ 2023-11-20 18:27 ` Leif Lindholm
0 siblings, 0 replies; 10+ messages in thread
From: Leif Lindholm @ 2023-11-20 18:27 UTC (permalink / raw)
To: Pierre Gondois
Cc: devel, Jiewen Yao, Yi Li, Xiaoyu Lu, Guomin Jiang, Ard Biesheuvel,
Sami Mujawar, Gerd Hoffmann
On Mon, Nov 20, 2023 at 14:48:21 +0100, Pierre Gondois wrote:
> Add macro definitions and helper functions to access AArch64
> capabilities described in the AA64Isar0 register.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
> ArmPkg/Include/Chipset/AArch64.h | 60 +++-
> ArmPkg/Include/Library/ArmLib.h | 228 ++++++++++++-
> ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c | 367 +++++++++++++++++++++
> 3 files changed, 653 insertions(+), 2 deletions(-)
>
> diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h
> index 5390bf0a2774..97c20e71a811 100644
> --- a/ArmPkg/Include/Chipset/AArch64.h
> +++ b/ArmPkg/Include/Chipset/AArch64.h
> @@ -1,7 +1,7 @@
> /** @file
>
> Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> - Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.<BR>
> + Copyright (c) 2011 - 2023, Arm Limited. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> @@ -127,6 +127,64 @@
> // build for ARMv8.0, we need to define the register here.
> #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
>
> +//
> +// Bit shifts for the ID_AA64ISAR0_EL1 register.
> +//
> +#define ARM_ID_AA64ISAR0_EL1_AES_SHIFT (4U)
> +#define ARM_ID_AA64ISAR0_EL1_SHA1_SHIFT (8U)
> +#define ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT (12U)
> +#define ARM_ID_AA64ISAR0_EL1_CRC32_SHIFT (16U)
> +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_SHIFT (20U)
> +#define ARM_ID_AA64ISAR0_EL1_RDM_SHIFT (28U)
> +#define ARM_ID_AA64ISAR0_EL1_SHA3_SHIFT (32U)
> +#define ARM_ID_AA64ISAR0_EL1_SM3_SHIFT (36U)
> +#define ARM_ID_AA64ISAR0_EL1_SM4_SHIFT (40U)
> +#define ARM_ID_AA64ISAR0_EL1_DP_SHIFT (44U)
> +#define ARM_ID_AA64ISAR0_EL1_FHM_SHIFT (48U)
> +#define ARM_ID_AA64ISAR0_EL1_TS_SHIFT (52U)
> +#define ARM_ID_AA64ISAR0_EL1_TLB_SHIFT (56U)
> +#define ARM_ID_AA64ISAR0_EL1_RNDR_SHIFT (60U)
> +
> +//
> +// Bit masks for the ID_AA64ISAR0_EL1 fields.
> +//
> +#define ARM_ID_AA64ISAR0_EL1_AES_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_SHA1_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_SHA2_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_CRC32_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_RDM_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_SHA3_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_SM3_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_SM4_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_DP_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_FHM_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_TS_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_TLB_MASK (0xFU)
> +#define ARM_ID_AA64ISAR0_EL1_RNDR_MASK (0xFU)
> +
> +//
> +// Bit masks for the ID_AA64ISAR0_EL1 field values.
> +//
> +#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_AES_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_AES_FEAT_PMULL_MASK (0x2U)
> +#define ARM_ID_AA64ISAR0_EL1_SHA1_FEAT_SHA1_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA256_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA512_MASK (0x2U)
> +#define ARM_ID_AA64ISAR0_EL1_CRC32_HAVE_CRC32_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_ATOMIC_FEAT_LSE_MASK (0x2U)
> +#define ARM_ID_AA64ISAR0_EL1_RDM_FEAT_RDM_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_SHA3_FEAT_SHA3_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_SM3_FEAT_SM3_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_SM4_FEAT_SM4_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_DP_FEAT_DOTPROD_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_FHM_FEAT_FHM_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM2_MASK (0x2U)
> +#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIOS_MASK (0x1U)
> +#define ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIRANGE_MASK (0x2U)
> +#define ARM_ID_AA64ISAR0_EL1_RNDR_FEAT_RNG_MASK (0x1U)
> +
> #define VECTOR_BASE(tbl) \
> .section .text.##tbl##,"ax"; \
> .align 11; \
> diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
> index 6aa8a48f07f3..a176fcd7bf0a 100644
> --- a/ArmPkg/Include/Library/ArmLib.h
> +++ b/ArmPkg/Include/Library/ArmLib.h
> @@ -1,7 +1,7 @@
> /** @file
>
> Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> - Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
> + Copyright (c) 2011 - 2023, Arm Limited. All rights reserved.<BR>
> Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
> @@ -805,6 +805,232 @@ ArmHasEte (
> VOID
> );
>
> +/** Read AA64Isar0 register.
> +
> + @return AA64Isar0's register value.
> +**/
> +UINTN
> +EFIAPI
> +ArmReadIdAA64Isar0 (
> + VOID
> + );
This declaration already exists in
Library/ArmLib/AArch64/AArch64Lib.h, so can be dropped.
With that:
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
Thanks!
/
Leif
> +
> +/**
> + Checks whether the CPU implements FEAT_AES.
> +
> + @retval TRUE FEAT_AES is implemented.
> + @retval FALSE FEAT_AES is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasAes (
> + VOID
> + );
> +
> +/**
> + Checks whether the CPU implements FEAT_PMULL.
> +
> + @retval TRUE FEAT_PMULL is implemented.
> + @retval FALSE FEAT_PMULL is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasPmull (
> + VOID
> + );
> +
> +/**
> + Checks whether the CPU implements FEAT_SHA1.
> +
> + @retval TRUE FEAT_SHA1 is implemented.
> + @retval FALSE FEAT_SHA1 is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasSha1 (
> + VOID
> + );
> +
> +/**
> + Checks whether the CPU implements FEAT_SHA256.
> +
> + @retval TRUE FEAT_SHA256 is implemented.
> + @retval FALSE FEAT_SHA256 is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasSha256 (
> + VOID
> + );
> +
> +/**
> + Checks whether the CPU implements FEAT_SHA512.
> +
> + @retval TRUE FEAT_SHA512 is implemented.
> + @retval FALSE FEAT_SHA512 is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasSha512 (
> + VOID
> + );
> +
> +/**
> + Checks whether the CPU implements CRC32 instruction.
> +
> + @retval TRUE CRC32 instruction is implemented.
> + @retval FALSE CRC32 instruction is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasCrc32 (
> + VOID
> + );
> +
> +/**
> + Checks whether the CPU implements FEAT_LSE.
> +
> + @retval TRUE FEAT_LSE is implemented.
> + @retval FALSE FEAT_LSE is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasLse (
> + VOID
> + );
> +
> +/**
> + Checks whether the CPU implements FEAT_RDM.
> +
> + @retval TRUE FEAT_RDM is implemented.
> + @retval FALSE FEAT_RDM is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasRdm (
> + VOID
> + );
> +
> +/**
> + Checks whether the CPU implements FEAT_SHA3.
> +
> + @retval TRUE FEAT_SHA3 is implemented.
> + @retval FALSE FEAT_SHA3 is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasSha3 (
> + VOID
> + );
> +
> +/**
> + Checks whether the CPU implements FEAT_SM3.
> +
> + @retval TRUE FEAT_SM3 is implemented.
> + @retval FALSE FEAT_SM3 is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasSm3 (
> + VOID
> + );
> +
> +/**
> + Checks whether the CPU implements FEAT_SM4.
> +
> + @retval TRUE FEAT_SM4 is implemented.
> + @retval FALSE FEAT_SM4 is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasSm4 (
> + VOID
> + );
> +
> +/**
> + Checks whether the CPU implements FEAT_DotProd.
> +
> + @retval TRUE FEAT_DotProd is implemented.
> + @retval FALSE FEAT_DotProd is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasDp (
> + VOID
> + );
> +
> +/**
> + Checks whether the CPU implements FEAT_FHM.
> +
> + @retval TRUE FEAT_FHM is implemented.
> + @retval FALSE FEAT_FHM is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasFhm (
> + VOID
> + );
> +
> +/**
> + Checks whether the CPU implements FEAT_FlagM.
> +
> + @retval TRUE FEAT_FlagM is implemented.
> + @retval FALSE FEAT_FlagM is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasFlagm (
> + VOID
> + );
> +
> +/**
> + Checks whether the CPU implements FEAT_FlagM2.
> +
> + @retval TRUE FEAT_FlagM2 is implemented.
> + @retval FALSE FEAT_FlagM2 is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasFlagm2 (
> + VOID
> + );
> +
> +/**
> + Checks whether the CPU implements FEAT_TLBIOS.
> +
> + @retval TRUE FEAT_TLBIOS is implemented.
> + @retval FALSE FEAT_TLBIOS is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasTlbios (
> + VOID
> + );
> +
> +/**
> + Checks whether the CPU implements FEAT_TLBIRANGE.
> +
> + @retval TRUE FEAT_TLBIRANGE is implemented.
> + @retval FALSE FEAT_TLBIRANGE is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasTlbirange (
> + VOID
> + );
> +
> +/**
> + Checks whether the CPU implements FEAT_RNG.
> +
> + @retval TRUE FEAT_RNG is implemented.
> + @retval FALSE FEAT_RNG is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasRndr (
> + VOID
> + );
> +
> #endif // MDE_CPU_AARCH64
>
> #ifdef MDE_CPU_ARM
> diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
> index 87285465871d..c64c015844a6 100644
> --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
> +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
> @@ -18,6 +18,19 @@
> #include "AArch64Lib.h"
> #include "ArmLibPrivate.h"
>
> +/** Get bits from a value.
> +
> + Shift the input value from 'shift' bits and apply 'mask'.
> +
> + @param value The value to get the bits from.
> + @param shift Index of the bits to read.
> + @param mask Mask to apply to the value once shifted.
> +
> + @return The desired bitfield from the value.
> +**/
> +#define GET_BITFIELD(value, shift, mask) \
> + ((value >> shift) & mask)
> +
> VOID
> AArch64DataCacheOperation (
> IN AARCH64_CACHE_OPERATION DataCacheOperation
> @@ -150,3 +163,357 @@ ArmHasEte (
> // The ID_AA64DFR0_EL1.TraceVer field identifies the presence of FEAT_ETE.
> return ((ArmReadIdAA64Dfr0 () & AARCH64_DFR0_TRACEVER) != 0);
> }
> +
> +/**
> + Checks whether the CPU implements FEAT_AES.
> +
> + @retval TRUE FEAT_AES is implemented.
> + @retval FALSE FEAT_AES is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasAes (
> + VOID
> + )
> +{
> + return GET_BITFIELD (
> + ArmReadIdAA64Isar0 (),
> + ARM_ID_AA64ISAR0_EL1_AES_SHIFT,
> + ARM_ID_AA64ISAR0_EL1_AES_MASK
> + ) != 0;
> +}
> +
> +/**
> + Checks whether the CPU implements FEAT_PMULL.
> +
> + @retval TRUE FEAT_PMULL is implemented.
> + @retval FALSE FEAT_PMULL is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasPmull (
> + VOID
> + )
> +{
> + //
> + // Only check BIT1 of AES field, bits [7:4]
> + //
> + return GET_BITFIELD (
> + ArmReadIdAA64Isar0 (),
> + ARM_ID_AA64ISAR0_EL1_AES_SHIFT,
> + ARM_ID_AA64ISAR0_EL1_AES_FEAT_PMULL_MASK
> + ) != 0;
> +}
> +
> +/**
> + Checks whether the CPU implements FEAT_SHA1.
> +
> + @retval TRUE FEAT_SHA1 is implemented.
> + @retval FALSE FEAT_SHA1 is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasSha1 (
> + VOID
> + )
> +{
> + return GET_BITFIELD (
> + ArmReadIdAA64Isar0 (),
> + ARM_ID_AA64ISAR0_EL1_SHA1_SHIFT,
> + ARM_ID_AA64ISAR0_EL1_SHA1_MASK
> + ) != 0;
> +}
> +
> +/**
> + Checks whether the CPU implements FEAT_SHA256.
> +
> + @retval TRUE FEAT_SHA256 is implemented.
> + @retval FALSE FEAT_SHA256 is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasSha256 (
> + VOID
> + )
> +{
> + return GET_BITFIELD (
> + ArmReadIdAA64Isar0 (),
> + ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT,
> + ARM_ID_AA64ISAR0_EL1_SHA2_MASK
> + ) != 0;
> +}
> +
> +/**
> + Checks whether the CPU implements FEAT_SHA512.
> +
> + @retval TRUE FEAT_SHA512 is implemented.
> + @retval FALSE FEAT_SHA512 is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasSha512 (
> + VOID
> + )
> +{
> + //
> + // Only check BIT1 of SHA2 field, bits [15:12]
> + //
> + return GET_BITFIELD (
> + ArmReadIdAA64Isar0 (),
> + ARM_ID_AA64ISAR0_EL1_SHA2_SHIFT,
> + ARM_ID_AA64ISAR0_EL1_SHA2_FEAT_SHA512_MASK
> + ) != 0;
> +}
> +
> +/**
> + Checks whether the CPU implements CRC32 instruction.
> +
> + @retval TRUE CRC32 instruction is implemented.
> + @retval FALSE CRC32 instruction is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasCrc32 (
> + VOID
> + )
> +{
> + return GET_BITFIELD (
> + ArmReadIdAA64Isar0 (),
> + ARM_ID_AA64ISAR0_EL1_CRC32_SHIFT,
> + ARM_ID_AA64ISAR0_EL1_CRC32_MASK
> + ) != 0;
> +}
> +
> +/**
> + Checks whether the CPU implements FEAT_LSE.
> +
> + @retval TRUE FEAT_LSE is implemented.
> + @retval FALSE FEAT_LSE is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasLse (
> + VOID
> + )
> +{
> + return GET_BITFIELD (
> + ArmReadIdAA64Isar0 (),
> + ARM_ID_AA64ISAR0_EL1_ATOMIC_SHIFT,
> + ARM_ID_AA64ISAR0_EL1_ATOMIC_MASK
> + ) != 0;
> +}
> +
> +/**
> + Checks whether the CPU implements FEAT_RDM.
> +
> + @retval TRUE FEAT_RDM is implemented.
> + @retval FALSE FEAT_RDM is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasRdm (
> + VOID
> + )
> +{
> + return GET_BITFIELD (
> + ArmReadIdAA64Isar0 (),
> + ARM_ID_AA64ISAR0_EL1_RDM_SHIFT,
> + ARM_ID_AA64ISAR0_EL1_RDM_MASK
> + ) != 0;
> +}
> +
> +/**
> + Checks whether the CPU implements FEAT_SHA3.
> +
> + @retval TRUE FEAT_SHA3 is implemented.
> + @retval FALSE FEAT_SHA3 is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasSha3 (
> + VOID
> + )
> +{
> + return GET_BITFIELD (
> + ArmReadIdAA64Isar0 (),
> + ARM_ID_AA64ISAR0_EL1_SHA3_SHIFT,
> + ARM_ID_AA64ISAR0_EL1_SHA3_MASK
> + ) != 0;
> +}
> +
> +/**
> + Checks whether the CPU implements FEAT_SM3.
> +
> + @retval TRUE FEAT_SM3 is implemented.
> + @retval FALSE FEAT_SM3 is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasSm3 (
> + VOID
> + )
> +{
> + return GET_BITFIELD (
> + ArmReadIdAA64Isar0 (),
> + ARM_ID_AA64ISAR0_EL1_SM3_SHIFT,
> + ARM_ID_AA64ISAR0_EL1_SM3_MASK
> + ) != 0;
> +}
> +
> +/**
> + Checks whether the CPU implements FEAT_SM4.
> +
> + @retval TRUE FEAT_SM4 is implemented.
> + @retval FALSE FEAT_SM4 is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasSm4 (
> + VOID
> + )
> +{
> + return GET_BITFIELD (
> + ArmReadIdAA64Isar0 (),
> + ARM_ID_AA64ISAR0_EL1_SM4_SHIFT,
> + ARM_ID_AA64ISAR0_EL1_SM4_MASK
> + ) != 0;
> +}
> +
> +/**
> + Checks whether the CPU implements FEAT_DotProd.
> +
> + @retval TRUE FEAT_DotProd is implemented.
> + @retval FALSE FEAT_DotProd is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasDp (
> + VOID
> + )
> +{
> + return GET_BITFIELD (
> + ArmReadIdAA64Isar0 (),
> + ARM_ID_AA64ISAR0_EL1_DP_SHIFT,
> + ARM_ID_AA64ISAR0_EL1_DP_MASK
> + ) != 0;
> +}
> +
> +/**
> + Checks whether the CPU implements FEAT_FHM.
> +
> + @retval TRUE FEAT_FHM is implemented.
> + @retval FALSE FEAT_FHM is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasFhm (
> + VOID
> + )
> +{
> + return GET_BITFIELD (
> + ArmReadIdAA64Isar0 (),
> + ARM_ID_AA64ISAR0_EL1_FHM_SHIFT,
> + ARM_ID_AA64ISAR0_EL1_FHM_MASK
> + ) != 0;
> +}
> +
> +/**
> + Checks whether the CPU implements FEAT_FlagM.
> +
> + @retval TRUE FEAT_FlagM is implemented.
> + @retval FALSE FEAT_FlagM is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasFlagm (
> + VOID
> + )
> +{
> + return GET_BITFIELD (
> + ArmReadIdAA64Isar0 (),
> + ARM_ID_AA64ISAR0_EL1_TS_SHIFT,
> + ARM_ID_AA64ISAR0_EL1_TS_MASK
> + ) != 0;
> +}
> +
> +/**
> + Checks whether the CPU implements FEAT_FlagM2.
> +
> + @retval TRUE FEAT_FlagM2 is implemented.
> + @retval FALSE FEAT_FlagM2 is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasFlagm2 (
> + VOID
> + )
> +{
> + //
> + // Only check BIT1 of TS field, bits [55:52]
> + //
> + return GET_BITFIELD (
> + ArmReadIdAA64Isar0 (),
> + ARM_ID_AA64ISAR0_EL1_TS_SHIFT,
> + ARM_ID_AA64ISAR0_EL1_TS_FEAT_FLAGM2_MASK
> + ) != 0;
> +}
> +
> +/**
> + Checks whether the CPU implements FEAT_TLBIOS.
> +
> + @retval TRUE FEAT_TLBIOS is implemented.
> + @retval FALSE FEAT_TLBIOS is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasTlbios (
> + VOID
> + )
> +{
> + return GET_BITFIELD (
> + ArmReadIdAA64Isar0 (),
> + ARM_ID_AA64ISAR0_EL1_TLB_SHIFT,
> + ARM_ID_AA64ISAR0_EL1_TLB_MASK
> + ) != 0;
> +}
> +
> +/**
> + Checks whether the CPU implements FEAT_TLBIRANGE.
> +
> + @retval TRUE FEAT_TLBIRANGE is implemented.
> + @retval FALSE FEAT_TLBIRANGE is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasTlbirange (
> + VOID
> + )
> +{
> + //
> + // Only check BIT1 of TLB field, bits [59:56]
> + //
> + return GET_BITFIELD (
> + ArmReadIdAA64Isar0 (),
> + ARM_ID_AA64ISAR0_EL1_TLB_SHIFT,
> + ARM_ID_AA64ISAR0_EL1_TLB_FEAT_TLBIRANGE_MASK
> + ) != 0;
> +}
> +
> +/**
> + Checks whether the CPU implements FEAT_RNG.
> +
> + @retval TRUE FEAT_RNG is implemented.
> + @retval FALSE FEAT_RNG is not implemented.
> +**/
> +BOOLEAN
> +EFIAPI
> +ArmHasRndr (
> + VOID
> + )
> +{
> + return GET_BITFIELD (
> + ArmReadIdAA64Isar0 (),
> + ARM_ID_AA64ISAR0_EL1_RNDR_SHIFT,
> + ARM_ID_AA64ISAR0_EL1_RNDR_MASK
> + ) != 0;
> +}
> --
> 2.25.1
>
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* Re: [edk2-devel] [PATCH v4 5/6] CryptoPkg/OpensslLib: Add AArch64Cap for arch specific hooks
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 5/6] CryptoPkg/OpensslLib: Add AArch64Cap for arch specific hooks PierreGondois
@ 2023-11-20 18:39 ` Leif Lindholm
2023-11-21 8:49 ` PierreGondois
0 siblings, 1 reply; 10+ messages in thread
From: Leif Lindholm @ 2023-11-20 18:39 UTC (permalink / raw)
To: Pierre Gondois
Cc: devel, Jiewen Yao, Yi Li, Xiaoyu Lu, Guomin Jiang, Ard Biesheuvel,
Sami Mujawar, Gerd Hoffmann
On Mon, Nov 20, 2023 at 14:48:25 +0100, Pierre Gondois wrote:
> Add AARCH64 specific implementations of:
> - OPENSSL_cpuid_setup(), probing hardware capabilitie
> (presence of FEAT_AES, etc.)
> - OPENSSL_rdtsc(), returning non-trusted entropy by accessing
> system counter.
>
> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
> .../Library/OpensslLib/OpensslLibAccel.inf | 7 ++
> .../OpensslLib/OpensslLibFullAccel.inf | 7 ++
> .../OpensslLib/OpensslStub/AArch64Cap.c | 84 +++++++++++++++++++
> 3 files changed, 98 insertions(+)
> create mode 100644 CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c
>
> diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf b/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf
> index 3d1a9638b1c1..08e8be6ea9e1 100644
> --- a/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf
> +++ b/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf
> @@ -1329,6 +1329,7 @@ [Sources.X64]
> # Autogenerated files list ends here
>
> [Sources.AARCH64]
> + OpensslStub/AArch64Cap.c
> # Autogenerated files list starts here
> $(OPENSSL_PATH)/crypto/aes/aes_cbc.c
> $(OPENSSL_PATH)/crypto/aes/aes_cfb.c
> @@ -1955,11 +1956,17 @@ [Packages]
> MdePkg/MdePkg.dec
> CryptoPkg/CryptoPkg.dec
>
> +[Packages.AARCH64]
> + ArmPkg/ArmPkg.dec
> +
> [LibraryClasses]
> BaseLib
> DebugLib
> RngLib
>
> +[LibraryClasses.AARCH64]
> + ArmLib
> +
> [BuildOptions]
> #
> # Disables the following Visual Studio compiler warnings brought by openssl source,
> diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf b/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf
> index e7e83d419f4b..2a01ffe06bd7 100644
> --- a/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf
> +++ b/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf
> @@ -1432,6 +1432,7 @@ [Sources.X64]
> # Autogenerated files list ends here
>
> [Sources.AARCH64]
> + OpensslStub/AArch64Cap.c
> # Autogenerated files list starts here
> $(OPENSSL_PATH)/crypto/aes/aes_cbc.c
> $(OPENSSL_PATH)/crypto/aes/aes_cfb.c
> @@ -2107,11 +2108,17 @@ [Packages]
> MdePkg/MdePkg.dec
> CryptoPkg/CryptoPkg.dec
>
> +[Packages.AARCH64]
> + ArmPkg/ArmPkg.dec
> +
> [LibraryClasses]
> BaseLib
> DebugLib
> RngLib
>
> +[LibraryClasses.AARCH64]
> + ArmLib
> +
> [BuildOptions]
> #
> # Disables the following Visual Studio compiler warnings brought by openssl source,
> diff --git a/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c b/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c
> new file mode 100644
> index 000000000000..7468ef3ab54e
> --- /dev/null
> +++ b/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c
> @@ -0,0 +1,84 @@
> +/** @file
> + Arm capabilities probing.
> +
> + Copyright (c) 2023, Arm Limited. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <openssl/types.h>
> +#include "crypto/arm_arch.h"
> +
> +#include <Library/ArmLib.h>
> +
> +/** Get bits from a value.
> +
> + Shift the input value from 'shift' bits and apply 'mask'.
> +
> + @param value The value to get the bits from.
> + @param shift Index of the bits to read.
> + @param mask Mask to apply to the value once shifted.
> +
> + @return The desired bitfield from the value.
> +**/
> +#define GET_BITFIELD(value, shift, mask) \
> + ((value >> shift) & mask)
(This macro appears unused here now.)
> +
> +UINT32 OPENSSL_armcap_P = 0;
> +
> +void
> +OPENSSL_cpuid_setup (
> + void
> + )
> +{
> + OPENSSL_armcap_P = 0;
> +
> + /* Access to EL0 registers is possible from higher ELx. */
> + OPENSSL_armcap_P |= ARMV8_CPUID;
> + /* Access to Physical timer is possible. */
> + OPENSSL_armcap_P |= ARMV7_TICK;
> +
> + /* Neon support is not guaranteed, but it is assumed to be present.
> + Arm ARM for Armv8, sA1.5 Advanced SIMD and floating-point support
> + */
> + OPENSSL_armcap_P |= ARMV7_NEON;
> +
> + if (ArmHasAes ())
> + {
And I think that curly bracket is supposed to be on the previous line
(and similarly below), but this may be intional to align with nearby
code?
Anyway, this is a big readability improvement, thank you very much!
Acked-by: Leif Lindholm <quic_llindhol@quicinc.com>
/
Leif
> + OPENSSL_armcap_P |= ARMV8_AES;
> + }
> +
> + if (ArmHasSha1 ())
> + {
> + OPENSSL_armcap_P |= ARMV8_SHA1;
> + }
> +
> + if (ArmHasSha256 ())
> + {
> + OPENSSL_armcap_P |= ARMV8_SHA256;
> + }
> +
> + if (ArmHasPmull ())
> + {
> + OPENSSL_armcap_P |= ARMV8_PMULL;
> + }
> +
> + if (ArmHasSha512 ())
> + {
> + OPENSSL_armcap_P |= ARMV8_SHA512;
> + }
> +}
> +
> +/** Read system counter value.
> +
> + Used to get some non-trusted entropy.
> +
> + @return Lower bits of the physical counter.
> +**/
> +uint32_t
> +OPENSSL_rdtsc (
> + void
> + )
> +{
> + return (UINT32)ArmReadCntPct ();
> +}
> --
> 2.25.1
>
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* Re: [edk2-devel] [PATCH v4 5/6] CryptoPkg/OpensslLib: Add AArch64Cap for arch specific hooks
2023-11-20 18:39 ` Leif Lindholm
@ 2023-11-21 8:49 ` PierreGondois
0 siblings, 0 replies; 10+ messages in thread
From: PierreGondois @ 2023-11-21 8:49 UTC (permalink / raw)
To: Leif Lindholm
Cc: devel, Jiewen Yao, Yi Li, Xiaoyu Lu, Guomin Jiang, Ard Biesheuvel,
Sami Mujawar, Gerd Hoffmann
On 11/20/23 19:39, Leif Lindholm wrote:
> On Mon, Nov 20, 2023 at 14:48:25 +0100, Pierre Gondois wrote:
>> Add AARCH64 specific implementations of:
>> - OPENSSL_cpuid_setup(), probing hardware capabilitie
>> (presence of FEAT_AES, etc.)
>> - OPENSSL_rdtsc(), returning non-trusted entropy by accessing
>> system counter.
>>
>> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
>> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
>> ---
>> .../Library/OpensslLib/OpensslLibAccel.inf | 7 ++
>> .../OpensslLib/OpensslLibFullAccel.inf | 7 ++
>> .../OpensslLib/OpensslStub/AArch64Cap.c | 84 +++++++++++++++++++
>> 3 files changed, 98 insertions(+)
>> create mode 100644 CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c
>>
>> diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf b/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf
>> index 3d1a9638b1c1..08e8be6ea9e1 100644
>> --- a/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf
>> +++ b/CryptoPkg/Library/OpensslLib/OpensslLibAccel.inf
>> @@ -1329,6 +1329,7 @@ [Sources.X64]
>> # Autogenerated files list ends here
>>
>> [Sources.AARCH64]
>> + OpensslStub/AArch64Cap.c
>> # Autogenerated files list starts here
>> $(OPENSSL_PATH)/crypto/aes/aes_cbc.c
>> $(OPENSSL_PATH)/crypto/aes/aes_cfb.c
>> @@ -1955,11 +1956,17 @@ [Packages]
>> MdePkg/MdePkg.dec
>> CryptoPkg/CryptoPkg.dec
>>
>> +[Packages.AARCH64]
>> + ArmPkg/ArmPkg.dec
>> +
>> [LibraryClasses]
>> BaseLib
>> DebugLib
>> RngLib
>>
>> +[LibraryClasses.AARCH64]
>> + ArmLib
>> +
>> [BuildOptions]
>> #
>> # Disables the following Visual Studio compiler warnings brought by openssl source,
>> diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf b/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf
>> index e7e83d419f4b..2a01ffe06bd7 100644
>> --- a/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf
>> +++ b/CryptoPkg/Library/OpensslLib/OpensslLibFullAccel.inf
>> @@ -1432,6 +1432,7 @@ [Sources.X64]
>> # Autogenerated files list ends here
>>
>> [Sources.AARCH64]
>> + OpensslStub/AArch64Cap.c
>> # Autogenerated files list starts here
>> $(OPENSSL_PATH)/crypto/aes/aes_cbc.c
>> $(OPENSSL_PATH)/crypto/aes/aes_cfb.c
>> @@ -2107,11 +2108,17 @@ [Packages]
>> MdePkg/MdePkg.dec
>> CryptoPkg/CryptoPkg.dec
>>
>> +[Packages.AARCH64]
>> + ArmPkg/ArmPkg.dec
>> +
>> [LibraryClasses]
>> BaseLib
>> DebugLib
>> RngLib
>>
>> +[LibraryClasses.AARCH64]
>> + ArmLib
>> +
>> [BuildOptions]
>> #
>> # Disables the following Visual Studio compiler warnings brought by openssl source,
>> diff --git a/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c b/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c
>> new file mode 100644
>> index 000000000000..7468ef3ab54e
>> --- /dev/null
>> +++ b/CryptoPkg/Library/OpensslLib/OpensslStub/AArch64Cap.c
>> @@ -0,0 +1,84 @@
>> +/** @file
>> + Arm capabilities probing.
>> +
>> + Copyright (c) 2023, Arm Limited. All rights reserved.<BR>
>> +
>> + SPDX-License-Identifier: BSD-2-Clause-Patent
>> +**/
>> +
>> +#include <openssl/types.h>
>> +#include "crypto/arm_arch.h"
>> +
>> +#include <Library/ArmLib.h>
>> +
>> +/** Get bits from a value.
>> +
>> + Shift the input value from 'shift' bits and apply 'mask'.
>> +
>> + @param value The value to get the bits from.
>> + @param shift Index of the bits to read.
>> + @param mask Mask to apply to the value once shifted.
>> +
>> + @return The desired bitfield from the value.
>> +**/
>> +#define GET_BITFIELD(value, shift, mask) \
>> + ((value >> shift) & mask)
>
> (This macro appears unused here now.)
>
>> +
>> +UINT32 OPENSSL_armcap_P = 0;
>> +
>> +void
>> +OPENSSL_cpuid_setup (
>> + void
>> + )
>> +{
>> + OPENSSL_armcap_P = 0;
>> +
>> + /* Access to EL0 registers is possible from higher ELx. */
>> + OPENSSL_armcap_P |= ARMV8_CPUID;
>> + /* Access to Physical timer is possible. */
>> + OPENSSL_armcap_P |= ARMV7_TICK;
>> +
>> + /* Neon support is not guaranteed, but it is assumed to be present.
>> + Arm ARM for Armv8, sA1.5 Advanced SIMD and floating-point support
>> + */
>> + OPENSSL_armcap_P |= ARMV7_NEON;
>> +
>> + if (ArmHasAes ())
>> + {
>
> And I think that curly bracket is supposed to be on the previous line
> (and similarly below), but this may be intional to align with nearby
> code?
I think it was changed by uncrustify. I changed it back.
Thanks for the review,
Regards,
Pierre
>
> Anyway, this is a big readability improvement, thank you very much!
> Acked-by: Leif Lindholm <quic_llindhol@quicinc.com>
>
> /
> Leif
>
>> + OPENSSL_armcap_P |= ARMV8_AES;
>> + }
>> +
>> + if (ArmHasSha1 ())
>> + {
>> + OPENSSL_armcap_P |= ARMV8_SHA1;
>> + }
>> +
>> + if (ArmHasSha256 ())
>> + {
>> + OPENSSL_armcap_P |= ARMV8_SHA256;
>> + }
>> +
>> + if (ArmHasPmull ())
>> + {
>> + OPENSSL_armcap_P |= ARMV8_PMULL;
>> + }
>> +
>> + if (ArmHasSha512 ())
>> + {
>> + OPENSSL_armcap_P |= ARMV8_SHA512;
>> + }
>> +}
>> +
>> +/** Read system counter value.
>> +
>> + Used to get some non-trusted entropy.
>> +
>> + @return Lower bits of the physical counter.
>> +**/
>> +uint32_t
>> +OPENSSL_rdtsc (
>> + void
>> + )
>> +{
>> + return (UINT32)ArmReadCntPct ();
>> +}
>> --
>> 2.25.1
>>
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end of thread, other threads:[~2023-11-21 8:49 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-11-20 13:48 [edk2-devel] [PATCH v4 0/6] CryptoPkg: Enable Openssl native instruction support for AARCH64 PierreGondois
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 1/6] ArmPkg/ArmLib: Add macros/helper functions around AA64Isar0 register PierreGondois
2023-11-20 18:27 ` Leif Lindholm
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 2/6] CryptoPkg/CryptoPkg.ci.yaml: Allow dependency upon ArmPkg PierreGondois
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 3/6] CryptoPkg/OpensslLib: Add native instruction support for AARCH64 PierreGondois
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 4/6] CryptoPkg/OpensslLib: Generate files for AARCH64 native support PierreGondois
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 5/6] CryptoPkg/OpensslLib: Add AArch64Cap for arch specific hooks PierreGondois
2023-11-20 18:39 ` Leif Lindholm
2023-11-21 8:49 ` PierreGondois
2023-11-20 13:48 ` [edk2-devel] [PATCH v4 6/6] CryptoPkg: Enable Openssl Accel builds for AARCH64 PierreGondois
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