From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 7EB63941B43 for ; Mon, 20 Nov 2023 18:48:07 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=Y4UPVGMVTD5UpCtMxu68yJKAFKeIloOc3aowKdm6ihw=; c=relaxed/simple; d=groups.io; h=Date:From:To:CC:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20140610; t=1700506086; v=1; b=Kg0rK98aPIN1fb5SHBwcqZoFDEWW/kMrTc7OEXdaSiN/x4MMcdRKlQB/3477+SgM4u+/2MFS i73bMZONudAmbtdw6YxAdbgEZrHSPPZCgvACF3fAUnE9IlQdkq++zXgKb+k6g/VLYx1vH1G5kv/ y0R4oC4Fb5diGjKmOWg+Rm8g= X-Received: by 127.0.0.2 with SMTP id wnSCYY7687511xgJrtTyNQ1U; Mon, 20 Nov 2023 10:48:06 -0800 X-Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by mx.groups.io with SMTP id smtpd.web10.9580.1700506085730947158 for ; Mon, 20 Nov 2023 10:48:05 -0800 X-Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AKHGKQZ011732; Mon, 20 Nov 2023 18:48:02 GMT X-Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ug53719he-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 20 Nov 2023 18:48:01 +0000 X-Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AKIm1Pj014550 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 20 Nov 2023 18:48:01 GMT X-Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 20 Nov 2023 10:47:59 -0800 Date: Mon, 20 Nov 2023 18:47:55 +0000 From: "Leif Lindholm" To: Chao Li CC: , Ard Biesheuvel , Sami Mujawar Subject: Re: [edk2-devel] [PATCH v3 22/39] ArmPkg: Remove ArmPciCpuIo2Dxe from ArmPkg Message-ID: References: <20231117095742.3605778-1-lichao@loongs> <20231117100139.3609937-1-lichao@loongson.cn> MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-ORIG-GUID: ujdlYllFFIZyBE5n0LtYiGDcWOLmIRbt X-Proofpoint-GUID: ujdlYllFFIZyBE5n0LtYiGDcWOLmIRbt Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,quic_llindhol@quicinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: HvSQwNxQcD88y13B2gberPFpx7686176AA= Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=Kg0rK98a; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=quicinc.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Hi Chao, Yes, correct. So we can update the existing users of this driver in edk2-platforms before deleting it. Regards, Leif On Mon, Nov 20, 2023 at 11:24:03 +0800, Chao Li wrote: > Hi Leif, > > Do you mean that CpuIo2Dxe adds MMIO method first, then waits for this patch > series to be merged, and finally makes a new BZ and remove the ARM version? > > > Thanks, > Chao > On 2023/11/17 21:13, Leif Lindholm wrote: > > On Fri, Nov 17, 2023 at 18:01:39 +0800, Chao Li wrote: > > > ArmPciCpuIo2Dxe has been merged into CpuIo2Dxe, and CpuIo2Dxe is already > > > used by all ARM virtual platforms, so remove it. > > This does affect 15 platforms in edk2-platforms. > > You should ping the maintainers of the affected platforms, or even > > better write a patch yourself, so we don't end up with sudden > > mass-breakage. > > > > It might be worth splitting this patch out of the rest of the set in > > order to permit a more graceful switchover. > > > > / > > Leif > > > > > BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=4584 > > > > > > Cc: Leif Lindholm > > > Cc: Ard Biesheuvel > > > Cc: Sami Mujawar > > > --- > > > ArmPkg/ArmPkg.dsc | 1 - > > > .../Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c | 556 ------------------ > > > .../ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf | 47 -- > > > 3 files changed, 604 deletions(-) > > > delete mode 100644 ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c > > > delete mode 100644 ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf > > > > > > diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc > > > index 6dd91e6941..7af25a91a1 100644 > > > --- a/ArmPkg/ArmPkg.dsc > > > +++ b/ArmPkg/ArmPkg.dsc > > > @@ -143,7 +143,6 @@ > > > ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf > > > - ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf > > > ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf > > > ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf > > > ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf > > > diff --git a/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c b/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c > > > deleted file mode 100644 > > > index 5a2866ccd8..0000000000 > > > --- a/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c > > > +++ /dev/null > > > @@ -1,556 +0,0 @@ > > > -/** @file > > > - Produces the CPU I/O 2 Protocol. > > > - > > > -Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
> > > -Copyright (c) 2016, Linaro Ltd. All rights reserved.
> > > - > > > -SPDX-License-Identifier: BSD-2-Clause-Patent > > > - > > > -**/ > > > - > > > -#include > > > - > > > -#include > > > - > > > -#include > > > -#include > > > -#include > > > -#include > > > -#include > > > - > > > -#define MAX_IO_PORT_ADDRESS 0xFFFF > > > - > > > -// > > > -// Handle for the CPU I/O 2 Protocol > > > -// > > > -STATIC EFI_HANDLE mHandle = NULL; > > > - > > > -// > > > -// Lookup table for increment values based on transfer widths > > > -// > > > -STATIC CONST UINT8 mInStride[] = { > > > - 1, // EfiCpuIoWidthUint8 > > > - 2, // EfiCpuIoWidthUint16 > > > - 4, // EfiCpuIoWidthUint32 > > > - 8, // EfiCpuIoWidthUint64 > > > - 0, // EfiCpuIoWidthFifoUint8 > > > - 0, // EfiCpuIoWidthFifoUint16 > > > - 0, // EfiCpuIoWidthFifoUint32 > > > - 0, // EfiCpuIoWidthFifoUint64 > > > - 1, // EfiCpuIoWidthFillUint8 > > > - 2, // EfiCpuIoWidthFillUint16 > > > - 4, // EfiCpuIoWidthFillUint32 > > > - 8 // EfiCpuIoWidthFillUint64 > > > -}; > > > - > > > -// > > > -// Lookup table for increment values based on transfer widths > > > -// > > > -STATIC CONST UINT8 mOutStride[] = { > > > - 1, // EfiCpuIoWidthUint8 > > > - 2, // EfiCpuIoWidthUint16 > > > - 4, // EfiCpuIoWidthUint32 > > > - 8, // EfiCpuIoWidthUint64 > > > - 1, // EfiCpuIoWidthFifoUint8 > > > - 2, // EfiCpuIoWidthFifoUint16 > > > - 4, // EfiCpuIoWidthFifoUint32 > > > - 8, // EfiCpuIoWidthFifoUint64 > > > - 0, // EfiCpuIoWidthFillUint8 > > > - 0, // EfiCpuIoWidthFillUint16 > > > - 0, // EfiCpuIoWidthFillUint32 > > > - 0 // EfiCpuIoWidthFillUint64 > > > -}; > > > - > > > -/** > > > - Check parameters to a CPU I/O 2 Protocol service request. > > > - > > > - The I/O operations are carried out exactly as requested. The caller is responsible > > > - for satisfying any alignment and I/O width restrictions that a PI System on a > > > - platform might require. For example on some platforms, width requests of > > > - EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will > > > - be handled by the driver. > > > - > > > - @param[in] MmioOperation TRUE for an MMIO operation, FALSE for I/O Port operation. > > > - @param[in] Width Signifies the width of the I/O or Memory operation. > > > - @param[in] Address The base address of the I/O operation. > > > - @param[in] Count The number of I/O operations to perform. The number of > > > - bytes moved is Width size * Count, starting at Address. > > > - @param[in] Buffer For read operations, the destination buffer to store the results. > > > - For write operations, the source buffer from which to write data. > > > - > > > - @retval EFI_SUCCESS The parameters for this request pass the checks. > > > - @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. > > > - @retval EFI_INVALID_PARAMETER Buffer is NULL. > > > - @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width. > > > - @retval EFI_UNSUPPORTED The address range specified by Address, Width, > > > - and Count is not valid for this PI system. > > > - > > > -**/ > > > -STATIC > > > -EFI_STATUS > > > -CpuIoCheckParameter ( > > > - IN BOOLEAN MmioOperation, > > > - IN EFI_CPU_IO_PROTOCOL_WIDTH Width, > > > - IN UINT64 Address, > > > - IN UINTN Count, > > > - IN VOID *Buffer > > > - ) > > > -{ > > > - UINT64 MaxCount; > > > - UINT64 Limit; > > > - > > > - // > > > - // Check to see if Buffer is NULL > > > - // > > > - if (Buffer == NULL) { > > > - return EFI_INVALID_PARAMETER; > > > - } > > > - > > > - // > > > - // Check to see if Width is in the valid range > > > - // > > > - if ((UINT32)Width >= EfiCpuIoWidthMaximum) { > > > - return EFI_INVALID_PARAMETER; > > > - } > > > - > > > - // > > > - // For FIFO type, the target address won't increase during the access, > > > - // so treat Count as 1 > > > - // > > > - if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64)) { > > > - Count = 1; > > > - } > > > - > > > - // > > > - // Check to see if Width is in the valid range for I/O Port operations > > > - // > > > - Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); > > > - if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) { > > > - return EFI_INVALID_PARAMETER; > > > - } > > > - > > > - // > > > - // Check to see if Address is aligned > > > - // > > > - if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) { > > > - return EFI_UNSUPPORTED; > > > - } > > > - > > > - // > > > - // Check to see if any address associated with this transfer exceeds the maximum > > > - // allowed address. The maximum address implied by the parameters passed in is > > > - // Address + Size * Count. If the following condition is met, then the transfer > > > - // is not supported. > > > - // > > > - // Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1 > > > - // > > > - // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count > > > - // can also be the maximum integer value supported by the CPU, this range > > > - // check must be adjusted to avoid all overflow conditions. > > > - // > > > - // The following form of the range check is equivalent but assumes that > > > - // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1). > > > - // > > > - Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS); > > > - if (Count == 0) { > > > - if (Address > Limit) { > > > - return EFI_UNSUPPORTED; > > > - } > > > - } else { > > > - MaxCount = RShiftU64 (Limit, Width); > > > - if (MaxCount < (Count - 1)) { > > > - return EFI_UNSUPPORTED; > > > - } > > > - > > > - if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { > > > - return EFI_UNSUPPORTED; > > > - } > > > - } > > > - > > > - // > > > - // Check to see if Buffer is aligned > > > - // > > > - if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width]) - 1))) != 0) { > > > - return EFI_UNSUPPORTED; > > > - } > > > - > > > - return EFI_SUCCESS; > > > -} > > > - > > > -/** > > > - Reads memory-mapped registers. > > > - > > > - The I/O operations are carried out exactly as requested. The caller is responsible > > > - for satisfying any alignment and I/O width restrictions that a PI System on a > > > - platform might require. For example on some platforms, width requests of > > > - EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will > > > - be handled by the driver. > > > - > > > - If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, > > > - or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for > > > - each of the Count operations that is performed. > > > - > > > - If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, > > > - EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is > > > - incremented for each of the Count operations that is performed. The read or > > > - write operation is performed Count times on the same Address. > > > - > > > - If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, > > > - EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is > > > - incremented for each of the Count operations that is performed. The read or > > > - write operation is performed Count times from the first element of Buffer. > > > - > > > - @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. > > > - @param[in] Width Signifies the width of the I/O or Memory operation. > > > - @param[in] Address The base address of the I/O operation. > > > - @param[in] Count The number of I/O operations to perform. The number of > > > - bytes moved is Width size * Count, starting at Address. > > > - @param[out] Buffer For read operations, the destination buffer to store the results. > > > - For write operations, the source buffer from which to write data. > > > - > > > - @retval EFI_SUCCESS The data was read from or written to the PI system. > > > - @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. > > > - @retval EFI_INVALID_PARAMETER Buffer is NULL. > > > - @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width. > > > - @retval EFI_UNSUPPORTED The address range specified by Address, Width, > > > - and Count is not valid for this PI system. > > > - > > > -**/ > > > -STATIC > > > -EFI_STATUS > > > -EFIAPI > > > -CpuMemoryServiceRead ( > > > - IN EFI_CPU_IO2_PROTOCOL *This, > > > - IN EFI_CPU_IO_PROTOCOL_WIDTH Width, > > > - IN UINT64 Address, > > > - IN UINTN Count, > > > - OUT VOID *Buffer > > > - ) > > > -{ > > > - EFI_STATUS Status; > > > - UINT8 InStride; > > > - UINT8 OutStride; > > > - EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; > > > - UINT8 *Uint8Buffer; > > > - > > > - Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer); > > > - if (EFI_ERROR (Status)) { > > > - return Status; > > > - } > > > - > > > - // > > > - // Select loop based on the width of the transfer > > > - // > > > - InStride = mInStride[Width]; > > > - OutStride = mOutStride[Width]; > > > - OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); > > > - for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { > > > - if (OperationWidth == EfiCpuIoWidthUint8) { > > > - *Uint8Buffer = MmioRead8 ((UINTN)Address); > > > - } else if (OperationWidth == EfiCpuIoWidthUint16) { > > > - *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address); > > > - } else if (OperationWidth == EfiCpuIoWidthUint32) { > > > - *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address); > > > - } else if (OperationWidth == EfiCpuIoWidthUint64) { > > > - *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address); > > > - } > > > - } > > > - > > > - return EFI_SUCCESS; > > > -} > > > - > > > -/** > > > - Writes memory-mapped registers. > > > - > > > - The I/O operations are carried out exactly as requested. The caller is responsible > > > - for satisfying any alignment and I/O width restrictions that a PI System on a > > > - platform might require. For example on some platforms, width requests of > > > - EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will > > > - be handled by the driver. > > > - > > > - If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, > > > - or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for > > > - each of the Count operations that is performed. > > > - > > > - If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, > > > - EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is > > > - incremented for each of the Count operations that is performed. The read or > > > - write operation is performed Count times on the same Address. > > > - > > > - If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, > > > - EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is > > > - incremented for each of the Count operations that is performed. The read or > > > - write operation is performed Count times from the first element of Buffer. > > > - > > > - @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. > > > - @param[in] Width Signifies the width of the I/O or Memory operation. > > > - @param[in] Address The base address of the I/O operation. > > > - @param[in] Count The number of I/O operations to perform. The number of > > > - bytes moved is Width size * Count, starting at Address. > > > - @param[in] Buffer For read operations, the destination buffer to store the results. > > > - For write operations, the source buffer from which to write data. > > > - > > > - @retval EFI_SUCCESS The data was read from or written to the PI system. > > > - @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. > > > - @retval EFI_INVALID_PARAMETER Buffer is NULL. > > > - @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width. > > > - @retval EFI_UNSUPPORTED The address range specified by Address, Width, > > > - and Count is not valid for this PI system. > > > - > > > -**/ > > > -STATIC > > > -EFI_STATUS > > > -EFIAPI > > > -CpuMemoryServiceWrite ( > > > - IN EFI_CPU_IO2_PROTOCOL *This, > > > - IN EFI_CPU_IO_PROTOCOL_WIDTH Width, > > > - IN UINT64 Address, > > > - IN UINTN Count, > > > - IN VOID *Buffer > > > - ) > > > -{ > > > - EFI_STATUS Status; > > > - UINT8 InStride; > > > - UINT8 OutStride; > > > - EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; > > > - UINT8 *Uint8Buffer; > > > - > > > - Status = CpuIoCheckParameter (TRUE, Width, Address, Count, Buffer); > > > - if (EFI_ERROR (Status)) { > > > - return Status; > > > - } > > > - > > > - // > > > - // Select loop based on the width of the transfer > > > - // > > > - InStride = mInStride[Width]; > > > - OutStride = mOutStride[Width]; > > > - OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); > > > - for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { > > > - if (OperationWidth == EfiCpuIoWidthUint8) { > > > - MmioWrite8 ((UINTN)Address, *Uint8Buffer); > > > - } else if (OperationWidth == EfiCpuIoWidthUint16) { > > > - MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); > > > - } else if (OperationWidth == EfiCpuIoWidthUint32) { > > > - MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); > > > - } else if (OperationWidth == EfiCpuIoWidthUint64) { > > > - MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); > > > - } > > > - } > > > - > > > - return EFI_SUCCESS; > > > -} > > > - > > > -/** > > > - Reads I/O registers. > > > - > > > - The I/O operations are carried out exactly as requested. The caller is responsible > > > - for satisfying any alignment and I/O width restrictions that a PI System on a > > > - platform might require. For example on some platforms, width requests of > > > - EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will > > > - be handled by the driver. > > > - > > > - If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, > > > - or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for > > > - each of the Count operations that is performed. > > > - > > > - If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, > > > - EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is > > > - incremented for each of the Count operations that is performed. The read or > > > - write operation is performed Count times on the same Address. > > > - > > > - If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, > > > - EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is > > > - incremented for each of the Count operations that is performed. The read or > > > - write operation is performed Count times from the first element of Buffer. > > > - > > > - @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. > > > - @param[in] Width Signifies the width of the I/O or Memory operation. > > > - @param[in] Address The base address of the I/O operation. > > > - @param[in] Count The number of I/O operations to perform. The number of > > > - bytes moved is Width size * Count, starting at Address. > > > - @param[out] Buffer For read operations, the destination buffer to store the results. > > > - For write operations, the source buffer from which to write data. > > > - > > > - @retval EFI_SUCCESS The data was read from or written to the PI system. > > > - @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. > > > - @retval EFI_INVALID_PARAMETER Buffer is NULL. > > > - @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width. > > > - @retval EFI_UNSUPPORTED The address range specified by Address, Width, > > > - and Count is not valid for this PI system. > > > - > > > -**/ > > > -STATIC > > > -EFI_STATUS > > > -EFIAPI > > > -CpuIoServiceRead ( > > > - IN EFI_CPU_IO2_PROTOCOL *This, > > > - IN EFI_CPU_IO_PROTOCOL_WIDTH Width, > > > - IN UINT64 Address, > > > - IN UINTN Count, > > > - OUT VOID *Buffer > > > - ) > > > -{ > > > - EFI_STATUS Status; > > > - UINT8 InStride; > > > - UINT8 OutStride; > > > - EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; > > > - UINT8 *Uint8Buffer; > > > - > > > - Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer); > > > - if (EFI_ERROR (Status)) { > > > - return Status; > > > - } > > > - > > > - Address += PcdGet64 (PcdPciIoTranslation); > > > - > > > - // > > > - // Select loop based on the width of the transfer > > > - // > > > - InStride = mInStride[Width]; > > > - OutStride = mOutStride[Width]; > > > - OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); > > > - > > > - for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { > > > - if (OperationWidth == EfiCpuIoWidthUint8) { > > > - *Uint8Buffer = MmioRead8 ((UINTN)Address); > > > - } else if (OperationWidth == EfiCpuIoWidthUint16) { > > > - *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address); > > > - } else if (OperationWidth == EfiCpuIoWidthUint32) { > > > - *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address); > > > - } > > > - } > > > - > > > - return EFI_SUCCESS; > > > -} > > > - > > > -/** > > > - Write I/O registers. > > > - > > > - The I/O operations are carried out exactly as requested. The caller is responsible > > > - for satisfying any alignment and I/O width restrictions that a PI System on a > > > - platform might require. For example on some platforms, width requests of > > > - EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will > > > - be handled by the driver. > > > - > > > - If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, > > > - or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for > > > - each of the Count operations that is performed. > > > - > > > - If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, > > > - EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is > > > - incremented for each of the Count operations that is performed. The read or > > > - write operation is performed Count times on the same Address. > > > - > > > - If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, > > > - EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is > > > - incremented for each of the Count operations that is performed. The read or > > > - write operation is performed Count times from the first element of Buffer. > > > - > > > - @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance. > > > - @param[in] Width Signifies the width of the I/O or Memory operation. > > > - @param[in] Address The base address of the I/O operation. > > > - @param[in] Count The number of I/O operations to perform. The number of > > > - bytes moved is Width size * Count, starting at Address. > > > - @param[in] Buffer For read operations, the destination buffer to store the results. > > > - For write operations, the source buffer from which to write data. > > > - > > > - @retval EFI_SUCCESS The data was read from or written to the PI system. > > > - @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. > > > - @retval EFI_INVALID_PARAMETER Buffer is NULL. > > > - @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width. > > > - @retval EFI_UNSUPPORTED The address range specified by Address, Width, > > > - and Count is not valid for this PI system. > > > - > > > -**/ > > > -STATIC > > > -EFI_STATUS > > > -EFIAPI > > > -CpuIoServiceWrite ( > > > - IN EFI_CPU_IO2_PROTOCOL *This, > > > - IN EFI_CPU_IO_PROTOCOL_WIDTH Width, > > > - IN UINT64 Address, > > > - IN UINTN Count, > > > - IN VOID *Buffer > > > - ) > > > -{ > > > - EFI_STATUS Status; > > > - UINT8 InStride; > > > - UINT8 OutStride; > > > - EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; > > > - UINT8 *Uint8Buffer; > > > - > > > - // > > > - // Make sure the parameters are valid > > > - // > > > - Status = CpuIoCheckParameter (FALSE, Width, Address, Count, Buffer); > > > - if (EFI_ERROR (Status)) { > > > - return Status; > > > - } > > > - > > > - Address += PcdGet64 (PcdPciIoTranslation); > > > - > > > - // > > > - // Select loop based on the width of the transfer > > > - // > > > - InStride = mInStride[Width]; > > > - OutStride = mOutStride[Width]; > > > - OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03); > > > - > > > - for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) { > > > - if (OperationWidth == EfiCpuIoWidthUint8) { > > > - MmioWrite8 ((UINTN)Address, *Uint8Buffer); > > > - } else if (OperationWidth == EfiCpuIoWidthUint16) { > > > - MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); > > > - } else if (OperationWidth == EfiCpuIoWidthUint32) { > > > - MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); > > > - } > > > - } > > > - > > > - return EFI_SUCCESS; > > > -} > > > - > > > -// > > > -// CPU I/O 2 Protocol instance > > > -// > > > -STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = { > > > - { > > > - CpuMemoryServiceRead, > > > - CpuMemoryServiceWrite > > > - }, > > > - { > > > - CpuIoServiceRead, > > > - CpuIoServiceWrite > > > - } > > > -}; > > > - > > > -/** > > > - The user Entry Point for module CpuIo2Dxe. The user code starts with this function. > > > - > > > - @param[in] ImageHandle The firmware allocated handle for the EFI image. > > > - @param[in] SystemTable A pointer to the EFI System Table. > > > - > > > - @retval EFI_SUCCESS The entry point is executed successfully. > > > - @retval other Some error occurs when executing this entry point. > > > - > > > -**/ > > > -EFI_STATUS > > > -EFIAPI > > > -ArmPciCpuIo2Initialize ( > > > - IN EFI_HANDLE ImageHandle, > > > - IN EFI_SYSTEM_TABLE *SystemTable > > > - ) > > > -{ > > > - EFI_STATUS Status; > > > - > > > - ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid); > > > - Status = gBS->InstallMultipleProtocolInterfaces ( > > > - &mHandle, > > > - &gEfiCpuIo2ProtocolGuid, > > > - &mCpuIo2, > > > - NULL > > > - ); > > > - ASSERT_EFI_ERROR (Status); > > > - > > > - return Status; > > > -} > > > diff --git a/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf b/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf > > > deleted file mode 100644 > > > index 9339c2b532..0000000000 > > > --- a/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf > > > +++ /dev/null > > > @@ -1,47 +0,0 @@ > > > -## @file > > > -# Produces the CPU I/O 2 Protocol by using the services of the I/O Library. > > > -# > > > -# Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.
> > > -# Copyright (c) 2016, Linaro Ltd. All rights reserved.
> > > -# > > > -# SPDX-License-Identifier: BSD-2-Clause-Patent > > > -# > > > -## > > > - > > > -[Defines] > > > - INF_VERSION = 0x00010005 > > > - BASE_NAME = ArmPciCpuIo2Dxe > > > - FILE_GUID = 168D1A6E-F4A5-448A-9E95-795661BB3067 > > > - MODULE_TYPE = DXE_DRIVER > > > - VERSION_STRING = 1.0 > > > - ENTRY_POINT = ArmPciCpuIo2Initialize > > > - > > > -# > > > -# The following information is for reference only and not required by the build tools. > > > -# > > > -# VALID_ARCHITECTURES = ARM AARCH64 > > > -# > > > - > > > -[Sources] > > > - ArmPciCpuIo2Dxe.c > > > - > > > -[Packages] > > > - ArmPkg/ArmPkg.dec > > > - MdePkg/MdePkg.dec > > > - > > > -[LibraryClasses] > > > - UefiDriverEntryPoint > > > - BaseLib > > > - DebugLib > > > - IoLib > > > - PcdLib > > > - UefiBootServicesTableLib > > > - > > > -[Pcd] > > > - gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation > > > - > > > -[Protocols] > > > - gEfiCpuIo2ProtocolGuid ## PRODUCES > > > - > > > -[Depex] > > > - TRUE > > > -- > > > 2.27.0 > > > > > > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#111487): https://edk2.groups.io/g/devel/message/111487 Mute This Topic: https://groups.io/mt/102644788/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/12367111/7686176/1913456212/xyzzy [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-