Re: [edk2-devel] [PATCH v2 0/4] RISC-V: Add support for Sstc extension

["Sunil V L" <sunilvl@ventanamicro.com>]

On Mon, Jan 08, 2024 at 05:06:46PM +0530, Sunil V L wrote:
> This series adds the support for RISC-V Sstc extension in EDK2 timer
> implementation. Sstc extension allows S-mode software to program the
> timer directly without using SBI calls.
> 
> Currently, PCD variable is used to detect whether feature is enabled. By
> default the feature is enabled and platforms need to set the PCD to
> disable the feature if Sstc is not supported.
> 
> For RiscVVirtQemu, it is disabled by default (until extension discovery
> feature is enabled).
> 
> Changes since v1:
> 	1) Updated "PATCH 3" to address Laszlo's comments.
> 	2) Updated RB tag for PATCH 4.
> 
> Cc: Andrei Warkentin <andrei.warkentin@intel.com>
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> 
Thank you very much for reviews!. Merged as #5232.

Thanks,
Sunil


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