From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 5831594194A for ; Thu, 4 Jan 2024 15:01:45 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=+Ob1BFKPcc+sT3zWOrgLYhffiB4eqLrNKRnxosaEAF4=; c=relaxed/simple; d=groups.io; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20140610; t=1704380504; v=1; b=Xl20JJuSu/+wmqmUZoRzWTDvRED1cehhd7jJG9sNINTShyLOFQLyAsbWgseAeZm2FDjP/qK9 RAOwZHZzGVTOaoqL4B8RHviN8LDzAcpJbRaVDjQIMWGfeg/bP56LKcrWf+gXNuw3LRCD1bkKgZC Dtt43wXbs44wasYMHud229bY= X-Received: by 127.0.0.2 with SMTP id gN8qYY7687511xNb2j4SIuVs; Thu, 04 Jan 2024 07:01:44 -0800 X-Received: from mail-io1-f54.google.com (mail-io1-f54.google.com [209.85.166.54]) by mx.groups.io with SMTP id smtpd.web10.55942.1704380503311013947 for ; Thu, 04 Jan 2024 07:01:43 -0800 X-Received: by mail-io1-f54.google.com with SMTP id ca18e2360f4ac-7bbbe7b1b36so29131239f.1 for ; Thu, 04 Jan 2024 07:01:43 -0800 (PST) X-Gm-Message-State: EtnfpAvhuABC89LjRXSr0Kn4x7686176AA= X-Google-Smtp-Source: AGHT+IGA2i4uaT8fE0TVoUzDiIe2hx3DYvFKFTNzpGrxocmHKd5Uytl9OrTJCLAr7ZpZ0ZQJbfMGtQ== X-Received: by 2002:a6b:7701:0:b0:7ba:dd12:ce01 with SMTP id n1-20020a6b7701000000b007badd12ce01mr712758iom.13.1704380502342; Thu, 04 Jan 2024 07:01:42 -0800 (PST) X-Received: from sunil-laptop ([106.51.188.200]) by smtp.gmail.com with ESMTPSA id y25-20020a02a399000000b0046cf2de8c74sm7589233jak.18.2024.01.04.07.01.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 07:01:42 -0800 (PST) Date: Thu, 4 Jan 2024 20:31:34 +0530 From: "Sunil V L" To: Laszlo Ersek Cc: devel@edk2.groups.io, Gerd Hoffmann , Rahul Kumar , Ray Ni , Andrei Warkentin Subject: Re: [edk2-devel] [PATCH 3/4] UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc Message-ID: References: <20240103135849.127251-1-sunilvl@ventanamicro.com> <20240103135849.127251-4-sunilvl@ventanamicro.com> MIME-Version: 1.0 In-Reply-To: Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=Xl20JJuS; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io Hi Laszlo, Thank you very much for the review!. On Thu, Jan 04, 2024 at 03:38:17PM +0100, Laszlo Ersek wrote: > On 1/3/24 14:58, Sunil V L wrote: > > Sstc extension allows to program the timer and receive the interrupt > > without using an SBI call. This reduces the latency to generate the timer > > interrupt. So, detect whether Sstc extension is supported and use the > > stimecmp register directly to program the timer interrupt. > > > > Cc: Gerd Hoffmann > > Cc: Rahul Kumar > > Cc: Laszlo Ersek > > Cc: Ray Ni > > Cc: Andrei Warkentin > > Signed-off-by: Sunil V L > > --- > > .../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 1 + > > UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h | 2 ++ > > UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 30 +++++++++++++++++-- > > 3 files changed, 31 insertions(+), 2 deletions(-) > > > > diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf > > index aba660186dc0..f2a2cf12caef 100644 > > --- a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf > > +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf > > @@ -41,6 +41,7 @@ [Sources.RISCV64] > > Timer.c > > > > [Pcd] > > + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES > > gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## CONSUMES > > > > [Protocols] > > diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h > > index 9b3542230cb5..5e5071b3f0b2 100644 > > --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h > > +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h > > @@ -26,6 +26,8 @@ > > // > > #define DEFAULT_TIMER_TICK_DURATION 100000 > > > > +#define RISCV_CPU_FEATURE_SSTC_BITMASK 0x2 > > (1) Not a bug by any means, but BIT1 might read more idiomatic. > Agree. Would RISCV_CPU_FEATURE_BIT1_SSTC be better? > > + > > extern VOID > > RiscvSetTimerPeriod ( > > UINT32 TimerPeriod > > diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c > > index 30e48061cd06..4babfb4bfc60 100644 > > --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c > > +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c > > @@ -44,6 +44,19 @@ STATIC EFI_TIMER_NOTIFY mTimerNotifyFunction; > > STATIC UINT64 mTimerPeriod = 0; > > STATIC UINT64 mLastPeriodStart = 0; > > > > +/** > > + Check whether Sstc is enabled in PCD. > > + > > +**/ > > +STATIC > > +BOOLEAN > > +RiscVIsSstcEnabled ( > > + VOID > > + ) > > +{ > > + return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_SSTC_BITMASK) != 0); > > +} > > + > > /** > > Timer Interrupt Handler. > > > > @@ -94,7 +107,12 @@ TimerInterruptHandler ( > > ), > > 1000000u > > ); // convert to tick > > - SbiSetTimer (PeriodStart); > > + if (RiscVIsSstcEnabled ()) { > > (2) Even though the PCD is currently declared as fixed or > patchable-in-module, seeing a PcdGet64() call on the call stack of the > timer interrupt handler (and at a high TPL) makes me uncomfortable. It > carries a risk that later on we relax the PCD decl to dynamic, and then > this code would become brittle. > > I propose: either replace the PcdGet64 call above with FixedPcdGet64 (so > it can never land in the runtime / dynamic PCD protocol), or perform the > PCD check in the entry point function of the driver, and store the > result in a STATIC BOOLEAN variable. Then further PCD accesses (dynamic > or otherwise) will not be needed. > Ahh yes. Good point. Let me use a static variable as you suggested. > > + RiscVSetSupervisorTimeCompareRegister (PeriodStart); > > + } else { > > + SbiSetTimer (PeriodStart); > > + } > > + > > RiscVEnableTimerInterrupt (); // enable SMode timer int > > gBS->RestoreTPL (OriginalTPL); > > } > > @@ -197,7 +215,11 @@ TimerDriverSetTimerPeriod ( > > ), > > 1000000u > > ); // convert to tick > > - SbiSetTimer (PeriodStart); > > + if (RiscVIsSstcEnabled ()) { > > + RiscVSetSupervisorTimeCompareRegister (PeriodStart); > > + } else { > > + SbiSetTimer (PeriodStart); > > + } > > > > mCpu->EnableInterrupt (mCpu); > > RiscVEnableTimerInterrupt (); // enable SMode timer int > > (3) This seems like duplicated code. How about replacing the > RiscVIsSstcEnabled() function with a more substantive function that > incorporates both the feature check *and* the "PeriodStart" setting? > Then you can easily call that function from both TimerInterruptHandler() > and TimerDriverSetTimerPeriod(). > I agree. Let me update in the next version. > > @@ -282,6 +304,10 @@ TimerDriverInitialize ( > > // > > mTimerNotifyFunction = NULL; > > > > + if (RiscVIsSstcEnabled ()) { > > + DEBUG ((DEBUG_INFO, "%a: Timer interrupt is via Sstc extension\n", __func__)); > > + } > > + > > Right, this would be the place to fetch the PCD explicitly and to store > the result (based on bit-masking) into the global boolean. > Yes! Thanks! Sunil -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113181): https://edk2.groups.io/g/devel/message/113181 Mute This Topic: https://groups.io/mt/103501843/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-