From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 264F5AC134E for ; Thu, 4 Jan 2024 15:46:38 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=o2jPkU2cZ+f+8FxxIG1dS2wOLtCTkLGORGcSdHYgeNg=; c=relaxed/simple; d=groups.io; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20140610; t=1704383196; v=1; b=pkg4PJgVQXDzF7veyPyV1n25kznQutqyM49kabGE69cHk2zsDZe5kgmNpaQ7YoQ/FlzrTBQ4 ZlzVnyhyPO3wX0KkRja9mVfBp7KomhAuULFfEWyZsCsVkn97MPg0G3LUt/TdO9jGDUI8skiDs7N Pc+6LYavQj7iaBOzJ3rE5ax4= X-Received: by 127.0.0.2 with SMTP id 8BxPYY7687511xyg8yBYMEW2; Thu, 04 Jan 2024 07:46:36 -0800 X-Received: from mail-io1-f48.google.com (mail-io1-f48.google.com [209.85.166.48]) by mx.groups.io with SMTP id smtpd.web11.57046.1704383196032826130 for ; Thu, 04 Jan 2024 07:46:36 -0800 X-Received: by mail-io1-f48.google.com with SMTP id ca18e2360f4ac-7b7fb34265fso27784039f.3 for ; Thu, 04 Jan 2024 07:46:35 -0800 (PST) X-Gm-Message-State: xCO8PG7NitaBHtjJdjFHuB0Zx7686176AA= X-Google-Smtp-Source: AGHT+IFxUR+a4Zr/cUygZSbNUYYx/JkqhOb7VfCkLcc9malgxp+nX34LlISI4UQEX51ouE+RzF42qQ== X-Received: by 2002:a6b:7941:0:b0:7bb:4bcb:960e with SMTP id j1-20020a6b7941000000b007bb4bcb960emr911468iop.13.1704383195246; Thu, 04 Jan 2024 07:46:35 -0800 (PST) X-Received: from sunil-laptop ([106.51.188.200]) by smtp.gmail.com with ESMTPSA id bs6-20020a056638450600b00466bc0ff9fesm8003707jab.169.2024.01.04.07.46.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Jan 2024 07:46:34 -0800 (PST) Date: Thu, 4 Jan 2024 21:16:25 +0530 From: "Sunil V L" To: Laszlo Ersek Cc: devel@edk2.groups.io, Gerd Hoffmann , Rahul Kumar , Ray Ni , Andrei Warkentin Subject: Re: [edk2-devel] [PATCH 3/4] UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc Message-ID: References: <20240103135849.127251-1-sunilvl@ventanamicro.com> <20240103135849.127251-4-sunilvl@ventanamicro.com> MIME-Version: 1.0 In-Reply-To: Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=pkg4PJgV; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On Thu, Jan 04, 2024 at 03:38:17PM +0100, Laszlo Ersek wrote: > On 1/3/24 14:58, Sunil V L wrote: > > Sstc extension allows to program the timer and receive the interrupt > > without using an SBI call. This reduces the latency to generate the timer > > interrupt. So, detect whether Sstc extension is supported and use the > > stimecmp register directly to program the timer interrupt. > > > > Cc: Gerd Hoffmann > > Cc: Rahul Kumar > > Cc: Laszlo Ersek > > Cc: Ray Ni > > Cc: Andrei Warkentin > > Signed-off-by: Sunil V L > > --- > > .../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 1 + > > UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h | 2 ++ > > UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 30 +++++++++++++++++-- > > 3 files changed, 31 insertions(+), 2 deletions(-) > > > > diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf > > index aba660186dc0..f2a2cf12caef 100644 > > --- a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf > > +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf > > @@ -41,6 +41,7 @@ [Sources.RISCV64] > > Timer.c > > > > [Pcd] > > + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES > > gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## CONSUMES > > > > [Protocols] > > diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h > > index 9b3542230cb5..5e5071b3f0b2 100644 > > --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h > > +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h > > @@ -26,6 +26,8 @@ > > // > > #define DEFAULT_TIMER_TICK_DURATION 100000 > > > > +#define RISCV_CPU_FEATURE_SSTC_BITMASK 0x2 > > (1) Not a bug by any means, but BIT1 might read more idiomatic. > I misunderstood your comment. Will use BIT1 instead of 0x2. Thanks! Sunil -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113184): https://edk2.groups.io/g/devel/message/113184 Mute This Topic: https://groups.io/mt/103501843/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-