* [edk2-devel] [PATCH v1 0/1] Add cache operations support for CPU Arch proto @ 2024-01-29 4:01 Dhaval Sharma 2024-01-29 4:01 ` [edk2-devel] [PATCH v1 1/1] UefiCpuPkg: Add cache operations support for " Dhaval Sharma 0 siblings, 1 reply; 3+ messages in thread From: Dhaval Sharma @ 2024-01-29 4:01 UTC (permalink / raw) To: devel With CMO operations available for RISC-V, utilize them in CPU Architecture protocol. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Gerd Hoffmann <kraxel@redhat.com> Laszlo Ersek <lersek@redhat.com> Rahul Kumar <rahul1.kumar@intel.com> Ray Ni <ray.ni@intel.com> Sunil VL <sunilvl@ventanamicro.com> Andrei Warkentin <andrei.warkentin@intel.com> devel@edk2.groups.io Dhaval (1): UefiCpuPkg: Add cache operations support for Arch proto UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 1 + UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+) -- 2.39.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114672): https://edk2.groups.io/g/devel/message/114672 Mute This Topic: https://groups.io/mt/104025801/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=- ^ permalink raw reply [flat|nested] 3+ messages in thread
* [edk2-devel] [PATCH v1 1/1] UefiCpuPkg: Add cache operations support for Arch proto 2024-01-29 4:01 [edk2-devel] [PATCH v1 0/1] Add cache operations support for CPU Arch proto Dhaval Sharma @ 2024-01-29 4:01 ` Dhaval Sharma 2024-01-30 5:52 ` Sunil V L 0 siblings, 1 reply; 3+ messages in thread From: Dhaval Sharma @ 2024-01-29 4:01 UTC (permalink / raw) To: devel With CMO operations available for RISC-V, utilize them in CPU Architecture protocol. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Gerd Hoffmann <kraxel@redhat.com> Laszlo Ersek <lersek@redhat.com> Rahul Kumar <rahul1.kumar@intel.com> Ray Ni <ray.ni@intel.com> Sunil VL <sunilvl@ventanamicro.com> Andrei Warkentin <andrei.warkentin@intel.com> devel@edk2.groups.io --- UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 1 + UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+) diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h index 68e6d038b66e..d4d67778eb1c 100644 --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h @@ -17,6 +17,7 @@ #include <Library/BaseRiscVSbiLib.h> #include <Library/BaseRiscVMmuLib.h> #include <Library/BaseLib.h> +#include <Library/CacheMaintenanceLib.h> #include <Library/CpuExceptionHandlerLib.h> #include <Library/DebugLib.h> #include <Library/UefiBootServicesTableLib.h> diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c index 2af3b6223450..c6bae100a9e4 100644 --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c @@ -90,6 +90,20 @@ CpuFlushCpuDataCache ( IN EFI_CPU_FLUSH_TYPE FlushType ) { + switch (FlushType) { + case EfiCpuFlushTypeWriteBack: + WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length); + break; + case EfiCpuFlushTypeInvalidate: + InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length); + break; + case EfiCpuFlushTypeWriteBackInvalidate: + WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length); + break; + default: + return EFI_INVALID_PARAMETER; + } + return EFI_SUCCESS; } -- 2.39.2 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114673): https://edk2.groups.io/g/devel/message/114673 Mute This Topic: https://groups.io/mt/104025802/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=- ^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [edk2-devel] [PATCH v1 1/1] UefiCpuPkg: Add cache operations support for Arch proto 2024-01-29 4:01 ` [edk2-devel] [PATCH v1 1/1] UefiCpuPkg: Add cache operations support for " Dhaval Sharma @ 2024-01-30 5:52 ` Sunil V L 0 siblings, 0 replies; 3+ messages in thread From: Sunil V L @ 2024-01-30 5:52 UTC (permalink / raw) To: devel, dhaval Cc: Gerd Hoffmann, Laszlo Ersek, Rahul Kumar, Ray Ni, Sunil VL, Andrei Warkentin Hi Dhaval, Thank you very much for the patch!. On Mon, Jan 29, 2024 at 09:31:16AM +0530, Dhaval Sharma wrote: > With CMO operations available for RISC-V, utilize them in CPU > Architecture protocol. > > Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> > Gerd Hoffmann <kraxel@redhat.com> > Laszlo Ersek <lersek@redhat.com> > Rahul Kumar <rahul1.kumar@intel.com> > Ray Ni <ray.ni@intel.com> > Sunil VL <sunilvl@ventanamicro.com> > Andrei Warkentin <andrei.warkentin@intel.com> > devel@edk2.groups.io You have missed adding "Cc:". Without this tag, they will not be copied explicitly. I am copying them in this reply and I will update the commit message during merge to fix it. > --- > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 1 + > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 14 ++++++++++++++ > 2 files changed, 15 insertions(+) > > diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h > index 68e6d038b66e..d4d67778eb1c 100644 > --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h > +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h > @@ -17,6 +17,7 @@ > #include <Library/BaseRiscVSbiLib.h> > #include <Library/BaseRiscVMmuLib.h> > #include <Library/BaseLib.h> > +#include <Library/CacheMaintenanceLib.h> > #include <Library/CpuExceptionHandlerLib.h> > #include <Library/DebugLib.h> > #include <Library/UefiBootServicesTableLib.h> > diff --git a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c > index 2af3b6223450..c6bae100a9e4 100644 > --- a/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c > +++ b/UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c > @@ -90,6 +90,20 @@ CpuFlushCpuDataCache ( > IN EFI_CPU_FLUSH_TYPE FlushType > ) > { > + switch (FlushType) { > + case EfiCpuFlushTypeWriteBack: > + WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length); > + break; > + case EfiCpuFlushTypeInvalidate: > + InvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length); > + break; > + case EfiCpuFlushTypeWriteBackInvalidate: > + WriteBackInvalidateDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length); > + break; > + default: > + return EFI_INVALID_PARAMETER; > + } > + > return EFI_SUCCESS; > } > Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114760): https://edk2.groups.io/g/devel/message/114760 Mute This Topic: https://groups.io/mt/104025802/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=- ^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2024-01-30 5:52 UTC | newest] Thread overview: 3+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-01-29 4:01 [edk2-devel] [PATCH v1 0/1] Add cache operations support for CPU Arch proto Dhaval Sharma 2024-01-29 4:01 ` [edk2-devel] [PATCH v1 1/1] UefiCpuPkg: Add cache operations support for " Dhaval Sharma 2024-01-30 5:52 ` Sunil V L
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