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From: "Sunil V L" <sunilvl@ventanamicro.com>
To: Tuan Phan <tphan@ventanamicro.com>
Cc: devel@edk2.groups.io, michael.d.kinney@intel.com,
	gaoliming@byosoft.com.cn, zhiguang.liu@intel.com,
	git@danielschaefer.me, andrei.warkentin@intel.com,
	eric.dong@intel.com, kraxel@redhat.com, rahul1.kumar@intel.com,
	ray.ni@intel.com
Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension
Date: Thu, 1 Feb 2024 15:14:57 +0530	[thread overview]
Message-ID: <ZbtoGSGXbxZ9qm24@sunil-laptop> (raw)
In-Reply-To: <20240131010443.28552-1-tphan@ventanamicro.com>

Hi Tuan,

On Tue, Jan 30, 2024 at 05:04:43PM -0800, Tuan Phan wrote:
> The GCD EFI_MEMORY_UC and EFI_MEMORY_WC memory attributes will be
> supported when Svpbmt extension be available.
> 
> Signed-off-by: Tuan Phan <tphan@ventanamicro.com>
> ---
>  MdePkg/MdePkg.dec                             |  2 ++
>  OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc           |  2 +-
>  .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 25 ++++++++++++++++++-
>  .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf       |  1 +
>  4 files changed, 28 insertions(+), 2 deletions(-)
> 
Could you please split this into 3 commits since packages are different
and "Cc:" the relevant maintainers/reviewers? You seem to have old list of
maintainers. Please run BaseTools/Scripts/GetMaintainer.py on each patch
to get latest maintainer list.

Thanks,
Sunil

> diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
> index 0459418906f8..6850acb96b92 100644
> --- a/MdePkg/MdePkg.dec
> +++ b/MdePkg/MdePkg.dec
> @@ -2407,6 +2407,8 @@
>    # previous stage has feature enabled and user wants to disable it.
>    # BIT 1 = Supervisor Time Compare (Sstc). This bit is relevant only if
>    # previous stage has feature enabled and user wants to disable it.
> +  # BIT 2 = Page-Based Memory Types (Pbmt). This bit is relevant only if
> +  # previous stage has feature enabled and user wants to disable it.
>    #
>    gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT64|0x69
>  
> diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> index 6bc7c90f31dc..b8338d2eb5f5 100644
> --- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
> @@ -203,7 +203,7 @@
>    gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
>  
>  [PcdsFixedAtBuild.common]
> -  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFC
> +  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFF8
>    gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
>    gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
>    gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> index 826a1d32a1d4..c50a28e97e4b 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c
> @@ -36,6 +36,15 @@
>  #define PTE_PPN_SHIFT         10
>  #define RISCV_MMU_PAGE_SHIFT  12
>  
> +#define RISCV_CPU_FEATURE_PBMT_BITMASK  BIT2
> +#define PTE_PBMT_NC                     BIT61
> +#define PTE_PBMT_IO                     BIT62
> +#define PTE_PBMT_MASK                   (PTE_PBMT_NC | PTE_PBMT_IO)
> +
> +#define EFI_MEMORY_CACHETYPE_MASK  (EFI_MEMORY_UC | EFI_MEMORY_WC |  \
> +                                     EFI_MEMORY_WT | EFI_MEMORY_WB | \
> +                                     EFI_MEMORY_UCE)
> +
>  STATIC UINTN  mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF };
>  STATIC UINTN  mMaxRootTableLevel;
>  STATIC UINTN  mBitPerLevel;
> @@ -514,6 +523,20 @@ GcdAttributeToPageAttribute (
>      RiscVAttributes &= ~RISCV_PG_X;
>    }
>  
> +  if ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_PBMT_BITMASK) != 0) {
> +    switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) {
> +      case EFI_MEMORY_UC:
> +        RiscVAttributes |= PTE_PBMT_IO;
> +        break;
> +      case EFI_MEMORY_WC:
> +        RiscVAttributes |= PTE_PBMT_NC;
> +        break;
> +      default:
> +        // Default PMA mode
> +        break;
> +    }
> +  }
> +
>    return RiscVAttributes;
>  }
>  
> @@ -559,7 +582,7 @@ RiscVSetMemoryAttributes (
>             BaseAddress,
>             Length,
>             PageAttributesSet,
> -           PTE_ATTRIBUTES_MASK,
> +           PTE_ATTRIBUTES_MASK | PTE_PBMT_MASK,
>             (UINTN *)RiscVGetRootTranslateTable (),
>             TRUE
>             );
> diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> index 51ebe1750e97..1dbaa81f3608 100644
> --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> @@ -28,3 +28,4 @@
>  
>  [Pcd]
>    gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode  ## CONSUMES
> +  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride     ## CONSUMES
> -- 
> 2.25.1
> 


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      reply	other threads:[~2024-02-01  9:45 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-31  1:04 [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension Tuan Phan
2024-02-01  9:44 ` Sunil V L [this message]

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