From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 1ACFAD8065A for ; Thu, 1 Feb 2024 09:45:05 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=CFmKWrK/GEQUVSf8kX+EHYpg53Taxb7ABaoEwSIhF4o=; c=relaxed/simple; d=groups.io; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20140610; t=1706780704; v=1; b=LFb/xuDnyl5DOfYPARAm8qkR9iXKCdCPEN9XHGbI1IOseYRjox0jca/TlIYmSkz0Iwie7IwZ R4EMja+sHHzFgCqxXIL0OAh++dDHo9KRfbmDzlN/oceQXO4ufUHFeugX72tUCXibnN8fDV3SdNq Zm6jsJo5UvoCi1wPxjEWDjfA= X-Received: by 127.0.0.2 with SMTP id 6heiYY7687511xSoskWBYHK1; Thu, 01 Feb 2024 01:45:04 -0800 X-Received: from mail-pl1-f174.google.com (mail-pl1-f174.google.com [209.85.214.174]) by mx.groups.io with SMTP id smtpd.web10.12117.1706780703986960694 for ; Thu, 01 Feb 2024 01:45:04 -0800 X-Received: by mail-pl1-f174.google.com with SMTP id d9443c01a7336-1d70b0e521eso4999865ad.1 for ; Thu, 01 Feb 2024 01:45:03 -0800 (PST) X-Gm-Message-State: p4nj5S6t35Kne0fGb6cscF75x7686176AA= X-Google-Smtp-Source: AGHT+IH1VnKsyHGO4M5XNuJaeTH4fIyhRG5rKlFDoLP9y0w5Uc0oGYvKMg/Sad4OpC8Y1Bvwe1mybw== X-Received: by 2002:a17:902:e541:b0:1d8:f200:6ae2 with SMTP id n1-20020a170902e54100b001d8f2006ae2mr5685411plf.30.1706780703416; Thu, 01 Feb 2024 01:45:03 -0800 (PST) X-Received: from sunil-laptop ([106.51.184.12]) by smtp.gmail.com with ESMTPSA id u12-20020a170902e20c00b001d95ec70db9sm2457plb.287.2024.02.01.01.45.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 01:45:03 -0800 (PST) Date: Thu, 1 Feb 2024 15:14:57 +0530 From: "Sunil V L" To: Tuan Phan Cc: devel@edk2.groups.io, michael.d.kinney@intel.com, gaoliming@byosoft.com.cn, zhiguang.liu@intel.com, git@danielschaefer.me, andrei.warkentin@intel.com, eric.dong@intel.com, kraxel@redhat.com, rahul1.kumar@intel.com, ray.ni@intel.com Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg: RISC-V: MMU: Support Svpbmt extension Message-ID: References: <20240131010443.28552-1-tphan@ventanamicro.com> MIME-Version: 1.0 In-Reply-To: <20240131010443.28552-1-tphan@ventanamicro.com> Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="LFb/xuDn"; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=none Hi Tuan, On Tue, Jan 30, 2024 at 05:04:43PM -0800, Tuan Phan wrote: > The GCD EFI_MEMORY_UC and EFI_MEMORY_WC memory attributes will be > supported when Svpbmt extension be available. > > Signed-off-by: Tuan Phan > --- > MdePkg/MdePkg.dec | 2 ++ > OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 2 +- > .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 25 ++++++++++++++++++- > .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 1 + > 4 files changed, 28 insertions(+), 2 deletions(-) > Could you please split this into 3 commits since packages are different and "Cc:" the relevant maintainers/reviewers? You seem to have old list of maintainers. Please run BaseTools/Scripts/GetMaintainer.py on each patch to get latest maintainer list. Thanks, Sunil > diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec > index 0459418906f8..6850acb96b92 100644 > --- a/MdePkg/MdePkg.dec > +++ b/MdePkg/MdePkg.dec > @@ -2407,6 +2407,8 @@ > # previous stage has feature enabled and user wants to disable it. > # BIT 1 = Supervisor Time Compare (Sstc). This bit is relevant only if > # previous stage has feature enabled and user wants to disable it. > + # BIT 2 = Page-Based Memory Types (Pbmt). This bit is relevant only if > + # previous stage has feature enabled and user wants to disable it. > # > gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFF|UINT64|0x69 > > diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc > index 6bc7c90f31dc..b8338d2eb5f5 100644 > --- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc > +++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc > @@ -203,7 +203,7 @@ > gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE > > [PcdsFixedAtBuild.common] > - gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFC > + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFF8 > gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 > gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 > gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0 > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > index 826a1d32a1d4..c50a28e97e4b 100644 > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > @@ -36,6 +36,15 @@ > #define PTE_PPN_SHIFT 10 > #define RISCV_MMU_PAGE_SHIFT 12 > > +#define RISCV_CPU_FEATURE_PBMT_BITMASK BIT2 > +#define PTE_PBMT_NC BIT61 > +#define PTE_PBMT_IO BIT62 > +#define PTE_PBMT_MASK (PTE_PBMT_NC | PTE_PBMT_IO) > + > +#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \ > + EFI_MEMORY_WT | EFI_MEMORY_WB | \ > + EFI_MEMORY_UCE) > + > STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF }; > STATIC UINTN mMaxRootTableLevel; > STATIC UINTN mBitPerLevel; > @@ -514,6 +523,20 @@ GcdAttributeToPageAttribute ( > RiscVAttributes &= ~RISCV_PG_X; > } > > + if ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_PBMT_BITMASK) != 0) { > + switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) { > + case EFI_MEMORY_UC: > + RiscVAttributes |= PTE_PBMT_IO; > + break; > + case EFI_MEMORY_WC: > + RiscVAttributes |= PTE_PBMT_NC; > + break; > + default: > + // Default PMA mode > + break; > + } > + } > + > return RiscVAttributes; > } > > @@ -559,7 +582,7 @@ RiscVSetMemoryAttributes ( > BaseAddress, > Length, > PageAttributesSet, > - PTE_ATTRIBUTES_MASK, > + PTE_ATTRIBUTES_MASK | PTE_PBMT_MASK, > (UINTN *)RiscVGetRootTranslateTable (), > TRUE > ); > diff --git a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > index 51ebe1750e97..1dbaa81f3608 100644 > --- a/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > +++ b/UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > @@ -28,3 +28,4 @@ > > [Pcd] > gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ## CONSUMES > + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES > -- > 2.25.1 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114941): https://edk2.groups.io/g/devel/message/114941 Mute This Topic: https://groups.io/mt/104066781/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-