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From: "Sunil V L" <sunilvl@ventanamicro.com>
To: devel@edk2.groups.io, wangyang@bosc.ac.cn
Cc: Ran Wang <wangran@bosc.ac.cn>,
	YunFeng Yang <yangyunfeng@bosc.ac.cn>,
	YaXing Guo <guoyaxing@bosc.ac.cn>,
	Bamvor Jian ZHANG <zhangjian@bosc.ac.cn>
Subject: Re: [edk2-devel] [PATCH] NanhuDev:Add BOSC NanhuDev platform
Date: Fri, 08 Mar 2024 03:44:13 -0800	[thread overview]
Message-ID: <Zer6AhIXpJGWZlVP@sunil-laptop> (raw)
In-Reply-To: <5dea3e68.e7.18e1d30121c.Coremail.wangyang@bosc.ac.cn>

On Fri, Mar 08, 2024 at 12:31:26AM -0800, WangYang wrote:
> Hi,Sunil V L
> 
>     How about this status.
> 
> 
> > -----原始邮件-----
> > 发件人: WangYang <wangyang@bosc.ac.cn>
> > 发送时间: 2024-02-28 14:34:11 (星期三)
> > 收件人: devel@edk2.groups.io, sunilvl@ventanamicro.com
> > 抄送: "Yang Wang" <wangyang@bosc.ac.cn>, "Ran Wang" <wangran@bosc.ac.cn>, "YunFeng Yang" <yangyunfeng@bosc.ac.cn>, "YaXing Guo" <guoyaxing@bosc.ac.cn>, "Bamvor Jian ZHANG" <zhangjian@bosc.ac.cn>
> > 主题: [edk2-devel] [PATCH] NanhuDev:Add BOSC NanhuDev platform
> > 
> > This commit adds the initial support for BOSC's
> > nanhu platform which provides up to 2 RISC-V RV64
> > processor cores.
> > 
Somehow I missed this when you sent first. What do you mean by "initial
support" here?

Looks like you are following old integrated opensbi approach.
If so, I recommend you to look at payload design. You can see Sophgo
board as reference.

Also, please remember to CC all maintainers as per Maintainers.txt.

Thanks
Sunil
> 
> > 
> > Signed-off-by: Yang Wang <wangyang@bosc.ac.cn>
> > Signed-off-by: Ran Wang <wangran@bosc.ac.cn>
> > Signed-off-by: YunFeng Yang <yangyunfeng@bosc.ac.cn>
> > Signed-off-by: YaXing Guo <guoyaxing@bosc.ac.cn>
> > Cc: Bamvor Jian ZHANG <zhangjian@bosc.ac.cn>
> > Cc: Sunil V L <sunilvl@ventanamicro.com>
> > ---
> >  .../NanhuDev/DeviceTree.fdf.inc               |  36 ++
> >  .../NanhuDev/DeviceTree/NanhuDev.dts          | 120 ++++
> >  .../NanhuDev/DeviceTree/NanhuDeviceTree.inf   |  22 +
> >  .../XiangshanSeriesPkg/NanhuDev/NanhuDev.dec  |  24 +
> >  .../XiangshanSeriesPkg/NanhuDev/NanhuDev.dsc  | 547 ++++++++++++++++++
> >  .../XiangshanSeriesPkg/NanhuDev/NanhuDev.fdf  | 326 +++++++++++
> >  .../NanhuDev/NanhuDev.fdf.inc                 | 108 ++++
> >  .../XiangshanSeriesPkg/NanhuDev/NanhuDev.uni  |  13 +
> >  .../NanhuDev/NanhuDevPkgExtra.uni             |  12 +
> >  .../NanhuDev/Universal/Sec/SecMain.inf        |  82 +++
> >  .../NanhuDev/VarStore.fdf.inc                 |  70 +++
> >  Platform/Bosc/XiangshanSeriesPkg/Readme.md    |  59 ++
> >  .../XiangshanSeriesPkg/XiangshanSeriesPkg.dec |  29 +
> >  .../XiangshanSeriesPkg/XiangshanSeriesPkg.uni |  12 +
> >  .../XiangshanSeriesPkgExtra.uni               |  12 +
> >  Silicon/Bosc/NanHuPkg/NanHuPkg.dec            |  33 ++
> >  16 files changed, 1505 insertions(+)
> >  create mode 100644 Platform/Bosc/XiangshanSeriesPkg/NanhuDev/DeviceTree.fdf.inc
> >  create mode 100644 Platform/Bosc/XiangshanSeriesPkg/NanhuDev/DeviceTree/NanhuDev.dts
> >  create mode 100644 Platform/Bosc/XiangshanSeriesPkg/NanhuDev/DeviceTree/NanhuDeviceTree.inf
> >  create mode 100644 Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.dec
> >  create mode 100644 Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.dsc
> >  create mode 100644 Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.fdf
> >  create mode 100644 Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.fdf.inc
> >  create mode 100644 Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.uni
> >  create mode 100644 Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDevPkgExtra.uni
> >  create mode 100644 Platform/Bosc/XiangshanSeriesPkg/NanhuDev/Universal/Sec/SecMain.inf
> >  create mode 100644 Platform/Bosc/XiangshanSeriesPkg/NanhuDev/VarStore.fdf.inc
> >  create mode 100644 Platform/Bosc/XiangshanSeriesPkg/Readme.md
> >  create mode 100644 Platform/Bosc/XiangshanSeriesPkg/XiangshanSeriesPkg.dec
> >  create mode 100644 Platform/Bosc/XiangshanSeriesPkg/XiangshanSeriesPkg.uni
> >  create mode 100644 Platform/Bosc/XiangshanSeriesPkg/XiangshanSeriesPkgExtra.uni
> >  create mode 100644 Silicon/Bosc/NanHuPkg/NanHuPkg.dec
> > 
> > diff --git a/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/DeviceTree.fdf.inc b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/DeviceTree.fdf.inc
> > new file mode 100644
> > index 0000000000..f489e5631f
> > --- /dev/null
> > +++ b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/DeviceTree.fdf.inc
> > @@ -0,0 +1,36 @@
> > +## @file
> > +#  FDF include file with Layout Regions that define an empty variable store.
> > +#
> > +#  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> > +#  Copyright (C) 2014, Red Hat, Inc.
> > +#  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
> > +#  Copyright (c) 2024, BOSC. All rights reserved.<BR>
> > +#
> > +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +##
> > +
> > +$(DTB_OFFSET)|$(DTB_SIZE)
> > +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase|gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvSize
> > +FV = DTBFV
> > +
> > +[FV.DTBFV]
> > +BlockSize          = 0x1000
> > +FvAlignment        = 16
> > +ERASE_POLARITY     = 1
> > +MEMORY_MAPPED      = TRUE
> > +STICKY_WRITE       = TRUE
> > +LOCK_CAP           = TRUE
> > +LOCK_STATUS        = TRUE
> > +WRITE_DISABLED_CAP = TRUE
> > +WRITE_ENABLED_CAP  = TRUE
> > +WRITE_STATUS       = TRUE
> > +WRITE_LOCK_CAP     = TRUE
> > +WRITE_LOCK_STATUS  = TRUE
> > +READ_DISABLED_CAP  = TRUE
> > +READ_ENABLED_CAP   = TRUE
> > +READ_STATUS        = TRUE
> > +READ_LOCK_CAP      = TRUE
> > +READ_LOCK_STATUS   = TRUE
> > +
> > +INF RuleOverride = DTB Platform/Bosc/XiangshanSeriesPkg/NanhuDev/DeviceTree/NanhuDeviceTree.inf
> > diff --git a/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/DeviceTree/NanhuDev.dts b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/DeviceTree/NanhuDev.dts
> > new file mode 100644
> > index 0000000000..12617cab69
> > --- /dev/null
> > +++ b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/DeviceTree/NanhuDev.dts
> > @@ -0,0 +1,120 @@
> > +/** @file
> > + Nanhu platform Device Tree
> > +
> > + Copyright (c) 2024, BOSC. All rights reserved.
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +/dts-v1/;
> > +/ {
> > +    #address-cells = <2>;
> > +    #size-cells = <2>;
> > +    compatible = "bosc,nanhu-dev";
> > +    model = "bosc,nanhu-dev";
> > +    cpus {
> > +        #address-cells = <1>;
> > +        #size-cells = <0>;
> > +        timebase-frequency = <500000>;//500Khz
> > +        cpu0: cpu@0 {
> > +            clock-frequency = <1000000>;
> > +            compatible = "bosc,nanhu", "riscv";
> > +            d-cache-block-size = <64>;
> > +            d-cache-sets = <64>;
> > +            d-cache-size = <16384>;
> > +            d-tlb-sets = <1>;
> > +            d-tlb-size = <32>;
> > +            device_type = "cpu";
> > +            i-cache-block-size = <64>;
> > +            i-cache-sets = <64>;
> > +            i-cache-size = <16384>;
> > +            i-tlb-sets = <1>;
> > +            i-tlb-size = <32>;
> > +            mmu-type = "riscv,sv39";
> > +            next-level-cache = <&memory>;
> > +            reg = <0x0>;
> > +            riscv,isa = "rv64imafdc";
> > +            status = "okay";
> > +            timebase-frequency = <500000>;//500Khz
> > +            tlb-split;
> > +            cpu0_intc: interrupt-controller {
> > +                #interrupt-cells = <1>;
> > +                compatible = "riscv,cpu-intc";
> > +                interrupt-controller;
> > +            };
> > +        };
> > +
> > +        cpu1: cpu@1 {
> > +            clock-frequency = <0>;
> > +            compatible = "bosc,nanhu", "riscv";
> > +            d-cache-block-size = <64>;
> > +            d-cache-sets = <64>;
> > +            d-cache-size = <16384>;
> > +            d-tlb-sets = <1>;
> > +            d-tlb-size = <32>;
> > +            device_type = "cpu";
> > +            i-cache-block-size = <64>;
> > +            i-cache-sets = <64>;
> > +            i-cache-size = <16384>;
> > +            i-tlb-sets = <1>;
> > +            i-tlb-size = <32>;
> > +            mmu-type = "riscv,sv39";
> > +            next-level-cache = <&memory>;
> > +            reg = <0x1>;
> > +            riscv,isa = "rv64imafdc";
> > +            status = "okay";
> > +            timebase-frequency = <500000>;//500Khz
> > +            tlb-split;
> > +            cpu1_intc: interrupt-controller {
> > +                #interrupt-cells = <1>;
> > +                compatible = "riscv,cpu-intc";
> > +                interrupt-controller;
> > +            };
> > +        };
> > +
> > +    };
> > +
> > +    soc {
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> > +        compatible = "bosc,nanhu-soc", "simple-bus";
> > +        ranges;
> > +        clint0: clint@38000000 {
> > +            compatible = "riscv,clint0";
> > +            interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7>;
> > +            reg = <0x0 0x38000000 0x0 0x10000>;
> > +            reg-names = "control";
> > +            clock-frequency-mhz = <25>;
> > +        };
> > +
> > +        PLIC: interrupt-controller@3c000000 {
> > +            #interrupt-cells = <1>;
> > +            compatible = "riscv,plic0";
> > +            interrupt-controller;
> > +            interrupts-extended = <&cpu0_intc 0xb &cpu0_intc 0x9 &cpu1_intc 0xb &cpu1_intc 0x9>;
> > +            reg = <0 0x3c000000 0 0x4000000>;
> > +            reg-names = "control";
> > +            riscv,max-priority = <7>;
> > +            riscv,ndev = <64>;
> > +        };
> > +
> > +        serial@310B0000 {
> > +            compatible = "ns16550a";
> > +            reg = <0x0 0x310B0000 0x0 0x10000>;
> > +            reg-shift = <0x02>;
> > +            reg-io-width = <0x04>;
> > +            interrupt-parent = <&PLIC>;
> > +            interrupts = <40>;
> > +            clock-frequency = <50000000>;
> > +            status = "okay";
> > +        };
> > +
> > +    };
> > +
> > +    memory: memory@80000000 {
> > +         device_type = "memory";
> > +         reg = <0x0 0x80000000 0x0 0x80000000>;
> > +    };
> > +};
> > +
> > diff --git a/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/DeviceTree/NanhuDeviceTree.inf b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/DeviceTree/NanhuDeviceTree.inf
> > new file mode 100644
> > index 0000000000..658eec7a7c
> > --- /dev/null
> > +++ b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/DeviceTree/NanhuDeviceTree.inf
> > @@ -0,0 +1,22 @@
> > +## @file
> > +#
> > +#  Device tree description of the Nanhu platform
> > +#
> > +#  Copyright (c) 2024, BOSC. All rights reserved.
> > +#
> > +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +##
> > +
> > +[Defines]
> > +  INF_VERSION    = 0x0001001A
> > +  BASE_NAME      = NanhuDeviceTree
> > +  FILE_GUID      = 7778785C-0D2B-4556-AA9A-D151398270E2 # gDtPlatformDefaultDtbFileGuid
> > +  MODULE_TYPE    = USER_DEFINED
> > +  VERSION_STRING = 1.0
> > +
> > +[Sources]
> > +  NanhuDev.dts
> > +
> > +[Packages]
> > +  MdePkg/MdePkg.dec
> > diff --git a/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.dec b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.dec
> > new file mode 100644
> > index 0000000000..20eb55e336
> > --- /dev/null
> > +++ b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.dec
> > @@ -0,0 +1,24 @@
> > +## @file  NanHu.dec
> > +# This Package provides BOSC NanHu modules and libraries.
> > +#
> > +# Copyright (c) 2024, BOSC. All rights reserved.<BR>
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +##
> > +
> > +[Defines]
> > +  DEC_SPECIFICATION              = 0x0001001b
> > +  PACKAGE_NAME                   = NanHuDev
> > +  PACKAGE_UNI_FILE               = NanHuDev.uni
> > +  PACKAGE_GUID                   = D1960FA8-D3A4-422F-A22C-3C49735753A5
> > +  PACKAGE_VERSION                = 1.0
> > +
> > +[Includes]
> > +
> > +[LibraryClasses]
> > +
> > +[Guids]
> > +
> > +[UserExtensions.TianoCore."ExtraFiles"]
> > +  NanHuDevPkgExtra.uni
> > diff --git a/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.dsc b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.dsc
> > new file mode 100644
> > index 0000000000..e8d8393b89
> > --- /dev/null
> > +++ b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.dsc
> > @@ -0,0 +1,547 @@
> > +## @file
> > +#  RISC-V EFI on BOSC Nanhu RISC-V platform
> > +#
> > +#  Copyright (c) 2019-2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> > +#  Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
> > +#  Copyright (c) 2024, BOSC. All rights reserved.<BR>
> > +#
> > +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +##
> > +
> > +################################################################################
> > +#
> > +# Defines Section - statements that will be processed to create a Makefile.
> > +#
> > +################################################################################
> > +[Defines]
> > +  PLATFORM_NAME                  = NanhuDev
> > +  PLATFORM_GUID                  = A6342E89-CCA1-4489-895F-7098C2224123
> > +  PLATFORM_VERSION               = 0.1
> > +  DSC_SPECIFICATION              = 0x0001001c
> > +  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
> > +  SUPPORTED_ARCHITECTURES        = RISCV64
> > +  BUILD_TARGETS                  = DEBUG|RELEASE|NOOPT
> > +  SKUID_IDENTIFIER               = DEFAULT
> > +  FLASH_DEFINITION               = Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.fdf
> > +
> > +  #
> > +  # Enable below options may cause build error or may not work on
> > +  # the initial version of RISC-V package
> > +  # Defines for default states.  These can be changed on the command line.
> > +  # -D FLAG=VALUE
> > +  #
> > +  DEFINE DEBUG_ON_SERIAL_PORT    = TRUE
> > +
> > +  #
> > +  # Network definition
> > +  #
> > +  DEFINE NETWORK_SNP_ENABLE       = FALSE
> > +  DEFINE NETWORK_IP6_ENABLE       = FALSE
> > +  DEFINE NETWORK_TLS_ENABLE       = FALSE
> > +  DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
> > +  DEFINE NETWORK_ISCSI_ENABLE     = FALSE
> > +
> > +[BuildOptions]
> > +  GCC:RELEASE_*_*_CC_FLAGS       = -DMDEPKG_NDEBUG
> > +!ifdef $(SOURCE_DEBUG_ENABLE)
> > +  GCC:*_*_RISCV64_GENFW_FLAGS    = --keepexceptiontable
> > +!endif
> > +
> > +################################################################################
> > +#
> > +# SKU Identification section - list of all SKU IDs supported by this Platform.
> > +#
> > +################################################################################
> > +[SkuIds]
> > +  0|DEFAULT
> > +
> > +################################################################################
> > +#
> > +# Library Class section - list of all Library Classes needed by this Platform.
> > +#
> > +################################################################################
> > +
> > +!include MdePkg/MdeLibs.dsc.inc
> > +
> > +[LibraryClasses]
> > +  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> > +  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> > +  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
> > +  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
> > +  SafeIntLib|MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
> > +  SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> > +  CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
> > +  PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
> > +  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > +  CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> > +  UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
> > +  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
> > +  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
> > +  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
> > +  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
> > +  DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
> > +  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
> > +  PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
> > +  PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
> > +  IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> > +  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
> > +  SerialPortLib|Silicon/Hisilicon/Library/Dw8250SerialPortLib/Dw8250SerialPortLib.inf
> > +  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
> > +  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
> > +  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
> > +  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
> > +  UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
> > +  DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
> > +  FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
> > +  SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
> > +  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
> > +  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
> > +  SortLib|MdeModulePkg/Library/BaseSortLib/BaseSortLib.inf
> > +  ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> > +  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
> > +  FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
> > +  VariableFlashInfoLib|MdeModulePkg/Library/BaseVariableFlashInfoLib/BaseVariableFlashInfoLib.inf
> > +  VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf
> > +
> > +# RISC-V Platform Library
> > +  TimeBaseLib|EmbeddedPkg//Library/TimeBaseLib/TimeBaseLib.inf
> > +  RealTimeClockLib|EmbeddedPkg//Library/VirtualRealTimeClockLib/VirtualRealTimeClockLib.inf
> > +
> > +# RISC-V Core Library
> > +  RiscVOpensbiLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> > +  ImagePropertiesRecordLib|MdeModulePkg/Library/ImagePropertiesRecordLib/ImagePropertiesRecordLib.inf
> > +
> > +!ifdef $(SOURCE_DEBUG_ENABLE)
> > +  PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf
> > +  DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf
> > +!else
> > +  PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
> > +  DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
> > +!endif
> > +
> > +  DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
> > +
> > +  TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
> > +  AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
> > +  VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
> > +
> > +!if $(HTTP_BOOT_ENABLE) == TRUE
> > +  HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf
> > +!endif
> > +
> > +  SmbusLib|MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf
> > +  OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
> > +
> > +[LibraryClasses.common]
> > +
> > +  # RISC-V Architectural Libraries
> > +  RiscVCpuLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
> > +  RiscVSbiLib|MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf
> > +  RiscVMmuLib|UefiCpuPkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf
> > +  MachineModeTimerLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVReadMachineModeTimer/EmulatedMachineModeTimerLib/EmulatedMachineModeTimerLib.inf
> > +  CpuExceptionHandlerLib|UefiCpuPkg/Library/BaseRiscV64CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf
> > +
> > +  # Flattened Device Tree (FDT) access library
> > +  FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
> > +
> > +[LibraryClasses.common.SEC]
> > +!ifdef $(DEBUG_ON_SERIAL_PORT)
> > +  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
> > +!else
> > +  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> > +!endif
> > +
> > +  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
> > +  ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
> > +  Edk2OpensbiPlatformWrapperLib|Platform/RISC-V/PlatformPkg/Library/Edk2OpensbiPlatformWrapperLib/Edk2OpensbiPlatformWrapperLib.inf
> > +  RiscVSpecialPlatformLib|Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/Library/RiscVSpecialPlatformLib/RiscVSpecialPlatformLib.inf
> > +
> > +!ifdef $(SOURCE_DEBUG_ENABLE)
> > +  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
> > +!endif
> > +
> > +  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
> > +
> > +#
> > +# OpenSBi Platform Library
> > +#
> > +  RiscVOpensbiPlatformLib|Platform/RISC-V/PlatformPkg/Library/OpensbiPlatformLib/OpensbiPlatformLib.inf
> > +
> > +[LibraryClasses.common.PEI_CORE]
> > +  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> > +  PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
> > +  RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
> > +  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
> > +  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
> > +  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
> > +  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
> > +  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
> > +!ifdef $(DEBUG_ON_SERIAL_PORT)
> > +  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
> > +!else
> > +  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> > +!endif
> > +  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > +  # RISC-V platform PEI core entry point.
> > +  PeiCoreEntryPoint|Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
> > +  PlatformSecPpiLib|Platform/SiFive/U5SeriesPkg/Library/PlatformSecPpiLib/PlatformSecPpiLib.inf
> > +
> > +[LibraryClasses.common.PEIM]
> > +  HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> > +  PeiServicesTablePointerLib|Silicon/RISC-V/ProcessorPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
> > +  RiscVFirmwareContextLib|Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
> > +  PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
> > +  MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
> > +  PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
> > +  ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
> > +  OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
> > +  PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
> > +!ifdef $(DEBUG_ON_SERIAL_PORT)
> > +  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
> > +!else
> > +  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> > +!endif
> > +  PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
> > +  PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
> > +  ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
> > +!ifdef $(SOURCE_DEBUG_ENABLE)
> > +  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
> > +!endif
> > +  FirmwareContextProcessorSpecificLib|Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
> > +
> > +#
> > +# RISC-V core libraries
> > +#
> > +  SiliconSiFiveU54CoreInfoLib|Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
> > +  RiscVCoreplexInfoLib|Platform/SiFive/U5SeriesPkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
> > +
> > +[LibraryClasses.common.DXE_CORE]
> > +  TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
> > +  HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
> > +  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
> > +  MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
> > +  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
> > +!ifdef $(DEBUG_ON_SERIAL_PORT)
> > +  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
> > +!else
> > +  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> > +!endif
> > +  ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
> > +!ifdef $(SOURCE_DEBUG_ENABLE)
> > +  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
> > +!endif
> > +
> > +[LibraryClasses.common.DXE_RUNTIME_DRIVER]
> > +  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> > +  TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
> > +  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> > +  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
> > +  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> > +  ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
> > +  ResetSystemLib|Platform/RISC-V/PlatformPkg/Library/ResetSystemLib/ResetSystemLib.inf
> > +  UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
> > +!ifdef $(DEBUG_ON_SERIAL_PORT)
> > +  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
> > +!else
> > +  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> > +!endif
> > +  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
> > +  VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLibRuntimeDxe.inf
> > +
> > +[LibraryClasses.common.UEFI_DRIVER]
> > +  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> > +  TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
> > +  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> > +  DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
> > +  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> > +  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
> > +!ifdef $(DEBUG_ON_SERIAL_PORT)
> > +  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
> > +!else
> > +  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> > +!endif
> > +  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
> > +  VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyLib.inf
> > +
> > +[LibraryClasses.common.DXE_DRIVER]
> > +  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> > +  TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
> > +  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> > +  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> > +  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
> > +  UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
> > +!ifdef $(DEBUG_ON_SERIAL_PORT)
> > +  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
> > +!else
> > +  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> > +!endif
> > +!ifdef $(SOURCE_DEBUG_ENABLE)
> > +  DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
> > +!endif
> > +  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
> > +  PlatformBootManagerLib|Platform/RISC-V/PlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
> > +  PlatformMemoryTestLib|Platform/RISC-V/PlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
> > +  PlatformUpdateProgressLib|Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
> > +
> > +[LibraryClasses.common.UEFI_APPLICATION]
> > +  PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> > +  TimerLib|UefiCpuPkg/Library/BaseRiscV64CpuTimerLib/BaseRiscV64CpuTimerLib.inf
> > +  HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> > +  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
> > +!ifdef $(DEBUG_ON_SERIAL_PORT)
> > +  DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
> > +!else
> > +  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
> > +!endif
> > +  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
> > +
> > +################################################################################
> > +#
> > +# Pcd Section - list of all EDK II PCD Entries defined by this Platform.
> > +#
> > +################################################################################
> > +[PcdsFeatureFlag]
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
> > +
> > +[PcdsFixedAtBuild]
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
> > +  #Disable CMO and Sstc features
> > +  gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride|0xFFFFFFFFFFFFFFFC
> > +  gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0xe000
> > +
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
> > +
> > +  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> > +  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F
> > +!ifdef $(SOURCE_DEBUG_ENABLE)
> > +  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17
> > +!else
> > +  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
> > +!endif
> > +
> > +!ifdef $(SOURCE_DEBUG_ENABLE)
> > +  gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2
> > +!endif
> > +
> > +  #
> > +  # F2 for UI APP
> > +  #
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
> > +
> > +  #
> > +  # Control the maximum SATP mode that MMU allowed to use.
> > +  # 0 - Bare mode.
> > +  # 8 - 39bit mode.
> > +  # 9 - 48bit mode.
> > +  # 10 - 57bit mode.
> > +  #
> > +  gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|0
> > +################################################################################
> > +#
> > +# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform
> > +#
> > +################################################################################
> > +
> > +[PcdsDynamicDefault]
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
> > +
> > +  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0
> > +
> > +  # Set video resolution for text setup.
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480
> > +
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0
> > +
> > +################################################################################
> > +#
> > +# Components Section - list of all EDK II Modules needed by this Platform.
> > +#
> > +################################################################################
> > +[Components]
> > +
> > +  #
> > +  # SEC Phase modules
> > +  #
> > +  Platform/Bosc/XiangshanSeriesPkg/NanhuDev/Universal/Sec/SecMain.inf
> > +
> > +  #
> > +  # PEI Phase modules
> > +  #
> > +  MdeModulePkg/Core/Pei/PeiMain.inf
> > +  MdeModulePkg/Universal/PCD/Pei/Pcd.inf  {
> > +    <LibraryClasses>
> > +      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> > +  }
> > +  MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
> > +  MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
> > +  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
> > +    <LibraryClasses>
> > +    NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
> > +  }
> > +
> > +  Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf {
> > +    <LibraryClasses>
> > +      PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> > +  }
> > +  Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf
> > +
> > +  #
> > +  # DXE Phase modules
> > +  #
> > +  MdeModulePkg/Core/Dxe/DxeMain.inf {
> > +    <LibraryClasses>
> > +      NULL|MdeModulePkg//Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
> > +      DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
> > +  }
> > +
> > +  MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
> > +  MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
> > +
> > +  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf  {
> > +   <LibraryClasses>
> > +      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> > +  }
> > +
> > +  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> > +
> > +  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> > +
> > +  UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
> > +  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf {
> > +    <LibraryClasses>
> > +      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> > +  }
> > +  MdeModulePkg/Universal/Metronome/Metronome.inf
> > +  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> > +  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf {
> > +    <LibraryClasses>
> > +      ResetSystemLib|MdeModulePkg/Library/BaseResetSystemLibNull/BaseResetSystemLibNull.inf
> > +  }
> > +  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> > +
> > +  #
> > +  # RISC-V Platform module
> > +  #
> > +  UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
> > +  Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
> > +
> > +  #
> > +  # RISC-V Core module
> > +  #
> > +  UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> > +  Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
> > +  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> > +
> > +  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
> > +  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
> > +    <LibraryClasses>
> > +      NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
> > +      VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/VariablePolicyHelperLib.inf
> > +  }
> > +  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
> > +  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
> > +  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> > +  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> > +  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> > +
> > +# No graphic console supported yet.
> > +#  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf {
> > +#    <LibraryClasses>
> > +#      PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
> > +#  }
> > +  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> > +  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf {
> > +    <LibraryClasses>
> > +      DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
> > +      PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
> > +  }
> > +  MdeModulePkg/Universal/PrintDxe/PrintDxe.inf
> > +  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> > +  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> > +  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> > +  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> > +  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> > +  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> > +  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> > +  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> > +  MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
> > +  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> > +
> > +  Platform/Bosc/XiangshanSeriesPkg/NanhuDev/DeviceTree/NanhuDeviceTree.inf
> > +
> > +  #
> > +  # SMBIOS Support
> > +  #
> > +  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
> > +
> > +  #
> > +  # Network Support
> > +  #
> > +  !include NetworkPkg/Network.dsc.inc
> > +
> > +  #
> > +  # Usb Support
> > +  #
> > +  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
> > +  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
> > +  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
> > +  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> > +  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
> > +  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> > +
> > +  Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf
> > +
> > +  #
> > +  # FAT filesystem + GPT/MBR partitioning + UDF filesystem
> > +  #
> > +  FatPkg/EnhancedFatDxe/Fat.inf
> > +  MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf
> > +
> > +  OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf {
> > +    <PcdsFixedAtBuild>
> > +      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> > +    <LibraryClasses>
> > +      ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> > +      SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
> > +  }
> > +
> > +  ShellPkg/Application/Shell/Shell.inf {
> > +    <LibraryClasses>
> > +      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
> > +      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
> > +      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
> > +      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
> > +      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
> > +      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
> > +      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
> > +      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
> > +      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
> > +      FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
> > +      SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
> > +      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
> > +      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
> > +
> > +    <PcdsFixedAtBuild>
> > +      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
> > +      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> > +      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
> > +  }
> > +
> > +  MdeModulePkg/Application/UiApp/UiApp.inf
> > diff --git a/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.fdf b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.fdf
> > new file mode 100644
> > index 0000000000..e6118a4c3f
> > --- /dev/null
> > +++ b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.fdf
> > @@ -0,0 +1,326 @@
> > +# @file
> > +# Flash definition file on NanhuDev RISC-V platform
> > +#
> > +#  Copyright (c) 2019-2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> > +#  Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
> > +#  Copyright (c) 2024, BOSC. All rights reserved.
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +!include NanhuDev.fdf.inc
> > +
> > +#
> > +# Build the variable store and the firmware code as one unified flash device
> > +# image.
> > +#
> > +[FD.NANHUDEV]
> > +BaseAddress   = $(FW_BASE_ADDRESS)
> > +Size          = $(FW_SIZE)
> > +ErasePolarity = 1
> > +BlockSize     = $(BLOCK_SIZE)
> > +NumBlocks     = $(FW_BLOCKS)
> > +
> > +$(SECFV_OFFSET)|$(SECFV_SIZE)
> > +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvBase|gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvSize
> > +FV = SECFV
> > +
> > +$(PEIFV_OFFSET)|$(PEIFV_SIZE)
> > +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase|gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize
> > +FV = PEIFV
> > +
> > +$(FVMAIN_OFFSET)|$(FVMAIN_SIZE)
> > +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize
> > +FV = FVMAIN_COMPACT
> > +
> > +!include VarStore.fdf.inc
> > +!include DeviceTree.fdf.inc
> > +
> > +################################################################################
> > +
> > +[FV.SECFV]
> > +BlockSize          = 0x1000
> > +FvAlignment        = 16
> > +ERASE_POLARITY     = 1
> > +MEMORY_MAPPED      = TRUE
> > +STICKY_WRITE       = TRUE
> > +LOCK_CAP           = TRUE
> > +LOCK_STATUS        = TRUE
> > +WRITE_DISABLED_CAP = TRUE
> > +WRITE_ENABLED_CAP  = TRUE
> > +WRITE_STATUS       = TRUE
> > +WRITE_LOCK_CAP     = TRUE
> > +WRITE_LOCK_STATUS  = TRUE
> > +READ_DISABLED_CAP  = TRUE
> > +READ_ENABLED_CAP   = TRUE
> > +READ_STATUS        = TRUE
> > +READ_LOCK_CAP      = TRUE
> > +READ_LOCK_STATUS   = TRUE
> > +
> > +#
> > +# SEC Phase modules
> > +#
> > +# The code in this FV handles the initial firmware startup, and
> > +# decompresses the PEI and DXE FVs which handles the rest of the boot sequence.
> > +#
> > +INF Platform/Bosc/XiangshanSeriesPkg/NanhuDev/Universal/Sec/SecMain.inf
> > +
> > +################################################################################
> > +[FV.PEIFV]
> > +BlockSize          = 0x10000
> > +FvAlignment        = 16
> > +ERASE_POLARITY     = 1
> > +MEMORY_MAPPED      = TRUE
> > +STICKY_WRITE       = TRUE
> > +LOCK_CAP           = TRUE
> > +LOCK_STATUS        = TRUE
> > +WRITE_DISABLED_CAP = TRUE
> > +WRITE_ENABLED_CAP  = TRUE
> > +WRITE_STATUS       = TRUE
> > +WRITE_LOCK_CAP     = TRUE
> > +WRITE_LOCK_STATUS  = TRUE
> > +READ_DISABLED_CAP  = TRUE
> > +READ_ENABLED_CAP   = TRUE
> > +READ_STATUS        = TRUE
> > +READ_LOCK_CAP      = TRUE
> > +READ_LOCK_STATUS   = TRUE
> > +
> > +APRIORI PEI {
> > +  INF  MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
> > +  INF  MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
> > +  INF  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
> > +}
> > +
> > +#
> > +#  PEI Phase modules
> > +#
> > +INF  MdeModulePkg/Core/Pei/PeiMain.inf
> > +INF  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
> > +INF  MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
> > +INF  MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
> > +INF  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
> > +
> > +# RISC-V Platform PEI Driver
> > +INF  Platform/RISC-V/PlatformPkg/Universal/Pei/PlatformPei/PlatformPei.inf
> > +INF  Platform/RISC-V/PlatformPkg/Universal/FdtPeim/FdtPeim.inf
> > +
> > +################################################################################
> > +
> > +[FV.DXEFV]
> > +BlockSize          = 0x10000
> > +FvAlignment        = 16
> > +ERASE_POLARITY     = 1
> > +MEMORY_MAPPED      = TRUE
> > +STICKY_WRITE       = TRUE
> > +LOCK_CAP           = TRUE
> > +LOCK_STATUS        = TRUE
> > +WRITE_DISABLED_CAP = TRUE
> > +WRITE_ENABLED_CAP  = TRUE
> > +WRITE_STATUS       = TRUE
> > +WRITE_LOCK_CAP     = TRUE
> > +WRITE_LOCK_STATUS  = TRUE
> > +READ_DISABLED_CAP  = TRUE
> > +READ_ENABLED_CAP   = TRUE
> > +READ_STATUS        = TRUE
> > +READ_LOCK_CAP      = TRUE
> > +READ_LOCK_STATUS   = TRUE
> > +
> > +APRIORI DXE {
> > +  INF  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> > +  INF  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> > +  INF  Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
> > +}
> > +
> > +#
> > +# DXE Phase modules
> > +#
> > +INF  MdeModulePkg/Core/Dxe/DxeMain.inf
> > +
> > +INF  MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
> > +INF  MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
> > +INF  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> > +
> > +INF  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
> > +INF  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
> > +INF  UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
> > +INF  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
> > +INF  MdeModulePkg/Universal/Metronome/Metronome.inf
> > +INF  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
> > +
> > +# RISC-V Platform Drivers
> > +INF  Platform/SiFive/U5SeriesPkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
> > +
> > +# RISC-V Core Drivers
> > +INF  UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf
> > +INF  UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf
> > +INF  Silicon/RISC-V/ProcessorPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
> > +
> > +INF  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
> > +
> > +INF  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
> > +
> > +INF  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
> > +INF  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
> > +INF  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
> > +INF  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
> > +INF  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
> > +INF  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
> > +INF  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> > +INF  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
> > +INF  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
> > +INF  MdeModulePkg/Universal/PrintDxe/PrintDxe.inf
> > +INF  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
> > +INF  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
> > +INF  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
> > +INF  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> > +INF  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> > +INF  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
> > +INF  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
> > +INF  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
> > +INF  MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
> > +INF  FatPkg/EnhancedFatDxe/Fat.inf
> > +INF  MdeModulePkg/Universal/Disk/UdfDxe/UdfDxe.inf
> > +INF  Silicon/RISC-V/ProcessorPkg/Universal/FdtDxe/FdtDxe.inf
> > +
> > +!ifndef $(SOURCE_DEBUG_ENABLE)
> > +INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
> > +!endif
> > +
> > +INF  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
> > +
> > +INF  OvmfPkg/LinuxInitrdDynamicShellCommand/LinuxInitrdDynamicShellCommand.inf
> > +INF  ShellPkg/Application/Shell/Shell.inf
> > +
> > +#
> > +# Network modules
> > +#
> > +!if $(E1000_ENABLE)
> > +  FILE DRIVER = 5D695E11-9B3F-4b83-B25F-4A8D5D69BE07 {
> > +    SECTION PE32 = Intel3.5/EFIX64/E3507X2.EFI
> > +  }
> > +!endif
> > +
> > +!include NetworkPkg/Network.fdf.inc
> > +
> > +#
> > +# Usb Support
> > +#
> > +INF  MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
> > +INF  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
> > +INF  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
> > +INF  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
> > +INF  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
> > +INF  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
> > +
> > +INF  MdeModulePkg/Application/UiApp/UiApp.inf
> > +
> > +################################################################################
> > +
> > +[FV.FVMAIN_COMPACT]
> > +FvAlignment        = 16
> > +ERASE_POLARITY     = 1
> > +MEMORY_MAPPED      = TRUE
> > +STICKY_WRITE       = TRUE
> > +LOCK_CAP           = TRUE
> > +LOCK_STATUS        = TRUE
> > +WRITE_DISABLED_CAP = TRUE
> > +WRITE_ENABLED_CAP  = TRUE
> > +WRITE_STATUS       = TRUE
> > +WRITE_LOCK_CAP     = TRUE
> > +WRITE_LOCK_STATUS  = TRUE
> > +READ_DISABLED_CAP  = TRUE
> > +READ_ENABLED_CAP   = TRUE
> > +READ_STATUS        = TRUE
> > +READ_LOCK_CAP      = TRUE
> > +READ_LOCK_STATUS   = TRUE
> > +FvNameGuid         = 3D6404C0-9303-11ED-BFDA-00155D96A1C8
> > +
> > +FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> > +   SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
> > +     #
> > +     # These firmware volumes will have files placed in them uncompressed,
> > +     # and then both firmware volumes will be compressed in a single
> > +     # compression operation in order to achieve better overall compression.
> > +     #
> > +     SECTION FV_IMAGE = DXEFV
> > +   }
> > + }
> > +
> > +[Rule.Common.SEC]
> > +  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
> > +    PE32     PE32   Align=4K $(INF_OUTPUT)/$(MODULE_NAME).efi
> > +    UI       STRING ="$(MODULE_NAME)" Optional
> > +    VERSION  STRING ="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> > +  }
> > +
> > +[Rule.Common.PEI_CORE]
> > +  FILE PEI_CORE = $(NAMED_GUID) {
> > +    PE32     PE32   Align=4K    $(INF_OUTPUT)/$(MODULE_NAME).efi
> > +    UI       STRING ="$(MODULE_NAME)" Optional
> > +    VERSION  STRING ="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> > +  }
> > +
> > +[Rule.Common.PEIM]
> > +  FILE PEIM = $(NAMED_GUID) {
> > +     PEI_DEPEX PEI_DEPEX Optional        $(INF_OUTPUT)/$(MODULE_NAME).depex
> > +     PE32     PE32   Align=4K         $(INF_OUTPUT)/$(MODULE_NAME).efi
> > +     UI       STRING="$(MODULE_NAME)" Optional
> > +     VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> > +  }
> > +
> > +[Rule.Common.DXE_CORE]
> > +  FILE DXE_CORE = $(NAMED_GUID) {
> > +    PE32     PE32   Align=4K  $(INF_OUTPUT)/$(MODULE_NAME).efi
> > +    UI       STRING="$(MODULE_NAME)" Optional
> > +    VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> > +  }
> > +
> > +[Rule.Common.DXE_DRIVER]
> > +  FILE DRIVER = $(NAMED_GUID) {
> > +    DXE_DEPEX    DXE_DEPEX Optional      $(INF_OUTPUT)/$(MODULE_NAME).depex
> > +    PE32     PE32   Align=4K  $(INF_OUTPUT)/$(MODULE_NAME).efi
> > +    UI       STRING="$(MODULE_NAME)" Optional
> > +    VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> > +  }
> > +
> > +[Rule.Common.DXE_RUNTIME_DRIVER]
> > +  FILE DRIVER = $(NAMED_GUID) {
> > +    DXE_DEPEX    DXE_DEPEX Optional      $(INF_OUTPUT)/$(MODULE_NAME).depex
> > +    PE32     PE32   Align = 4K    $(INF_OUTPUT)/$(MODULE_NAME).efi
> > +    UI       STRING="$(MODULE_NAME)" Optional
> > +    VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> > +  }
> > +
> > +[Rule.Common.UEFI_DRIVER]
> > +  FILE DRIVER = $(NAMED_GUID) {
> > +    DXE_DEPEX    DXE_DEPEX Optional      $(INF_OUTPUT)/$(MODULE_NAME).depex
> > +    PE32     PE32  Align=4K  $(INF_OUTPUT)/$(MODULE_NAME).efi
> > +    UI       STRING="$(MODULE_NAME)" Optional
> > +    VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> > +  }
> > +
> > +[Rule.Common.UEFI_DRIVER.BINARY]
> > +  FILE DRIVER = $(NAMED_GUID) {
> > +    DXE_DEPEX DXE_DEPEX Optional      |.depex
> > +    PE32      PE32   Align=4K   |.efi
> > +    UI        STRING="$(MODULE_NAME)" Optional
> > +    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> > +  }
> > +
> > +[Rule.Common.UEFI_APPLICATION]
> > +  FILE APPLICATION = $(NAMED_GUID) {
> > +    PE32     PE32   Align=4K   $(INF_OUTPUT)/$(MODULE_NAME).efi
> > +    UI       STRING="$(MODULE_NAME)" Optional
> > +    VERSION  STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> > +  }
> > +
> > +[Rule.Common.UEFI_APPLICATION.BINARY]
> > +  FILE APPLICATION = $(NAMED_GUID) {
> > +    PE32      PE32  Align=4K  |.efi
> > +    UI        STRING="$(MODULE_NAME)" Optional
> > +    VERSION   STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
> > +  }
> > +
> > +[Rule.Common.USER_DEFINED.DTB]
> > +  FILE FREEFORM = $(NAMED_GUID) {
> > +    RAW BIN                |.dtb
> > +  }
> > diff --git a/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.fdf.inc b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.fdf.inc
> > new file mode 100644
> > index 0000000000..5339fd9427
> > --- /dev/null
> > +++ b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.fdf.inc
> > @@ -0,0 +1,108 @@
> > +## @file
> > +#  Definitions of Flash definition file on BOSC NanhuDev RISC-V platform
> > +#
> > +#  Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> > +#  Copyright (c) 2024, BOSC. All rights reserved.<BR>
> > +#
> > +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +##
> > +[Defines]
> > +DEFINE BLOCK_SIZE        = 0x1000
> > +
> > +DEFINE FW_BASE_ADDRESS   = 0x80000000
> > +DEFINE FW_SIZE           = 0x00900000
> > +DEFINE FW_BLOCKS         = 0x900
> > +
> > +#
> > +# 0x000000-0x7DFFFF code
> > +# 0x7E0000-0x800000 variables
> > +#
> > +DEFINE CODE_BASE_ADDRESS = 0x80000000
> > +DEFINE CODE_SIZE         = 0x00800000
> > +DEFINE CODE_BLOCKS       = 0x800
> > +DEFINE VARS_BLOCKS       = 0x20
> > +
> > +#
> > +# SEC + opensbi library is the root FW domain.
> > +# The base address must be round up to log2.
> > +#
> > +DEFINE SECFV_OFFSET        = 0x00000000
> > +DEFINE SECFV_SIZE          = 0x00040000
> > +DEFINE ROOT_FW_DOMAIN_SIZE = $(SECFV_SIZE)
> > +
> > +#
> > +# Other FV regions are in the second FW domain.
> > +# The size of memory region must be power of 2.
> > +# The base address must be aligned with the size.
> > +#
> > +# FW memory region
> > +#
> > +DEFINE PEIFV_OFFSET                  = 0x00400000
> > +DEFINE PEIFV_SIZE                    = 0x00180000
> > +DEFINE FVMAIN_OFFSET                 = 0x00580000
> > +DEFINE FVMAIN_SIZE                   = 0x00280000
> > +
> > +#
> > +# EFI Variable memory region.
> > +# The total size of EFI Variable FD must include
> > +# all of sub regions of EFI Variable
> > +#
> > +DEFINE VARS_OFFSET                   = 0x00800000
> > +DEFINE VARS_SIZE                     = 0x00007000
> > +DEFINE VARS_FTW_WORKING_OFFSET       = 0x00807000
> > +DEFINE VARS_FTW_WORKING_SIZE         = 0x00001000
> > +DEFINE VARS_FTW_SPARE_OFFSET         = 0x00808000
> > +DEFINE VARS_FTW_SPARE_SIZE           = 0x00018000
> > +
> > +#
> > +# Device Tree memory region
> > +#
> > +DEFINE DTB_OFFSET                    = 0x00840000
> > +DEFINE DTB_SIZE                      = 0x00002000
> > +
> > +#
> > +# Scratch area memory region
> > +#
> > +DEFINE SCRATCH_OFFSET                = 0x00880000
> > +DEFINE SCRATCH_SIZE                  = 0x00010000
> > +
> > +
> > +DEFINE FW_DOMAIN_SIZE    = $(FVMAIN_OFFSET) + $(FVMAIN_SIZE) - $(PEIFV_OFFSET)
> > +DEFINE VARIABLE_FW_SIZE  = $(VARS_FTW_SPARE_OFFSET) + $(VARS_FTW_SPARE_SIZE) - $(VARS_OFFSET)
> > +
> > +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress = $(CODE_BASE_ADDRESS) + $(SECFV_OFFSET)
> > +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize        = $(ROOT_FW_DOMAIN_SIZE)
> > +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainBaseAddress     = $(CODE_BASE_ADDRESS) + $(PEIFV_OFFSET)
> > +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFirmwareDomainSize            = $(FW_DOMAIN_SIZE)
> > +
> > +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress = $(FW_BASE_ADDRESS) + $(VARS_OFFSET)
> > +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize        = $(VARS_SIZE) + $(VARS_FTW_WORKING_SIZE) + $(VARS_FTW_SPARE_SIZE)
> > +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize   = $(BLOCK_SIZE)
> > +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress = $(CODE_BASE_ADDRESS) + $(VARS_OFFSET)
> > +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize        = $(VARIABLE_FW_SIZE)
> > +
> > +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize = 8192
> > +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase   = $(CODE_BASE_ADDRESS) + $(SCRATCH_OFFSET)
> > +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize   = $(SCRATCH_SIZE)
> > +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase = $(CODE_BASE_ADDRESS) + $(FW_SIZE)
> > +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize = 0x10000
> > +
> > +
> > +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId                  = 0          # Boot hart ID
> > +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency          = 500000 # Adapted CPU clock is 50MHz
> > +
> > +SET gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase              = 0x310B0000
> > +SET gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate                   = 115200
> > +SET gHisiTokenSpaceGuid.PcdSerialPortSendDelay                        = 50
> > +SET gHisiTokenSpaceGuid.PcdUartClkInHz                                = 50000000
> > +
> > +#
> > +# The bootable hart number the platform would like to use during boot.
> > +#
> > +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber          = 2
> > +#
> > +# Only use hart ID 0, 1
> > +#
> > +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId       = {0x0, 0x1}
> > +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPeiCorePrivilegeMode        = 1          # Set PeiCore to S-Mode
> > diff --git a/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.uni b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.uni
> > new file mode 100644
> > index 0000000000..d6c24f83d2
> > --- /dev/null
> > +++ b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.uni
> > @@ -0,0 +1,13 @@
> > +// /** @file
> > +// BOSC Nanhu Package Localized Strings and Content.
> > +//
> > +// Copyright (c) 2024, BOSC. All rights reserved.<BR>
> > +//
> > +// SPDX-License-Identifier: BSD-2-Clause-Patent
> > +//
> > +// **/
> > +
> > +
> > +#string STR_PACKAGE_ABSTRACT            #language en-US "Provides BOSC NanhuDev platform modules and libraries"
> > +
> > +#string STR_PACKAGE_DESCRIPTION         #language en-US "This Package BOSC NanhuDev platform modules and libraries."
> > diff --git a/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDevPkgExtra.uni b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDevPkgExtra.uni
> > new file mode 100644
> > index 0000000000..fe1bf367de
> > --- /dev/null
> > +++ b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDevPkgExtra.uni
> > @@ -0,0 +1,12 @@
> > +// /** @file
> > +// BOSC Nanhu Package Localized Strings and Content.
> > +//
> > +// Copyright (c) 2024, BOSC. All rights reserved.<BR>
> > +//
> > +// SPDX-License-Identifier: BSD-2-Clause-Patent
> > +//
> > +// **/
> > +
> > +#string STR_PROPERTIES_PACKAGE_NAME
> > +#language en-US
> > +"BOSC NanhuDev board package"
> > diff --git a/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/Universal/Sec/SecMain.inf b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/Universal/Sec/SecMain.inf
> > new file mode 100644
> > index 0000000000..e0b0396052
> > --- /dev/null
> > +++ b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/Universal/Sec/SecMain.inf
> > @@ -0,0 +1,82 @@
> > +## @file
> > +#  RISC-V SEC module.
> > +#
> > +#  Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> > +#  Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
> > +#  Copyright (c) 2024, BOSC Corporation. All rights reserved.<BR>
> > +#
> > +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +##
> > +
> > +[Defines]
> > +  INF_VERSION                    = 0x0001001b
> > +  BASE_NAME                      = SecMain
> > +  FILE_GUID                      = 4114C7F3-6037-4ADA-9331-836421F9739F
> > +  MODULE_TYPE                    = SEC
> > +  VERSION_STRING                 = 1.0
> > +  ENTRY_POINT                    = SecMain
> > +
> > +#
> > +# The following information is for reference only and not required by the build tools.
> > +#
> > +#  VALID_ARCHITECTURES           = RISCV64
> > +#
> > +
> > +[Sources]
> > +  Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.h
> > +  Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.c
> > +
> > +[Sources.RISCV64]
> > +  Platform/RISC-V/PlatformPkg/Universal/Sec/Riscv64/SecEntry.S
> > +
> > +[Packages]
> > +  EmbeddedPkg/EmbeddedPkg.dec
> > +  MdeModulePkg/MdeModulePkg.dec
> > +  MdePkg/MdePkg.dec
> > +  Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> > +  Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec
> > +  Silicon/Bosc/NanHuPkg/NanHuPkg.dec
> > +
> > +[LibraryClasses]
> > +  BaseLib
> > +  BaseMemoryLib
> > +  DebugAgentLib
> > +  DebugLib
> > +  Edk2OpensbiPlatformWrapperLib
> > +  ExtractGuidedSectionLib
> > +  FdtLib
> > +  IoLib
> > +  PcdLib
> > +  PeCoffLib
> > +  PeCoffGetEntryPointLib
> > +  PeCoffExtraActionLib
> > +  PrintLib
> > +  RiscVCpuLib
> > +  RiscVOpensbiLib
> > +  RiscVOpensbiPlatformLib
> > +  RiscVSbiLib
> > +
> > +[FixedPcd]
> > +  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase
> > +  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize
> > +  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDtbFvBase
> > +  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdDeviceTreeAddress
> > +
> > +[Pcd]
> > +  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
> > +  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainBaseAddress
> > +  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRootFirmwareDomainSize
> > +  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartNumber
> > +  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootableHartIndexToId
> > +  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
> > +  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase
> > +  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize
> > +  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase
> > +  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize
> > +  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPeiCorePrivilegeMode
> > +
> > +[BuildOptions]
> > +  GCC:*_*_*_PP_FLAGS = -D__ASSEMBLY__
> > +
> > +
> > diff --git a/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/VarStore.fdf.inc b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/VarStore.fdf.inc
> > new file mode 100644
> > index 0000000000..6fe28455a0
> > --- /dev/null
> > +++ b/Platform/Bosc/XiangshanSeriesPkg/NanhuDev/VarStore.fdf.inc
> > @@ -0,0 +1,70 @@
> > +## @file
> > +#  FDF include file with Layout Regions that define an empty variable store.
> > +#
> > +#  Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> > +#  Copyright (C) 2014, Red Hat, Inc.
> > +#  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
> > +#
> > +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +##
> > +
> > +$(VARS_OFFSET)|$(VARS_SIZE)
> > +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> > +#
> > +# NV_VARIABLE_STORE
> > +#
> > +DATA = {
> > +  ## This is the EFI_FIRMWARE_VOLUME_HEADER
> > +  # ZeroVector []
> > +  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> > +  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> > +  # FileSystemGuid: gEfiSystemNvDataFvGuid         =
> > +  #   { 0xFFF12B8D, 0x7696, 0x4C8B,
> > +  #     { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
> > +  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
> > +  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
> > +  # FvLength: 0x20000
> > +  0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
> > +  # Signature "_FVH"       # Attributes
> > +  0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
> > +  # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision
> > +  0x48, 0x00, 0x39, 0xF1, 0x00, 0x00, 0x00, 0x02,
> > +  # Blockmap[0]: 0x20 Blocks * 0x1000 Bytes / Block
> > +  0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
> > +  # Blockmap[1]: End
> > +  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> > +  ## This is the VARIABLE_STORE_HEADER
> > +  # Signature: gEfiVariableGuid =
> > +  #   { 0xddcf3616, 0x3275, 0x4164,
> > +  #     { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
> > +  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
> > +  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
> > +  # Size: 0x7000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) -
> > +  #         0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x6fb8
> > +  # This can speed up the Variable Dispatch a bit.
> > +  0xB8, 0x6F, 0x00, 0x00,
> > +  # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
> > +  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> > +}
> > +
> > +$(VARS_FTW_WORKING_OFFSET)|$(VARS_FTW_WORKING_SIZE)
> > +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> > +#
> > +#NV_FTW_WROK
> > +#
> > +DATA = {
> > +  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid         =
> > +  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
> > +  0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
> > +  0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95,
> > +  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
> > +  0x2c, 0xaf, 0x2c, 0x64, 0xFE, 0xFF, 0xFF, 0xFF,
> > +  # WriteQueueSize: UINT64
> > +  0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> > +}
> > +
> > +$(VARS_FTW_SPARE_OFFSET)|$(VARS_FTW_SPARE_SIZE)
> > +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> > +#
> > +#NV_FTW_SPARE
> > diff --git a/Platform/Bosc/XiangshanSeriesPkg/Readme.md b/Platform/Bosc/XiangshanSeriesPkg/Readme.md
> > new file mode 100644
> > index 0000000000..e64025f3ad
> > --- /dev/null
> > +++ b/Platform/Bosc/XiangshanSeriesPkg/Readme.md
> > @@ -0,0 +1,59 @@
> > +# Introduction to BOSC Xiangshan Series Platform #
> > +
> > +This document provides guidelines for building UEFI firmware for BOSC NanhuDev.
> > +BOSC NanhuDev is a 64 and processor of RISC-V architecture.
> > +BOSC NanhuDev UEFI can currently use UEFI+Opensbi firmware to successfully enter the EDK2 Shell.
> > +
> > +## How to build (X86 Linux Environment)
> > +
> > +### NanhuDev EDK2 Initial Environment  ###
> > +
> > +**statement**:The operating environment of this project is deployed on the Sophgo original environment.
> > +
> > +
> > +1. Install package on ubuntu
> > +
> > +     ```
> > +     sudo apt-get install autoconf automake autotools-dev curl python3 libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev ninja-build uuide-dev
> > +     ```
> > +
> > +2. Follow edk2-platforms/Readme.md to obtaining source code, and config build env. For Example:
> > +
> > +   ```
> > +   export WORKSPACE=/work/git/tianocore
> > +   mkdir -p $WORKSPACE
> > +   cd $WORKSPACE
> > +   git clone https://github.com/tianocore/edk2.git
> > +   cd edk2
> > +   git submodule update --init
> > +   cd ..
> > +   git clone https://github.com/tianocore/edk2-platforms.git
> > +   cd edk2-platforms
> > +   git submodule update --init
> > +   cd ..
> > +   ```
> > +
> > +3. Build
> > +
> > +   3.1 Using GCC toolchain
> > +
> > +   ```
> > +   export GCC5_RISCV64_PREFIX=riscv64-linux-gnu-
> > +   export PYTHON_COMMAND=python3
> > +   export EDK_TOOLS_PATH=$WORKSPACE/edk2/BaseTools
> > +   source edk2/edksetup.sh --reconfig
> > +   make -C edk2/BaseTools
> > +   source edk2/edksetup.sh BaseTools
> > +   build --buildtarget=DEBUG -a RISCV64 -t GCC5 -p Platform/Bosc/XiangshanSeriesPkg/NanhuDev/NanhuDev.dsc
> > +   ```
> > +
> > +4. The NANHUDEV.fd file is burned in flash and copy it to the starting address of memory.
> > +
> > +
> > +5. You can enter the EDK2 Shell.
> > +
> > +
> > +## Known Issues and Limitations
> > +This test only runs on NanhuDev with RISC-V RV64 architecture
> > +
> > +
> > diff --git a/Platform/Bosc/XiangshanSeriesPkg/XiangshanSeriesPkg.dec b/Platform/Bosc/XiangshanSeriesPkg/XiangshanSeriesPkg.dec
> > new file mode 100644
> > index 0000000000..1e81d6e25d
> > --- /dev/null
> > +++ b/Platform/Bosc/XiangshanSeriesPkg/XiangshanSeriesPkg.dec
> > @@ -0,0 +1,29 @@
> > +## @file  XiangshanSeriesPkg.dec
> > +# This Package provides modules and libraries.for BOSC Xiangshan series platforms.
> > +#
> > +#  Copyright (c) 2024, BOSC Corporation. All rights reserved.
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +##
> > +
> > +[Defines]
> > +  DEC_SPECIFICATION              = 0x0001001b
> > +  PACKAGE_NAME                   = XiangshanSeriesPkg
> > +  PACKAGE_UNI_FILE               = XiangshanSeriesPkg.uni
> > +  PACKAGE_GUID                   = 2C58ABCB-99C3-4519-96b0-EA0E4738237D
> > +  PACKAGE_VERSION                = 1.0
> > +
> > +[Includes]
> > +  Include
> > +
> > +[LibraryClasses]
> > +
> > +[Guids]
> > +
> > +[PcdsFixedAtBuild]
> > +
> > +[PcdsPatchableInModule]
> > +
> > +[UserExtensions.TianoCore."ExtraFiles"]
> > +  XiangshanSeriesPkgExtra.uni
> > diff --git a/Platform/Bosc/XiangshanSeriesPkg/XiangshanSeriesPkg.uni b/Platform/Bosc/XiangshanSeriesPkg/XiangshanSeriesPkg.uni
> > new file mode 100644
> > index 0000000000..c3a60c035b
> > --- /dev/null
> > +++ b/Platform/Bosc/XiangshanSeriesPkg/XiangshanSeriesPkg.uni
> > @@ -0,0 +1,12 @@
> > +## @file
> > +# BOSC Xiangshan Series Package Localized Strings and Content.
> > +#
> > +#  Copyright (c) 2024, BOSC. All rights reserved.
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +##
> > +
> > +#string STR_PACKAGE_ABSTRACT            #language en-US "Provides BOSC RISC-V Xiangshan series platform modules and libraries"
> > +
> > +#string STR_PACKAGE_DESCRIPTION         #language en-US "This Package BOSC RISC-V Xiangshan series platform modules and libraries."
> > diff --git a/Platform/Bosc/XiangshanSeriesPkg/XiangshanSeriesPkgExtra.uni b/Platform/Bosc/XiangshanSeriesPkg/XiangshanSeriesPkgExtra.uni
> > new file mode 100644
> > index 0000000000..15c7d85926
> > --- /dev/null
> > +++ b/Platform/Bosc/XiangshanSeriesPkg/XiangshanSeriesPkgExtra.uni
> > @@ -0,0 +1,12 @@
> > +## @file  XiangshanSeriesPkg.dec
> > +# BOSC Xiangshan Series Package Localized Strings and Content.
> > +#
> > +#  Copyright (c) 2024, BOSC. All rights reserved.
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +##
> > +
> > +#string STR_PROPERTIES_PACKAGE_NAME
> > +#language en-US
> > +"BOSC Xiangshan series platform package"
> > diff --git a/Silicon/Bosc/NanHuPkg/NanHuPkg.dec b/Silicon/Bosc/NanHuPkg/NanHuPkg.dec
> > new file mode 100644
> > index 0000000000..395f1bac76
> > --- /dev/null
> > +++ b/Silicon/Bosc/NanHuPkg/NanHuPkg.dec
> > @@ -0,0 +1,33 @@
> > +## @file
> > +#  BOSC NanHu silicon package definitions
> > +#
> > +#  Copyright (c) 2024, BOSC Corporation. All rights reserved.<BR>
> > +#
> > +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +##
> > +
> > +[Defines]
> > +  DEC_SPECIFICATION              = 0x0001001b
> > +  PACKAGE_NAME                   = NanHuSiliconPkg
> > +  PACKAGE_GUID                   = 80DE79D4-F19C-4088-97BB-D4DA70D11BC6
> > +  PACKAGE_VERSION                = 1.0
> > +
> > +[Includes]
> > +
> > +[LibraryClasses]
> > +
> > +[Guids]
> > +
> > +[Protocols]
> > +
> > +[PcdsFixedAtBuild]
> > +  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x0|UINT64|0x00001004
> > +  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|0x0|UINT64|0x00001005
> > +  gHisiTokenSpaceGuid.PcdSerialPortSendDelay|0x0|UINT32|0x00001006
> > +  gHisiTokenSpaceGuid.PcdUartClkInHz|0x0|UINT32|0x00001007
> > +
> > +[PcdsDynamic, PcdsDynamicEx]
> > +
> > +[PcdsFeatureFlag]
> > +
> > -- 
> > 2.34.1
> > 
> > 
> > 
> > 
> > 
> 
> 
> 
> 
> 


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  reply	other threads:[~2024-03-08 11:44 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <17B7F347DFE5DC11.6249@groups.io>
2024-03-08  8:31 ` [edk2-devel] [PATCH] NanhuDev:Add BOSC NanhuDev platform WangYang
2024-03-08 11:44   ` Sunil V L [this message]
     [not found]     ` <ab413a6f-f9d9-4f22-bb2a-706f0691ecd5@bosc.ac.cn>
2024-03-14  5:28       ` Sunil V L
2024-03-14  9:23         ` Ran Wang
2024-02-28  6:34 WangYang

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