From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 6B6B7740032 for ; Mon, 25 Mar 2024 18:27:33 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=DspAdyVNY+n+m5bxKRKcuHCfMXgbIn0YmXZi/cKHokE=; c=relaxed/simple; d=groups.io; h=Date:From:To:CC:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20240206; t=1711391252; v=1; b=4K68MFBOM5KNel9LNNKcoi8uZsTPMrfzCBQelYNgkOfEwfGdx/XU9Zcic+TsB+GtueD99c5Y j7BOsLp0cZ93JXUkoFHIq6UQSvwZnAS+nK3F+5F8KzxMY4xtRTB/Hp5Rji6Y54qPdpCafqffpTR DoMiMtY0dgM2MY7jAqTgXb7+05wNCZZ+N2ooVFVnF/fcIlbkLpqtYxl+JY3vNpekllNV9M5RhIT wi7oHMZ7o4auRci/33qLW0yf8kThVRiFXGcl/qnJLyrnMBSYVM/7qp4aDxTCoJqhZeVHrT6eMXy u+wIdkYZPojSHLwKpSMJow9M1ML8P8OfuWf3innRolh9g== X-Received: by 127.0.0.2 with SMTP id Ks8qYY7687511xd1v6v2QrVM; Mon, 25 Mar 2024 11:27:32 -0700 X-Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by mx.groups.io with SMTP id smtpd.web11.3011.1711391251207555648 for ; Mon, 25 Mar 2024 11:27:31 -0700 X-Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42PHrZac027382; Mon, 25 Mar 2024 18:27:31 GMT X-Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3x3626hcx3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Mar 2024 18:27:30 +0000 (GMT) X-Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 42PIRUKM014788 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Mar 2024 18:27:30 GMT X-Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 25 Mar 2024 11:27:28 -0700 Date: Mon, 25 Mar 2024 18:27:25 +0000 From: "Leif Lindholm" To: Marcin Juszkiewicz CC: , Ard Biesheuvel , Graeme Gregory , Xiong Yining , Chen Baozi Subject: Re: [edk2-devel] [PATCH edk2-platforms v9 1/4] Platform/SbsaQemu: add SbsaQemuHardwareInfoLib Message-ID: References: <20240322-no-dt-for-cpu-v9-0-92e947e0fbdf@linaro.org> <20240322-no-dt-for-cpu-v9-1-92e947e0fbdf@linaro.org> MIME-Version: 1.0 In-Reply-To: <20240322-no-dt-for-cpu-v9-1-92e947e0fbdf@linaro.org> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-ORIG-GUID: p0tfF8czUtIUX9W0MiR51XKr9rMkUUEu X-Proofpoint-GUID: p0tfF8czUtIUX9W0MiR51XKr9rMkUUEu Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Mon, 25 Mar 2024 11:27:31 -0700 Reply-To: devel@edk2.groups.io,quic_llindhol@quicinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: zomUk9JD5jaAyGrrDToVIfpDx7686176AA= Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=4K68MFBO; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=quicinc.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On Fri, Mar 22, 2024 at 17:08:47 +0100, Marcin Juszkiewicz wrote: > This library provides functions to check for hardware information. > For now it covers CPU ones: > > - amount of cpu cores > - MPIDR value for cpu core > - NUMA node id for cpu core > > Values are read from TF-A using platform specific SMC calls. > > Signed-off-by: Marcin Juszkiewicz All comments below are of the variety: "should we namespace separate this"? > --- > Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 2 + > Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 3 +- > .../SbsaQemuHardwareInfoLib.inf | 29 ++++++ > .../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h | 17 +++- > .../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h | 45 +++++++++ > .../SbsaQemuHardwareInfoLib.c | 96 ++++++++++++++++++++ > 6 files changed, 187 insertions(+), 5 deletions(-) > > diff --git a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec > index 913d1d75ef29..427ff8b31aac 100644 > --- a/Silicon/Qemu/SbsaQemu/SbsaQemu.dec > +++ b/Silicon/Qemu/SbsaQemu/SbsaQemu.dec > @@ -12,6 +12,8 @@ [Defines] > PACKAGE_GUID = 8db32c5a-2821-43e2-b4ac-bc148e2b0b05 > PACKAGE_VERSION = 0.1 > > +[LibraryClasses] > +HardwareInfoLib|Include/Library/HardwareInfoLib.h We don't *have* to address this now, but it would be worth considering what function this could have as a core, rather than platform-specific, library. What hardware? SoC or whole platform? As it stands, the name is very generic. I think we'll eventually want standardised APIs for these kinds of queries. But maybe until then it would be easier to prepend SbsaQemu to both filename and LibraryClass (like you do in the actual implementation)? > ################################################################################ > # > # Include Section - list of Include Paths that are provided by this package. > diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > index 378600050df9..3c3d2449bff4 100644 > --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > @@ -1,6 +1,6 @@ > # > # Copyright (c) 2021, NUVIA Inc. All rights reserved. > -# Copyright (c) 2019, Linaro Limited. All rights reserved. > +# Copyright (c) 2019-2024, Linaro Ltd. All rights reserved. > # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -128,6 +128,7 @@ [LibraryClasses.common] > > FdtHelperLib|Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf > OemMiscLib|Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf > + HardwareInfoLib|Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf Like you do here. > > # Debug Support > PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf > diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf > new file mode 100644 > index 000000000000..2acb2a1e7c76 > --- /dev/null > +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf > @@ -0,0 +1,29 @@ > +#/* @file > +# > +# Copyright (c) 2024, Linaro Ltd. All rights reserved. > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +#*/ > + > +[Defines] > + INF_VERSION = 0x0001001c > + BASE_NAME = SbsaQemuHardwareInfoLib > + FILE_GUID = 6454006f-6502-46e2-9be4-4bba8d4b29fb > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = HardwareInfoLib > + > +[Sources] > + SbsaQemuHardwareInfoLib.c > + > +[Packages] > + ArmPkg/ArmPkg.dec > + EmbeddedPkg/EmbeddedPkg.dec > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + Silicon/Qemu/SbsaQemu/SbsaQemu.dec > + > +[LibraryClasses] > + ArmSmcLib > + ResetSystemLib > diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h > index 7934875e4aba..2317c1f0ae69 100644 > --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h > +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h > @@ -1,6 +1,6 @@ > /** @file > * > -* Copyright (c) 2023, Linaro Ltd. All rights reserved.
> +* Copyright (c) 2023-2024, Linaro Ltd. All rights reserved.
> * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > @@ -11,8 +11,17 @@ > > #include > > -#define SIP_SVC_VERSION SMC_SIP_FUNCTION_ID(1) > -#define SIP_SVC_GET_GIC SMC_SIP_FUNCTION_ID(100) > -#define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) > +#define SIP_SVC_VERSION SMC_SIP_FUNCTION_ID(1) > +#define SIP_SVC_GET_GIC SMC_SIP_FUNCTION_ID(100) > +#define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) > +#define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200) > +#define SIP_SVC_GET_CPU_NODE SMC_SIP_FUNCTION_ID(201) > + > +/* > + * SMCC does not define return codes for SiP functions. > + * We use Architecture ones then. > + */ > + > +#define SMC_SIP_CALL_SUCCESS SMC_ARCH_CALL_SUCCESS > > #endif /* SBSA_QEMU_SMC_H_ */ > diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h > new file mode 100644 > index 000000000000..9c7281f123d2 > --- /dev/null > +++ b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h > @@ -0,0 +1,45 @@ > +/** @file > +* > +* Copyright (c) 2024, Linaro Ltd. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > + > +#ifndef HARDWARE_INFO_LIB > +#define HARDWARE_INFO_LIB Separate namespace? > + > +/** > + Get CPU count from information passed by Qemu. > + > +**/ > +UINT32 > +GetCpuCount ( Here also, "GetCpuCount", "SbsaQemuGetCpuCount" is tedious, but very clear. (Same for below functions, at least until/if we create this as a core interface.) / Leif > + VOID > + ); > + > +/** > + Get MPIDR for a given cpu from device tree passed by Qemu. > + > + @param [in] CpuId Index of cpu to retrieve MPIDR value for. > + > + @retval MPIDR value of CPU at index > +**/ > +UINT64 > +GetMpidr ( > + IN UINTN CpuId > + ); > + > +/** > + Get NUMA node id for a given cpu from device tree passed by Qemu. > + > + @param [in] CpuId Index of cpu to retrieve NUMA node id for. > + > + @retval NUMA node id for CPU at index > +**/ > +UINT64 > +GetCpuNumaNode ( > + IN UINTN CpuId > + ); > + > +#endif /* HARDWARE_INFO_LIB */ > diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c > new file mode 100644 > index 000000000000..e96328978a55 > --- /dev/null > +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c > @@ -0,0 +1,96 @@ > +/** @file > +* > +* Copyright (c) 2021, NUVIA Inc. All rights reserved. > +* Copyright (c) 2024, Linaro Ltd. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + Get CPU count from information passed by Qemu. > + > +**/ > +UINT32 > +GetCpuCount ( > + VOID > + ) > +{ > + UINTN Arg0; > + UINTN SmcResult; > + > + SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_COUNT, &Arg0, NULL, NULL); > + if (SmcResult != SMC_SIP_CALL_SUCCESS) { > + DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_COUNT call failed. We have no cpu information.\n", __FUNCTION__)); > + ResetShutdown (); > + } > + > + DEBUG ((DEBUG_INFO, "%a: We have %d cpus.\n", __FUNCTION__, Arg0)); > + > + return Arg0; > +} > + > +/** > + Get MPIDR for a given cpu from device tree passed by Qemu. > + > + @param [in] CpuId Index of cpu to retrieve MPIDR value for. > + > + @retval MPIDR value of CPU at index > +**/ > +UINT64 > +GetMpidr ( > + IN UINTN CpuId > + ) > +{ > + UINTN SmcResult; > + UINTN Arg0; > + UINTN Arg1; > + > + Arg0 = CpuId; > + > + SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_NODE, &Arg0, &Arg1, NULL); > + if (SmcResult != SMC_SIP_CALL_SUCCESS) { > + DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_NODE call failed. We have no MPIDR for CPU%d.\n", __FUNCTION__, CpuId)); > + ResetShutdown (); > + } > + > + DEBUG ((DEBUG_INFO, "%a: MPIDR for CPU%d: = %d\n", __FUNCTION__, CpuId, Arg1)); > + > + return Arg1; > +} > + > +/** > + Get NUMA node id for a given cpu from device tree passed by Qemu. > + > + @param [in] CpuId Index of cpu to retrieve NUMA node id for. > + > + @retval NUMA node id for CPU at index > +**/ > +UINT64 > +GetCpuNumaNode ( > + IN UINTN CpuId > + ) > +{ > + UINTN SmcResult; > + UINTN Arg0; > + UINTN Arg1; > + > + Arg0 = CpuId; > + > + SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_NODE, &Arg0, &Arg1, NULL); > + if (SmcResult != SMC_SIP_CALL_SUCCESS) { > + DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_NODE call failed. Could not find information for CPU%d.\n", __FUNCTION__, CpuId)); > + return 0; > + } > + > + DEBUG ((DEBUG_INFO, "%a: NUMA node for CPU%d: = %d\n", __FUNCTION__, CpuId, Arg0)); > + > + return Arg0; > +} > > -- > 2.44.0 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#117088): https://edk2.groups.io/g/devel/message/117088 Mute This Topic: https://groups.io/mt/105088436/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=-=-=-=-=-=-=-=-=-=-=-