From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id D5F77D801D3 for ; Mon, 25 Mar 2024 18:48:37 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=U2z0tFrj+mWHszASnR14E3D84hoFLSZWkDEe0ZZ7kh8=; c=relaxed/simple; d=groups.io; h=Date:From:To:CC:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20240206; t=1711392516; v=1; b=41TVH+B3UGpJA4e1qQUPAEjD1f7YfgC82pPz1/XgTv4pAnrjqEG9BkQKKyGT888DcPAnu1ZW qls/hgzYtbWK7e2jLJrfVjTMcJ8xbMXiaF4lJQrL+rqGdpFjKlz62yPMUvaVzRXGoMMIFGcR0/B DWHpg7LXYCttPODP5YzKoKYQJvYutrnp8J6eOg7Gam54ANBFqLFmP+l1oiSorZcIW7gbtPhrB7W iv0Zv8AFisumbMG5j90xk94yRwBx0rzco8k1s4MOjcqWEitSp9t9foY4W3r7PNae9qn6WggO3fW TX4ICCZlSaoE7UF8peg3R+uTBEJGEXuURw1Al4IrPkuuQ== X-Received: by 127.0.0.2 with SMTP id xoifYY7687511x00u6vcGKww; Mon, 25 Mar 2024 11:48:36 -0700 X-Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by mx.groups.io with SMTP id smtpd.web11.3516.1711392515901114472 for ; Mon, 25 Mar 2024 11:48:36 -0700 X-Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42PHdw5K027830; Mon, 25 Mar 2024 18:48:35 GMT X-Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3x3b0yrj24-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Mar 2024 18:48:34 +0000 (GMT) X-Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 42PImYVs019751 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Mar 2024 18:48:34 GMT X-Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 25 Mar 2024 11:48:32 -0700 Date: Mon, 25 Mar 2024 18:48:28 +0000 From: "Leif Lindholm" To: Marcin Juszkiewicz CC: , Ard Biesheuvel , Graeme Gregory , Xiong Yining , Chen Baozi Subject: Re: [edk2-devel] [PATCH edk2-platforms v9 4/4] Platform/SbsaQemu: get the information of memory via SMC calls Message-ID: References: <20240322-no-dt-for-cpu-v9-0-92e947e0fbdf@linaro.org> <20240322-no-dt-for-cpu-v9-4-92e947e0fbdf@linaro.org> MIME-Version: 1.0 In-Reply-To: <20240322-no-dt-for-cpu-v9-4-92e947e0fbdf@linaro.org> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-ORIG-GUID: iCJp1aV2K9jb7xDaJD1sxe4rpnTzevsb X-Proofpoint-GUID: iCJp1aV2K9jb7xDaJD1sxe4rpnTzevsb Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Mon, 25 Mar 2024 11:48:36 -0700 Reply-To: devel@edk2.groups.io,quic_llindhol@quicinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: kNZU5zWeQ3cXEZVOQmguIMklx7686176AA= Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=41TVH+B3; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=quicinc.com (policy=none) On Fri, Mar 22, 2024 at 17:08:50 +0100, Marcin Juszkiewicz wrote: > From: Xiong Yining > > Provide functions to check for memory information: > > - amount of memory nodes > - memory address > - NUMA node id for memory > > Values are read from TF-A using platform specific SMC calls. Same namespace comments as on 1/4, but given I've dragged my heels reviewing, I see no need to delay further for that. Current naming can go in, and we can worry about appropriate naming if we promote this the hwinfo library to a core interface later. You did however say this one needs reworking, so won't give r-b on this one yet. / Leif > Signed-off-by: Xiong Yining > Signed-off-by: Chen Baozi > Signed-off-by: Marcin Juszkiewicz > --- > .../SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf | 3 +- > .../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h | 2 + > .../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h | 28 ++++++++++ > .../SbsaQemuHardwareInfoLib.c | 50 ++++++++++++++++++ > .../Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c | 54 +++++--------------- > 5 files changed, 94 insertions(+), 43 deletions(-) > > diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf > index 07e6bc4e9b11..384cbb349200 100644 > --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf > +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf > @@ -32,14 +32,13 @@ [LibraryClasses] > ArmLib > BaseMemoryLib > DebugLib > + HardwareInfoLib > MemoryAllocationLib > PcdLib > - SbsaQemuHardwareInfoLib > > [Pcd] > gArmTokenSpaceGuid.PcdSystemMemoryBase > gArmTokenSpaceGuid.PcdSystemMemorySize > - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress > > [FixedPcd] > gArmTokenSpaceGuid.PcdFdBaseAddress > diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h > index 2317c1f0ae69..e3092007d27d 100644 > --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h > +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h > @@ -16,6 +16,8 @@ > #define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) > #define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200) > #define SIP_SVC_GET_CPU_NODE SMC_SIP_FUNCTION_ID(201) > +#define SIP_SVC_GET_MEMORY_NODE_COUNT SMC_SIP_FUNCTION_ID(300) > +#define SIP_SVC_GET_MEMORY_NODE SMC_SIP_FUNCTION_ID(301) > > /* > * SMCC does not define return codes for SiP functions. > diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h > index 9c7281f123d2..c7d397c590a8 100644 > --- a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h > +++ b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h > @@ -9,6 +9,12 @@ > #ifndef HARDWARE_INFO_LIB > #define HARDWARE_INFO_LIB > > +typedef struct{ > + UINT32 NodeId; > + UINT64 AddressBase; > + UINT64 AddressSize; > +} MemoryInfo; > + > /** > Get CPU count from information passed by Qemu. > > @@ -42,4 +48,26 @@ GetCpuNumaNode ( > IN UINTN CpuId > ); > > +/** > + Get the number of memory node from device tree passed by Qemu. > + > + @retval the number of memory nodes. > +**/ > +UINT32 > +GetMemNodeCount ( > + VOID > + ); > + > +/** > + Get memory infomation(node-id, addressbase, addresssize) for a given memory node from device tree passed by Qemu. > + > + @param [in] MemoryId Index of memory to retrieve memory information. > + > + @retval memory infomation for given memory node. > +**/ > +MemoryInfo > +GetMemInfo ( > + IN UINTN MemoryId > + ); > + > #endif /* HARDWARE_INFO_LIB */ > diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c > index e96328978a55..4f49ae7e1862 100644 > --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c > +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c > @@ -94,3 +94,53 @@ GetCpuNumaNode ( > > return Arg0; > } > + > +UINT32 > +GetMemNodeCount ( > + VOID > + ) > +{ > + UINTN SmcResult; > + UINTN Arg0; > + > + SmcResult = ArmCallSmc0 (SIP_SVC_GET_MEMORY_NODE_COUNT, &Arg0, NULL, NULL); > + if (SmcResult != SMC_SIP_CALL_SUCCESS) { > + DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_MEMORY_NODE_COUNT call failed. We have no memory information.\n", __FUNCTION__)); > + ResetShutdown (); > + } > + > + DEBUG (( DEBUG_INFO, "%a: The number of the memory nodes is %ld\n", __FUNCTION__, Arg0)); > + return (UINT32)Arg0; > +} > + > +MemoryInfo > +GetMemInfo ( > + IN UINTN MemoryId > + ) > +{ > + UINTN SmcResult; > + UINTN Arg0; > + UINTN Arg1; > + UINTN Arg2; > + MemoryInfo MemInfo; > + > + Arg0 = MemoryId; > + > + SmcResult = ArmCallSmc1 (SIP_SVC_GET_MEMORY_NODE, &Arg0, &Arg1, &Arg2); > + if (SmcResult != SMC_SIP_CALL_SUCCESS) { > + DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_MEMORY_NODE call failed. We have no memory information.\n", __FUNCTION__)); > + ResetShutdown (); > + } else { > + MemInfo.NodeId = Arg0; > + MemInfo.AddressBase = Arg1; > + MemInfo.AddressSize = Arg2; > + } > + > + DEBUG(( DEBUG_INFO, "%a: NUMA node for System RAM:%d = 0x%lx - 0x%lx\n", > + __FUNCTION__, > + MemInfo.NodeId, > + MemInfo.AddressBase, > + MemInfo.AddressBase + MemInfo.AddressSize -1 )); > + > + return MemInfo; > +} > diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c > index 8c2eb0b6a028..264ca9acb203 100644 > --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c > +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c > @@ -12,7 +12,7 @@ > #include > #include > #include > -#include > +#include > > // Number of Virtual Memory Map Descriptors > #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 4 > @@ -23,53 +23,25 @@ SbsaQemuLibConstructor ( > VOID > ) > { > - VOID *DeviceTreeBase; > - INT32 Node, Prev; > UINT64 NewBase, CurBase; > UINT64 NewSize, CurSize; > - CONST CHAR8 *Type; > - INT32 Len; > - CONST UINT64 *RegProp; > + UINT32 NumMemNodes; > + UINT32 Index; > + MemoryInfo MemInfo; > RETURN_STATUS PcdStatus; > > NewBase = 0; > NewSize = 0; > > - DeviceTreeBase = (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); > - ASSERT (DeviceTreeBase != NULL); > - > - // Make sure we have a valid device tree blob > - ASSERT (fdt_check_header (DeviceTreeBase) == 0); > - > - // Look for the lowest memory node > - for (Prev = 0;; Prev = Node) { > - Node = fdt_next_node (DeviceTreeBase, Prev, NULL); > - if (Node < 0) { > - break; > - } > - > - // Check for memory node > - Type = fdt_getprop (DeviceTreeBase, Node, "device_type", &Len); > - if (Type && AsciiStrnCmp (Type, "memory", Len) == 0) { > - // Get the 'reg' property of this node. For now, we will assume > - // two 8 byte quantities for base and size, respectively. > - RegProp = fdt_getprop (DeviceTreeBase, Node, "reg", &Len); > - if (RegProp != 0 && Len == (2 * sizeof (UINT64))) { > - > - CurBase = fdt64_to_cpu (ReadUnaligned64 (RegProp)); > - CurSize = fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); > - > - DEBUG ((DEBUG_INFO, "%a: System RAM @ 0x%lx - 0x%lx\n", > - __FUNCTION__, CurBase, CurBase + CurSize - 1)); > - > - if (NewBase > CurBase || NewBase == 0) { > - NewBase = CurBase; > - NewSize = CurSize; > - } > - } else { > - DEBUG ((DEBUG_ERROR, "%a: Failed to parse FDT memory node\n", > - __FUNCTION__)); > - } > + NumMemNodes = GetMemNodeCount(); > + for(Index = 0; Index < NumMemNodes; Index++){ > + MemInfo = GetMemInfo(Index); > + CurBase = MemInfo.AddressBase; > + CurSize = MemInfo.AddressSize; > + > + if (NewBase > CurBase || NewBase == 0) { > + NewBase = CurBase; > + NewSize = CurSize; > } > } > > > -- > 2.44.0 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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