From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 14E2D74004D for ; Thu, 28 Mar 2024 12:59:11 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=ZeyeCWBhspe+vf2QKvVDNWPBIpCX6pdPEdo0BybpXqU=; c=relaxed/simple; d=groups.io; h=Date:From:To:CC:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20240206; t=1711630750; v=1; b=x1gkcp7ANCyGVOIh0iqKAFNWzgaZL91MHIkVD/acpQoMI8k22kk3cTTdtlyGG3usbhy3ob2R A28QlDfuFOEr9k3348napTxxWtWWxsZ/fW3cK5oWSxb/4/FhvrRd7VT+fFzEewyg8FZHhzhPHND qvjB0oyfFTy8HUc5dz6oBsEAiBSh+Qv+ULgjkMk+4GAjrw3AoOKddhAByxhwTY2qODzajdMyXIQ S0Akt4ZEIBcFUjaELTNBxam+LVf00bRFEuJmQMFH2TTuJckIdkQglCG0FeOM7Pkqp8Ldfm2GnVf GJwZCUNuUZSMfmOTadocr1APDtVe4hDU1KiAVloL2b4uw== X-Received: by 127.0.0.2 with SMTP id o8A7YY7687511xwlizhEiFrW; Thu, 28 Mar 2024 05:59:10 -0700 X-Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by mx.groups.io with SMTP id smtpd.web11.15118.1711630750018563837 for ; Thu, 28 Mar 2024 05:59:10 -0700 X-Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 42SAVYFm006037; Thu, 28 Mar 2024 12:59:09 GMT X-Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3x53nxh7jk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Mar 2024 12:59:09 +0000 (GMT) X-Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 42SCx8O3020225 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Mar 2024 12:59:08 GMT X-Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 28 Mar 2024 05:59:07 -0700 Date: Thu, 28 Mar 2024 12:59:03 +0000 From: "Leif Lindholm" To: Xiong Yining CC: , , , , Subject: Re: [edk2-devel] [PATCH v11 2/4] Platform/SbsaQemu: use SbsaQemuHardwareInfoLib for cpu information Message-ID: References: <20240328074630.3817643-1-xiongyining1480@phytium.com.cn> <20240328074630.3817643-3-xiongyining1480@phytium.com.cn> MIME-Version: 1.0 In-Reply-To: <20240328074630.3817643-3-xiongyining1480@phytium.com.cn> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-GUID: yHxUrCJZ2KLe84FzZGNBi7By5PhkE3Dt X-Proofpoint-ORIG-GUID: yHxUrCJZ2KLe84FzZGNBi7By5PhkE3Dt Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Thu, 28 Mar 2024 05:59:10 -0700 Reply-To: devel@edk2.groups.io,quic_llindhol@quicinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: asZWMjre1Panypa0Mgv72Nw1x7686176AA= Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=x1gkcp7A; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=quicinc.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On Thu, Mar 28, 2024 at 07:46:28 +0000, Xiong Yining wrote: > From: Marcin Juszkiewicz > > We have SbsaQemuHardwareInfoLib to ask for hardware details. No need to > parse DeviceTree anymore. > > Signed-off-by: Marcin Juszkiewicz > Signed-off-by: Xiong Yining > Reviewed-by: Leif Lindholm > --- > .../Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf | 6 ++---- > .../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 5 ++--- > .../Library/SbsaQemuLib/SbsaQemuLib.inf | 4 ++-- > .../Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c | 11 +++++----- > .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 21 +++++++------------ > 5 files changed, 18 insertions(+), 29 deletions(-) > Two mistakes in this file breaks bisect again, this time between 2/4 and 3/4. > diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf > index c067a80cc715..07e6bc4e9b11 100644 > --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf > +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.inf > @@ -1,6 +1,6 @@ > #/* @file > # > -# Copyright (c) 2019, Linaro Limited. All rights reserved. > +# Copyright (c) 2019-2024, Linaro Limited. All rights reserved. > # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -32,9 +32,9 @@ > ArmLib > BaseMemoryLib > DebugLib > - FdtLib 1) We don't update the memory discovery to use HardwareInfoLib until the next commit. > MemoryAllocationLib > PcdLib > + SbsaQemuHardwareInfoLib 2) This is now just called HardwareInfoLib. I really don't want to see a v12, so I have fixed this up locally and pushed this set as 8e5981584663..4e77c070c070. Thanks! (But please be more careful with bisect breakage in future.) / Leif > > [Pcd] > gArmTokenSpaceGuid.PcdSystemMemoryBase > diff --git a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c > index c38f2851904f..854f6f4072d5 100644 > --- a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c > +++ b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c > @@ -2,7 +2,7 @@ > * OemMiscLib.c > * > * Copyright (c) 2021, NUVIA Inc. All rights reserved. > -* Copyright (c) 2020, Linaro Ltd. All rights reserved. > +* Copyright (c) 2020-2024, Linaro Ltd. All rights reserved. > * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > @@ -12,14 +12,13 @@ > #include > #include > #include > -#include > #include > #include > #include > #include > +#include > #include > #include > -#include > > /** Returns whether the specified processor is present or not. > > @@ -33,7 +32,7 @@ OemIsProcessorPresent ( > UINTN ProcessorIndex > ) > { > - if (ProcessorIndex < FdtHelperCountCpus ()) { > + if (ProcessorIndex < GetCpuCount ()) { > return TRUE; > } > > @@ -76,7 +75,7 @@ OemGetProcessorInformation ( > { > UINT16 ProcessorCount; > > - ProcessorCount = FdtHelperCountCpus (); > + ProcessorCount = GetCpuCount (); > > if (ProcessorIndex < ProcessorCount) { > ProcessorStatus->Bits.CpuStatus = 1; // CPU enabled > @@ -121,7 +120,7 @@ OemGetMaxProcessors ( > VOID > ) > { > - return FdtHelperCountCpus (); > + return GetCpuCount (); > } > > /** Gets information about the cache at the specified cache level. > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > index 9fb17151d7b8..4ebe2a445344 100644 > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > @@ -1,7 +1,7 @@ > /** @file > * This file is an ACPI driver for the Qemu SBSA platform. > * > -* Copyright (c) 2020, Linaro Ltd. All rights reserved. > +* Copyright (c) 2020-2024, Linaro Ltd. All rights reserved. > * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > @@ -15,10 +15,10 @@ > #include > #include > #include > -#include > #include > #include > #include > +#include > #include > #include > #include > @@ -255,8 +255,7 @@ AddMadtTable ( > // Initialize GIC Redistributor Structure > EFI_ACPI_6_0_GICR_STRUCTURE Gicr = SBSAQEMU_MADT_GICR_INIT(); > > - // Get CoreCount which was determined eariler after parsing device tree > - NumCores = PcdGet32 (PcdCoreCount); > + NumCores = GetCpuCount (); > > // Calculate the new table size based on the number of cores > TableSize = sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER) + > @@ -291,13 +290,13 @@ AddMadtTable ( > New += sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER); > > // Add new GICC structures for the Cores > - for (CoreIndex = 0; CoreIndex < PcdGet32 (PcdCoreCount); CoreIndex++) { > + for (CoreIndex = 0; CoreIndex < NumCores; CoreIndex++) { > EFI_ACPI_6_0_GIC_STRUCTURE *GiccPtr; > > CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_STRUCTURE)); > GiccPtr = (EFI_ACPI_6_0_GIC_STRUCTURE *) New; > GiccPtr->AcpiProcessorUid = CoreIndex; > - GiccPtr->MPIDR = FdtHelperGetMpidr (CoreIndex); > + GiccPtr->MPIDR = GetMpidr (CoreIndex); > New += sizeof (EFI_ACPI_6_0_GIC_STRUCTURE); > } > > @@ -396,7 +395,7 @@ AddSsdtTable ( > UINT32 CpuId; > UINT32 Offset; > UINT8 ScopeOpName[] = SBSAQEMU_ACPI_SCOPE_NAME; > - UINT32 NumCores = PcdGet32 (PcdCoreCount); > + UINT32 NumCores = GetCpuCount (); > > EFI_ACPI_DESCRIPTION_HEADER Header = > SBSAQEMU_ACPI_HEADER ( > @@ -497,7 +496,7 @@ AddPpttTable ( > EFI_PHYSICAL_ADDRESS PageAddress; > UINT8 *New; > UINT32 CpuId; > - UINT32 NumCores = PcdGet32 (PcdCoreCount); > + UINT32 NumCores = GetCpuCount (); > > EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT; > EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT; > @@ -758,12 +757,6 @@ InitializeSbsaQemuAcpiDxe ( > { > EFI_STATUS Status; > EFI_ACPI_TABLE_PROTOCOL *AcpiTable; > - UINT32 NumCores; > - > - // Parse the device tree and get the number of CPUs > - NumCores = FdtHelperCountCpus (); > - Status = PcdSet32S (PcdCoreCount, NumCores); > - ASSERT_RETURN_ERROR (Status); > > // Check if ACPI Table Protocol has been installed > Status = gBS->LocateProtocol ( > -- > 2.34.1 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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