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From: "Sunil V L" <sunilvl@ventanamicro.com>
To: "dylanlhdu(杜林恒)" <dylanlhdu@tencent.com>
Cc: devel <devel@edk2.groups.io>, gaoliming <gaoliming@byosoft.com.cn>
Subject: Re: 回复:[Internet]Re: [edk2-devel] [PATCH] Added support for ACPI related data structures for RISC_V64 platform
Date: Thu, 9 May 2024 14:05:45 +0530	[thread overview]
Message-ID: <ZjyK4WNUac5/bjdF@sunil-laptop> (raw)
In-Reply-To: <tencent_13F44E2D19B01A716BA59420@qq.com>

On Mon, May 06, 2024 at 10:54:45AM +0800, dylanlhdu(杜林恒) wrote:
> Hi Sunil,
> 
> 
> 
> We mainly want to use UEFI+ACPI mode to start RISCV64 server. However, during the development process, we found that ACPI(6.5) in the current version of UEFI does not support riscv for the time being. In order to solve this problem, We refer to the upstream RISC-V ACPI platform specification provided by Ventana to implement RISC-V ACPI support, so adding this header file can make ACPI support RISCV architecture until the new version of ACPI specification supports RISCV architecture.
> 
Understood. But adding as 6_5* doesn't make sense.

I will let maintainers of MdePkg to comment. I don't know
whether they can accept approved ECRs but not yet released spec.

Thanks,
Sunil

> 
> 
> 
> 
> 
> 
> Thanks
> 
> 
> 
> 
> 发自我的企业微信
> 
> 
> 
> 
> 
>              ----------回复的邮件信息----------
>        Sunil V L<sunilvl@ventanamicro.com&gt;&nbsp;在 2024-04-30 周二 20:02 写道:
> 
> Hi Lingheng Du,
> 
> What is the use of adding this header file and how did you create it? I
> think EDK2 needs ACPI spec to be released to get these definitions
> added. Also, these are not part of 6.5 and hence names like
> EFI_ACPI_6_5* are incorrect. So, it will be helpful if you add some
> commit message why do we need this header.
> 
> Thanks,
> Sunil
> On Mon, Apr 29, 2024 at 05:53:55PM +0800, gaoliming via groups.io wrote:
> &gt; From: dylanlhdu <dylanlhdu@tencent.com&gt;
> &gt; 
> &gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Signed-off-by: Lingheng Du <dylanlhdu@tencent.com&gt;
> &gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Reviewed-by: Song Huang&nbsp; <vicshuang@tencent.com&gt;
> &gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Reviewed-by: Bing Fan <tombinfan@tencent.com&gt;
> &gt; ---
> &gt;&nbsp; .../Include/IndustryStandard/AcpiRiscv64.h&nbsp;&nbsp;&nbsp; | 176 ++++++++++++++++++
> &gt;&nbsp; 1 file changed, 176 insertions(+)
> &gt;&nbsp; create mode 100644 edk2/MdePkg/Include/IndustryStandard/AcpiRiscv64.h
> &gt; 
> &gt; diff --git a/edk2/MdePkg/Include/IndustryStandard/AcpiRiscv64.h b/edk2/MdePkg/Include/IndustryStandard/AcpiRiscv64.h
> &gt; new file mode 100644
> &gt; index 00000000..4111b3ea
> &gt; --- /dev/null
> &gt; +++ b/edk2/MdePkg/Include/IndustryStandard/AcpiRiscv64.h
> &gt; @@ -0,0 +1,176 @@
> &gt; +/** @file
> &gt; +&nbsp; RISCV64 platform ACPI related support April, 2022.
> &gt; +
> &gt; +&nbsp; SPDX-License-Identifier: BSD-2-Clause-Patent
> &gt; +**/
> &gt; +
> &gt; +#ifndef ACPI_RISCV64_H_
> &gt; +#define ACPI_RISCV64_H_
> &gt; +
> &gt; +//
> &gt; +// Ensure proper structure formats
> &gt; +//
> &gt; +#pragma pack(1)
> &gt; +
> &gt; +///
> &gt; +/// RISC-V Interrupt Type
> &gt; +///
> &gt; +#define EFI_ACPI_6_5_INC_RINTC_TYPE&nbsp; 0x18
> &gt; +#define EFI_ACPI_6_5_INC_IMSIC_TYPE&nbsp; 0x19
> &gt; +#define EFI_ACPI_6_5_INC_APLIC_TYPE&nbsp; 0x1A
> &gt; +#define EFI_ACPI_6_5_INC_PLIC_TYPE&nbsp;&nbsp; 0x1B
> &gt; +
> &gt; +///
> &gt; +///&nbsp; RISC-V Interrupt Controller (RINTC)
> &gt; +///
> &gt; +typedef struct {
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; Type;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; Length;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; Version;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; Reserved;
> &gt; +&nbsp; UINT32&nbsp;&nbsp;&nbsp; Flags;
> &gt; +&nbsp; UINT64&nbsp;&nbsp;&nbsp; HartId;
> &gt; +&nbsp; UINT32&nbsp;&nbsp;&nbsp; Uid;
> &gt; +&nbsp; UINT32&nbsp;&nbsp;&nbsp; ExtIntcId;
> &gt; +&nbsp; UINT64&nbsp;&nbsp;&nbsp; ImsicAddr;
> &gt; +&nbsp; UINT32&nbsp;&nbsp;&nbsp; ImsicSize;
> &gt; +} EFI_ACPI_6_5_INC_RINTC_STRUCTURE;
> &gt; +
> &gt; +///
> &gt; +///&nbsp; Incoming MSI Controller (IMSIC)
> &gt; +///
> &gt; +typedef struct {
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; Type;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; Length;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; Version;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; Reserved;
> &gt; +&nbsp; UINT32&nbsp;&nbsp;&nbsp; Flags;
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; NumIds;
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; NumGuestIds;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; GuestIndexBits;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; HartIndexBits;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; GroupIndexBits;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; GroupIndexShift;
> &gt; +} EFI_ACPI_6_5_INC_IMSIC_STRUCTURE;
> &gt; +
> &gt; +///
> &gt; +///&nbsp; RISC-V Advanced Platform Level Interrupt Controller (APLIC)
> &gt; +///
> &gt; +typedef struct {
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; Type;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; Length;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; Version;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; AplicId;
> &gt; +&nbsp; UINT32&nbsp;&nbsp;&nbsp; Flags;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; HW_ID[8];
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; NumIdc;
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; ExternSoureceSupport;
> &gt; +&nbsp; UINT32&nbsp;&nbsp;&nbsp; GSysInterruptBase;
> &gt; +&nbsp; UINT64&nbsp;&nbsp;&nbsp; AplicAddress;
> &gt; +&nbsp; UINT32&nbsp;&nbsp;&nbsp; AplicSize;
> &gt; +} EFI_ACPI_6_5_INC_APLIC_STRUCTURE;
> &gt; +
> &gt; +///
> &gt; +///&nbsp;&nbsp; RISC-V Platform Level Interrupt Controller (PLIC)
> &gt; +///
> &gt; +typedef struct {
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; Type;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; Length;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; Version;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; PlicId;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; HwId[8];
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; NumIrqs;
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; MaxPrio;
> &gt; +&nbsp; UINT32&nbsp;&nbsp;&nbsp; Flags;
> &gt; +&nbsp; UINT32&nbsp;&nbsp;&nbsp; PlicSize;
> &gt; +&nbsp; UINT64&nbsp;&nbsp;&nbsp; PlicAddress;
> &gt; +&nbsp; UINT32&nbsp;&nbsp;&nbsp; GsiBase;
> &gt; +} EFI_ACPI_6_5_INC_PLIC_STRUCTURE;
> &gt; +
> &gt; +///
> &gt; +/// RISC-V Hart Capabilities Table (RHCT)
> &gt; +///
> &gt; +typedef struct {
> &gt; +&nbsp; EFI_ACPI_DESCRIPTION_HEADER&nbsp;&nbsp;&nbsp; Header;
> &gt; +} EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER;
> &gt; +
> &gt; +///
> &gt; +/// RHCT Revision
> &gt; +///
> &gt; +#define EFI_ACPI_6_5_RHCT_APIC_DESCRIPTION_TABLE_REVISION&nbsp; 0x05
> &gt; +
> &gt; +///
> &gt; +/// RHCT types
> &gt; +///
> &gt; +#define EFI_ACPI_6_5_NODE_ISA_TYPE&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0x0
> &gt; +#define EFI_ACPI_6_5_NODE_CM0_TYPE&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0x1
> &gt; +#define EFI_ACPI_6_5_NODE_MMU_TYPE&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0x2
> &gt; +#define EFI_ACPI_6_5_NODE_RESERVED_TYPE&nbsp; 0x3
> &gt; +#define EFI_ACPI_6_5_NODE_HART_TYPE&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0xFFFF
> &gt; +
> &gt; +///
> &gt; +/// RHCT Flags
> &gt; +///
> &gt; +#define ACPI_RHCT_TIMER_CANNOT_WAKEUP_CPU&nbsp; (1)
> &gt; +
> &gt; +///
> &gt; +/// ISA string node
> &gt; +///
> &gt; +typedef struct {
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; Type;
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; Length;
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; Revision;
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; IsaLength;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; IsaString[];
> &gt; +} EFI_ACPI_6_5_NODE_ISA_STRING_STRUCTURE;
> &gt; +
> &gt; +///
> &gt; +/// CM0 node
> &gt; +///
> &gt; +typedef struct {
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; Type;
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; Length;
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; Revision;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; Reserved;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; CbomSize;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; CbopSize;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; CbozSize;
> &gt; +} EFI_ACPI_6_5_NODE_CM0_STRUCTURE;
> &gt; +
> &gt; +///
> &gt; +/// MMU node
> &gt; +///
> &gt; +typedef struct {
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; Type;
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; Length;
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; Revision;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; Reserved;
> &gt; +&nbsp; UINT8&nbsp;&nbsp;&nbsp;&nbsp; MmuType;
> &gt; +} EFI_ACPI_6_5_NODE_MMU_STRUCTURE;
> &gt; +
> &gt; +///
> &gt; +/// MMU type
> &gt; +///
> &gt; +#define EFI_ACPI_6_5_MMU_SV39_TYPE&nbsp; 0x0
> &gt; +#define EFI_ACPI_6_5_MMU_SV48_TYPE&nbsp; 0x1
> &gt; +#define EFI_ACPI_6_5_MMU_SV57_TYPE&nbsp; 0x2
> &gt; +
> &gt; +///
> &gt; +/// Hart Info Node
> &gt; +///
> &gt; +typedef struct {
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; Type;
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; Length;
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; Revision;
> &gt; +&nbsp; UINT16&nbsp;&nbsp;&nbsp; NumOffsets;
> &gt; +&nbsp; UINT32&nbsp;&nbsp;&nbsp; Uid;
> &gt; +} EFI_ACPI_6_5_NODE_HARTINFO_STRUCTURE;
> &gt; +
> &gt; +///
> &gt; +/// "RHCT" RISC-V Hart Capabilities Table
> &gt; +///
> &gt; +#define EFI_ACPI_6_5_RHCT_HART_DESCRIPTION_TABLE_SIGNATURE&nbsp; SIGNATURE_32('R', 'H', 'C', 'T')
> &gt; +
> &gt; +#pragma pack()
> &gt; +
> &gt; +#endif
> &gt; \ No newline at end of file
> &gt; -- 
> &gt; 2.34.1
> &gt; 
> &gt; 
> &gt; 
> &gt; 
> &gt; 
> &gt; 
> &gt;


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  reply	other threads:[~2024-05-09  8:36 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-06  2:54 回复:[Internet]Re: [edk2-devel] [PATCH] Added support for ACPI related data structures for RISC_V64 platform "dylanlhdu(杜林恒) via groups.io
2024-05-09  8:35 ` Sunil V L [this message]
2024-05-09  9:06   ` 回复: " gaoliming via groups.io

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