From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id C23CEAC0EA9 for ; Thu, 9 May 2024 08:36:42 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=mdDv/YRiGXQqPVwo5/Pb6zCDJoA5odVjJjJgKPuDZBo=; c=relaxed/simple; d=groups.io; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition:Content-Transfer-Encoding; s=20240206; t=1715243801; v=1; b=gHEFjrGL5Ub7XQdkoMfPJeKeFB+r0/8DC+yVV3QfnZKS0Gcsy6lM82GcXFlgwBH4YARn+FXS 4xDotm8L7X0IFpZYSNYCkVSwCa+qgNKxYh5sV942WvuCThEqujBsmhi3B8b5CCZSAXJwPQDR+Fu Fo5Dtt5W/jz7o7p2yXRVaZVieuGxptz2nJ01ifSE0iLVAa5uCTBKjhsnaYdsw1k+5XvVOfkP1EU 4O2uBX97pYo3U8B3sl1ZRdxC2lgunn/6goztQJiqQzDn0mB0bBZm3Yufo0ZtnTiNLlPfY1zInBc dAxdsEHTEv/RlMJSJK//rPo3XGBc8da0A7cME90EZyLcQ== X-Received: by 127.0.0.2 with SMTP id xjhjYY7687511x9h9W7VSGsN; Thu, 09 May 2024 01:36:41 -0700 X-Received: from mail-oi1-f180.google.com (mail-oi1-f180.google.com [209.85.167.180]) by mx.groups.io with SMTP id smtpd.web11.5346.1715243800464707742 for ; Thu, 09 May 2024 01:36:40 -0700 X-Received: by mail-oi1-f180.google.com with SMTP id 5614622812f47-3c97dab75bbso366436b6e.0 for ; Thu, 09 May 2024 01:36:40 -0700 (PDT) X-Gm-Message-State: dUXAHMPjhuKJkfKwTspYe9pqx7686176AA= X-Google-Smtp-Source: AGHT+IFBisKXhOwj4QII/2zFUHSgLTGOlkMHff4IqWSQQ6dqKofBngyMOr+H76EWtzrINDHIA7z/Tw== X-Received: by 2002:a05:6808:634e:b0:3c9:6c1f:64f8 with SMTP id 5614622812f47-3c9852c37b5mr4966520b6e.33.1715243799662; Thu, 09 May 2024 01:36:39 -0700 (PDT) X-Received: from sunil-laptop ([106.51.188.31]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-6f0e01b6d98sm167523a34.29.2024.05.09.01.36.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 May 2024 01:36:39 -0700 (PDT) Date: Thu, 9 May 2024 14:05:45 +0530 From: "Sunil V L" To: =?utf-8?B?ZHlsYW5saGR1KOadnOael+aBkik=?= Cc: devel , gaoliming Subject: =?UTF-8?B?UmU6IOWbnuWkje+8mltJbnRlcm5ldF1SZTogW2VkazItZGV2ZWxdIFtQQVRDSF0gQWRkZWQgc3VwcG9ydCBmb3IgQUNQSSByZWxhdGVkIGRhdGEgc3RydWN0dXJlcyBmb3IgUklTQ19WNjQgcGxhdGZvcm0=?= Message-ID: References: MIME-Version: 1.0 In-Reply-To: Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Thu, 09 May 2024 01:36:40 -0700 Resent-From: sunilvl@ventanamicro.com Reply-To: devel@edk2.groups.io,sunilvl@ventanamicro.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=gHEFjrGL; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io On Mon, May 06, 2024 at 10:54:45AM +0800, dylanlhdu(杜林恒) wrote: > Hi Sunil, > > > > We mainly want to use UEFI+ACPI mode to start RISCV64 server. However, during the development process, we found that ACPI(6.5) in the current version of UEFI does not support riscv for the time being. In order to solve this problem, We refer to the upstream RISC-V ACPI platform specification provided by Ventana to implement RISC-V ACPI support, so adding this header file can make ACPI support RISCV architecture until the new version of ACPI specification supports RISCV architecture. > Understood. But adding as 6_5* doesn't make sense. I will let maintainers of MdePkg to comment. I don't know whether they can accept approved ECRs but not yet released spec. Thanks, Sunil > > > > > > > Thanks > > > > > 发自我的企业微信 > > > > > > ----------回复的邮件信息---------- > Sunil V L > Hi Lingheng Du, > > What is the use of adding this header file and how did you create it? I > think EDK2 needs ACPI spec to be released to get these definitions > added. Also, these are not part of 6.5 and hence names like > EFI_ACPI_6_5* are incorrect. So, it will be helpful if you add some > commit message why do we need this header. > > Thanks, > Sunil > On Mon, Apr 29, 2024 at 05:53:55PM +0800, gaoliming via groups.io wrote: > > From: dylanlhdu > > >         Signed-off-by: Lingheng Du >         Reviewed-by: Song Huang  >         Reviewed-by: Bing Fan > --- > >  .../Include/IndustryStandard/AcpiRiscv64.h    | 176 ++++++++++++++++++ > >  1 file changed, 176 insertions(+) > >  create mode 100644 edk2/MdePkg/Include/IndustryStandard/AcpiRiscv64.h > > > > diff --git a/edk2/MdePkg/Include/IndustryStandard/AcpiRiscv64.h b/edk2/MdePkg/Include/IndustryStandard/AcpiRiscv64.h > > new file mode 100644 > > index 00000000..4111b3ea > > --- /dev/null > > +++ b/edk2/MdePkg/Include/IndustryStandard/AcpiRiscv64.h > > @@ -0,0 +1,176 @@ > > +/** @file > > +  RISCV64 platform ACPI related support April, 2022. > > + > > +  SPDX-License-Identifier: BSD-2-Clause-Patent > > +**/ > > + > > +#ifndef ACPI_RISCV64_H_ > > +#define ACPI_RISCV64_H_ > > + > > +// > > +// Ensure proper structure formats > > +// > > +#pragma pack(1) > > + > > +/// > > +/// RISC-V Interrupt Type > > +/// > > +#define EFI_ACPI_6_5_INC_RINTC_TYPE  0x18 > > +#define EFI_ACPI_6_5_INC_IMSIC_TYPE  0x19 > > +#define EFI_ACPI_6_5_INC_APLIC_TYPE  0x1A > > +#define EFI_ACPI_6_5_INC_PLIC_TYPE   0x1B > > + > > +/// > > +///  RISC-V Interrupt Controller (RINTC) > > +/// > > +typedef struct { > > +  UINT8     Type; > > +  UINT8     Length; > > +  UINT8     Version; > > +  UINT8     Reserved; > > +  UINT32    Flags; > > +  UINT64    HartId; > > +  UINT32    Uid; > > +  UINT32    ExtIntcId; > > +  UINT64    ImsicAddr; > > +  UINT32    ImsicSize; > > +} EFI_ACPI_6_5_INC_RINTC_STRUCTURE; > > + > > +/// > > +///  Incoming MSI Controller (IMSIC) > > +/// > > +typedef struct { > > +  UINT8     Type; > > +  UINT8     Length; > > +  UINT8     Version; > > +  UINT8     Reserved; > > +  UINT32    Flags; > > +  UINT16    NumIds; > > +  UINT16    NumGuestIds; > > +  UINT8     GuestIndexBits; > > +  UINT8     HartIndexBits; > > +  UINT8     GroupIndexBits; > > +  UINT8     GroupIndexShift; > > +} EFI_ACPI_6_5_INC_IMSIC_STRUCTURE; > > + > > +/// > > +///  RISC-V Advanced Platform Level Interrupt Controller (APLIC) > > +/// > > +typedef struct { > > +  UINT8     Type; > > +  UINT8     Length; > > +  UINT8     Version; > > +  UINT8     AplicId; > > +  UINT32    Flags; > > +  UINT8     HW_ID[8]; > > +  UINT16    NumIdc; > > +  UINT16    ExternSoureceSupport; > > +  UINT32    GSysInterruptBase; > > +  UINT64    AplicAddress; > > +  UINT32    AplicSize; > > +} EFI_ACPI_6_5_INC_APLIC_STRUCTURE; > > + > > +/// > > +///   RISC-V Platform Level Interrupt Controller (PLIC) > > +/// > > +typedef struct { > > +  UINT8     Type; > > +  UINT8     Length; > > +  UINT8     Version; > > +  UINT8     PlicId; > > +  UINT8     HwId[8]; > > +  UINT16    NumIrqs; > > +  UINT16    MaxPrio; > > +  UINT32    Flags; > > +  UINT32    PlicSize; > > +  UINT64    PlicAddress; > > +  UINT32    GsiBase; > > +} EFI_ACPI_6_5_INC_PLIC_STRUCTURE; > > + > > +/// > > +/// RISC-V Hart Capabilities Table (RHCT) > > +/// > > +typedef struct { > > +  EFI_ACPI_DESCRIPTION_HEADER    Header; > > +} EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER; > > + > > +/// > > +/// RHCT Revision > > +/// > > +#define EFI_ACPI_6_5_RHCT_APIC_DESCRIPTION_TABLE_REVISION  0x05 > > + > > +/// > > +/// RHCT types > > +/// > > +#define EFI_ACPI_6_5_NODE_ISA_TYPE       0x0 > > +#define EFI_ACPI_6_5_NODE_CM0_TYPE       0x1 > > +#define EFI_ACPI_6_5_NODE_MMU_TYPE       0x2 > > +#define EFI_ACPI_6_5_NODE_RESERVED_TYPE  0x3 > > +#define EFI_ACPI_6_5_NODE_HART_TYPE      0xFFFF > > + > > +/// > > +/// RHCT Flags > > +/// > > +#define ACPI_RHCT_TIMER_CANNOT_WAKEUP_CPU  (1) > > + > > +/// > > +/// ISA string node > > +/// > > +typedef struct { > > +  UINT16    Type; > > +  UINT16    Length; > > +  UINT16    Revision; > > +  UINT16    IsaLength; > > +  UINT8     IsaString[]; > > +} EFI_ACPI_6_5_NODE_ISA_STRING_STRUCTURE; > > + > > +/// > > +/// CM0 node > > +/// > > +typedef struct { > > +  UINT16    Type; > > +  UINT16    Length; > > +  UINT16    Revision; > > +  UINT8     Reserved; > > +  UINT8     CbomSize; > > +  UINT8     CbopSize; > > +  UINT8     CbozSize; > > +} EFI_ACPI_6_5_NODE_CM0_STRUCTURE; > > + > > +/// > > +/// MMU node > > +/// > > +typedef struct { > > +  UINT16    Type; > > +  UINT16    Length; > > +  UINT16    Revision; > > +  UINT8     Reserved; > > +  UINT8     MmuType; > > +} EFI_ACPI_6_5_NODE_MMU_STRUCTURE; > > + > > +/// > > +/// MMU type > > +/// > > +#define EFI_ACPI_6_5_MMU_SV39_TYPE  0x0 > > +#define EFI_ACPI_6_5_MMU_SV48_TYPE  0x1 > > +#define EFI_ACPI_6_5_MMU_SV57_TYPE  0x2 > > + > > +/// > > +/// Hart Info Node > > +/// > > +typedef struct { > > +  UINT16    Type; > > +  UINT16    Length; > > +  UINT16    Revision; > > +  UINT16    NumOffsets; > > +  UINT32    Uid; > > +} EFI_ACPI_6_5_NODE_HARTINFO_STRUCTURE; > > + > > +/// > > +/// "RHCT" RISC-V Hart Capabilities Table > > +/// > > +#define EFI_ACPI_6_5_RHCT_HART_DESCRIPTION_TABLE_SIGNATURE  SIGNATURE_32('R', 'H', 'C', 'T') > > + > > +#pragma pack() > > + > > +#endif > > \ No newline at end of file > > -- > > 2.34.1 > > > > > > > > > > > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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