From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id 20D63740038 for ; Sat, 22 Jun 2024 13:18:19 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=564lMt1AqK3dVudv4u60rm2JGjjhj2RxtvmAp5S3Pbk=; c=relaxed/simple; d=groups.io; h=Date:From:To:CC:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20240206; t=1719062299; v=1; b=J5ByqSzbMXfzApf5WDeZGB07+Sw4pMYsiNveAy2jrTf34m0sBQLqRp53AlwawsPq0cLAWv4S sfzTc+gb+u/EIv/m1s/MxgIOQFqir+QV8dD/DOmeupsdB+m07IBFz/8tXxP2OfZ5D+NPTrSmyOI PeRNZWQQAE/q/FJl/G/bJjqb2mh7kVNLokgUtzVlmTGjo0x8CiEM59JhjuSetAjiXQmXvzc+kLN xV0NZKIEEsXC+jCa33s+UOdEbN4hlhLebG6lq2tWnvp3pkPgmUeB92IDWKf99SKw85oGMins6Z7 mX4ySH8VJ6rfuV6kotYaEGXka2kChACEonUEVWEaFMesA== X-Received: by 127.0.0.2 with SMTP id LBgaYY7687511xrZgJv4zhCq; Sat, 22 Jun 2024 06:18:18 -0700 X-Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by mx.groups.io with SMTP id smtpd.web11.97152.1719062297607161484 for ; Sat, 22 Jun 2024 06:18:17 -0700 X-Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45MD02Jq016152; Sat, 22 Jun 2024 13:18:17 GMT X-Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3ywmaerpmn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 22 Jun 2024 13:18:16 +0000 (GMT) X-Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 45MDIF3l023366 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 22 Jun 2024 13:18:15 GMT X-Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sat, 22 Jun 2024 06:18:14 -0700 Date: Sat, 22 Jun 2024 14:18:10 +0100 From: "Leif Lindholm" To: , CC: Ard Biesheuvel Subject: Re: [edk2-devel] [PATCH edk2-platforms v2 1/1] SbsaQemu: reformat all sources using uncrustify Message-ID: References: <20240621140407.89100-1-marcin.juszkiewicz@linaro.org> MIME-Version: 1.0 In-Reply-To: <20240621140407.89100-1-marcin.juszkiewicz@linaro.org> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-ORIG-GUID: KXuJSWI3dHLW1R8DrzYbS2-wHI4e-aOw X-Proofpoint-GUID: KXuJSWI3dHLW1R8DrzYbS2-wHI4e-aOw Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Sat, 22 Jun 2024 06:18:17 -0700 Resent-From: quic_llindhol@quicinc.com Reply-To: devel@edk2.groups.io,quic_llindhol@quicinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 1T5tF0MAkLveJ20sg6HDzwe9x7686176AA= Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=J5ByqSzb; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=quicinc.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io On Fri, Jun 21, 2024 at 16:04:07 +0200, Marcin Juszkiewicz wrote: > uncrustify is required in EDK2 repository. SbsaQemu (and other platforms > in edk2-platforms) code was free from using it IIRC. > > Reformat all files to make new contributions easier. We can recommend > formatting sources without generating extra work for developers. > > Signed-off-by: Marcin Juszkiewicz Reviewed-by: Leif Lindholm Thanks! / Leif > --- > .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 50 +- > .../Include/IndustryStandard/SbsaQemuAcpi.h | 86 +-- > .../SbsaQemuPlatformVersion.h | 2 +- > .../Include/IndustryStandard/SbsaQemuSmc.h | 14 +- > .../Include/Library/HardwareInfoLib.h | 8 +- > .../Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c | 78 +-- > .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 490 +++++++++--------- > .../SbsaQemuHighMemDxe/SbsaQemuHighMemDxe.c | 8 +- > .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 88 ++-- > .../SbsaQemuSmbiosDxe/SbsaQemuSmbiosDxe.c | 94 ++-- > .../SbsaQemuHardwareInfoLib.c | 66 +-- > .../Library/SbsaQemuLib/SbsaQemuLib.c | 23 +- > .../Library/SbsaQemuLib/SbsaQemuMem.c | 49 +- > .../SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.c | 14 +- > .../SbsaQemuPciHostBridgeLib.c | 90 ++-- > 15 files changed, 603 insertions(+), 557 deletions(-) > > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h > index 83a085cd86f4..e5f0748bb16e 100644 > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h > @@ -11,60 +11,58 @@ > #define SBSAQEMU_ACPI_DXE_H > > typedef struct { > - EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Node; > - UINT32 Identifiers; > + EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Node; > + UINT32 Identifiers; > } SBSA_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE; > > -typedef struct > -{ > - EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE SmmuNode; > - EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE SmmuIdMap; > +typedef struct { > + EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE SmmuNode; > + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE SmmuIdMap; > } SBSA_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE; > > -typedef struct > -{ > - EFI_ACPI_6_0_IO_REMAPPING_RC_NODE RcNode; > - EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMap; > +typedef struct { > + EFI_ACPI_6_0_IO_REMAPPING_RC_NODE RcNode; > + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMap; > } SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE; > > typedef struct { > - EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; > - SBSA_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE ItsNode; > - SBSA_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE SmmuNode; > - SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE RcNode; > + EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; > + SBSA_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE ItsNode; > + SBSA_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE SmmuNode; > + SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE RcNode; > } SBSA_IO_REMAPPING_STRUCTURE; > > typedef struct { > - EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE mGtdt; > - EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE mGwdt; > + EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE mGtdt; > + EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE mGwdt; > } GENERIC_TIMER_DESCRIPTION_TABLES; > > #ifndef SYSTEM_TIMER_BASE_ADDRESS > - #define SYSTEM_TIMER_BASE_ADDRESS MAX_ADDRESS > +#define SYSTEM_TIMER_BASE_ADDRESS MAX_ADDRESS > #endif > > #define GTDT_TIMER_LEVEL_TRIGGERED 0 > #define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_3_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY > #define GTDT_TIMER_ALWAYS_ON EFI_ACPI_6_3_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY > > -#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | \ > +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | \ > GTDT_TIMER_LEVEL_TRIGGERED | \ > GTDT_TIMER_ALWAYS_ON) > > -#define SBSA_PLATFORM_WATCHDOG_COUNT 1 > -#define SBSA_PLATFORM_TIMER_COUNT (SBSA_PLATFORM_WATCHDOG_COUNT) > +#define SBSA_PLATFORM_WATCHDOG_COUNT 1 > +#define SBSA_PLATFORM_TIMER_COUNT (SBSA_PLATFORM_WATCHDOG_COUNT) > > -#define SBSAQEMU_WDT_REFRESH_FRAME_BASE 0x50010000 > -#define SBSAQEMU_WDT_CONTROL_FRAME_BASE 0x50011000 > -#define SBSAQEMU_WDT_IRQ 48 > +#define SBSAQEMU_WDT_REFRESH_FRAME_BASE 0x50010000 > +#define SBSAQEMU_WDT_CONTROL_FRAME_BASE 0x50011000 > +#define SBSAQEMU_WDT_IRQ 48 > > #define GTDT_WDTIMER_LEVEL_TRIGGERED 0 > #define GTDT_WDTIMER_ACTIVE_HIGH 0 > > -#define GTDT_WDTIMER_FLAGS (GTDT_WDTIMER_ACTIVE_HIGH | GTDT_WDTIMER_LEVEL_TRIGGERED) > +#define GTDT_WDTIMER_FLAGS (GTDT_WDTIMER_ACTIVE_HIGH | GTDT_WDTIMER_LEVEL_TRIGGERED) > > #define SBSAQEMU_ACPI_MEMORY_AFFINITY_STRUCTURE_INIT( \ > - ProximityDomain, Base, Length, Flags) \ > + ProximityDomain, Base, Length, Flags) \ > { \ > 1, /* Type */ \ > sizeof (EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE), /* Length */ \ > @@ -80,7 +78,7 @@ typedef struct { > } > > #define SBSAQEMU_ACPI_GICC_AFFINITY_STRUCTURE_INIT( \ > - ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \ > + ProximityDomain, ACPIProcessorUID, Flags, ClockDomain) \ > { \ > 3, /* Type */ \ > sizeof (EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE), /* Length */ \ > diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h > index 61d8bce8c959..ae151210c2c6 100644 > --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h > +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h > @@ -10,27 +10,27 @@ > > // A macro to initialise the common header part of EFI ACPI tables as defined by > // EFI_ACPI_DESCRIPTION_HEADER structure. > -#define SBSAQEMU_ACPI_HEADER(Signature, Type, Revision) { \ > - Signature, /* UINT32 Signature */ \ > - sizeof (Type), /* UINT32 Length */ \ > - Revision, /* UINT8 Revision */ \ > - 0, /* UINT8 Checksum */ \ > - { 'L', 'I', 'N', 'A', 'R', 'O' }, /* UINT8 OemId[6] */ \ > - FixedPcdGet64 (PcdAcpiDefaultOemTableId), /* UINT64 OemTableId */ \ > - FixedPcdGet32 (PcdAcpiDefaultOemRevision), /* UINT32 OemRevision */ \ > - FixedPcdGet32 (PcdAcpiDefaultCreatorId), /* UINT32 CreatorId */ \ > - FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)/* UINT32 CreatorRevision */ \ > +#define SBSAQEMU_ACPI_HEADER(Signature, Type, Revision) { \ > + Signature, /* UINT32 Signature */ \ > + sizeof (Type), /* UINT32 Length */ \ > + Revision, /* UINT8 Revision */ \ > + 0, /* UINT8 Checksum */ \ > + { 'L', 'I', 'N', 'A', 'R', 'O' }, /* UINT8 OemId[6] */ \ > + FixedPcdGet64 (PcdAcpiDefaultOemTableId), /* UINT64 OemTableId */ \ > + FixedPcdGet32 (PcdAcpiDefaultOemRevision), /* UINT32 OemRevision */ \ > + FixedPcdGet32 (PcdAcpiDefaultCreatorId), /* UINT32 CreatorId */ \ > + FixedPcdGet32 (PcdAcpiDefaultCreatorRevision) /* UINT32 CreatorRevision */ \ > } > > // Defines for MADT > -#define SBSAQEMU_MADT_GIC_VBASE 0x2c020000 > -#define SBSAQEMU_MADT_GIC_HBASE 0x2c010000 > -#define SBSAQEMU_MADT_GIC_PMU_IRQ 23 > -#define SBSAQEMU_MADT_GICR_SIZE 0x4000000 > -#define SBSAQEMU_MADT_GITS_SIZE 0x20000 > +#define SBSAQEMU_MADT_GIC_VBASE 0x2c020000 > +#define SBSAQEMU_MADT_GIC_HBASE 0x2c010000 > +#define SBSAQEMU_MADT_GIC_PMU_IRQ 23 > +#define SBSAQEMU_MADT_GICR_SIZE 0x4000000 > +#define SBSAQEMU_MADT_GITS_SIZE 0x20000 > > // Macro for MADT GIC Redistributor Structure > -#define SBSAQEMU_MADT_GICR_INIT() { \ > +#define SBSAQEMU_MADT_GICR_INIT() { \ > EFI_ACPI_6_0_GICR, /* Type */ \ > sizeof (EFI_ACPI_6_0_GICR_STRUCTURE), /* Length */ \ > EFI_ACPI_RESERVED_WORD, /* Reserved */ \ > @@ -39,7 +39,7 @@ > } > > // Macro for MADT GIC ITS Structure > -#define SBSAQEMU_MADT_GIC_ITS_INIT(GicItsId) { \ > +#define SBSAQEMU_MADT_GIC_ITS_INIT(GicItsId) { \ > EFI_ACPI_6_5_GIC_ITS, /* Type */ \ > sizeof (EFI_ACPI_6_5_GIC_ITS_STRUCTURE), /* Length */ \ > EFI_ACPI_RESERVED_WORD, /* Reserved */ \ > @@ -48,50 +48,50 @@ > EFI_ACPI_RESERVED_DWORD /* Reserved2 */ \ > } > > -#define SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH 5 > +#define SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH 5 > > -#define SBSAQEMU_ACPI_SCOPE_NAME { '_', 'S', 'B', '_' } > +#define SBSAQEMU_ACPI_SCOPE_NAME { '_', 'S', 'B', '_' } > > -#define SBSAQEMU_ACPI_CPU_DEV_LEN 0x1C > -#define SBSAQEMU_ACPI_CPU_DEV_NAME { 'C', '0', '0', '0' } > +#define SBSAQEMU_ACPI_CPU_DEV_LEN 0x1C > +#define SBSAQEMU_ACPI_CPU_DEV_NAME { 'C', '0', '0', '0' } > > -#define SBSAQEMU_ACPI_CPU_HID { \ > +#define SBSAQEMU_ACPI_CPU_HID { \ > AML_NAME_OP, AML_NAME_CHAR__, 'H', 'I', 'D', \ > AML_STRING_PREFIX, 'A', 'C', 'P', 'I', '0', '0', '0', '7', \ > AML_ZERO_OP \ > } > > -#define SBSAQEMU_ACPI_CPU_UID { \ > +#define SBSAQEMU_ACPI_CPU_UID { \ > AML_NAME_OP, AML_NAME_CHAR__, 'U', 'I', 'D', AML_WORD_PREFIX, \ > AML_ZERO_OP, AML_ZERO_OP \ > } > > typedef struct { > - UINT8 device_header[2]; > - UINT8 length; > - UINT8 dev_name[4]; > - UINT8 hid[15]; > - UINT8 uid[8]; > + UINT8 device_header[2]; > + UINT8 length; > + UINT8 dev_name[4]; > + UINT8 hid[15]; > + UINT8 uid[8]; > } SBSAQEMU_ACPI_CPU_DEVICE; > > -#define SBSAQEMU_L1_D_CACHE_SIZE SIZE_32KB > -#define SBSAQEMU_L1_D_CACHE_SETS 256 > -#define SBSAQEMU_L1_D_CACHE_ASSC 2 > +#define SBSAQEMU_L1_D_CACHE_SIZE SIZE_32KB > +#define SBSAQEMU_L1_D_CACHE_SETS 256 > +#define SBSAQEMU_L1_D_CACHE_ASSC 2 > > -#define SBSAQEMU_L1_I_CACHE_SIZE SIZE_32KB > -#define SBSAQEMU_L1_I_CACHE_SETS 256 > -#define SBSAQEMU_L1_I_CACHE_ASSC 2 > +#define SBSAQEMU_L1_I_CACHE_SIZE SIZE_32KB > +#define SBSAQEMU_L1_I_CACHE_SETS 256 > +#define SBSAQEMU_L1_I_CACHE_ASSC 2 > > -#define SBSAQEMU_L2_CACHE_SIZE SIZE_512KB > -#define SBSAQEMU_L2_CACHE_SETS 1024 > -#define SBSAQEMU_L2_CACHE_ASSC 8 > +#define SBSAQEMU_L2_CACHE_SIZE SIZE_512KB > +#define SBSAQEMU_L2_CACHE_SETS 1024 > +#define SBSAQEMU_L2_CACHE_ASSC 8 > > -#define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER)) > -#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)) > -#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)) > -#define L2_CACHE_INDEX (L1_I_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)) > +#define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER)) > +#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)) > +#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)) > +#define L2_CACHE_INDEX (L1_I_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)) > > -#define SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT { \ > +#define SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT { \ > EFI_ACPI_6_3_PPTT_TYPE_CACHE, \ > sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \ > { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \ > @@ -116,7 +116,7 @@ typedef struct { > 64 /* LineSize */ \ > } > > -#define SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT { \ > +#define SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT { \ > EFI_ACPI_6_3_PPTT_TYPE_CACHE, \ > sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \ > { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \ > diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuPlatformVersion.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuPlatformVersion.h > index d342f8f363a8..5972807468e7 100644 > --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuPlatformVersion.h > +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuPlatformVersion.h > @@ -13,7 +13,7 @@ > * > */ > > -#define PLATFORM_VERSION_LESS_THAN(Major, Minor) ( \ > +#define PLATFORM_VERSION_LESS_THAN(Major, Minor) ( \ > ( \ > ( PcdGet32 (PcdPlatformVersionMajor) < Major) || \ > ( \ > diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h > index e3092007d27d..af6b120561ad 100644 > --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h > +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h > @@ -11,13 +11,13 @@ > > #include > > -#define SIP_SVC_VERSION SMC_SIP_FUNCTION_ID(1) > -#define SIP_SVC_GET_GIC SMC_SIP_FUNCTION_ID(100) > -#define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) > -#define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200) > -#define SIP_SVC_GET_CPU_NODE SMC_SIP_FUNCTION_ID(201) > -#define SIP_SVC_GET_MEMORY_NODE_COUNT SMC_SIP_FUNCTION_ID(300) > -#define SIP_SVC_GET_MEMORY_NODE SMC_SIP_FUNCTION_ID(301) > +#define SIP_SVC_VERSION SMC_SIP_FUNCTION_ID(1) > +#define SIP_SVC_GET_GIC SMC_SIP_FUNCTION_ID(100) > +#define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) > +#define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200) > +#define SIP_SVC_GET_CPU_NODE SMC_SIP_FUNCTION_ID(201) > +#define SIP_SVC_GET_MEMORY_NODE_COUNT SMC_SIP_FUNCTION_ID(300) > +#define SIP_SVC_GET_MEMORY_NODE SMC_SIP_FUNCTION_ID(301) > > /* > * SMCC does not define return codes for SiP functions. > diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h > index 46fdad45353c..e5076274fa0a 100644 > --- a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h > +++ b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h > @@ -9,10 +9,10 @@ > #ifndef HARDWARE_INFO_LIB > #define HARDWARE_INFO_LIB > > -typedef struct{ > - UINT32 NodeId; > - UINT64 AddressBase; > - UINT64 AddressSize; > +typedef struct { > + UINT32 NodeId; > + UINT64 AddressBase; > + UINT64 AddressSize; > } MemoryInfo; > > /** > diff --git a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c > index 854f6f4072d5..e515c403f7ae 100644 > --- a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c > +++ b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c > @@ -29,7 +29,7 @@ > BOOLEAN > EFIAPI > OemIsProcessorPresent ( > - UINTN ProcessorIndex > + UINTN ProcessorIndex > ) > { > if (ProcessorIndex < GetCpuCount ()) { > @@ -48,7 +48,7 @@ OemIsProcessorPresent ( > UINTN > EFIAPI > OemGetCpuFreq ( > - UINT8 ProcessorIndex > + UINT8 ProcessorIndex > ) > { > return 2000000000; // 2 GHz > @@ -67,13 +67,13 @@ OemGetCpuFreq ( > BOOLEAN > EFIAPI > OemGetProcessorInformation ( > - IN UINTN ProcessorIndex, > - IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus, > - IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics, > - IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData > + IN UINTN ProcessorIndex, > + IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus, > + IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics, > + IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData > ) > { > - UINT16 ProcessorCount; > + UINT16 ProcessorCount; > > ProcessorCount = GetCpuCount (); > > @@ -89,17 +89,17 @@ OemGetProcessorInformation ( > ProcessorStatus->Bits.Reserved2 = 0; > } > > - ProcessorCharacteristics->ProcessorReserved1 = 0; > - ProcessorCharacteristics->ProcessorUnknown = 0; > - ProcessorCharacteristics->Processor64BitCapable = 1; > - ProcessorCharacteristics->ProcessorMultiCore = 0; > - ProcessorCharacteristics->ProcessorHardwareThread = 0; > + ProcessorCharacteristics->ProcessorReserved1 = 0; > + ProcessorCharacteristics->ProcessorUnknown = 0; > + ProcessorCharacteristics->Processor64BitCapable = 1; > + ProcessorCharacteristics->ProcessorMultiCore = 0; > + ProcessorCharacteristics->ProcessorHardwareThread = 0; > ProcessorCharacteristics->ProcessorExecuteProtection = 1; > ProcessorCharacteristics->ProcessorEnhancedVirtualization = 0; > ProcessorCharacteristics->ProcessorPowerPerformanceCtrl = 0; > - ProcessorCharacteristics->Processor128BitCapable = 0; > - ProcessorCharacteristics->ProcessorArm64SocId = 1; > - ProcessorCharacteristics->ProcessorReserved2 = 0; > + ProcessorCharacteristics->Processor128BitCapable = 0; > + ProcessorCharacteristics->ProcessorArm64SocId = 1; > + ProcessorCharacteristics->ProcessorReserved2 = 0; > > MiscProcessorData->CurrentSpeed = 2000; > MiscProcessorData->MaxSpeed = 2000; > @@ -136,16 +136,16 @@ OemGetMaxProcessors ( > BOOLEAN > EFIAPI > OemGetCacheInformation ( > - IN UINT8 ProcessorIndex, > - IN UINT8 CacheLevel, > - IN BOOLEAN DataCache, > - IN BOOLEAN UnifiedCache, > - IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable > + IN UINT8 ProcessorIndex, > + IN UINT8 CacheLevel, > + IN BOOLEAN DataCache, > + IN BOOLEAN UnifiedCache, > + IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable > ) > { > SmbiosCacheTable->CacheConfiguration = CacheLevel - 1; > > - if (CacheLevel == 1 && !DataCache && !UnifiedCache) { > + if ((CacheLevel == 1) && !DataCache && !UnifiedCache) { > // Unknown operational mode > SmbiosCacheTable->CacheConfiguration |= (3 << 8); > } else { > @@ -178,57 +178,57 @@ OemGetChassisType ( > VOID > EFIAPI > OemUpdateSmbiosInfo ( > - IN EFI_HII_HANDLE HiiHandle, > - IN EFI_STRING_ID TokenToUpdate, > - IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field > + IN EFI_HII_HANDLE HiiHandle, > + IN EFI_STRING_ID TokenToUpdate, > + IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field > ) > { > - CHAR16 *String; > + CHAR16 *String; > > // These values are fixed for now, but should be configurable via > // something like an emulated SCP. > switch (Field) { > case SystemManufacturerType01: > - String = (CHAR16*)PcdGetPtr (PcdSystemManufacturer); > + String = (CHAR16 *)PcdGetPtr (PcdSystemManufacturer); > break; > case SerialNumType01: > - String = (CHAR16*)PcdGetPtr (PcdSystemSerialNumber); > + String = (CHAR16 *)PcdGetPtr (PcdSystemSerialNumber); > break; > case SkuNumberType01: > - String = (CHAR16*)PcdGetPtr (PcdSystemSKU); > + String = (CHAR16 *)PcdGetPtr (PcdSystemSKU); > break; > case FamilyType01: > - String = (CHAR16*)PcdGetPtr (PcdSystemFamily); > + String = (CHAR16 *)PcdGetPtr (PcdSystemFamily); > break; > case AssetTagType02: > - String = (CHAR16*)PcdGetPtr (PcdBaseBoardAssetTag); > + String = (CHAR16 *)PcdGetPtr (PcdBaseBoardAssetTag); > break; > case SerialNumberType02: > - String = (CHAR16*)PcdGetPtr (PcdBaseBoardSerialNumber); > + String = (CHAR16 *)PcdGetPtr (PcdBaseBoardSerialNumber); > break; > case BoardManufacturerType02: > - String = (CHAR16*)PcdGetPtr (PcdBaseBoardManufacturer); > + String = (CHAR16 *)PcdGetPtr (PcdBaseBoardManufacturer); > break; > case SkuNumberType02: > - String = (CHAR16*)PcdGetPtr (PcdBaseBoardSKU); > + String = (CHAR16 *)PcdGetPtr (PcdBaseBoardSKU); > break; > case ChassisLocationType02: > - String = (CHAR16*)PcdGetPtr (PcdBaseBoardLocation); > + String = (CHAR16 *)PcdGetPtr (PcdBaseBoardLocation); > break; > case SerialNumberType03: > - String = (CHAR16*)PcdGetPtr (PcdChassisSerialNumber); > + String = (CHAR16 *)PcdGetPtr (PcdChassisSerialNumber); > break; > case VersionType03: > - String = (CHAR16*)PcdGetPtr (PcdChassisVersion); > + String = (CHAR16 *)PcdGetPtr (PcdChassisVersion); > break; > case ManufacturerType03: > - String = (CHAR16*)PcdGetPtr (PcdChassisManufacturer); > + String = (CHAR16 *)PcdGetPtr (PcdChassisManufacturer); > break; > case AssetTagType03: > - String = (CHAR16*)PcdGetPtr (PcdChassisAssetTag); > + String = (CHAR16 *)PcdGetPtr (PcdChassisAssetTag); > break; > case SkuNumberType03: > - String = (CHAR16*)PcdGetPtr (PcdChassisSKU); > + String = (CHAR16 *)PcdGetPtr (PcdChassisSKU); > break; > default: > String = NULL; > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > index 30239e7dca0d..e0eef54ff907 100644 > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > @@ -27,8 +27,7 @@ > > #pragma pack(1) > > - > -static UINTN GicItsBase; > +static UINTN GicItsBase; > > #pragma pack () > > @@ -37,18 +36,18 @@ static UINTN GicItsBase; > */ > VOID > AcpiPlatformChecksum ( > - IN UINT8 *Buffer, > - IN UINTN Size > + IN UINT8 *Buffer, > + IN UINTN Size > ) > { > - UINTN ChecksumOffset; > + UINTN ChecksumOffset; > > ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum); > > // Set checksum field to 0 since it is used as part of the calculation > Buffer[ChecksumOffset] = 0; > > - Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size); > + Buffer[ChecksumOffset] = CalculateCheckSum8 (Buffer, Size); > } > > /* > @@ -57,7 +56,7 @@ AcpiPlatformChecksum ( > */ > EFI_STATUS > AddIortTable ( > - IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable > + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable > ) > { > EFI_STATUS Status; > @@ -67,85 +66,88 @@ AddIortTable ( > UINT8 *New; > > // Initialize IORT ACPI Header > - EFI_ACPI_6_0_IO_REMAPPING_TABLE Header = { > - SBSAQEMU_ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, > - SBSA_IO_REMAPPING_STRUCTURE, > - EFI_ACPI_IO_REMAPPING_TABLE_REVISION_00), > + EFI_ACPI_6_0_IO_REMAPPING_TABLE Header = { > + SBSAQEMU_ACPI_HEADER ( > + EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, > + SBSA_IO_REMAPPING_STRUCTURE, > + EFI_ACPI_IO_REMAPPING_TABLE_REVISION_00 > + ), > 3, > - sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset > - 0 }; > + sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset > + 0 > + }; > > // Initialize SMMU3 Structure > - SBSA_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE Smmu3 = { > + SBSA_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE Smmu3 = { > { > { > EFI_ACPI_IORT_TYPE_SMMUv3, > sizeof (SBSA_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE), > - 2, // Revision > - 0, // Reserved > - 1, // NumIdMapping > + 2, // Revision > + 0, // Reserved > + 1, // NumIdMapping > OFFSET_OF (SBSA_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE, SmmuIdMap) // IdReference > }, > - PcdGet64 (PcdSmmuBase), // Base address > + PcdGet64 (PcdSmmuBase), // Base address > EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE, // Flags > - 0, // Reserved > - 0, // VATOS address > - EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC, // SMMUv3 Model > - 74, // Event > - 75, // Pri > - 77, // Gerror > - 76, // Sync > - 0, // Proximity domain > - 1 // DevIDMappingIndex > + 0, // Reserved > + 0, // VATOS address > + EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC, // SMMUv3 Model > + 74, // Event > + 75, // Pri > + 77, // Gerror > + 76, // Sync > + 0, // Proximity domain > + 1 // DevIDMappingIndex > }, > - { > - 0x0000, // InputBase > - 0xffff, // NumIds > - 0x0000, // OutputBase > - OFFSET_OF (SBSA_IO_REMAPPING_STRUCTURE, ItsNode), // OutputReference > - 0 // Flags > - } > + { > + 0x0000, // InputBase > + 0xffff, // NumIds > + 0x0000, // OutputBase > + OFFSET_OF (SBSA_IO_REMAPPING_STRUCTURE, ItsNode), // OutputReference > + 0 // Flags > + } > }; > > -//NOTE(hrw): update to IORT E.e? > - SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Rc = { > + // NOTE(hrw): update to IORT E.e? > + SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE Rc = { > { > { > - EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type > - sizeof (SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE), // Length > - 0, // Revision > - 0, // Reserved > - 1, // NumIdMappings > - OFFSET_OF (SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE, RcIdMap) // IdReference > + EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type > + sizeof (SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE), // Length > + 0, // Revision > + 0, // Reserved > + 1, // NumIdMappings > + OFFSET_OF (SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE, RcIdMap) // IdReference > }, > - 1, // CacheCoherent > - 0, // AllocationHints > - 0, // Reserved > - 0, // MemoryAccessFlags > - EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute > - 0x0, // PciSegmentNumber > - //0, //MemoryAddressSizeLimit > + 1, // CacheCoherent > + 0, // AllocationHints > + 0, // Reserved > + 0, // MemoryAccessFlags > + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute > + 0x0, // PciSegmentNumber > + // 0, //MemoryAddressSizeLimit > }, > { > - 0x0000, // InputBase > - 0xffff, // NumIds > - 0x0000, // OutputBase > - OFFSET_OF (SBSA_IO_REMAPPING_STRUCTURE, SmmuNode), // OutputReference > - 0, // Flags > + 0x0000, // InputBase > + 0xffff, // NumIds > + 0x0000, // OutputBase > + OFFSET_OF (SBSA_IO_REMAPPING_STRUCTURE, SmmuNode), // OutputReference > + 0, // Flags > } > }; > > - SBSA_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Its = { > + SBSA_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE Its = { > // EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE > { > // EFI_ACPI_6_0_IO_REMAPPING_NODE > { > - EFI_ACPI_IORT_TYPE_ITS_GROUP, // Type > + EFI_ACPI_IORT_TYPE_ITS_GROUP, // Type > sizeof (SBSA_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE), // Length > - 0, // Revision > - 0, // Identifier > - 0, // NumIdMappings > - 0, // IdReference > + 0, // Revision > + 0, // Identifier > + 0, // NumIdMappings > + 0, // IdReference > }, > 1, // ITS count > }, > @@ -164,18 +166,18 @@ AddIortTable ( > EFI_SIZE_TO_PAGES (TableSize), > &PageAddress > ); > - if (EFI_ERROR(Status)) { > + if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "Failed to allocate pages for IORT table\n")); > return EFI_OUT_OF_RESOURCES; > } > > - New = (UINT8 *)(UINTN) PageAddress; > + New = (UINT8 *)(UINTN)PageAddress; > ZeroMem (New, TableSize); > > // Add the ACPI Description table header > CopyMem (New, &Header, sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE)); > - ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize; > - New += sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE); > + ((EFI_ACPI_DESCRIPTION_HEADER *)New)->Length = TableSize; > + New += sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE); > > // ITS Node > CopyMem (New, &Its, sizeof (SBSA_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE)); > @@ -189,7 +191,7 @@ AddIortTable ( > CopyMem (New, &Rc, sizeof (SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE)); > New += sizeof (SBSA_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE); > > - AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); > + AcpiPlatformChecksum ((UINT8 *)PageAddress, TableSize); > > Status = AcpiTable->InstallAcpiTable ( > AcpiTable, > @@ -197,7 +199,7 @@ AddIortTable ( > TableSize, > &TableHandle > ); > - if (EFI_ERROR(Status)) { > + if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "Failed to install IORT table\n")); > } > > @@ -210,7 +212,7 @@ AddIortTable ( > */ > EFI_STATUS > AddMadtTable ( > - IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable > + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable > ) > { > EFI_STATUS Status; > @@ -222,49 +224,52 @@ AddMadtTable ( > UINT32 CoreIndex; > > // Initialize MADT ACPI Header > - EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header = { > - SBSAQEMU_ACPI_HEADER (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, > - EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER, > - EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION), > - 0, 0 }; > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header = { > + SBSAQEMU_ACPI_HEADER ( > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE, > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER, > + EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION > + ), > + 0, 0 > + }; > > // Initialize GICC Structure > - EFI_ACPI_6_0_GIC_STRUCTURE Gicc = EFI_ACPI_6_0_GICC_STRUCTURE_INIT ( > - 0, /* GicID */ > - 0, /* AcpiCpuUid */ > - 0, /* Mpidr */ > - EFI_ACPI_6_0_GIC_ENABLED, /* Flags */ > - SBSAQEMU_MADT_GIC_PMU_IRQ, /* PMU Irq */ > - 0, /* PhysicalBaseAddress */ > - SBSAQEMU_MADT_GIC_VBASE, /* GicVBase */ > - SBSAQEMU_MADT_GIC_HBASE, /* GicHBase */ > - 25, /* GsivId */ > - 0, /* GicRBase */ > - 0 /* Efficiency */ > - ); > + EFI_ACPI_6_0_GIC_STRUCTURE Gicc = EFI_ACPI_6_0_GICC_STRUCTURE_INIT ( > + 0, /* GicID */ > + 0, /* AcpiCpuUid */ > + 0, /* Mpidr */ > + EFI_ACPI_6_0_GIC_ENABLED, /* Flags */ > + SBSAQEMU_MADT_GIC_PMU_IRQ, /* PMU Irq */ > + 0, /* PhysicalBaseAddress */ > + SBSAQEMU_MADT_GIC_VBASE, /* GicVBase */ > + SBSAQEMU_MADT_GIC_HBASE, /* GicHBase */ > + 25, /* GsivId */ > + 0, /* GicRBase */ > + 0 /* Efficiency */ > + ); > > // Initialize GIC Distributor Structure > - EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE Gicd = > + EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE Gicd = > EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT ( > 0, > PcdGet64 (PcdGicDistributorBase), > 0, > 3 /* GicVersion */ > - ); > + ); > > - // Initialize GIC Redistributor Structure > - EFI_ACPI_6_0_GICR_STRUCTURE Gicr = SBSAQEMU_MADT_GICR_INIT(); > + // Initialize GIC Redistributor Structure > + EFI_ACPI_6_0_GICR_STRUCTURE Gicr = SBSAQEMU_MADT_GICR_INIT (); > > NumCores = GetCpuCount (); > > // Calculate the new table size based on the number of cores > TableSize = sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER) + > - (sizeof (EFI_ACPI_6_0_GIC_STRUCTURE) * NumCores) + > - sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE) + > - sizeof (EFI_ACPI_6_0_GICR_STRUCTURE); > + (sizeof (EFI_ACPI_6_0_GIC_STRUCTURE) * NumCores) + > + sizeof (EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE) + > + sizeof (EFI_ACPI_6_0_GICR_STRUCTURE); > > // Initialize GIC ITS Structure > - EFI_ACPI_6_5_GIC_ITS_STRUCTURE Gic_Its = SBSAQEMU_MADT_GIC_ITS_INIT(0); > + EFI_ACPI_6_5_GIC_ITS_STRUCTURE Gic_Its = SBSAQEMU_MADT_GIC_ITS_INIT (0); > > if (GicItsBase > 0) { > TableSize += sizeof (EFI_ACPI_6_5_GIC_ITS_STRUCTURE); > @@ -276,28 +281,28 @@ AddMadtTable ( > EFI_SIZE_TO_PAGES (TableSize), > &PageAddress > ); > - if (EFI_ERROR(Status)) { > + if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "Failed to allocate pages for MADT table\n")); > return EFI_OUT_OF_RESOURCES; > } > > - New = (UINT8 *)(UINTN) PageAddress; > + New = (UINT8 *)(UINTN)PageAddress; > ZeroMem (New, TableSize); > > // Add the ACPI Description table header > CopyMem (New, &Header, sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER)); > - ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize; > - New += sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER); > + ((EFI_ACPI_DESCRIPTION_HEADER *)New)->Length = TableSize; > + New += sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER); > > // Add new GICC structures for the Cores > for (CoreIndex = 0; CoreIndex < NumCores; CoreIndex++) { > - EFI_ACPI_6_0_GIC_STRUCTURE *GiccPtr; > + EFI_ACPI_6_0_GIC_STRUCTURE *GiccPtr; > > CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_STRUCTURE)); > - GiccPtr = (EFI_ACPI_6_0_GIC_STRUCTURE *) New; > + GiccPtr = (EFI_ACPI_6_0_GIC_STRUCTURE *)New; > GiccPtr->AcpiProcessorUid = CoreIndex; > - GiccPtr->MPIDR = GetMpidr (CoreIndex); > - New += sizeof (EFI_ACPI_6_0_GIC_STRUCTURE); > + GiccPtr->MPIDR = GetMpidr (CoreIndex); > + New += sizeof (EFI_ACPI_6_0_GIC_STRUCTURE); > } > > // GIC Distributor Structure > @@ -314,7 +319,7 @@ AddMadtTable ( > New += sizeof (EFI_ACPI_6_5_GIC_ITS_STRUCTURE); > } > > - AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); > + AcpiPlatformChecksum ((UINT8 *)PageAddress, TableSize); > > Status = AcpiTable->InstallAcpiTable ( > AcpiTable, > @@ -322,7 +327,7 @@ AddMadtTable ( > TableSize, > &TableHandle > ); > - if (EFI_ERROR(Status)) { > + if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "Failed to install MADT table\n")); > } > > @@ -335,24 +340,25 @@ AddMadtTable ( > STATIC > UINT32 > SetPkgLength ( > - IN UINT8 *TablePtr, > - IN UINT32 Length > -) > + IN UINT8 *TablePtr, > + IN UINT32 Length > + ) > { > UINT8 ByteCount; > UINT8 *PkgLeadByte = TablePtr; > > // Increase Payload Length to include the size of the Length Field > - if (Length <= (0x3F - 1)) > + if (Length <= (0x3F - 1)) { > Length += 1; > - else if (Length <= (0xFFF - 2)) > + } else if (Length <= (0xFFF - 2)) { > Length += 2; > - else if (Length <= (0xFFFFF - 3)) > + } else if (Length <= (0xFFFFF - 3)) { > Length += 3; > - else if (Length <= (0xFFFFFFF - 4)) > + } else if (Length <= (0xFFFFFFF - 4)) { > Length += 4; > - else > + } else { > DEBUG ((DEBUG_ERROR, "Failed to set PkgLength: too large\n")); > + } > > // Smaller payloads fit into a single length byte > if (Length < 64) { > @@ -362,17 +368,17 @@ SetPkgLength ( > > // Set the LSB of Length in PkgLeadByte and advance Length > *PkgLeadByte = Length & 0xF; > - Length = Length >> 4; > + Length = Length >> 4; > > while (Length) { > TablePtr++; > *TablePtr = (Length & 0xFF); > - Length = (Length >> 8); > + Length = (Length >> 8); > } > > // Calculate the number of bytes the Length field uses > // and set the ByteCount field in PkgLeadByte. > - ByteCount = (TablePtr - PkgLeadByte) & 0xF; > + ByteCount = (TablePtr - PkgLeadByte) & 0xF; > *PkgLeadByte |= (ByteCount << 6); > > return ByteCount + 1; > @@ -383,7 +389,7 @@ SetPkgLength ( > */ > EFI_STATUS > AddSsdtTable ( > - IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable > + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable > ) > { > EFI_STATUS Status; > @@ -395,15 +401,16 @@ AddSsdtTable ( > UINT32 CpuId; > UINT32 Offset; > UINT8 ScopeOpName[] = SBSAQEMU_ACPI_SCOPE_NAME; > - UINT32 NumCores = GetCpuCount (); > + UINT32 NumCores = GetCpuCount (); > > - EFI_ACPI_DESCRIPTION_HEADER Header = > + EFI_ACPI_DESCRIPTION_HEADER Header = > SBSAQEMU_ACPI_HEADER ( > EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, > EFI_ACPI_DESCRIPTION_HEADER, > - EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION); > + EFI_ACPI_6_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_REVISION > + ); > > - SBSAQEMU_ACPI_CPU_DEVICE CpuDevice = { > + SBSAQEMU_ACPI_CPU_DEVICE CpuDevice = { > { AML_EXT_OP, AML_EXT_DEVICE_OP }, /* Device () */ > SBSAQEMU_ACPI_CPU_DEV_LEN, /* Length */ > SBSAQEMU_ACPI_CPU_DEV_NAME, /* Device Name "C000" */ > @@ -422,12 +429,12 @@ AddSsdtTable ( > EFI_SIZE_TO_PAGES (TableSize), > &PageAddress > ); > - if (EFI_ERROR(Status)) { > + if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "Failed to allocate pages for SSDT table\n")); > return EFI_OUT_OF_RESOURCES; > } > > - HeaderAddr = New = (UINT8 *)(UINTN) PageAddress; > + HeaderAddr = New = (UINT8 *)(UINTN)PageAddress; > ZeroMem (New, TableSize); > > // Add the ACPI Description table header > @@ -438,12 +445,14 @@ AddSsdtTable ( > // Insert the top level ScopeOp > *New = AML_SCOPE_OP; > New++; > - Offset = SetPkgLength (New, > - (sizeof (ScopeOpName) + (sizeof (CpuDevice) * NumCores))); > + Offset = SetPkgLength ( > + New, > + (sizeof (ScopeOpName) + (sizeof (CpuDevice) * NumCores)) > + ); > > // Adjust TableSize now we know header length of _SB > - TableSize -= (SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH - (Offset + 1)); > - ((EFI_ACPI_DESCRIPTION_HEADER*) HeaderAddr)->Length = TableSize; > + TableSize -= (SBSAQEMU_ACPI_SCOPE_OP_MAX_LENGTH - (Offset + 1)); > + ((EFI_ACPI_DESCRIPTION_HEADER *)HeaderAddr)->Length = TableSize; > > New += Offset; > CopyMem (New, &ScopeOpName, sizeof (ScopeOpName)); > @@ -451,23 +460,23 @@ AddSsdtTable ( > > // Add new Device structures for the Cores > for (CpuId = 0; CpuId < NumCores; CpuId++) { > - SBSAQEMU_ACPI_CPU_DEVICE *CpuDevicePtr; > + SBSAQEMU_ACPI_CPU_DEVICE *CpuDevicePtr; > > CopyMem (New, &CpuDevice, sizeof (SBSAQEMU_ACPI_CPU_DEVICE)); > - CpuDevicePtr = (SBSAQEMU_ACPI_CPU_DEVICE *) New; > + CpuDevicePtr = (SBSAQEMU_ACPI_CPU_DEVICE *)New; > > - AsciiSPrint((CHAR8 *)&CpuDevicePtr->dev_name[1], 4, "%03X", CpuId); > + AsciiSPrint ((CHAR8 *)&CpuDevicePtr->dev_name[1], 4, "%03X", CpuId); > > /* replace character lost by above NULL termination */ > CpuDevicePtr->hid[0] = AML_NAME_OP; > > CpuDevicePtr->uid[6] = CpuId & 0xFF; > CpuDevicePtr->uid[7] = (CpuId >> 8) & 0xFF; > - New += sizeof (SBSAQEMU_ACPI_CPU_DEVICE); > + New += sizeof (SBSAQEMU_ACPI_CPU_DEVICE); > } > > // Perform Checksum > - AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); > + AcpiPlatformChecksum ((UINT8 *)PageAddress, TableSize); > > Status = AcpiTable->InstallAcpiTable ( > AcpiTable, > @@ -475,7 +484,7 @@ AddSsdtTable ( > TableSize, > &TableHandle > ); > - if (EFI_ERROR(Status)) { > + if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "Failed to install SSDT table\n")); > } > > @@ -487,7 +496,7 @@ AddSsdtTable ( > */ > EFI_STATUS > AddPpttTable ( > - IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable > + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable > ) > { > EFI_STATUS Status; > @@ -498,24 +507,25 @@ AddPpttTable ( > UINT32 CpuId; > UINT32 NumCores = GetCpuCount (); > > - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT; > - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT; > - EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT; > + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT; > + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT; > + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT; > > - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT; > - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PPTT_CORE_STRUCT; > + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT; > + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PPTT_CORE_STRUCT; > > - EFI_ACPI_DESCRIPTION_HEADER Header = > + EFI_ACPI_DESCRIPTION_HEADER Header = > SBSAQEMU_ACPI_HEADER ( > EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, > EFI_ACPI_DESCRIPTION_HEADER, > - EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION); > + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION > + ); > > TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) + > - sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + > - (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3) + > - (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) * NumCores) + > - (sizeof (UINT32) * 2 * NumCores); > + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + > + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3) + > + (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) * NumCores) + > + (sizeof (UINT32) * 2 * NumCores); > > Status = gBS->AllocatePages ( > AllocateAnyPages, > @@ -523,18 +533,18 @@ AddPpttTable ( > EFI_SIZE_TO_PAGES (TableSize), > &PageAddress > ); > - if (EFI_ERROR(Status)) { > + if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "Failed to allocate pages for PPTT table\n")); > return EFI_OUT_OF_RESOURCES; > } > > - New = (UINT8 *)(UINTN) PageAddress; > + New = (UINT8 *)(UINTN)PageAddress; > ZeroMem (New, TableSize); > > // Add the ACPI Description table header > CopyMem (New, &Header, sizeof (EFI_ACPI_DESCRIPTION_HEADER)); > - ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize; > - New += sizeof (EFI_ACPI_DESCRIPTION_HEADER); > + ((EFI_ACPI_DESCRIPTION_HEADER *)New)->Length = TableSize; > + New += sizeof (EFI_ACPI_DESCRIPTION_HEADER); > > // Add the Cluster PPTT structure > CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)); > @@ -542,37 +552,37 @@ AddPpttTable ( > > // Add L1 D Cache structure > CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)); > - ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache = L2_CACHE_INDEX; > - New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); > + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2_CACHE_INDEX; > + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); > > // Add L1 I Cache structure > CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)); > - ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache = L2_CACHE_INDEX; > - New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); > + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2_CACHE_INDEX; > + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); > > // Add L2 Cache structure > CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE)); > - ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE*) New)->NextLevelOfCache = 0; /* L2 is LLC */ > - New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); > + ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 0; /* L2 is LLC */ > + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE); > > for (CpuId = 0; CpuId < NumCores; CpuId++) { > - EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *CorePtr; > - UINT32 *PrivateResourcePtr; > + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *CorePtr; > + UINT32 *PrivateResourcePtr; > > CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR)); > - CorePtr = (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *) New; > - CorePtr->Parent = CLUSTER_INDEX; > + CorePtr = (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *)New; > + CorePtr->Parent = CLUSTER_INDEX; > CorePtr->AcpiProcessorId = CpuId; > - New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR); > + New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR); > > - PrivateResourcePtr = (UINT32 *) New; > + PrivateResourcePtr = (UINT32 *)New; > PrivateResourcePtr[0] = L1_D_CACHE_INDEX; > PrivateResourcePtr[1] = L1_I_CACHE_INDEX; > - New += (2 * sizeof (UINT32)); > + New += (2 * sizeof (UINT32)); > } > > // Perform Checksum > - AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); > + AcpiPlatformChecksum ((UINT8 *)PageAddress, TableSize); > > Status = AcpiTable->InstallAcpiTable ( > AcpiTable, > @@ -580,7 +590,7 @@ AddPpttTable ( > TableSize, > &TableHandle > ); > - if (EFI_ERROR(Status)) { > + if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "Failed to install PPTT table\n")); > } > > @@ -592,7 +602,7 @@ AddPpttTable ( > */ > EFI_STATUS > AddGtdtTable ( > - IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable > + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable > ) > { > EFI_STATUS Status; > @@ -602,7 +612,7 @@ AddGtdtTable ( > UINT8 *New; > > TableSize = sizeof (EFI_ACPI_6_5_GENERIC_TIMER_DESCRIPTION_TABLE) + > - sizeof (EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE); > + sizeof (EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE); > > Status = gBS->AllocatePages ( > AllocateAnyPages, > @@ -611,45 +621,45 @@ AddGtdtTable ( > &PageAddress > ); > > - if (EFI_ERROR(Status)) { > + if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "Failed to allocate pages for GTDT table\n")); > return EFI_OUT_OF_RESOURCES; > } > > - EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = { > - > + EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = { > SBSAQEMU_ACPI_HEADER ( > EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE, > GENERIC_TIMER_DESCRIPTION_TABLES, > - EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION), > + EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION > + ), > > - SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress > - 0, // UINT32 Reserved > - FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV > - GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags > - FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV > - GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags > - FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV > - GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags > - FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV > - GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags > - MAX_ADDRESS, // UINT64 CntReadBasePhysicalAddress > - SBSA_PLATFORM_TIMER_COUNT, // UINT32 PlatformTimerCount > - sizeof(EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE), > - // UINT32 PlatformTimerOffset > - FixedPcdGet32 (PcdArmArchTimerHypVirtIntrNum),// UINT32 VirtualPL2TimerGSIV > - GTDT_GTIMER_FLAGS // UINT32 VirtualPL2TimerFlags > + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress > + 0, // UINT32 Reserved > + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV > + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags > + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV > + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags > + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV > + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags > + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV > + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags > + MAX_ADDRESS, // UINT64 CntReadBasePhysicalAddress > + SBSA_PLATFORM_TIMER_COUNT, // UINT32 PlatformTimerCount > + sizeof (EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE), > + // UINT32 PlatformTimerOffset > + FixedPcdGet32 (PcdArmArchTimerHypVirtIntrNum), // UINT32 VirtualPL2TimerGSIV > + GTDT_GTIMER_FLAGS // UINT32 VirtualPL2TimerFlags > }; > > // Non-secure EL2 virtual timer requires VHE support (v8.1+) > - if (! ArmHasVhe()) { > - Gtdt.VirtualPL2TimerGSIV = 0; > + if (!ArmHasVhe ()) { > + Gtdt.VirtualPL2TimerGSIV = 0; > Gtdt.VirtualPL2TimerFlags = 0; > } > > - EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Gwdt = { > + EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Gwdt = { > EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG, > - sizeof(EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), > + sizeof (EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), > EFI_ACPI_RESERVED_WORD, > SBSAQEMU_WDT_REFRESH_FRAME_BASE, > SBSAQEMU_WDT_CONTROL_FRAME_BASE, > @@ -657,7 +667,7 @@ AddGtdtTable ( > GTDT_WDTIMER_FLAGS > }; > > - New = (UINT8 *)(UINTN) PageAddress; > + New = (UINT8 *)(UINTN)PageAddress; > ZeroMem (New, TableSize); > > CopyMem (New, &Gtdt, sizeof (EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE)); > @@ -667,7 +677,7 @@ AddGtdtTable ( > New += sizeof (EFI_ACPI_6_3_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE); > > // Perform Checksum > - AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); > + AcpiPlatformChecksum ((UINT8 *)PageAddress, TableSize); > > Status = AcpiTable->InstallAcpiTable ( > AcpiTable, > @@ -675,7 +685,7 @@ AddGtdtTable ( > TableSize, > &TableHandle > ); > - if (EFI_ERROR(Status)) { > + if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "Failed to install GTDT table\n")); > } > > @@ -687,7 +697,7 @@ AddGtdtTable ( > */ > EFI_STATUS > AddSratTable ( > - IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable > + IN EFI_ACPI_TABLE_PROTOCOL *AcpiTable > ) > { > EFI_STATUS Status; > @@ -702,57 +712,60 @@ AddSratTable ( > UINT32 NumCores = GetCpuCount (); > > // Initialize SRAT ACPI Header > - EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header = { > - SBSAQEMU_ACPI_HEADER (EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, > - EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER, > - EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION), > - 1, 0 }; > + EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header = { > + SBSAQEMU_ACPI_HEADER ( > + EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE, > + EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER, > + EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION > + ), > + 1, 0 > + }; > > - NumMemNodes = GetMemNodeCount(); > + NumMemNodes = GetMemNodeCount (); > > // Calculate the new table size based on the number of cores > TableSize = sizeof (EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER) + > - (sizeof (EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE) * NumMemNodes ) + > - (sizeof (EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE) * NumCores); > + (sizeof (EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE) * NumMemNodes) + > + (sizeof (EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE) * NumCores); > > Status = gBS->AllocatePages ( > - AllocateAnyPages, > - EfiACPIReclaimMemory, > - EFI_SIZE_TO_PAGES (TableSize), > - &PageAddress > - ); > + AllocateAnyPages, > + EfiACPIReclaimMemory, > + EFI_SIZE_TO_PAGES (TableSize), > + &PageAddress > + ); > > - if (EFI_ERROR(Status)) { > + if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "Failed to allocate pages for SRAT table\n")); > return EFI_OUT_OF_RESOURCES; > } > > - New = (UINT8 *)(UINTN) PageAddress; > + New = (UINT8 *)(UINTN)PageAddress; > ZeroMem (New, TableSize); > > // Add the ACPI Description table header > CopyMem (New, &Header, sizeof (EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER)); > - ((EFI_ACPI_DESCRIPTION_HEADER*) New)->Length = TableSize; > - New += sizeof (EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER); > + ((EFI_ACPI_DESCRIPTION_HEADER *)New)->Length = TableSize; > + New += sizeof (EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER); > > // Add memory structures > - for (Index = 0; Index < NumMemNodes ; Index++) { > + for (Index = 0; Index < NumMemNodes; Index++) { > GetMemInfo (Index, &MemInfo); > - EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE memory = SBSAQEMU_ACPI_MEMORY_AFFINITY_STRUCTURE_INIT (MemInfo.NodeId, MemInfo.AddressBase, MemInfo.AddressSize, 1); > + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE memory = SBSAQEMU_ACPI_MEMORY_AFFINITY_STRUCTURE_INIT (MemInfo.NodeId, MemInfo.AddressBase, MemInfo.AddressSize, 1); > CopyMem (New, &memory, sizeof (EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE)); > New += sizeof (EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE); > } > > // Add processor structures for the cores > for (Index = 0; Index < NumCores; Index++) { > - NodeId = GetCpuNumaNode(Index); > - EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE gicc = SBSAQEMU_ACPI_GICC_AFFINITY_STRUCTURE_INIT(NodeId, Index, 1, 0); > + NodeId = GetCpuNumaNode (Index); > + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE gicc = SBSAQEMU_ACPI_GICC_AFFINITY_STRUCTURE_INIT (NodeId, Index, 1, 0); > CopyMem (New, &gicc, sizeof (EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE)); > New += sizeof (EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE); > } > > // Perform Checksum > - AcpiPlatformChecksum ((UINT8*) PageAddress, TableSize); > + AcpiPlatformChecksum ((UINT8 *)PageAddress, TableSize); > > Status = AcpiTable->InstallAcpiTable ( > AcpiTable, > @@ -760,7 +773,7 @@ AddSratTable ( > TableSize, > &TableHandle > ); > - if (EFI_ERROR(Status)) { > + if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "Failed to install SRAT table\n")); > } > > @@ -788,22 +801,22 @@ DisableXhciOnOlderPlatVer ( > if ( PLATFORM_VERSION_LESS_THAN (0, 3)) { > DEBUG ((DEBUG_ERROR, "Platform Version < 0.3 - disabling XHCI\n")); > Status = gBS->LocateProtocol ( > - &gEfiAcpiSdtProtocolGuid, > - NULL, > - (VOID **)&AcpiSdtProtocol > - ); > + &gEfiAcpiSdtProtocolGuid, > + NULL, > + (VOID **)&AcpiSdtProtocol > + ); > if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "Unable to locate ACPI table protocol\n")); > return Status; > } > > Status = AcpiLocateTableBySignature ( > - AcpiSdtProtocol, > - EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, > - &TableIndex, > - &Table, > - &TableKey > - ); > + AcpiSdtProtocol, > + EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, > + &TableIndex, > + &Table, > + &TableKey > + ); > if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "ACPI DSDT table not found!\n")); > ASSERT_EFI_ERROR (Status); > @@ -832,16 +845,15 @@ DisableXhciOnOlderPlatVer ( > return Status; > } > > - > EFI_STATUS > EFIAPI > InitializeSbsaQemuAcpiDxe ( > - IN EFI_HANDLE ImageHandle, > - IN EFI_SYSTEM_TABLE *SystemTable > + IN EFI_HANDLE ImageHandle, > + IN EFI_SYSTEM_TABLE *SystemTable > ) > { > - EFI_STATUS Status; > - EFI_ACPI_TABLE_PROTOCOL *AcpiTable; > + EFI_STATUS Status; > + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; > > // Check if ACPI Table Protocol has been installed > Status = gBS->LocateProtocol ( > @@ -857,20 +869,20 @@ InitializeSbsaQemuAcpiDxe ( > GicItsBase = PcdGet64 (PcdGicItsBase); > > if (GicItsBase > 0) { > - Status = AddIortTable (AcpiTable); > - if (EFI_ERROR (Status)) { > - DEBUG ((DEBUG_ERROR, "Failed to add IORT table\n")); > - } > + Status = AddIortTable (AcpiTable); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "Failed to add IORT table\n")); > + } > } > > Status = AddMadtTable (AcpiTable); > - if (EFI_ERROR(Status)) { > - DEBUG ((DEBUG_ERROR, "Failed to add MADT table\n")); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "Failed to add MADT table\n")); > } > > Status = AddSsdtTable (AcpiTable); > - if (EFI_ERROR(Status)) { > - DEBUG ((DEBUG_ERROR, "Failed to add SSDT table\n")); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "Failed to add SSDT table\n")); > } > > Status = AddPpttTable (AcpiTable); > @@ -878,7 +890,7 @@ InitializeSbsaQemuAcpiDxe ( > DEBUG ((DEBUG_ERROR, "Failed to add PPTT table\n")); > } > > - if (GetNumaNodeCount() > 1){ > + if (GetNumaNodeCount () > 1) { > Status = AddSratTable (AcpiTable); > if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "Failed to add SRAT table\n")); > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuHighMemDxe/SbsaQemuHighMemDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuHighMemDxe/SbsaQemuHighMemDxe.c > index d8dd80ae4bb4..81842a26bd3e 100644 > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuHighMemDxe/SbsaQemuHighMemDxe.c > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuHighMemDxe/SbsaQemuHighMemDxe.c > @@ -44,9 +44,9 @@ InitializeHighMemDxe ( > // > // Check for memory node and add the memory spaces except the lowest one > // > - NumMemNodes = GetMemNodeCount(); > - for (Index = 0; Index < NumMemNodes; Index++){ > - GetMemInfo(Index, &MemInfo); > + NumMemNodes = GetMemNodeCount (); > + for (Index = 0; Index < NumMemNodes; Index++) { > + GetMemInfo (Index, &MemInfo); > CurBase = MemInfo.AddressBase; > CurSize = MemInfo.AddressSize; > > @@ -101,7 +101,7 @@ InitializeHighMemDxe ( > > Attributes = EFI_MEMORY_WB; > if ((PcdGet64 (PcdDxeNxMemoryProtectionPolicy) & > - (1U << (UINT32)EfiConventionalMemory)) != 0) > + (1U << (UINT32)EfiConventionalMemory)) != 0) > { > Attributes |= EFI_MEMORY_XP; > } > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c > index 56be2455970d..657f9700062b 100644 > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c > @@ -20,39 +20,51 @@ > EFI_STATUS > EFIAPI > InitializeSbsaQemuPlatformDxe ( > - IN EFI_HANDLE ImageHandle, > - IN EFI_SYSTEM_TABLE *SystemTable > + IN EFI_HANDLE ImageHandle, > + IN EFI_SYSTEM_TABLE *SystemTable > ) > { > - EFI_STATUS Status; > - UINTN Size; > - VOID* Base; > - UINTN Arg0; > - UINTN Arg1; > - UINTN SmcResult; > - RETURN_STATUS Result; > + EFI_STATUS Status; > + UINTN Size; > + VOID *Base; > + UINTN Arg0; > + UINTN Arg1; > + UINTN SmcResult; > + RETURN_STATUS Result; > > DEBUG ((DEBUG_INFO, "%a: InitializeSbsaQemuPlatformDxe called\n", __FUNCTION__)); > > - Base = (VOID*)(UINTN)PcdGet64 (PcdPlatformAhciBase); > + Base = (VOID *)(UINTN)PcdGet64 (PcdPlatformAhciBase); > ASSERT (Base != NULL); > Size = (UINTN)PcdGet32 (PcdPlatformAhciSize); > ASSERT (Size != 0); > > - DEBUG ((DEBUG_INFO, "%a: Got platform AHCI %llx %u\n", > - __FUNCTION__, Base, Size)); > + DEBUG (( > + DEBUG_INFO, > + "%a: Got platform AHCI %llx %u\n", > + __FUNCTION__, > + Base, > + Size > + )); > > Status = RegisterNonDiscoverableMmioDevice ( > - NonDiscoverableDeviceTypeAhci, > - NonDiscoverableDeviceDmaTypeCoherent, > - NULL, > - NULL, > - 1, > - Base, Size); > + NonDiscoverableDeviceTypeAhci, > + NonDiscoverableDeviceDmaTypeCoherent, > + NULL, > + NULL, > + 1, > + Base, > + Size > + ); > > - if (EFI_ERROR(Status)) { > - DEBUG ((DEBUG_ERROR, "%a: NonDiscoverable: Cannot install AHCI device @%p (Staus == %r)\n", > - __FUNCTION__, Base, Status)); > + if (EFI_ERROR (Status)) { > + DEBUG (( > + DEBUG_ERROR, > + "%a: NonDiscoverable: Cannot install AHCI device @%p (Staus == %r)\n", > + __FUNCTION__, > + Base, > + Status > + )); > return Status; > } > > @@ -101,22 +113,32 @@ InitializeSbsaQemuPlatformDxe ( > Size = (UINTN)PcdGet32 (PcdPlatformXhciSize); > ASSERT (Size != 0); > > - DEBUG ((DEBUG_INFO, "%a: Got platform XHCI %llx %u\n", > - __FUNCTION__, Base, Size)); > + DEBUG (( > + DEBUG_INFO, > + "%a: Got platform XHCI %llx %u\n", > + __FUNCTION__, > + Base, > + Size > + )); > > Status = RegisterNonDiscoverableMmioDevice ( > - NonDiscoverableDeviceTypeXhci, > - NonDiscoverableDeviceDmaTypeCoherent, > - NULL, > - NULL, > - 1, > - Base, > - Size > - ); > + NonDiscoverableDeviceTypeXhci, > + NonDiscoverableDeviceDmaTypeCoherent, > + NULL, > + NULL, > + 1, > + Base, > + Size > + ); > > if (EFI_ERROR (Status)) { > - DEBUG ((DEBUG_ERROR, "%a: NonDiscoverable: Cannot install XHCI device @%p (Status == %r)\n", > - __FUNCTION__, Base, Status)); > + DEBUG (( > + DEBUG_ERROR, > + "%a: NonDiscoverable: Cannot install XHCI device @%p (Status == %r)\n", > + __FUNCTION__, > + Base, > + Status > + )); > return Status; > } > } > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuSmbiosDxe/SbsaQemuSmbiosDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuSmbiosDxe/SbsaQemuSmbiosDxe.c > index 9ef5168b79f6..1aeec8e4f75c 100644 > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuSmbiosDxe/SbsaQemuSmbiosDxe.c > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuSmbiosDxe/SbsaQemuSmbiosDxe.c > @@ -35,12 +35,12 @@ > A global variable to store the SMBIOS handle for table Type 16. This variable should > only be modified by calling PhyMemArrayInfoUpdateSmbiosType16. > **/ > -STATIC SMBIOS_HANDLE mPhyMemArrayInfoType16Handle = SMBIOS_HANDLE_PI_RESERVED; > +STATIC SMBIOS_HANDLE mPhyMemArrayInfoType16Handle = SMBIOS_HANDLE_PI_RESERVED; > > /** > SMBIOS data definition, TYPE16, Physical Memory Array > **/ > -SMBIOS_TABLE_TYPE16 mPhyMemArrayInfoType16 = { > +SMBIOS_TABLE_TYPE16 mPhyMemArrayInfoType16 = { > { EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, sizeof (SMBIOS_TABLE_TYPE16), 0 }, > MemoryArrayLocationSystemBoard, // Location; (system board) > MemoryArrayUseSystemMemory, // Use; (system memory) > @@ -50,14 +50,14 @@ SMBIOS_TABLE_TYPE16 mPhyMemArrayInfoType16 = { > 1, // NumberOfMemoryDevices > 0x0000080000000000ULL // ExtendedMaximumCapacity; (fixed at 8 TiB for SbsaQemu) > }; > -CHAR8 *mPhyMemArrayInfoType16Strings[] = { > +CHAR8 *mPhyMemArrayInfoType16Strings[] = { > NULL > }; > > /** > SMBIOS data definition, TYPE17, Physical Memory Array > **/ > -SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = { > +SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = { > { EFI_SMBIOS_TYPE_MEMORY_DEVICE, sizeof (SMBIOS_TABLE_TYPE17), 0 }, > 0, // MemoryArrayHandle; should match SMBIOS_TABLE_TYPE16.Handle, > // initialized at runtime, refer to MemDevInfoUpdateSmbiosType17 > @@ -70,7 +70,7 @@ SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = { > 0, // DeviceLocator String > 0, // BankLocator String > MemoryTypeUnknown, // MemoryType; (unknown) > - { // TypeDetail; > + { // TypeDetail; > 0, // Reserved :1; > 0, // Other :1; > 1, // Unknown :1; > @@ -101,15 +101,17 @@ SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = { > 0, // MaximumVoltage; (unknown) > 0, // ConfiguredVoltage; (unknown) > MemoryTechnologyDram, // MemoryTechnology; (DRAM) > - {{ // MemoryOperatingModeCapability > - 0, // Reserved :1; > - 0, // Other :1; > - 0, // Unknown :1; > - 1, // VolatileMemory :1; > - 0, // ByteAccessiblePersistentMemory :1; > - 0, // BlockAccessiblePersistentMemory :1; > - 0 // Reserved :10; > - }}, > + { // MemoryOperatingModeCapability > + { > + 0, // Reserved :1; > + 0, // Other :1; > + 0, // Unknown :1; > + 1, // VolatileMemory :1; > + 0, // ByteAccessiblePersistentMemory :1; > + 0, // BlockAccessiblePersistentMemory :1; > + 0 // Reserved :10; > + } > + }, > 0, // FirwareVersion > 0, // ModuleManufacturerID (unknown) > 0, // ModuleProductID (unknown) > @@ -122,12 +124,11 @@ SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = { > 0, // ExtendedSpeed > 0 // ExtendedConfiguredMemorySpeed > }; > -CHAR8 *mMemDevInfoType17Strings[] = { > +CHAR8 *mMemDevInfoType17Strings[] = { > NULL > }; > > - > -SMBIOS_TABLE_TYPE19 mMemArrMapInfoType19 = { > +SMBIOS_TABLE_TYPE19 mMemArrMapInfoType19 = { > { EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, sizeof (SMBIOS_TABLE_TYPE19), 0 }, > 0, // StartingAddress; initialized at runtime, refer to MemArrMapInfoUpdateSmbiosType19 > 0, // EndingAddress; initialized at runtime, refer to MemArrMapInfoUpdateSmbiosType19 > @@ -139,11 +140,10 @@ SMBIOS_TABLE_TYPE19 mMemArrMapInfoType19 = { > 0, // ExtendedEndingAddress; potentially initialized at runtime, > // refer to MemDevInfoUpdateSmbiosType17 > }; > -CHAR8 *mMemArrMapInfoType19Strings[] = { > +CHAR8 *mMemArrMapInfoType19Strings[] = { > NULL > }; > > - > /** > Create an SMBIOS record. > > @@ -159,26 +159,25 @@ CHAR8 *mMemArrMapInfoType19Strings[] = { > > @return EFI_SUCCESS on success, other values on error. > **/ > - > STATIC > EFI_STATUS > EFIAPI > LogSmbiosData ( > - IN EFI_SMBIOS_TABLE_HEADER *Template, > - IN CHAR8 **StringPack, > - OUT EFI_SMBIOS_HANDLE *DataSmbiosHandle > + IN EFI_SMBIOS_TABLE_HEADER *Template, > + IN CHAR8 **StringPack, > + OUT EFI_SMBIOS_HANDLE *DataSmbiosHandle > ) > { > - EFI_STATUS Status; > - EFI_SMBIOS_PROTOCOL *Smbios; > - EFI_SMBIOS_HANDLE SmbiosHandle; > - EFI_SMBIOS_TABLE_HEADER *Record; > - UINTN Index; > - UINTN StringSize; > - UINTN Size; > - CHAR8 *Str; > + EFI_STATUS Status; > + EFI_SMBIOS_PROTOCOL *Smbios; > + EFI_SMBIOS_HANDLE SmbiosHandle; > + EFI_SMBIOS_TABLE_HEADER *Record; > + UINTN Index; > + UINTN StringSize; > + UINTN Size; > + CHAR8 *Str; > > - Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID**)&Smbios); > + Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID **)&Smbios); > if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "Failed to locate SMBIOS protocol: %r\n", Status)); > return Status; > @@ -196,8 +195,9 @@ LogSmbiosData ( > } else { > for (Index = 0; StringPack[Index] != NULL; Index++) { > StringSize = AsciiStrSize (StringPack[Index]); > - Size += StringSize; > + Size += StringSize; > } > + > if (StringPack[0] == NULL) { > // > // If the only string is NULL, include it in size calculation > @@ -214,22 +214,24 @@ LogSmbiosData ( > // > // Copy over the template > // > - Record = (EFI_SMBIOS_TABLE_HEADER*)AllocateZeroPool (Size); > + Record = (EFI_SMBIOS_TABLE_HEADER *)AllocateZeroPool (Size); > if (Record == NULL) { > DEBUG ((DEBUG_ERROR, "Failed to allocate memory for SMBIOS table\n")); > return EFI_OUT_OF_RESOURCES; > } > + > CopyMem (Record, Template, Template->Length); > > // > // Append the string pack > // > - Str = ((CHAR8*)Record) + Record->Length; > + Str = ((CHAR8 *)Record) + Record->Length; > for (Index = 0; StringPack[Index] != NULL; Index++) { > StringSize = AsciiStrSize (StringPack[Index]); > CopyMem (Str, StringPack[Index], StringSize); > Str += StringSize; > } > + > // > // Add an additional NULL for a terminating double NULL > // > @@ -239,12 +241,12 @@ LogSmbiosData ( > // Add the table to SMBIOS > // > SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED; > - Status = Smbios->Add ( > - Smbios, > - gImageHandle, > - &SmbiosHandle, > - Record > - ); > + Status = Smbios->Add ( > + Smbios, > + gImageHandle, > + &SmbiosHandle, > + Record > + ); > > if ((Status == EFI_SUCCESS) && (DataSmbiosHandle != NULL)) { > *DataSmbiosHandle = SmbiosHandle; > @@ -255,7 +257,6 @@ LogSmbiosData ( > return Status; > } > > - > /** > Updates SMBIOS table Type 16 and creates an SMBIOS record for it. > > @@ -268,13 +269,12 @@ PhyMemArrayInfoUpdateSmbiosType16 ( > ) > { > LogSmbiosData ( > - (EFI_SMBIOS_TABLE_HEADER*)&mPhyMemArrayInfoType16, > + (EFI_SMBIOS_TABLE_HEADER *)&mPhyMemArrayInfoType16, > mPhyMemArrayInfoType16Strings, > &mPhyMemArrayInfoType16Handle > ); > } > > - > /** > Updates SMBIOS table Type 17 and creates an SMBIOS record for it. > > @@ -320,13 +320,12 @@ MemDevInfoUpdateSmbiosType17 ( > mMemDevInfoType17.VolatileSize = MemorySize; > > LogSmbiosData ( > - (EFI_SMBIOS_TABLE_HEADER*)&mMemDevInfoType17, > + (EFI_SMBIOS_TABLE_HEADER *)&mMemDevInfoType17, > mMemDevInfoType17Strings, > NULL > ); > } > > - > /** > Updates SMBIOS table Type 19 and creates an SMBIOS record for it. > > @@ -380,13 +379,12 @@ MemArrMapInfoUpdateSmbiosType19 ( > } > > LogSmbiosData ( > - (EFI_SMBIOS_TABLE_HEADER*)&mMemArrMapInfoType19, > + (EFI_SMBIOS_TABLE_HEADER *)&mMemArrMapInfoType19, > mMemArrMapInfoType19Strings, > NULL > ); > } > > - > /** > Driver entry point. > **/ > diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c > index 4c22e7d6ee47..596a3453c70f 100644 > --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c > +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c > @@ -23,8 +23,8 @@ GetCpuCount ( > VOID > ) > { > - UINTN Arg0; > - UINTN SmcResult; > + UINTN Arg0; > + UINTN SmcResult; > > SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_COUNT, &Arg0, NULL, NULL); > if (SmcResult != SMC_SIP_CALL_SUCCESS) { > @@ -100,8 +100,8 @@ GetMemNodeCount ( > VOID > ) > { > - UINTN SmcResult; > - UINTN Arg0; > + UINTN SmcResult; > + UINTN Arg0; > > SmcResult = ArmCallSmc0 (SIP_SVC_GET_MEMORY_NODE_COUNT, &Arg0, NULL, NULL); > if (SmcResult != SMC_SIP_CALL_SUCCESS) { > @@ -109,7 +109,7 @@ GetMemNodeCount ( > ResetShutdown (); > } > > - DEBUG (( DEBUG_INFO, "%a: The number of the memory nodes is %ld\n", __FUNCTION__, Arg0)); > + DEBUG ((DEBUG_INFO, "%a: The number of the memory nodes is %ld\n", __FUNCTION__, Arg0)); > return (UINT32)Arg0; > } > > @@ -119,10 +119,10 @@ GetMemInfo ( > OUT MemoryInfo *MemInfo > ) > { > - UINTN SmcResult; > - UINTN Arg0; > - UINTN Arg1; > - UINTN Arg2; > + UINTN SmcResult; > + UINTN Arg0; > + UINTN Arg1; > + UINTN Arg2; > > Arg0 = MemoryId; > > @@ -131,47 +131,49 @@ GetMemInfo ( > DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_MEMORY_NODE call failed. We have no memory information.\n", __FUNCTION__)); > ResetShutdown (); > } else { > - MemInfo->NodeId = Arg0; > + MemInfo->NodeId = Arg0; > MemInfo->AddressBase = Arg1; > MemInfo->AddressSize = Arg2; > } > > - DEBUG(( DEBUG_INFO, "%a: NUMA node for System RAM:%d = 0x%lx - 0x%lx\n", > - __FUNCTION__, > - MemInfo->NodeId, > - MemInfo->AddressBase, > - MemInfo->AddressBase + MemInfo->AddressSize -1 )); > - > + DEBUG (( > + DEBUG_INFO, > + "%a: NUMA node for System RAM:%d = 0x%lx - 0x%lx\n", > + __FUNCTION__, > + MemInfo->NodeId, > + MemInfo->AddressBase, > + MemInfo->AddressBase + MemInfo->AddressSize -1 > + )); > } > > UINT64 > GetNumaNodeCount ( > VOID > -) > + ) > { > - UINT64 Arg; > - UINT32 Index; > - UINT32 NumberNumaNodes; > - UINT32 NumberMemNodes; > - UINT32 NumCores = GetCpuCount(); > - MemoryInfo MemInfo; > + UINT64 Arg; > + UINT32 Index; > + UINT32 NumberNumaNodes; > + UINT32 NumberMemNodes; > + UINT32 NumCores = GetCpuCount (); > + MemoryInfo MemInfo; > > NumberNumaNodes = 0; > - NumberMemNodes = GetMemNodeCount(); > + NumberMemNodes = GetMemNodeCount (); > > - if (NumCores > 0){ > - for (Index = 0; Index < NumCores; Index ++){ > - Arg = GetCpuNumaNode(Index); > - if (NumberNumaNodes == 0 || NumberNumaNodes < (Arg + 1)){ > + if (NumCores > 0) { > + for (Index = 0; Index < NumCores; Index++) { > + Arg = GetCpuNumaNode (Index); > + if ((NumberNumaNodes == 0) || (NumberNumaNodes < (Arg + 1))) { > NumberNumaNodes = Arg + 1; > } > } > } > > - if (NumberMemNodes > 0){ > - for (Index = 0; Index < NumberMemNodes; Index ++){ > - GetMemInfo(Index, &MemInfo); > - if (NumberNumaNodes == 0 || NumberNumaNodes < (MemInfo.NodeId + 1)){ > + if (NumberMemNodes > 0) { > + for (Index = 0; Index < NumberMemNodes; Index++) { > + GetMemInfo (Index, &MemInfo); > + if ((NumberNumaNodes == 0) || (NumberNumaNodes < (MemInfo.NodeId + 1))) { > NumberNumaNodes = MemInfo.NodeId + 1; > } > } > diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.c > index 411f653913bd..56f563b42d4e 100644 > --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.c > +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuLib.c > @@ -11,8 +11,7 @@ > > #include > > - > -ARM_CORE_INFO mArmPlatformNullMpCoreInfoTable[] = { > +ARM_CORE_INFO mArmPlatformNullMpCoreInfoTable[] = { > { > // Cluster 0, Core 0 > 0x000, > @@ -88,7 +87,7 @@ ArmPlatformGetBootMode ( > **/ > RETURN_STATUS > ArmPlatformInitialize ( > - IN UINTN MpId > + IN UINTN MpId > ) > { > if (!ArmPlatformIsPrimaryCore (MpId)) { > @@ -100,12 +99,12 @@ ArmPlatformInitialize ( > > EFI_STATUS > PrePeiCoreGetMpCoreInfo ( > - OUT UINTN *CoreCount, > - OUT ARM_CORE_INFO **ArmCoreTable > + OUT UINTN *CoreCount, > + OUT ARM_CORE_INFO **ArmCoreTable > ) > { > - if (ArmIsMpCore()) { > - *CoreCount = ARRAY_SIZE(mArmPlatformNullMpCoreInfoTable); > + if (ArmIsMpCore ()) { > + *CoreCount = ARRAY_SIZE (mArmPlatformNullMpCoreInfoTable); > *ArmCoreTable = mArmPlatformNullMpCoreInfoTable; > return EFI_SUCCESS; > } else { > @@ -113,9 +112,9 @@ PrePeiCoreGetMpCoreInfo ( > } > } > > -ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; > +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo }; > > -EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { > +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { > { > EFI_PEI_PPI_DESCRIPTOR_PPI, > &gArmMpCoreInfoPpiGuid, > @@ -129,11 +128,11 @@ ArmPlatformGetPlatformPpiList ( > OUT EFI_PEI_PPI_DESCRIPTOR **PpiList > ) > { > - if (ArmIsMpCore()) { > + if (ArmIsMpCore ()) { > *PpiListSize = sizeof (gPlatformPpiTable); > - *PpiList = gPlatformPpiTable; > + *PpiList = gPlatformPpiTable; > } else { > *PpiListSize = 0; > - *PpiList = NULL; > + *PpiList = NULL; > } > } > diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c > index f838fdcf274d..48a3fa72d2d7 100644 > --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c > +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuLib/SbsaQemuMem.c > @@ -15,7 +15,7 @@ > #include > > // Number of Virtual Memory Map Descriptors > -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 4 > +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 4 > > RETURN_STATUS > EFIAPI > @@ -23,23 +23,23 @@ SbsaQemuLibConstructor ( > VOID > ) > { > - UINT64 NewBase, CurBase; > - UINT64 NewSize, CurSize; > - UINT32 NumMemNodes; > - UINT32 Index; > - MemoryInfo MemInfo; > - RETURN_STATUS PcdStatus; > + UINT64 NewBase, CurBase; > + UINT64 NewSize, CurSize; > + UINT32 NumMemNodes; > + UINT32 Index; > + MemoryInfo MemInfo; > + RETURN_STATUS PcdStatus; > > NewBase = 0; > NewSize = 0; > > - NumMemNodes = GetMemNodeCount(); > - for(Index = 0; Index < NumMemNodes; Index++){ > - GetMemInfo(Index, &MemInfo); > + NumMemNodes = GetMemNodeCount (); > + for (Index = 0; Index < NumMemNodes; Index++) { > + GetMemInfo (Index, &MemInfo); > CurBase = MemInfo.AddressBase; > CurSize = MemInfo.AddressSize; > > - if (NewBase > CurBase || NewBase == 0) { > + if ((NewBase > CurBase) || (NewBase == 0)) { > NewBase = CurBase; > NewSize = CurSize; > } > @@ -68,15 +68,17 @@ SbsaQemuLibConstructor ( > **/ > VOID > ArmPlatformGetVirtualMemoryMap ( > - OUT ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap > + OUT ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap > ) > { > ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; > > ASSERT (VirtualMemoryMap != NULL); > > - VirtualMemoryTable = AllocatePool (sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * > - MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); > + VirtualMemoryTable = AllocatePool ( > + sizeof (ARM_MEMORY_REGION_DESCRIPTOR) * > + MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS > + ); > > if (VirtualMemoryTable == NULL) { > DEBUG ((DEBUG_ERROR, "%a: Error: Failed AllocatePool()\n", __FUNCTION__)); > @@ -89,14 +91,17 @@ ArmPlatformGetVirtualMemoryMap ( > VirtualMemoryTable[0].Length = PcdGet64 (PcdSystemMemorySize); > VirtualMemoryTable[0].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; > > - DEBUG ((DEBUG_INFO, "%a: Dumping System DRAM Memory Map:\n" > - "\tPhysicalBase: 0x%lX\n" > - "\tVirtualBase: 0x%lX\n" > - "\tLength: 0x%lX\n", > - __FUNCTION__, > - VirtualMemoryTable[0].PhysicalBase, > - VirtualMemoryTable[0].VirtualBase, > - VirtualMemoryTable[0].Length)); > + DEBUG (( > + DEBUG_INFO, > + "%a: Dumping System DRAM Memory Map:\n" > + "\tPhysicalBase: 0x%lX\n" > + "\tVirtualBase: 0x%lX\n" > + "\tLength: 0x%lX\n", > + __FUNCTION__, > + VirtualMemoryTable[0].PhysicalBase, > + VirtualMemoryTable[0].VirtualBase, > + VirtualMemoryTable[0].Length > + )); > > // Peripheral space before DRAM > VirtualMemoryTable[1].PhysicalBase = 0x0; > diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.c > index 56c26019a140..b454ac6279b8 100644 > --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.c > +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuNorFlashLib/SbsaQemuNorFlashLib.c > @@ -10,7 +10,7 @@ > #include > #include > > -#define QEMU_NOR_BLOCK_SIZE SIZE_256KB > +#define QEMU_NOR_BLOCK_SIZE SIZE_256KB > > EFI_STATUS > VirtNorFlashPlatformInitialization ( > @@ -20,12 +20,12 @@ VirtNorFlashPlatformInitialization ( > return EFI_SUCCESS; > } > > -STATIC VIRT_NOR_FLASH_DESCRIPTION mNorFlashDevice = > +STATIC VIRT_NOR_FLASH_DESCRIPTION mNorFlashDevice = > { > - FixedPcdGet64(PcdFdBaseAddress), > - FixedPcdGet64(PcdFlashNvStorageVariableBase), > - FixedPcdGet32(PcdFdSize), > - QEMU_NOR_BLOCK_SIZE > + FixedPcdGet64 (PcdFdBaseAddress), > + FixedPcdGet64 (PcdFlashNvStorageVariableBase), > + FixedPcdGet32 (PcdFdSize), > + QEMU_NOR_BLOCK_SIZE > }; > > EFI_STATUS > @@ -35,6 +35,6 @@ VirtNorFlashPlatformGetDevices ( > ) > { > *NorFlashDescriptions = &mNorFlashDevice; > - *Count = 1; > + *Count = 1; > return EFI_SUCCESS; > } > diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c > index 9739c7500def..8994a5226289 100644 > --- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c > +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuPciHostBridgeLib/SbsaQemuPciHostBridgeLib.c > @@ -18,22 +18,22 @@ > > #pragma pack(1) > typedef struct { > - ACPI_HID_DEVICE_PATH AcpiDevicePath; > - EFI_DEVICE_PATH_PROTOCOL EndDevicePath; > + ACPI_HID_DEVICE_PATH AcpiDevicePath; > + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; > } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; > #pragma pack () > > -STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = { > +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = { > { > { > ACPI_DEVICE_PATH, > ACPI_DP, > { > - (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), > - (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) > + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)), > + (UINT8)((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) > } > }, > - EISA_PNP_ID(0x0A03), > + EISA_PNP_ID (0x0A03), > 0 > }, > > @@ -48,11 +48,11 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = { > }; > > GLOBAL_REMOVE_IF_UNREFERENCED > -CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { > +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { > L"Mem", L"I/O", L"Bus" > }; > > -STATIC PCI_ROOT_BRIDGE mRootBridge = { > +STATIC PCI_ROOT_BRIDGE mRootBridge = { > /* UINT32 Segment; Segment number */ > 0, > > @@ -78,20 +78,20 @@ STATIC PCI_ROOT_BRIDGE mRootBridge = { > > /* UINT64 AllocationAttributes; Allocation attributes. */ > EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | > - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, /* as Mmio64Size > 0 */ > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, /* as Mmio64Size > 0 */ > > { > - /* PCI_ROOT_BRIDGE_APERTURE Bus; Bus aperture which can be used by the > - * root bridge. */ > - FixedPcdGet32 (PcdPciBusMin), > - FixedPcdGet32 (PcdPciBusMax) > + /* PCI_ROOT_BRIDGE_APERTURE Bus; Bus aperture which can be used by the > + * root bridge. */ > + FixedPcdGet32 (PcdPciBusMin), > + FixedPcdGet32 (PcdPciBusMax) > }, > > /* PCI_ROOT_BRIDGE_APERTURE Io; IO aperture which can be used by the root > bridge */ > { > - FixedPcdGet64 (PcdPciIoBase), > - FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1 > + FixedPcdGet64 (PcdPciIoBase), > + FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1 > }, > > /* PCI_ROOT_BRIDGE_APERTURE Mem; MMIO aperture below 4GB which can be used by > @@ -114,11 +114,11 @@ STATIC PCI_ROOT_BRIDGE mRootBridge = { > can be used by the root bridge. > In our case, there are no separate ranges for prefetchable and > non-prefetchable BARs */ > - { MAX_UINT64, 0 }, > + { MAX_UINT64, 0 }, > > /* PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; Prefetchable MMIO aperture above 4GB > which can be used by the root bridge. */ > - { MAX_UINT64, 0 }, > + { MAX_UINT64, 0 }, > /* EFI_DEVICE_PATH_PROTOCOL *DevicePath; Device path. */ > (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath, > }; > @@ -135,7 +135,7 @@ STATIC PCI_ROOT_BRIDGE mRootBridge = { > PCI_ROOT_BRIDGE * > EFIAPI > PciHostBridgeGetRootBridges ( > - UINTN *Count > + UINTN *Count > ) > { > *Count = 1; > @@ -152,8 +152,8 @@ PciHostBridgeGetRootBridges ( > VOID > EFIAPI > PciHostBridgeFreeRootBridges ( > - PCI_ROOT_BRIDGE *Bridges, > - UINTN Count > + PCI_ROOT_BRIDGE *Bridges, > + UINTN Count > ) > { > ASSERT (Count == 1); > @@ -176,40 +176,50 @@ PciHostBridgeFreeRootBridges ( > VOID > EFIAPI > PciHostBridgeResourceConflict ( > - EFI_HANDLE HostBridgeHandle, > - VOID *Configuration > + EFI_HANDLE HostBridgeHandle, > + VOID *Configuration > ) > { > - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; > - UINTN RootBridgeIndex; > + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; > + UINTN RootBridgeIndex; > + > DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n")); > > RootBridgeIndex = 0; > - Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; > + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration; > while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { > DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); > - for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { > - ASSERT (Descriptor->ResType < > - ARRAY_SIZE(mPciHostBridgeLibAcpiAddressSpaceTypeStr)); > - DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n", > - mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], > - Descriptor->AddrLen, Descriptor->AddrRangeMax > - )); > + for ( ; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { > + ASSERT ( > + Descriptor->ResType < > + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr) > + ); > + DEBUG (( > + DEBUG_ERROR, > + " %s: Length/Alignment = 0x%lx / 0x%lx\n", > + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], > + Descriptor->AddrLen, > + Descriptor->AddrRangeMax > + )); > if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { > - DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n", > - Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, > - ((Descriptor->SpecificFlag & > - EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE > - ) != 0) ? L" (Prefetchable)" : L"" > - )); > + DEBUG (( > + DEBUG_ERROR, > + " Granularity/SpecificFlag = %ld / %02x%s\n", > + Descriptor->AddrSpaceGranularity, > + Descriptor->SpecificFlag, > + ((Descriptor->SpecificFlag & > + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE > + ) != 0) ? L" (Prefetchable)" : L"" > + )); > } > } > + > // > // Skip the END descriptor for root bridge > // > ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); > Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( > - (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 > - ); > + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 > + ); > } > } > -- > 2.45.2 > > > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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