From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id 873147803D8 for ; Tue, 9 Jul 2024 13:02:01 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=poKzNwEfu4K2+gDaGFnM3J0zMWPvgSmWsAqT5NvVBx0=; c=relaxed/simple; d=groups.io; h=Date:From:To:CC:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20240206; t=1720530121; v=1; b=lstKthNqsH6rJPCnwqCRVCyPJ768UPAcxZMf3URU/SO3GEbJJgn29sZ2sq5AMQX8JSqsPpZX kmgkOCZVwOWLy2htMfUfYxFcQniRIXrel/K1kdzSdJOiZkYoJJGMve8f13QmL+fMM9n7/3ze8/y C79g5CixvNBzq1p7Em4G2kRS+1LHT007UJYq44KH6lXDa3RkKsSGzcK69cdrXVbUb1oiFTM/p2W Zre8C+ua6N7yeq1udbPUU+lZEadhWjYpwPk5ItFlpkRytkhZalwtVW8yubCIOmDLMx12ejqgdCq y+1SH51CN87xOx6/9+SI37Ha8CqRlISn1x9GgBUrsi0ag== X-Received: by 127.0.0.2 with SMTP id VE9lYY7687511xKEhVaQ1UFL; Tue, 09 Jul 2024 06:02:00 -0700 X-Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by mx.groups.io with SMTP id smtpd.web10.12443.1720530119556774453 for ; Tue, 09 Jul 2024 06:01:59 -0700 X-Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 469CHCAF011903; Tue, 9 Jul 2024 13:01:59 GMT X-Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 406xpdp7gc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 Jul 2024 13:01:58 +0000 (GMT) X-Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 469D1we0022892 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 9 Jul 2024 13:01:58 GMT X-Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 9 Jul 2024 06:01:56 -0700 Date: Tue, 9 Jul 2024 14:01:53 +0100 From: "Leif Lindholm" To: Marcin Juszkiewicz CC: , Xiong Yining , Ard Biesheuvel , Graeme Gregory , Chen Baozi Subject: Re: [edk2-devel] [PATCH edk2-platforms v3 4/5] SbsaQemu: provide cache info per core in PPTT Message-ID: References: <20240709-acpi65-v3-0-ee93ba536fcf@linaro.org> <20240709-acpi65-v3-4-ee93ba536fcf@linaro.org> MIME-Version: 1.0 In-Reply-To: <20240709-acpi65-v3-4-ee93ba536fcf@linaro.org> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-GUID: 3sqRpmRWVZrSxKcnZoh8K0jstypMraqP X-Proofpoint-ORIG-GUID: 3sqRpmRWVZrSxKcnZoh8K0jstypMraqP Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Tue, 09 Jul 2024 06:01:59 -0700 Resent-From: quic_llindhol@quicinc.com Reply-To: devel@edk2.groups.io,quic_llindhol@quicinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: sgNAcklMk50B4VT8EU87womyx7686176AA= Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=lstKthNq; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=quicinc.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io On Tue, Jul 09, 2024 at 12:47:09 +0200, Marcin Juszkiewicz wrote: > During Linaro Connect MAD24 I was asked to move cache information from > being 'per cluster' to be 'per core'. This is a move for implementing > MPAM support. > > So topology moves from: > > Socket -> Clusters -> Cores + Caches -> Threads (if exist) > > to: > > Socket -> Clusters -> Cores -> Caches + Threads (if exist) > > Cache sizes are still 32+32+512KB (L1d, L1i, L2) as QEMU does not > implement them at all so we can tell whatever. > > Signed-off-by: Marcin Juszkiewicz Reviewed-by: Leif Lindholm / Leif > --- > .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 47 +++++++++++--------- > 1 file changed, 25 insertions(+), 22 deletions(-) > > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > index cf0102d11f1f..a7a9664abdcb 100644 > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > @@ -562,8 +562,8 @@ AddPpttTable ( > TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) + > CpuTopo.Sockets * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + > CpuTopo.Clusters * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + > - sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 + > CpuTopo.Cores * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + > + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 + > sizeof (UINT32) * 2))); > > if (CpuTopo.Threads > 1) { > @@ -609,10 +609,7 @@ AddPpttTable ( > > ClusterIndex = SocketIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR); > for (ClusterNum = 0; ClusterNum < CpuTopo.Clusters; ClusterNum++) { > - L1DCacheIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR); > - L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > - L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > - CoreIndex = L2CacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > + CoreIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR); > > // Add the Cluster PPTT structure > EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT ( > @@ -624,27 +621,15 @@ AddPpttTable ( > CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR)); > New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR); > > - // Add L1 D Cache structure > - L1DCache.CacheId = CacheId++; > - CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE)); > - ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex; > - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > - > - // Add L1 I Cache structure > - L1ICache.CacheId = CacheId++; > - CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE)); > - ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex; > - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > - > - // Add L2 Cache structure > - L2Cache.CacheId = CacheId++; > - CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE)); > - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > - > for (CoreNum = 0; CoreNum < CpuTopo.Cores; CoreNum++) { > UINT32 *PrivateResourcePtr; > UINT32 CoreCpuId; > > + // two UINT32s for PrivateResourcePtr data > + L1DCacheIndex = CoreIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2; > + L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > + L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > + > if (CpuTopo.Threads == 1) { > CoreCpuId = CpuId; > } else { > @@ -665,6 +650,23 @@ AddPpttTable ( > PrivateResourcePtr[1] = L1ICacheIndex; > New += (2 * sizeof (UINT32)); > > + // Add L1 D Cache structure > + L1DCache.CacheId = CacheId++; > + CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE)); > + ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex; > + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > + > + // Add L1 I Cache structure > + L1ICache.CacheId = CacheId++; > + CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE)); > + ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex; > + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > + > + // Add L2 Cache structure > + L2Cache.CacheId = CacheId++; > + CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE)); > + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > + > if (CpuTopo.Threads == 1) { > CpuId++; > } else { > @@ -685,6 +687,7 @@ AddPpttTable ( > } > > CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2; > + CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3; > } > > ClusterIndex = CoreIndex; > > -- > 2.45.2 > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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