From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail05.groups.io (mail05.groups.io [45.79.224.7]) by spool.mail.gandi.net (Postfix) with ESMTPS id 28F03740040 for ; Wed, 10 Jul 2024 14:40:05 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=GC74+KCLnowfx4LpMUof0Euz522LBp9XW8KKnaluZws=; c=relaxed/simple; d=groups.io; h=Date:From:To:CC:Subject:Message-ID:References:MIME-Version:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Resent-Date:Resent-From:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Disposition; s=20240206; t=1720622405; v=1; b=RB3HAs3xyt0kTFyE5gbs0mPScMVTaqc0zQ+UATWuVrTcU5dgsWMRhYYOi2Se5jFgm9F8zMgW cvrgebeJHL2ljfEL18XRkiGtbXu/iu2nVwarE/2Vj4vMwscygOSzcYIm4EXWADL0YsucJ2AsJYU FDb+4YMFeSk/G/80OnVq3DbV3Ndw1WX8GONg2ZOuhgUeRm5HwxClLr+pMkMgqfNl4JZklPNwe3t oPPXvo8r65JmkC4qN1vrjJgiy+nwpx+4wR3FFLW6E1Y/oaGw3AekAL6zNSowhR9wOBR+rEMWRp9 pgh2lojNB7dH/CZ7QG/vVIEUJWIUbYXa9SElNDSkR0/yw== X-Received: by 127.0.0.2 with SMTP id rATvYY7687511xdKban8asMC; Wed, 10 Jul 2024 07:40:04 -0700 X-Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by mx.groups.io with SMTP id smtpd.web10.16200.1720622403926867994 for ; Wed, 10 Jul 2024 07:40:03 -0700 X-Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 46AA93GY014295; Wed, 10 Jul 2024 14:40:03 GMT X-Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 406wg41ut6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Jul 2024 14:40:03 +0000 (GMT) X-Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46AEe2oX023792 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Jul 2024 14:40:02 GMT X-Received: from qc-i7.hemma.eciton.net (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 10 Jul 2024 07:40:00 -0700 Date: Wed, 10 Jul 2024 15:39:57 +0100 From: "Leif Lindholm" To: Jonathan Cameron CC: , Marcin Juszkiewicz , Xiong Yining , Ard Biesheuvel , Graeme Gregory , Chen Baozi Subject: Re: [edk2-devel] [PATCH edk2-platforms v3 4/5] SbsaQemu: provide cache info per core in PPTT Message-ID: References: <20240709-acpi65-v3-0-ee93ba536fcf@linaro.org> <20240709-acpi65-v3-4-ee93ba536fcf@linaro.org> <20240710145852.0000405a@Huawei.com> MIME-Version: 1.0 In-Reply-To: <20240710145852.0000405a@Huawei.com> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-ORIG-GUID: nGKec2-4-rWCac2-8QzDoJHjOO7cy0Cz X-Proofpoint-GUID: nGKec2-4-rWCac2-8QzDoJHjOO7cy0Cz Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Wed, 10 Jul 2024 07:40:04 -0700 Resent-From: quic_llindhol@quicinc.com Reply-To: devel@edk2.groups.io,quic_llindhol@quicinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: RXvMTh8VK9N1WLXXS1kcO9hYx7686176AA= Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=RB3HAs3x; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=quicinc.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io On Wed, Jul 10, 2024 at 14:58:52 +0100, Jonathan Cameron wrote: > On Tue, 9 Jul 2024 14:01:53 +0100 > "Leif Lindholm" wrote: > > > On Tue, Jul 09, 2024 at 12:47:09 +0200, Marcin Juszkiewicz wrote: > > > During Linaro Connect MAD24 I was asked to move cache information from > > > being 'per cluster' to be 'per core'. This is a move for implementing > > > MPAM support. > > > > > > So topology moves from: > > > > > > Socket -> Clusters -> Cores + Caches -> Threads (if exist) > > > > > > to: > > > > > > Socket -> Clusters -> Cores -> Caches + Threads (if exist) > > > > > > Cache sizes are still 32+32+512KB (L1d, L1i, L2) as QEMU does not > > > implement them at all so we can tell whatever. > > They should match the system registers. > CCSIDR etc which are provided by QEMU. That's a good point. Thanks for bringing that up. edk2-platforms/Platform/Ampere/JadePkg/Drivers/AcpiPlatformDxe/AcpiPptt.c demonstrates how this can be done with existing edk2 interfaces and definitions. Ultimately, this will only ever be possible to runtime-generate in edk2 for homogenous systems. Any big-little type setups need to get the information from TF-A. / Leif > Here's some old code for doing PPTT cache entry generation for arm-virt. > > https://lore.kernel.org/qemu-devel/20230808115713.2613-2-Jonathan.Cameron@huawei.com/ > > The numbers might happen to match what it has for the cpu you are using though. > https://elixir.bootlin.com/qemu/latest/source/target/arm/tcg/cpu64.c#L1051 > > For n2 that looks to be 64+64+512... > > > > > > > > > Signed-off-by: Marcin Juszkiewicz > > > > Reviewed-by: Leif Lindholm > > > > / > > Leif > > > > > --- > > > .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 47 +++++++++++--------- > > > 1 file changed, 25 insertions(+), 22 deletions(-) > > > > > > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > > > index cf0102d11f1f..a7a9664abdcb 100644 > > > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > > > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > > > @@ -562,8 +562,8 @@ AddPpttTable ( > > > TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) + > > > CpuTopo.Sockets * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + > > > CpuTopo.Clusters * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + > > > - sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 + > > > CpuTopo.Cores * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + > > > + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 + > > > sizeof (UINT32) * 2))); > > > > > > if (CpuTopo.Threads > 1) { > > > @@ -609,10 +609,7 @@ AddPpttTable ( > > > > > > ClusterIndex = SocketIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR); > > > for (ClusterNum = 0; ClusterNum < CpuTopo.Clusters; ClusterNum++) { > > > - L1DCacheIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR); > > > - L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > > > - L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > > > - CoreIndex = L2CacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > > > + CoreIndex = ClusterIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR); > > > > > > // Add the Cluster PPTT structure > > > EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT ( > > > @@ -624,27 +621,15 @@ AddPpttTable ( > > > CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR)); > > > New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR); > > > > > > - // Add L1 D Cache structure > > > - L1DCache.CacheId = CacheId++; > > > - CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE)); > > > - ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex; > > > - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > > > - > > > - // Add L1 I Cache structure > > > - L1ICache.CacheId = CacheId++; > > > - CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE)); > > > - ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex; > > > - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > > > - > > > - // Add L2 Cache structure > > > - L2Cache.CacheId = CacheId++; > > > - CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE)); > > > - New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > > > - > > > for (CoreNum = 0; CoreNum < CpuTopo.Cores; CoreNum++) { > > > UINT32 *PrivateResourcePtr; > > > UINT32 CoreCpuId; > > > > > > + // two UINT32s for PrivateResourcePtr data > > > + L1DCacheIndex = CoreIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2; > > > + L1ICacheIndex = L1DCacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > > > + L2CacheIndex = L1ICacheIndex + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > > > + > > > if (CpuTopo.Threads == 1) { > > > CoreCpuId = CpuId; > > > } else { > > > @@ -665,6 +650,23 @@ AddPpttTable ( > > > PrivateResourcePtr[1] = L1ICacheIndex; > > > New += (2 * sizeof (UINT32)); > > > > > > + // Add L1 D Cache structure > > > + L1DCache.CacheId = CacheId++; > > > + CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE)); > > > + ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex; > > > + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > > > + > > > + // Add L1 I Cache structure > > > + L1ICache.CacheId = CacheId++; > > > + CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE)); > > > + ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheIndex; > > > + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > > > + > > > + // Add L2 Cache structure > > > + L2Cache.CacheId = CacheId++; > > > + CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE)); > > > + New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE); > > > + > > > if (CpuTopo.Threads == 1) { > > > CpuId++; > > > } else { > > > @@ -685,6 +687,7 @@ AddPpttTable ( > > > } > > > > > > CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2; > > > + CoreIndex += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3; > > > } > > > > > > ClusterIndex = CoreIndex; > > > > > > -- > > > 2.45.2 > > > > > > > > > > > > > > -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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