From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 0A117AC0D57 for ; Thu, 15 Feb 2024 09:21:07 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=U1zRJsiAvfxbccTzsbw7HTsF+dA1fMZs3OIb7J7rLQc=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1707988866; v=1; b=tpwQtrJX6Sv6qLSKF0sgin73UFbu4DIyKoLtQrr0lUY4c8mo85YHrwkBelznSI3XutHG/ZBk ULz0IXzrW2ZDHnG+ywdh/wM+Au3AuW1pNXSd+hpQltvcz8qUtb/7rg13tWC7ZOSmlIqo0803weD ir+GJBI08ud6ES91DvN0R/44= X-Received: by 127.0.0.2 with SMTP id IXZoYY7687511xzDxAXYqrep; Thu, 15 Feb 2024 01:21:06 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by mx.groups.io with SMTP id smtpd.web11.10417.1707988865983578957 for ; Thu, 15 Feb 2024 01:21:06 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10984"; a="1943033" X-IronPort-AV: E=Sophos;i="6.06,161,1705392000"; d="scan'208";a="1943033" X-Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2024 01:21:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,161,1705392000"; d="scan'208";a="8086917" X-Received: from chsuehx-desk.gar.corp.intel.com ([10.225.77.6]) by fmviesa003.fm.intel.com with ESMTP; 15 Feb 2024 01:21:02 -0800 From: dorax.hsueh@intel.com To: devel@edk2.groups.io Cc: DoraX Hsueh , Sai Chaganty , Rosen Chuang , Saloni Kasbekar , Haoyu Tang , Nate DeSimone Subject: [edk2-devel] [PATCH] AlderlakeOpenBoardPkg: Change MinPlatform MinDsdt and Update SpiFlashCommonLib Date: Thu, 15 Feb 2024 17:20:55 +0800 Message-Id: MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,dorax.hsueh@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: CWwOzIG7jue1IzNz4MoyJg17x7686176AA= Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=tpwQtrJX; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io From: DoraX Hsueh https://bugzilla.tianocore.org/show_bug.cgi?id=3D4662 1. Change MinPlatform MinDsdt to fix hang logo issue. 2. Update SecFspWrapperPlatformSecLib for FSP use. 3. Update SpiFlashCommonLib to fix boot assert issue. Cc: Sai Chaganty Cc: Rosen Chuang Cc: Saloni Kasbekar Cc: Haoyu Tang Cc: Nate DeSimone Signed-off-by: DoraX Hsueh --- .../Acpi/MinDsdt/MinDsdt.asl | 68 --- .../Acpi/MinDsdt/MinDsdt.c | 232 ----------- .../Acpi/MinDsdt/MinDsdt.inf | 48 --- .../AlderlakePRvp/OpenBoardPkg.dsc | 6 +- .../AlderlakePRvp/OpenBoardPkg.fdf | 2 +- .../AlderlakePRvp/OpenBoardPkgPcd.dsc | 8 + .../FspWrapperPlatformSecLib.c | 186 +++++++++ .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 394 ++++++++++++++++++ .../SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 42 ++ .../Ia32/PeiCoreEntry.nasm | 130 ++++++ .../Ia32/SecEntry.nasm | 361 ++++++++++++++++ .../Ia32/Stack.nasm | 72 ++++ .../PlatformInit.c | 47 +++ .../SecFspWrapperPlatformSecLib.inf | 106 +++++ .../SecGetPerformance.c | 89 ++++ .../SecPlatformInformation.c | 78 ++++ .../SecRamInitData.c | 57 +++ .../SecTempRamDone.c | 93 +++++ .../Include/Library/SpiFlashCommon.h | 99 ----- .../SmmSpiFlashCommonLib.inf | 49 --- .../SmmSpiFlashCommonLib/SpiFlashCommon.c | 215 ---------- .../SpiFlashCommonSmmLib.c | 60 --- .../OpenBoardPlatformInitPostMem.c | 96 +---- .../OpenBoardPlatformInitPostMem.inf | 20 - .../PeiCpuPolicyUpdatePreMem.c | 3 - .../PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf | 3 +- 26 files changed, 1669 insertions(+), 895 deletions(-) delete mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDs= dt.asl delete mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDs= dt.c delete mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDs= dt.inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library= /SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library= /SecFspWrapperPlatformSecLib/FsptCoreUpd.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library= /SecFspWrapperPlatformSecLib/Ia32/Fsp.h create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library= /SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library= /SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library= /SecFspWrapperPlatformSecLib/Ia32/Stack.nasm create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library= /SecFspWrapperPlatformSecLib/PlatformInit.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library= /SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library= /SecFspWrapperPlatformSecLib/SecGetPerformance.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library= /SecFspWrapperPlatformSecLib/SecPlatformInformation.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library= /SecFspWrapperPlatformSecLib/SecRamInitData.c create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library= /SecFspWrapperPlatformSecLib/SecTempRamDone.c delete mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/Sp= iFlashCommon.h delete mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlas= hCommonLib/SmmSpiFlashCommonLib.inf delete mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlas= hCommonLib/SpiFlashCommon.c delete mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlas= hCommonLib/SpiFlashCommonSmmLib.c diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl = b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl deleted file mode 100644 index be110145..00000000 --- a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.asl +++ /dev/null @@ -1,68 +0,0 @@ -/** @file=0D - ACPI minimum DSDT table=0D -=0D - Copyright (c) 2022, Intel Corporation. All rights reserved.
=0D - SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -DefinitionBlock (=0D - "DSDT.aml",=0D - "DSDT",=0D - 0x01, // DSDT revision.=0D - // A Revision field value greater than or equal to 2 signifies tha= t integers=0D - // declared within the Definition Block are to be evaluated as 64-= bit values=0D - "INTEL ", // OEM ID (6 byte string)=0D - "MIN ",// OEM table ID (8 byte string)=0D - 0x00 // OEM version of DSDT table (4 byte Integer)=0D -)=0D -=0D -// BEGIN OF ASL SCOPE=0D -{=0D - Scope(\_SB) {=0D - //----------------------------------------------------------------------= -----=0D - // Begin PCI tree object scope=0D - //----------------------------------------------------------------------= -----=0D - Device(PCI0) { // PCI Bridge "Host Bridge"=0D - Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 h= ost hierarchy=0D - Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't u= nderstand the new HID=0D - Name(_SEG, 0)=0D - Method(^BN00, 0){ return(0x0000) } // Returns default Bus number fo= r Peer PCI busses. Name can be overriden with control method placed directl= y under Device scope=0D - Method(_BBN, 0){ return(BN00()) } // Bus number, optional for the Ro= ot PCI Bus=0D - Name(_UID, 0x0000) // Unique Bus ID, optional=0D - Name(BUF0,ResourceTemplate()=0D - {=0D - //=0D - // PCI Configuration Registers ( 0x0CF8 - 0x0CFF )=0D - //=0D - Io(Decode16,0x0CF8,0x0CF8,1,0x08)=0D - //=0D - // PCI MMIO space=0D - //=0D - DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCachea= ble,=0D - ReadWrite,0x00,0x00,0x00,0x00,0x00,,,PM01)=0D - })=0D - Method(_CRS,0,Serialized)=0D - {=0D - //=0D - // Create pointers to Memory Sizing values.=0D - //=0D - CreateDwordField(BUF0, ^PM01._MIN,M1MN)=0D - CreateDwordField(BUF0, ^PM01._MAX,M1MX)=0D - CreateDwordField(BUF0, ^PM01._LEN,M1LN)=0D -=0D - //=0D - // Set Memory Size Values. TLUD represents bits 31:20 of phyical=0D - // TOM, so shift these bits into the correct position and fix up=0D - // the Memory Region available to PCI.=0D - //=0D - Subtract (FixedPcdGet32(PcdPciReservedMemLimit),FixedPcdGet32(PcdP= ciReservedMemBase),M1LN)=0D - Store (FixedPcdGet32(PcdPciReservedMemBase), M1MN)=0D - Subtract (FixedPcdGet32(PcdPciReservedMemLimit), 1, M1MX)=0D -=0D - Return(BUF0)=0D - }=0D - }=0D - }=0D -}// End of ASL File=0D -=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c b/= Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c deleted file mode 100644 index 08709a43..00000000 --- a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.c +++ /dev/null @@ -1,232 +0,0 @@ -/** @file=0D - Min DSDT Driver=0D -=0D - Copyright (c) 2022, Intel Corporation. All rights reserved.
=0D - SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -=0D -#include =0D -#include =0D -=0D -//=0D -// Function implementations=0D -//=0D -=0D -/**=0D - Locate the first instance of a protocol. If the protocol requested is a= n=0D - FV protocol, then it will return the first FV that contains the ACPI tab= le=0D - storage file.=0D -=0D - @param[in] Protocol The protocol to find.=0D - @param[in] FfsGuid The FFS that contains the ACPI table.=0D - @param[out] Instance Return pointer to the first instance of t= he protocol.=0D -=0D - @retval EFI_SUCCESS The function completed successfully.=0D - @retval EFI_NOT_FOUND The protocol could not be located.=0D - @retval EFI_OUT_OF_RESOURCES There are not enough resources to find the= protocol.=0D -**/=0D -EFI_STATUS=0D -LocateSupportProtocol (=0D - IN EFI_GUID *Protocol,=0D - IN EFI_GUID *FfsGuid,=0D - OUT VOID **Instance=0D - )=0D -{=0D - EFI_STATUS Status;=0D - EFI_HANDLE *HandleBuffer;=0D - UINTN NumberOfHandles;=0D - EFI_FV_FILETYPE FileType;=0D - UINT32 FvStatus;=0D - EFI_FV_FILE_ATTRIBUTES Attributes;=0D - UINTN Size;=0D - UINTN Index;=0D -=0D - //=0D - // Locate protocol.=0D - //=0D - Status =3D gBS->LocateHandleBuffer (=0D - ByProtocol,=0D - Protocol,=0D - NULL,=0D - &NumberOfHandles,=0D - &HandleBuffer=0D - );=0D - if (EFI_ERROR (Status)) {=0D - //=0D - // Defined errors at this time are not found and out of resources.=0D - //=0D - return Status;=0D - }=0D -=0D - //=0D - // Looking for FV with ACPI storage file=0D - //=0D - for (Index =3D 0; Index < NumberOfHandles; Index++) {=0D -=0D - //=0D - // Get the protocol on this handle=0D - // This should not fail because of LocateHandleBuffer=0D - //=0D - Status =3D gBS->HandleProtocol (=0D - HandleBuffer[Index],=0D - Protocol,=0D - Instance=0D - );=0D - ASSERT_EFI_ERROR (Status);=0D -=0D - //=0D - // See if it has the ACPI storage file=0D - //=0D - Size =3D 0;=0D - FvStatus =3D 0;=0D - Status =3D ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile (= =0D - *Instance,=0D - FfsGuid,=0D - NULL,=0D - &Size,=0D - &FileType,=0D - &Attributes,= =0D - &FvStatus=0D - );=0D -=0D - //=0D - // If we found it, then we are done=0D - //=0D - if (Status =3D=3D EFI_SUCCESS) {=0D - break;=0D - }=0D - }=0D -=0D - //=0D - // Our exit status is determined by the success of the previous operatio= ns=0D - // If the protocol was found, Instance already points to it.=0D - //=0D - //=0D - // Free any allocated buffers=0D - //=0D - FreePool (HandleBuffer);=0D -=0D - return Status;=0D -}=0D -=0D -/**=0D - Publish ACPI table from FV.=0D -=0D - @param[in] FfsGuid The FFS that contains the ACPI table.=0D -=0D - @retval EFI_SUCCESS The function completed successfully.=0D -**/=0D -EFI_STATUS=0D -PublishAcpiTablesFromFv (=0D - IN EFI_GUID *FfsGuid=0D - )=0D -{=0D - EFI_STATUS Status;=0D - EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;=0D - EFI_ACPI_COMMON_HEADER *CurrentTable;=0D - UINT32 FvStatus;=0D - UINTN Size;=0D - UINTN TableHandle;=0D - INTN Instance;=0D - EFI_ACPI_TABLE_PROTOCOL *AcpiTable;=0D -=0D - Instance =3D 0;=0D - TableHandle =3D 0;=0D - CurrentTable =3D NULL;=0D - FwVol =3D NULL;=0D -=0D - Status =3D gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID = **)&AcpiTable);=0D - ASSERT_EFI_ERROR (Status);=0D -=0D - //=0D - // Locate the firmware volume protocol=0D - //=0D - Status =3D LocateSupportProtocol (=0D - &gEfiFirmwareVolume2ProtocolGuid,=0D - FfsGuid,=0D - (VOID **) &FwVol=0D - );=0D - ASSERT_EFI_ERROR (Status);=0D -=0D - //=0D - // Read tables from the storage file.=0D - //=0D -=0D - while (Status =3D=3D EFI_SUCCESS) {=0D - Status =3D FwVol->ReadSection (=0D - FwVol,=0D - FfsGuid,=0D - EFI_SECTION_RAW,=0D - Instance,=0D - (VOID **) &CurrentTable,=0D - &Size,=0D - &FvStatus=0D - );=0D -=0D - if (!EFI_ERROR (Status)) {=0D -=0D - //=0D - // Add the table=0D - //=0D - TableHandle =3D 0;=0D - Status =3D AcpiTable->InstallAcpiTable (=0D - AcpiTable,=0D - CurrentTable,=0D - CurrentTable->Length,=0D - &TableHandle=0D - );=0D - ASSERT_EFI_ERROR (Status);=0D -=0D - //=0D - // Increment the instance=0D - //=0D - Instance++;=0D - CurrentTable =3D NULL;=0D - }=0D - }=0D -=0D - //=0D - // Finished=0D - //=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - ACPI Platform driver installation function.=0D -=0D - @param[in] ImageHandle Handle for this drivers loaded image protocol= .=0D - @param[in] SystemTable EFI system table.=0D -=0D - @retval EFI_SUCCESS The driver installed without error.=0D - @retval EFI_ABORTED The driver encountered an error and could not= complete installation of=0D - the ACPI tables.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -InstallMinDsdt (=0D - IN EFI_HANDLE ImageHandle,=0D - IN EFI_SYSTEM_TABLE *SystemTable=0D - )=0D -{=0D - EFI_STATUS Status;=0D -=0D - Status =3D PublishAcpiTablesFromFv (&gEfiCallerIdGuid);=0D - ASSERT_EFI_ERROR (Status);=0D -=0D - return EFI_SUCCESS;=0D -}=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf = b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf deleted file mode 100644 index f2571407..00000000 --- a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/MinDsdt/MinDsdt.inf +++ /dev/null @@ -1,48 +0,0 @@ -### @file=0D -# Component information file for Minimal DSDT module=0D -#=0D -# Copyright (c) 2022, Intel Corporation. All rights reserved.
=0D -# SPDX-License-Identifier: BSD-2-Clause-Patent=0D -#=0D -#=0D -# @par Glossary:=0D -###=0D -=0D -[Defines]=0D - INF_VERSION =3D 0x00010005=0D - BASE_NAME =3D MinDsdt=0D - FILE_GUID =3D 8EB04370-482C-4505-AA27-7EB226A5729F= =0D - MODULE_TYPE =3D DXE_DRIVER=0D - VERSION_STRING =3D 1.0=0D - ENTRY_POINT =3D InstallMinDsdt=0D -=0D -[Sources.common]=0D - MinDsdt.c=0D - MinDsdt.asl=0D -=0D -[Packages]=0D - MdePkg/MdePkg.dec=0D - MinPlatformPkg/MinPlatformPkg.dec=0D -=0D -[LibraryClasses]=0D - UefiDriverEntryPoint=0D - BaseLib=0D - DebugLib=0D - PcdLib=0D - UefiBootServicesTableLib=0D - UefiRuntimeServicesTableLib=0D - BaseMemoryLib=0D - MemoryAllocationLib=0D -=0D -[Protocols]=0D - gEfiAcpiTableProtocolGuid ## CONSUMES=0D - gEfiFirmwareVolume2ProtocolGuid ## CONSUMES=0D -=0D -[Pcd]=0D - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase=0D - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit=0D -=0D -[Depex]=0D - gEfiAcpiTableProtocolGuid AND=0D - gEfiFirmwareVolume2ProtocolGuid=0D -=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPk= g.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.dsc index 4cdc9c01..59350f06 100644 --- a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.dsc +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.dsc @@ -101,7 +101,7 @@ =0D PostCodeMapLib|PostCodeDebugFeaturePkg/Library/PostCodeMapLib/PostCodeMa= pLib.inf=0D =0D - PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatf= ormSecLib/SecFspWrapperPlatformSecLib.inf=0D + PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrappe= rPlatformSecLib/SecFspWrapperPlatformSecLib.inf=0D FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf=0D FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWra= pperHobProcessLib/PeiFspWrapperHobProcessLib.inf=0D =0D @@ -234,7 +234,7 @@ [LibraryClasses.X64.DXE_SMM_DRIVER]=0D =0D !if $(TARGET) =3D=3D DEBUG=0D - SpiFlashCommonLib|$(PLATFORM_BOARD_PACKAGE)/Library/SmmSpiFlashCommonLib= /SmmSpiFlashCommonLib.inf=0D + SpiFlashCommonLib|IntelSiliconPkg/Library/SmmSpiFlashCommonLib/SmmSpiFla= shCommonLib.inf=0D TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Smm= TestPointCheckLib.inf=0D TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull= /TestPointCheckLibNull.inf=0D !endif=0D @@ -453,7 +453,7 @@ $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.i= nf #=0D !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE=0D $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf=0D - $(PLATFORM_BOARD_PACKAGE)/Acpi/MinDsdt/MinDsdt.inf=0D + $(PLATFORM_PACKAGE)/Acpi/MinDsdt/MinDsdt.inf=0D $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf {=0D =0D NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf= =0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPk= g.fdf b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.fdf index f1ce271b..27366fc4 100644 --- a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.fdf +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkg.fdf @@ -485,7 +485,7 @@ APRIORI DXE { !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE=0D INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf=0D INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf=0D -INF RuleOverride =3D DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/MinD= sdt/MinDsdt.inf=0D +INF RuleOverride =3D DRIVER_ACPITABLE $(PLATFORM_PACKAGE)/Acpi/MinDsdt/Mi= nDsdt.inf=0D INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf=0D =0D !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPk= gPcd.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgP= cd.dsc index 3eb9a575..edcd33e6 100644 --- a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/OpenBoardPkgPcd.dsc @@ -174,6 +174,13 @@ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07=0D !endif=0D =0D + #=0D + # INIT is now triggered before BIOS by ucode/hardware. In the OVMF=0D + # environment, QEMU lacks a simulation for the INIT process.=0D + # To address this, PcdFirstTimeWakeUpAPsBySipi set to FALSE to=0D + # broadcast INIT-SIPI-SIPI for the first time.=0D + #=0D + gUefiCpuPkgTokenSpaceGuid.PcdFirstTimeWakeUpAPsBySipi|FALSE=0D =0D !if $(TARGET) =3D=3D DEBUG=0D !if gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable =3D=3D TRUE=0D @@ -287,6 +294,7 @@ =0D =0D [PcdsDynamicDefault]=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE=0D gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0=0D gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0=0D gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020204C43= 49=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/FspWrapperPlatformSecLib.c b/Platform/Intel/Alderlake= OpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatf= ormSecLib.c new file mode 100644 index 00000000..d6796be5 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/FspWrapperPlatformSecLib.c @@ -0,0 +1,186 @@ +/** @file=0D + Provide FSP wrapper platform sec related function.=0D +=0D +Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + This interface conveys state information out of the Security (SEC) phase= into PEI.=0D +=0D + @param[in] PeiServices Pointer to the PEI Services Tab= le.=0D + @param[in,out] StructureSize Pointer to the variable describ= ing size of the input buffer.=0D + @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM= _INFORMATION_RECORD.=0D +=0D + @retval EFI_SUCCESS The data was successfully returned.=0D + @retval EFI_BUFFER_TOO_SMALL The buffer was too small.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SecPlatformInformation (=0D + IN CONST EFI_PEI_SERVICES **PeiServices,=0D + IN OUT UINT64 *StructureSize,=0D + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord= =0D + );=0D +=0D +/**=0D + This interface conveys performance information out of the Security (SEC)= phase into PEI.=0D +=0D + This service is published by the SEC phase. The SEC phase handoff has an= optional=0D + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed= from SEC into the=0D + PEI Foundation. As such, if the platform supports collecting performance= data in SEC,=0D + this information is encapsulated into the data structure abstracted by t= his service.=0D + This information is collected for the boot-strap processor (BSP) on IA-3= 2.=0D +=0D + @param[in] PeiServices The pointer to the PEI Services Table.=0D + @param[in] This The pointer to this instance of the PEI_SEC_PER= FORMANCE_PPI.=0D + @param[out] Performance The pointer to performance data collected in SE= C phase.=0D +=0D + @retval EFI_SUCCESS The data was successfully returned.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SecGetPerformance (=0D + IN CONST EFI_PEI_SERVICES **PeiServices,=0D + IN PEI_SEC_PERFORMANCE_PPI *This,=0D + OUT FIRMWARE_SEC_PERFORMANCE *Performance=0D + );=0D +=0D +PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi =3D {=0D + SecGetPerformance=0D +};=0D +=0D +EFI_PEI_CORE_FV_LOCATION_PPI mPeiCoreFvLocationPpi =3D {=0D + (VOID *) (UINTN) FixedPcdGet32 (PcdFspmBaseAddress)=0D +};=0D +=0D +EFI_PEI_PPI_DESCRIPTOR mPeiCoreFvLocationPpiList[] =3D {=0D + {=0D + EFI_PEI_PPI_DESCRIPTOR_PPI,=0D + &gEfiPeiCoreFvLocationPpiGuid,=0D + &mPeiCoreFvLocationPpi=0D + }=0D +};=0D +=0D +EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] =3D {=0D + {=0D + EFI_PEI_PPI_DESCRIPTOR_PPI,=0D + &gTopOfTemporaryRamPpiGuid,=0D + NULL // To be patched later.=0D + },=0D + {=0D + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,=0D + &gPeiSecPerformancePpiGuid,=0D + &mSecPerformancePpi=0D + },=0D +};=0D +=0D +#define LEGACY_8259_MASK_REGISTER_MASTER 0x21=0D +#define LEGACY_8259_MASK_REGISTER_SLAVE 0xA1=0D +#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0=0D +#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1=0D +=0D +/**=0D + Write to mask and edge/level triggered registers of master and slave 825= 9 PICs.=0D +=0D + @param[in] Mask low byte for master PIC mask register,=0D + high byte for slave PIC mask register.=0D + @param[in] EdgeLevel low byte for master PIC edge/level triggered regi= ster,=0D + high byte for slave PIC edge/level triggered regi= ster.=0D +=0D +**/=0D +VOID=0D +Interrupt8259WriteMask (=0D + IN UINT16 Mask,=0D + IN UINT16 EdgeLevel=0D + )=0D +{=0D + IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask);=0D + IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8));=0D + IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8) Edge= Level);=0D + IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8) (Edge= Level >> 8));=0D +}=0D +=0D +/**=0D + A developer supplied function to perform platform specific operations.=0D +=0D + It's a developer supplied function to perform any operations appropriate= to a=0D + given platform. It's invoked just before passing control to PEI core by = SEC=0D + core. Platform developer may modify the SecCoreData passed to PEI Core.= =0D + It returns a platform specific PPI list that platform wishes to pass to = PEI core.=0D + The Generic SEC core module will merge this list to join the final list = passed to=0D + PEI core.=0D +=0D + @param[in,out] SecCoreData The same parameter as passing to PE= I core. It=0D + could be overridden by this functio= n.=0D +=0D + @return The platform specific PPI list to be passed to PEI core or=0D + NULL if there is no need of such platform specific PPI list.=0D +=0D +**/=0D +EFI_PEI_PPI_DESCRIPTOR *=0D +EFIAPI=0D +SecPlatformMain (=0D + IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData=0D + )=0D +{=0D + EFI_PEI_PPI_DESCRIPTOR *PpiList;=0D + UINT8 TopOfTemporaryRamPpiIndex;=0D + UINT8 *CopyDestinationPointer;=0D +=0D + DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n", SecCo= reData->BootFirmwareVolumeBase));=0D + DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeSize - 0x%x\n", SecCo= reData->BootFirmwareVolumeSize));=0D + DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamBase - 0x%x\n", SecCo= reData->TemporaryRamBase));=0D + DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamSize - 0x%x\n", SecCo= reData->TemporaryRamSize));=0D + DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamBase - 0x%x\n", SecCo= reData->PeiTemporaryRamBase));=0D + DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamSize - 0x%x\n", SecCo= reData->PeiTemporaryRamSize));=0D + DEBUG ((DEBUG_INFO, "FSP Wrapper StackBase - 0x%x\n", SecCo= reData->StackBase));=0D + DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize - 0x%x\n", SecCo= reData->StackSize));=0D +=0D + InitializeApicTimer (0, (UINT32) -1, TRUE, 5);=0D +=0D + //=0D + // Set all 8259 interrupts to edge triggered and disabled=0D + //=0D + Interrupt8259WriteMask (0xFFFF, 0x0000);=0D +=0D + //=0D + // Use middle of Heap as temp buffer, it will be copied by caller.=0D + // Do not use Stack, because it will cause wrong calculation on stack by= PeiCore=0D + //=0D + PpiList =3D (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + (UINTN) = SecCoreData->PeiTemporaryRamSize/2);=0D + CopyDestinationPointer =3D (UINT8 *) PpiList;=0D + TopOfTemporaryRamPpiIndex =3D 0;=0D + if ((PcdGet8 (PcdFspModeSelection) =3D=3D 0) && PcdGetBool (PcdFspDispat= chModeUseFspPeiMain)) {=0D + //=0D + // In Dispatch mode, wrapper should provide PeiCoreFvLocationPpi.=0D + //=0D + CopyMem (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof (mP= eiCoreFvLocationPpiList));=0D + TopOfTemporaryRamPpiIndex =3D 1;=0D + CopyDestinationPointer +=3D sizeof (mPeiCoreFvLocationPpiList);=0D + }=0D + CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi, sizeof (mPeiSecPlat= formPpi));=0D + //=0D + // Patch TopOfTemporaryRamPpi=0D + //=0D + PpiList[TopOfTemporaryRamPpiIndex].Ppi =3D (VOID *)((UINTN) SecCoreData-= >TemporaryRamBase + SecCoreData->TemporaryRamSize);=0D +=0D + return PpiList;=0D +}=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/FsptCoreUpd.h b/Platform/Intel/AlderlakeOpenBoardPkg/= FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h new file mode 100644 index 00000000..f92ed50e --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/FsptCoreUpd.h @@ -0,0 +1,394 @@ +/** @file=0D +=0D +Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef __FSPT_CORE_UPD_H__=0D +#define __FSPT_CORE_UPD_H__=0D +=0D +#include =0D +=0D +#pragma pack(1)=0D +=0D +/** Fsp T Core UPD=0D +**/=0D +typedef struct {=0D +=0D +/** Offset 0x0020=0D +**/=0D + UINT32 MicrocodeRegionBase;=0D +=0D +/** Offset 0x0024=0D +**/=0D + UINT32 MicrocodeRegionSize;=0D +=0D +/** Offset 0x0028=0D +**/=0D + UINT32 CodeRegionBase;=0D +=0D +/** Offset 0x002C=0D +**/=0D + UINT32 CodeRegionSize;=0D +=0D +/** Offset 0x0030=0D +**/=0D + UINT8 Reserved[16];=0D +} FSPT_CORE_UPD;=0D +=0D +/** Fsp T Configuration=0D +**/=0D +typedef struct {=0D +=0D +/** Offset 0x0060 - PcdSerialIoUartDebugEnable=0D + Enable SerialIo Uart debug library with/without initializing SerialIo Ua= rt device in FSP.=0D + 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing=0D +**/=0D + UINT8 PcdSerialIoUartDebugEnable;=0D +=0D +/** Offset 0x0061 - PcdSerialIoUartNumber=0D + Select SerialIo Uart Controller for debug.=0D + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2=0D +**/=0D + UINT8 PcdSerialIoUartNumber;=0D +=0D +/** Offset 0x0062 - PcdSerialIoUartMode - FSPT=0D + Select SerialIo Uart Controller mode=0D + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:Seria= lIoUartCom,=0D + 4:SerialIoUartSkipInit=0D +**/=0D + UINT8 PcdSerialIoUartMode;=0D +=0D +/** Offset 0x0063 - PcdSerialIoUartPowerGating - FSPT=0D + Select SerialIo Uart Controller Powergating mode=0D + 0:Disabled, 1:Enabled, 2:Auto=0D +**/=0D + UINT8 PcdSerialIoUartPowerGating;=0D +=0D +/** Offset 0x0064 - PcdSerialIoUartBaudRate - FSPT=0D + Set default BaudRate Supported from 0 - default to 6000000=0D +**/=0D + UINT32 PcdSerialIoUartBaudRate;=0D +=0D +/** Offset 0x0068 - Pci Express Base Address=0D + Base address to be programmed for Pci Express=0D +**/=0D + UINT64 PcdPciExpressBaseAddress;=0D +=0D +/** Offset 0x0070 - Pci Express Region Length=0D + Region Length to be programmed for Pci Express=0D +**/=0D + UINT32 PcdPciExpressRegionLength;=0D +=0D +/** Offset 0x0074 - PcdSerialIoUartParity - FSPT=0D + Set default Parity.=0D + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity=0D +**/=0D + UINT8 PcdSerialIoUartParity;=0D +=0D +/** Offset 0x0075 - PcdSerialIoUartDataBits - FSPT=0D + Set default word length. 0: Default, 5,6,7,8=0D +**/=0D + UINT8 PcdSerialIoUartDataBits;=0D +=0D +/** Offset 0x0076 - PcdSerialIoUartStopBits - FSPT=0D + Set default stop bits.=0D + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits=0D +**/=0D + UINT8 PcdSerialIoUartStopBits;=0D +=0D +/** Offset 0x0077 - PcdSerialIoUartAutoFlow - FSPT=0D + Enables UART hardware flow control, CTS and RTS lines.=0D + 0: Disable, 1:Enable=0D +**/=0D + UINT8 PcdSerialIoUartAutoFlow;=0D +=0D +/** Offset 0x0078 - PcdSerialIoUartRxPinMux - FSPT=0D + Select RX pin muxing for SerialIo UART used for debug=0D +**/=0D + UINT32 PcdSerialIoUartRxPinMux;=0D +=0D +/** Offset 0x007C - PcdSerialIoUartTxPinMux - FSPT=0D + Select TX pin muxing for SerialIo UART used for debug=0D +**/=0D + UINT32 PcdSerialIoUartTxPinMux;=0D +=0D +/** Offset 0x0080 - PcdSerialIoUartRtsPinMux - FSPT=0D + Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXI= NG_SERIALIO_UARTx_RTS*=0D + for possible values.=0D +**/=0D + UINT32 PcdSerialIoUartRtsPinMux;=0D +=0D +/** Offset 0x0084 - PcdSerialIoUartCtsPinMux - FSPT=0D + Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXI= NG_SERIALIO_UARTx_CTS*=0D + for possible values.=0D +**/=0D + UINT32 PcdSerialIoUartCtsPinMux;=0D +=0D +/** Offset 0x0088 - PcdSerialIoUartDebugMmioBase - FSPT=0D + Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSeri= alIoUartMode=0D + =3D SerialIoUartPci.=0D +**/=0D + UINT32 PcdSerialIoUartDebugMmioBase;=0D +=0D +/** Offset 0x008C - PcdSerialIoUartDebugPciCfgBase - FSPT=0D + Specify PciCfgBase address. Allows for SerialIO UART functionality outsi= de Bus 0=0D +**/=0D + UINT32 PcdSerialIoUartDebugPciCfgBase;=0D +=0D +/** Offset 0x0090 - PcdLpcUartDebugEnable=0D + Enable to initialize LPC Uart device in FSP.=0D + 0:Disable, 1:Enable=0D +**/=0D + UINT8 PcdLpcUartDebugEnable;=0D +=0D +/** Offset 0x0091 - Debug Interfaces=0D + Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-T= raceHub,=0D + BIT2 - Not used.=0D +**/=0D + UINT8 PcdDebugInterfaceFlags;=0D +=0D +/** Offset 0x0092 - PcdSerialDebugLevel=0D + Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings,= 3:Load,=0D + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, E= rror, Warnings,=0D + Info & Verbose.=0D + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and= Info, 4:Load=0D + Error Warnings and Info, 5:Load Error Warnings Info and Verbose=0D +**/=0D + UINT8 PcdSerialDebugLevel;=0D +=0D +/** Offset 0x0093 - ISA Serial Base selection=0D + Select ISA Serial Base address. Default is 0x3F8.=0D + 0:0x3F8, 1:0x2F8=0D +**/=0D + UINT8 PcdIsaSerialUartBase;=0D +=0D +/** Offset 0x0094 - PcdSerialIo2ndUartEnable=0D + Enable Additional SerialIo Uart device in FSP.=0D + 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing=0D +**/=0D + UINT8 PcdSerialIo2ndUartEnable;=0D +=0D +/** Offset 0x0095 - PcdSerialIo2ndUartNumber=0D + Select SerialIo Uart Controller Number=0D + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2=0D +**/=0D + UINT8 PcdSerialIo2ndUartNumber;=0D +=0D +/** Offset 0x0096 - PcdSerialIo2ndUartMode - FSPT=0D + Select SerialIo Uart Controller mode=0D + 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:Seria= lIoUartCom,=0D + 4:SerialIoUartSkipInit=0D +**/=0D + UINT8 PcdSerialIo2ndUartMode;=0D +=0D +/** Offset 0x0097=0D +**/=0D + UINT8 Rsvd020[1];=0D +=0D +/** Offset 0x0098 - PcdSerialIo2ndUartBaudRate - FSPT=0D + Set default BaudRate Supported from 0 - default to 6000000=0D +**/=0D + UINT32 PcdSerialIo2ndUartBaudRate;=0D +=0D +/** Offset 0x009C - PcdSerialIo2ndUartParity - FSPT=0D + Set default Parity.=0D + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity=0D +**/=0D + UINT8 PcdSerialIo2ndUartParity;=0D +=0D +/** Offset 0x009D - PcdSerialIo2ndUartDataBits - FSPT=0D + Set default word length. 0: Default, 5,6,7,8=0D +**/=0D + UINT8 PcdSerialIo2ndUartDataBits;=0D +=0D +/** Offset 0x009E - PcdSerialIo2ndUartStopBits - FSPT=0D + Set default stop bits.=0D + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits=0D +**/=0D + UINT8 PcdSerialIo2ndUartStopBits;=0D +=0D +/** Offset 0x009F - PcdSerialIo2ndUartAutoFlow - FSPT=0D + Enables UART hardware flow control, CTS and RTS lines.=0D + 0: Disable, 1:Enable=0D +**/=0D + UINT8 PcdSerialIo2ndUartAutoFlow;=0D +=0D +/** Offset 0x00A0 - PcdSerialIo2ndUartRxPinMux - FSPT=0D + Select RX pin muxing for SerialIo UART=0D +**/=0D + UINT32 PcdSerialIo2ndUartRxPinMux;=0D +=0D +/** Offset 0x00A4 - PcdSerialIo2ndUartTxPinMux - FSPT=0D + Select TX pin muxing for SerialIo UART=0D +**/=0D + UINT32 PcdSerialIo2ndUartTxPinMux;=0D +=0D +/** Offset 0x00A8 - PcdSerialIo2ndUartRtsPinMux - FSPT=0D + Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UAR= Tx_RTS*=0D + for possible values.=0D +**/=0D + UINT32 PcdSerialIo2ndUartRtsPinMux;=0D +=0D +/** Offset 0x00AC - PcdSerialIo2ndUartCtsPinMux - FSPT=0D + Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UAR= Tx_CTS*=0D + for possible values.=0D +**/=0D + UINT32 PcdSerialIo2ndUartCtsPinMux;=0D +=0D +/** Offset 0x00B0 - PcdSerialIo2ndUartMmioBase - FSPT=0D + Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSeri= alIo2ndUartMode=0D + =3D SerialIoUartPci.=0D +**/=0D + UINT32 PcdSerialIo2ndUartMmioBase;=0D +=0D +/** Offset 0x00B4 - PcdSerialIo2ndUartPciCfgBase - FSPT=0D + Specify PciCfgBase address. Allows for SerialIO UART functionality outsi= de Bus 0=0D +**/=0D + UINT32 PcdSerialIo2ndUartPciCfgBase;=0D +=0D +/** Offset 0x00B8=0D +**/=0D + UINT32 TopMemoryCacheSize;=0D +=0D +/** Offset 0x00BC - FspDebugHandler=0D + Optional pointer to the boot loader's implementation of FSP_DEBUG= _HANDLER.=0D +**/=0D + UINT32 FspDebugHandler;=0D +=0D +/** Offset 0x00C0 - Serial Io SPI Chip Select Polarity=0D + Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsAc= tiveLow,=0D + 1:SerialIoSpiCsActiveHigh=0D +**/=0D + UINT8 PcdSerialIoSpiCsPolarity[2];=0D +=0D +/** Offset 0x00C2 - Serial Io SPI Chip Select Enable=0D + 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled=0D +**/=0D + UINT8 PcdSerialIoSpiCsEnable[2];=0D +=0D +/** Offset 0x00C4 - Serial Io SPI Device Mode=0D + When mode is set to Pci, controller is initalized in early stage. Availa= ble modes:=0D + 0:SerialIoSpiDisabled, 1:SerialIoSpiPci.=0D +**/=0D + UINT8 PcdSerialIoSpiMode;=0D +=0D +/** Offset 0x00C5 - Serial Io SPI Default Chip Select Output=0D + Sets Default CS as Output. Available options: 0:CS0, 1:CS1=0D +**/=0D + UINT8 PcdSerialIoSpiDefaultCsOutput;=0D +=0D +/** Offset 0x00C6 - Serial Io SPI Default Chip Select Mode HW/SW=0D + Sets Default CS Mode Hardware or Software. Available options: 0:HW, 1:SW= =0D +**/=0D + UINT8 PcdSerialIoSpiCsMode;=0D +=0D +/** Offset 0x00C7 - Serial Io SPI Default Chip Select State Low/High=0D + Sets Default CS State Low or High. Available options: 0:Low, 1:High=0D +**/=0D + UINT8 PcdSerialIoSpiCsState;=0D +=0D +/** Offset 0x00C8 - Serial Io SPI Device Number=0D + Select which Serial Io SPI controller is initalized in early stage.=0D +**/=0D + UINT8 PcdSerialIoSpiNumber;=0D +=0D +/** Offset 0x00C9=0D +**/=0D + UINT8 Rsvd030[3];=0D +=0D +/** Offset 0x00CC - Serial Io SPI Device MMIO Base=0D + Assigns MMIO for Serial Io SPI controller usage in early stage.=0D +**/=0D + UINT32 PcdSerialIoSpiMmioBase;=0D +=0D +/** Offset 0x00D0 - Serial IO SPI CS Pin Muxing=0D + Select SerialIo SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_= CS* for=0D + possible values.=0D +**/=0D + UINT32 PcdSerialIoSpiCsPinMux[2];=0D +=0D +/** Offset 0x00D8 - Serial IO SPI CLK Pin Muxing=0D + Select SerialIo SPI CLK pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx= _CLK* for=0D + possible values.=0D +**/=0D + UINT32 PcdSerialIoSpiClkPinMux;=0D +=0D +/** Offset 0x00DC - Serial IO SPI MISO Pin Muxing=0D + Select SerialIo SPI MISO pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPI= x_MISO*=0D + for possible values.=0D +**/=0D + UINT32 PcdSerialIoSpiMisoPinMux;=0D +=0D +/** Offset 0x00E0 - Serial IO SPI MOSI Pin Muxing=0D + Select SerialIo SPI MOSI pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPI= x_MOSI*=0D + for possible values.=0D +**/=0D + UINT32 PcdSerialIoSpiMosiPinMux;=0D +=0D +/** Offset 0x00E4 - Serial Io I2C Device MMIO Base=0D + Assigns MMIO for Serial Io I2C controller usage in early stage.=0D +**/=0D + UINT32 PcdSerialIoI2cMmioBase;=0D +=0D +/** Offset 0x00E8 - Serial Io I2C Sda Gpio Pin=0D + Select SerialIo I2C Rts pin. Refer to GPIO_*_MUXING_SERIALIO_I2C*_SDA* f= or possible values.=0D +**/=0D + UINT32 PcdSerialIoI2cSdaPin;=0D +=0D +/** Offset 0x00EC - Serial Io I2C Scl Gpio Pin=0D + Select SerialIo I2C Cts pin. Refer to GPIO_*_MUXING_SERIALIO_I2C*_SCL* f= or possible values.=0D +**/=0D + UINT32 PcdSerialIoI2cSclPin;=0D +=0D +/** Offset 0x00F0 - Serial Io I2C Gpio Pad termination=0D + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm = weak pull-up,=0D + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads t= ermination=0D + respectively. One byte for each controller, byte0 for I2C0, byte1 for I2= C1, and so on.=0D +**/=0D + UINT8 PcdSerialIoI2cPadsTerm;=0D +=0D +/** Offset 0x00F1 - Serial Io I2c Controller Number=0D + Select SerialIo I2C Controller number to be intilizaed during early boot= . Default is 0xFF=0D + 0:SerialIoI2c0, 1:SerialIoI2c1, 2:SerialIoI2c2, 0xFF:Disable=0D +**/=0D + UINT8 PcdSerialIoI2cNumber;=0D +=0D +/** Offset 0x00F2=0D +**/=0D + UINT8 ReservedFsptUpd1[6];=0D +} FSP_T_CONFIG;=0D +=0D +/** Fsp T UPD Configuration=0D +**/=0D +typedef struct {=0D +=0D +/** Offset 0x0000=0D +**/=0D + FSP_UPD_HEADER FspUpdHeader;=0D +=0D +/** Offset 0x0020=0D +**/=0D + FSPT_ARCH_UPD FsptArchUpd;=0D +=0D +/** Offset 0x0040=0D +**/=0D + FSPT_CORE_UPD FsptCoreUpd;=0D +=0D +/** Offset 0x0060=0D +**/=0D + FSP_T_CONFIG FsptConfig;=0D +=0D +/** Offset 0x00F8=0D +**/=0D + UINT8 Rsvd3[6];=0D +=0D +/** Offset 0x00FE=0D +**/=0D + UINT16 UpdTerminator;=0D +} FSPT_UPD;=0D +=0D +#pragma pack()=0D +=0D +#endif=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/Ia32/Fsp.h b/Platform/Intel/AlderlakeOpenBoardPkg/Fsp= Wrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h new file mode 100644 index 00000000..b8b5af6a --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/Ia32/Fsp.h @@ -0,0 +1,42 @@ +/** @file=0D + Fsp related definitions=0D +=0D +Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef __FSP_H__=0D +#define __FSP_H__=0D +=0D +//=0D +// Fv Header=0D +//=0D +#define FVH_SIGINATURE_OFFSET 0x28=0D +#define FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid signature:_FVH= =0D +#define FVH_HEADER_LENGTH_OFFSET 0x30=0D +#define FVH_EXTHEADER_OFFSET_OFFSET 0x34=0D +#define FVH_EXTHEADER_SIZE_OFFSET 0x10=0D +=0D +//=0D +// Ffs Header=0D +//=0D +#define FSP_HEADER_GUID_DWORD1 0x912740BE=0D +#define FSP_HEADER_GUID_DWORD2 0x47342284=0D +#define FSP_HEADER_GUID_DWORD3 0xB08471B9=0D +#define FSP_HEADER_GUID_DWORD4 0x0C3F3527=0D +#define FFS_HEADER_SIZE_VALUE 0x18=0D +=0D +//=0D +// Section Header=0D +//=0D +#define SECTION_HEADER_TYPE_OFFSET 0x03=0D +#define RAW_SECTION_HEADER_SIZE_VALUE 0x04=0D +=0D +//=0D +// Fsp Header=0D +//=0D +#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C=0D +#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30=0D +=0D +#endif=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm b/Platform/Intel/AlderlakeOpen= BoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.n= asm new file mode 100644 index 00000000..1b6f0e2d --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/Ia32/PeiCoreEntry.nasm @@ -0,0 +1,130 @@ +;-------------------------------------------------------------------------= -----=0D +;=0D +; Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D +; SPDX-License-Identifier: BSD-2-Clause-Patent=0D +;=0D +; Module Name:=0D +;=0D +; PeiCoreEntry.nasm=0D +;=0D +; Abstract:=0D +;=0D +; Find and call SecStartup=0D +;=0D +;-------------------------------------------------------------------------= -----=0D +=0D +SECTION .text=0D +=0D +extern ASM_PFX(SecStartup)=0D +extern ASM_PFX(PlatformInit)=0D +=0D +global ASM_PFX(CallPeiCoreEntryPoint)=0D +ASM_PFX(CallPeiCoreEntryPoint):=0D + ;=0D + ; Obtain the hob list pointer=0D + ;=0D + mov eax, [esp+4]=0D + ;=0D + ; Obtain the stack information=0D + ; ECX: start of range=0D + ; EDX: end of range=0D + ;=0D + mov ecx, [esp+8]=0D + mov edx, [esp+0xC]=0D +=0D + ;=0D + ; Platform init=0D + ;=0D + pushad=0D + push edx=0D + push ecx=0D + push eax=0D + call ASM_PFX(PlatformInit)=0D + pop eax=0D + pop eax=0D + pop eax=0D + popad=0D +=0D + ;=0D + ; Set stack top pointer=0D + ;=0D + mov esp, edx=0D +=0D + ;=0D + ; Push the hob list pointer=0D + ;=0D + push eax=0D +=0D + ;=0D + ; Save the value=0D + ; ECX: start of range=0D + ; EDX: end of range=0D + ;=0D + mov ebp, esp=0D + push ecx=0D + push edx=0D +=0D + ;=0D + ; Push processor count to stack first, then BIST status (AP then BSP)=0D + ;=0D + mov eax, 1=0D + cpuid=0D + shr ebx, 16=0D + and ebx, 0xFF=0D + cmp bl, 1=0D + jae PushProcessorCount=0D +=0D + ;=0D + ; Some processors report 0 logical processors. Effectively 0 =3D 1.=0D + ; So we fix up the processor count=0D + ;=0D + inc ebx=0D +=0D +PushProcessorCount:=0D + push ebx=0D +=0D + ;=0D + ; We need to implement a long-term solution for BIST capture. For now, = we just copy BSP BIST=0D + ; for all processor threads=0D + ;=0D + xor ecx, ecx=0D + mov cl, bl=0D +PushBist:=0D + movd eax, mm0=0D + push eax=0D + loop PushBist=0D +=0D + ; Save Time-Stamp Counter=0D + movd eax, mm5=0D + push eax=0D +=0D + movd eax, mm6=0D + push eax=0D +=0D + ;=0D + ; Pass entry point of the PEI core=0D + ;=0D + mov edi, 0xFFFFFFE0=0D + push DWORD [edi]=0D +=0D + ;=0D + ; Pass BFV into the PEI Core=0D + ;=0D + mov edi, 0xFFFFFFFC=0D + push DWORD [edi]=0D +=0D + ;=0D + ; Pass stack size into the PEI Core=0D + ;=0D + mov ecx, [ebp - 4]=0D + mov edx, [ebp - 8]=0D + push ecx ; RamBase=0D +=0D + sub edx, ecx=0D + push edx ; RamSize=0D +=0D + ;=0D + ; Pass Control into the PEI Core=0D + ;=0D + call ASM_PFX(SecStartup)=0D +=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/Ia32/SecEntry.nasm b/Platform/Intel/AlderlakeOpenBoar= dPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm new file mode 100644 index 00000000..c4533da1 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/Ia32/SecEntry.nasm @@ -0,0 +1,361 @@ +;-------------------------------------------------------------------------= -----=0D +;=0D +; Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D +; SPDX-License-Identifier: BSD-2-Clause-Patent=0D +; Module Name:=0D +;=0D +; SecEntry.nasm=0D +;=0D +; Abstract:=0D +;=0D +; This is the code that goes from real-mode to protected mode.=0D +; It consumes the reset vector, calls TempRamInit API from FSP binary.=0D +;=0D +;-------------------------------------------------------------------------= -----=0D +=0D +#include "Fsp.h"=0D +=0D +SECTION .text=0D +=0D +extern ASM_PFX(CallPeiCoreEntryPoint)=0D +extern ASM_PFX(FsptUpdDataPtr)=0D +extern ASM_PFX(BoardBeforeTempRamInit)=0D +; Pcds=0D +extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))=0D +extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress))=0D +=0D +;-------------------------------------------------------------------------= ---=0D +;=0D +; Procedure: _ModuleEntryPoint=0D +;=0D +; Input: None=0D +;=0D +; Output: None=0D +;=0D +; Destroys: Assume all registers=0D +;=0D +; Description:=0D +;=0D +; Transition to non-paged flat-model protected mode from a=0D +; hard-coded GDT that provides exactly two descriptors.=0D +; This is a bare bones transition to protected mode only=0D +; used for a while in PEI and possibly DXE.=0D +;=0D +; After enabling protected mode, a far jump is executed to=0D +; transfer to PEI using the newly loaded GDT.=0D +;=0D +; Return: None=0D +;=0D +; MMX Usage:=0D +; MM0 =3D BIST State=0D +; MM5 =3D Save time-stamp counter value high32bit=0D +; MM6 =3D Save time-stamp counter value low32bit.=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +=0D +BITS 16=0D +align 4=0D +global ASM_PFX(_ModuleEntryPoint)=0D +ASM_PFX(_ModuleEntryPoint):=0D + fninit ; clear any pending Floating point= exceptions=0D + ;=0D + ; Store the BIST value in mm0=0D + ;=0D + movd mm0, eax=0D + cli=0D +=0D + ;=0D + ; Check INIT# is asserted by port 0xCF9=0D + ;=0D + mov dx, 0CF9h=0D + in al, dx=0D + cmp al, 04h=0D + jnz NotWarmStart=0D +=0D +=0D + ;=0D + ; @note Issue warm reset, since if CPU only reset is issued not all MSRs= are restored to their defaults=0D + ;=0D + mov dx, 0CF9h=0D + mov al, 06h=0D + out dx, al=0D +=0D +NotWarmStart:=0D + ;=0D + ; Save time-stamp counter value=0D + ; rdtsc load 64bit time-stamp counter to EDX:EAX=0D + ;=0D + rdtsc=0D + movd mm5, edx=0D + movd mm6, eax=0D +=0D + ;=0D + ; Load the GDT table in GdtDesc=0D + ;=0D + mov esi, GdtDesc=0D + DB 66h=0D + lgdt [cs:si]=0D +=0D + ;=0D + ; Transition to 16 bit protected mode=0D + ;=0D + mov eax, cr0 ; Get control register 0=0D + or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #= 1)=0D + mov cr0, eax ; Activate protected mode=0D +=0D + mov eax, cr4 ; Get control register 4=0D + or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCP= T bit (bit #10)=0D + mov cr4, eax=0D +=0D + ;=0D + ; Now we're in 16 bit protected mode=0D + ; Set up the selectors for 32 bit protected mode entry=0D + ;=0D + mov ax, SYS_DATA_SEL=0D + mov ds, ax=0D + mov es, ax=0D + mov fs, ax=0D + mov gs, ax=0D + mov ss, ax=0D +=0D + ;=0D + ; Transition to Flat 32 bit protected mode=0D + ; The jump to a far pointer causes the transition to 32 bit mode=0D + ;=0D + mov esi, ProtectedModeEntryLinearAddress=0D + jmp dword far [cs:si]=0D +=0D +;-------------------------------------------------------------------------= ---=0D +;=0D +; Procedure: ProtectedModeEntryPoint=0D +;=0D +; Input: None=0D +;=0D +; Output: None=0D +;=0D +; Destroys: Assume all registers=0D +;=0D +; Description:=0D +;=0D +; This function handles:=0D +; Call two basic APIs from FSP binary=0D +; Initializes stack with some early data (BIST, PEI entry, etc)=0D +;=0D +; Return: None=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +=0D +BITS 32=0D +align 4=0D +ProtectedModeEntryPoint:=0D + ;=0D + ; Early board hooks=0D + ;=0D + mov esp, BoardBeforeTempRamInitRet=0D + jmp ASM_PFX(BoardBeforeTempRamInit)=0D +=0D +BoardBeforeTempRamInitRet:=0D +=0D + ; Find the fsp info header=0D + mov edi, [ASM_PFX(PcdGet32 (PcdFsptBaseAddress))]=0D +=0D + mov eax, dword [edi + FVH_SIGINATURE_OFFSET]=0D + cmp eax, FVH_SIGINATURE_VALID_VALUE=0D + jnz FspHeaderNotFound=0D +=0D + xor eax, eax=0D + mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]=0D + cmp ax, 0=0D + jnz FspFvExtHeaderExist=0D +=0D + xor eax, eax=0D + mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header=0D + add edi, eax=0D + jmp FspCheckFfsHeader=0D +=0D +FspFvExtHeaderExist:=0D + add edi, eax=0D + mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Heade= r=0D + add edi, eax=0D +=0D + ; Round up to 8 byte alignment=0D + mov eax, edi=0D + and al, 07h=0D + jz FspCheckFfsHeader=0D +=0D + and edi, 0FFFFFFF8h=0D + add edi, 08h=0D +=0D +FspCheckFfsHeader:=0D + ; Check the ffs guid=0D + mov eax, dword [edi]=0D + cmp eax, FSP_HEADER_GUID_DWORD1=0D + jnz FspHeaderNotFound=0D +=0D + mov eax, dword [edi + 4]=0D + cmp eax, FSP_HEADER_GUID_DWORD2=0D + jnz FspHeaderNotFound=0D +=0D + mov eax, dword [edi + 8]=0D + cmp eax, FSP_HEADER_GUID_DWORD3=0D + jnz FspHeaderNotFound=0D +=0D + mov eax, dword [edi + 0Ch]=0D + cmp eax, FSP_HEADER_GUID_DWORD4=0D + jnz FspHeaderNotFound=0D +=0D + add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header=0D +=0D + ; Check the section type as raw section=0D + mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]=0D + cmp al, 019h=0D + jnz FspHeaderNotFound=0D +=0D + add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header=0D + jmp FspHeaderFound=0D +=0D +FspHeaderNotFound:=0D + jmp $=0D +=0D +FspHeaderFound:=0D + ; Get the fsp TempRamInit Api address=0D + mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]=0D + add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]=0D +=0D + ; Setup the hardcode stack=0D + mov esp, TempRamInitStack=0D +=0D + ; Call the fsp TempRamInit Api=0D + jmp eax=0D +=0D +TempRamInitDone:=0D + cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND returned. Error code for= Microcode Update not found.=0D + je CallSecFspInit ;If microcode not found, don't hang, but continu= e.=0D +=0D + cmp eax, 0 ;Check if EFI_SUCCESS retuned.=0D + jnz FspApiFailed=0D +=0D + ; ECX: start of range=0D + ; EDX: end of range=0D +CallSecFspInit:=0D + sub edx, [ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))] ; TemporaryRam= for FSP=0D + xor eax, eax=0D + mov esp, edx=0D +=0D + ; Align the stack at DWORD=0D + add esp, 3=0D + and esp, 0FFFFFFFCh=0D +=0D + push edx=0D + push ecx=0D + push eax ; zero - no hob list yet=0D + call ASM_PFX(CallPeiCoreEntryPoint)=0D +=0D +FspApiFailed:=0D + jmp $=0D +=0D +align 10h=0D +TempRamInitStack:=0D + DD TempRamInitDone=0D + DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams=0D +=0D +;=0D +; ROM-based Global-Descriptor Table for the Tiano PEI Phase=0D +;=0D +align 16=0D +global ASM_PFX(BootGdtTable)=0D +=0D +;=0D +; GDT[0]: 0x00: Null entry, never used.=0D +;=0D +NULL_SEL EQU $ - GDT_BASE ; Selector [0]=0D +GDT_BASE:=0D +ASM_PFX(BootGdtTable):=0D + DD 0=0D + DD 0=0D +;=0D +; Linear data segment descriptor=0D +;=0D +LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]=0D + DW 0FFFFh ; limit 0xFFFFF=0D + DW 0 ; base 0=0D + DB 0=0D + DB 092h ; present, ring 0, data, expand-up= , writable=0D + DB 0CFh ; page-granular, 32-bit=0D + DB 0=0D +;=0D +; Linear code segment descriptor=0D +;=0D +LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10]=0D + DW 0FFFFh ; limit 0xFFFFF=0D + DW 0 ; base 0=0D + DB 0=0D + DB 09Bh ; present, ring 0, data, expand-up= , not-writable=0D + DB 0CFh ; page-granular, 32-bit=0D + DB 0=0D +;=0D +; System data segment descriptor=0D +;=0D +SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18]=0D + DW 0FFFFh ; limit 0xFFFFF=0D + DW 0 ; base 0=0D + DB 0=0D + DB 093h ; present, ring 0, data, expand-up= , not-writable=0D + DB 0CFh ; page-granular, 32-bit=0D + DB 0=0D +=0D +;=0D +; System code segment descriptor=0D +;=0D +SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20]=0D + DW 0FFFFh ; limit 0xFFFFF=0D + DW 0 ; base 0=0D + DB 0=0D + DB 09Ah ; present, ring 0, data, expand-up= , writable=0D + DB 0CFh ; page-granular, 32-bit=0D + DB 0=0D +;=0D +; Spare segment descriptor=0D +;=0D +SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28]=0D + DW 0FFFFh ; limit 0xFFFFF=0D + DW 0 ; base 0=0D + DB 0Eh ; Changed from F000 to E000.=0D + DB 09Bh ; present, ring 0, code, expand-up= , writable=0D + DB 00h ; byte-granular, 16-bit=0D + DB 0=0D +;=0D +; Spare segment descriptor=0D +;=0D +SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30]=0D + DW 0FFFFh ; limit 0xFFFF=0D + DW 0 ; base 0=0D + DB 0=0D + DB 093h ; present, ring 0, data, expand-up= , not-writable=0D + DB 00h ; byte-granular, 16-bit=0D + DB 0=0D +=0D +;=0D +; Spare segment descriptor=0D +;=0D +SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]=0D + DW 0 ; limit 0=0D + DW 0 ; base 0=0D + DB 0=0D + DB 0 ; present, ring 0, data, expand-up= , writable=0D + DB 0 ; page-granular, 32-bit=0D + DB 0=0D +GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes=0D +=0D +;=0D +; GDT Descriptor=0D +;=0D +GdtDesc: ; GDT descriptor=0D + DW GDT_SIZE - 1 ; GDT limit=0D + DD GDT_BASE ; GDT base address=0D +=0D +=0D +ProtectedModeEntryLinearAddress:=0D +ProtectedModeEntryLinear:=0D + DD ProtectedModeEntryPoint ; Offset of our 32 bit code=0D + DW LINEAR_CODE_SEL=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/Ia32/Stack.nasm b/Platform/Intel/AlderlakeOpenBoardPk= g/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm new file mode 100644 index 00000000..d893b692 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/Ia32/Stack.nasm @@ -0,0 +1,72 @@ +;-------------------------------------------------------------------------= -----=0D +;=0D +; Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D +; SPDX-License-Identifier: BSD-2-Clause-Patent=0D +; Abstract:=0D +;=0D +; Switch the stack from temporary memory to permanent memory.=0D +;=0D +;-------------------------------------------------------------------------= -----=0D +=0D + SECTION .text=0D +=0D +;-------------------------------------------------------------------------= -----=0D +; VOID=0D +; EFIAPI=0D +; SecSwitchStack (=0D +; UINT32 TemporaryMemoryBase,=0D +; UINT32 PermanentMemoryBase=0D +; );=0D +;-------------------------------------------------------------------------= -----=0D +global ASM_PFX(SecSwitchStack)=0D +ASM_PFX(SecSwitchStack):=0D + ;=0D + ; Save three register: eax, ebx, ecx=0D + ;=0D + push eax=0D + push ebx=0D + push ecx=0D + push edx=0D +=0D + ;=0D + ; !!CAUTION!! this function address's is pushed into stack after=0D + ; migration of whole temporary memory, so need save it to permanent=0D + ; memory at first!=0D + ;=0D +=0D + mov ebx, [esp + 20] ; Save the first parameter=0D + mov ecx, [esp + 24] ; Save the second parameter=0D +=0D + ;=0D + ; Save this function's return address into permanent memory at first.= =0D + ; Then, Fixup the esp point to permanent memory=0D + ;=0D + mov eax, esp=0D + sub eax, ebx=0D + add eax, ecx=0D + mov edx, dword [esp] ; copy pushed register's value to perma= nent memory=0D + mov dword [eax], edx=0D + mov edx, dword [esp + 4]=0D + mov dword [eax + 4], edx=0D + mov edx, dword [esp + 8]=0D + mov dword [eax + 8], edx=0D + mov edx, dword [esp + 12]=0D + mov dword [eax + 12], edx=0D + mov edx, dword [esp + 16] ; Update this function's return address= into permanent memory=0D + mov dword [eax + 16], edx=0D + mov esp, eax ; From now, esp is pointed to perma= nent memory=0D +=0D + ;=0D + ; Fixup the ebp point to permanent memory=0D + ;=0D + mov eax, ebp=0D + sub eax, ebx=0D + add eax, ecx=0D + mov ebp, eax ; From now, ebp is pointed to permanent = memory=0D +=0D + pop edx=0D + pop ecx=0D + pop ebx=0D + pop eax=0D + ret=0D +=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/PlatformInit.c b/Platform/Intel/AlderlakeOpenBoardPkg= /FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c new file mode 100644 index 00000000..f7ec4f9e --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/PlatformInit.c @@ -0,0 +1,47 @@ +/** @file=0D + Provide platform init function.=0D +=0D +Copyright (c) 2023, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Platform initialization.=0D +=0D + @param[in] FspHobList HobList produced by FSP.=0D + @param[in] StartOfRange Start of temporary RAM.=0D + @param[in] EndOfRange End of temporary RAM.=0D +**/=0D +VOID=0D +EFIAPI=0D +PlatformInit (=0D + IN VOID *FspHobList,=0D + IN VOID *StartOfRange,=0D + IN VOID *EndOfRange=0D + )=0D +{=0D + //=0D + // Platform initialization=0D + // Enable Serial port here=0D + //=0D + if (PcdGetBool(PcdSecSerialPortDebugEnable)) {=0D + SerialPortInitialize ();=0D + }=0D +=0D + DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in PlatformInit\n"));=0D + DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));=0D + DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange));=0D + DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange));=0D +=0D + BoardAfterTempRamInit ();=0D +=0D + TestPointTempMemoryFunction (StartOfRange, EndOfRange);=0D +}=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/Alde= rlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrap= perPlatformSecLib.inf new file mode 100644 index 00000000..71c19d1c --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecFspWrapperPlatformSecLib.inf @@ -0,0 +1,106 @@ +## @file=0D +# Provide FSP wrapper platform sec related function.=0D +#=0D +# Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.
= =0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#=0D +##=0D +=0D +##########################################################################= ######=0D +#=0D +# Defines Section - statements that will be processed to create a Makefile= .=0D +#=0D +##########################################################################= ######=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D SecFspWrapperPlatformSecLib=0D + FILE_GUID =3D 5C3B04E1-60BC-4CE7-AD6B-60E395EF0051= =0D + MODULE_TYPE =3D SEC=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D PlatformSecLib=0D +=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64=0D +#=0D +=0D +##########################################################################= ######=0D +#=0D +# Sources Section - list of files that are required for the build to succe= ed.=0D +#=0D +##########################################################################= ######=0D +=0D +[Sources]=0D + FspWrapperPlatformSecLib.c=0D + SecRamInitData.c=0D + SecPlatformInformation.c=0D + SecGetPerformance.c=0D + SecTempRamDone.c=0D + PlatformInit.c=0D + FsptCoreUpd.h=0D +=0D +[Sources.IA32]=0D + Ia32/SecEntry.nasm=0D + Ia32/PeiCoreEntry.nasm=0D + Ia32/Stack.nasm=0D + Ia32/Fsp.h=0D +=0D +##########################################################################= ######=0D +#=0D +# Package Dependency Section - list of Package files that are required for= =0D +# this module.=0D +#=0D +##########################################################################= ######=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + UefiCpuPkg/UefiCpuPkg.dec=0D + IntelFsp2Pkg/IntelFsp2Pkg.dec=0D + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + AlderlakeSiliconPkg/SiPkg.dec=0D + AlderLakeFspBinPkg/Client/AlderLakeP/AlderLakeFspBinPkg.dec=0D + AlderlakeOpenBoardPkg/OpenBoardPkg.dec=0D +=0D +[LibraryClasses]=0D + LocalApicLib=0D + SerialPortLib=0D + FspWrapperPlatformLib=0D + FspWrapperApiLib=0D + SecBoardInitLib=0D + TestPointCheckLib=0D + PeiServicesTablePointerLib=0D +=0D +[Ppis]=0D + gEfiSecPlatformInformationPpiGuid ## CONSUMES=0D + gPeiSecPerformancePpiGuid ## CONSUMES=0D + gTopOfTemporaryRamPpiGuid ## PRODUCES=0D + gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES=0D + gFspTempRamExitPpiGuid ## CONSUMES=0D + gPlatformInitTempRamExitPpiGuid ## CONSUMES=0D +=0D +[Pcd]=0D + gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## C= ONSUMES=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## C= ONSUMES=0D + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## C= ONSUMES=0D + gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## C= ONSUMES=0D +=0D +[FixedPcd]=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ## C= ONSUMES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ## C= ONSUMES=0D + gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv ## C= ONSUMES=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## C= ONSUMES=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## C= ONSUMES=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## C= ONSUMES=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## C= ONSUMES=0D + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## C= ONSUMES=0D + gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## C= ONSUMES=0D + gSiPkgTokenSpaceGuid.PcdSerialIoUartMode ## C= ONSUMES=0D + gSiPkgTokenSpaceGuid.PcdSerialIoUartBaudRate ## C= ONSUMES=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## P= RODUCES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ## C= ONSUMES \ No newline at end of file diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/SecGetPerformance.c b/Platform/Intel/AlderlakeOpenBoa= rdPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c new file mode 100644 index 00000000..a59ee9a3 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecGetPerformance.c @@ -0,0 +1,89 @@ +/** @file=0D + Sample to provide SecGetPerformance function.=0D +=0D +Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +=0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + This interface conveys performance information out of the Security (SEC)= phase into PEI.=0D +=0D + This service is published by the SEC phase. The SEC phase handoff has an= optional=0D + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed= from SEC into the=0D + PEI Foundation. As such, if the platform supports collecting performance= data in SEC,=0D + this information is encapsulated into the data structure abstracted by t= his service.=0D + This information is collected for the boot-strap processor (BSP) on IA-3= 2.=0D +=0D + @param[in] PeiServices The pointer to the PEI Services Table.=0D + @param[in] This The pointer to this instance of the PEI_SEC_PER= FORMANCE_PPI.=0D + @param[out] Performance The pointer to performance data collected in SE= C phase.=0D +=0D + @retval EFI_SUCCESS The data was successfully returned.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SecGetPerformance (=0D + IN CONST EFI_PEI_SERVICES **PeiServices,=0D + IN PEI_SEC_PERFORMANCE_PPI *This,=0D + OUT FIRMWARE_SEC_PERFORMANCE *Performance=0D + )=0D +{=0D + UINT32 Size;=0D + UINT32 Count;=0D + UINTN TopOfTemporaryRam;=0D + UINT64 Ticker;=0D + VOID *TopOfTemporaryRamPpi;=0D + EFI_STATUS Status;=0D +=0D + DEBUG ((DEBUG_INFO, "SecGetPerformance\n"));=0D +=0D + Status =3D (*PeiServices)->LocatePpi (=0D + PeiServices,=0D + &gTopOfTemporaryRamPpiGuid,=0D + 0,=0D + NULL,=0D + (VOID **) &TopOfTemporaryRamPpi=0D + );=0D + if (EFI_ERROR (Status)) {=0D + return EFI_NOT_FOUND;=0D + }=0D + //=0D + // |--------------| <- TopOfTemporaryRam - BL=0D + // | List Ptr |=0D + // |--------------|=0D + // | BL RAM Start |=0D + // |--------------|=0D + // | BL RAM End |=0D + // |--------------|=0D + // |Number of BSPs|=0D + // |--------------|=0D + // | BIST |=0D + // |--------------|=0D + // | .... |=0D + // |--------------|=0D + // | TSC[63:32] |=0D + // |--------------|=0D + // | TSC[31:00] |=0D + // |--------------|=0D + //=0D + TopOfTemporaryRam =3D (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32);=0D + TopOfTemporaryRam -=3D sizeof (UINT32) * 2;=0D + Count =3D *(UINT32 *)(TopOfTemporaryRam - sizeof (UINT32));= =0D + Size =3D Count * sizeof (UINT32);=0D +=0D + Ticker =3D *(UINT64 *) (TopOfTemporaryRam - sizeof (UINT32) - Size - siz= eof (UINT32) * 2);=0D + Performance->ResetEnd =3D GetTimeInNanoSecond (Ticker);=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/SecPlatformInformation.c b/Platform/Intel/AlderlakeOp= enBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInform= ation.c new file mode 100644 index 00000000..401f84e5 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecPlatformInformation.c @@ -0,0 +1,78 @@ +/** @file=0D + Provide SecPlatformInformation function.=0D +=0D +Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +=0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +=0D +/**=0D + This interface conveys state information out of the Security (SEC) phase= into PEI.=0D +=0D + @param[in] PeiServices Pointer to the PEI Services Tab= le.=0D + @param[in,out] StructureSize Pointer to the variable describ= ing size of the input buffer.=0D + @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM= _INFORMATION_RECORD.=0D +=0D + @retval EFI_SUCCESS The data was successfully returned.=0D + @retval EFI_BUFFER_TOO_SMALL The buffer was too small.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SecPlatformInformation (=0D + IN CONST EFI_PEI_SERVICES **PeiServices,=0D + IN OUT UINT64 *StructureSize,=0D + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord= =0D + )=0D +{=0D + UINT32 *Bist;=0D + UINT32 Size;=0D + UINT32 Count;=0D + UINTN TopOfTemporaryRam;=0D + VOID *TopOfTemporaryRamPpi;=0D + EFI_STATUS Status;=0D +=0D + DEBUG ((DEBUG_INFO, "SecPlatformInformation\n"));=0D +=0D + Status =3D (*PeiServices)->LocatePpi (=0D + PeiServices,=0D + &gTopOfTemporaryRamPpiGuid,=0D + 0,=0D + NULL,=0D + (VOID **) &TopOfTemporaryRamPpi=0D + );=0D + if (EFI_ERROR (Status)) {=0D + return EFI_NOT_FOUND;=0D + }=0D +=0D + //=0D + // The entries of BIST information, together with the number of them,=0D + // reside in the bottom of stack, left untouched by normal stack operati= on.=0D + // This routine copies the BIST information to the buffer pointed by=0D + // PlatformInformationRecord for output.=0D + //=0D + TopOfTemporaryRam =3D (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32);=0D + TopOfTemporaryRam -=3D sizeof (UINT32) * 2;=0D + Count =3D *((UINT32 *)(TopOfTemporaryRam - sizeof (UINT32)))= ;=0D + Size =3D Count * sizeof (IA32_HANDOFF_STATUS);=0D +=0D + if ((*StructureSize) < (UINT64) Size) {=0D + *StructureSize =3D Size;=0D + return EFI_BUFFER_TOO_SMALL;=0D + }=0D +=0D + *StructureSize =3D Size;=0D + Bist =3D (UINT32 *) (TopOfTemporaryRam - sizeof (UINT32) - Si= ze);=0D +=0D + CopyMem (PlatformInformationRecord, Bist, Size);=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/SecRamInitData.c b/Platform/Intel/AlderlakeOpenBoardP= kg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c new file mode 100644 index 00000000..a3cc8741 --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecRamInitData.c @@ -0,0 +1,57 @@ +/** @file=0D + Provide TempRamInitParams data.=0D +=0D +Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include "FsptCoreUpd.h"=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD FsptUpdDataPtr =3D {=0D + {=0D + FSPT_UPD_SIGNATURE,=0D + 0x02,=0D + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + 0x00, 0x00, 0x00=0D + }=0D + },=0D + {=0D + 0x01,=0D + {=0D + 0x00, 0x00, 0x00=0D + },=0D + 0x00000020,=0D + 0x00000000,=0D + {=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D + }=0D + },=0D + {=0D + FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeO= ffsetInFv),=0D + FixedPcdGet64 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeO= ffsetInFv),=0D + 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(C= odeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.=0D + FixedPcdGet32 (PcdFlashCodeCacheSize),=0D + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D + }=0D + },=0D + {=0D + FixedPcdGet8 (PcdSerialIoUartDebugEnable),=0D + FixedPcdGet8 (PcdSerialIoUartNumber),=0D + FixedPcdGet8 (PcdSerialIoUartMode),=0D + 0,=0D + FixedPcdGet32 (PcdSerialIoUartBaudRate),=0D + FixedPcdGet64 (PcdPciExpressBaseAddress),=0D + {=0D + 0x00=0D + }=0D + },=0D + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D + },=0D + 0x55AA=0D +};=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/SecTempRamDone.c b/Platform/Intel/AlderlakeOpenBoardP= kg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c new file mode 100644 index 00000000..d28e9b7c --- /dev/null +++ b/Platform/Intel/AlderlakeOpenBoardPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecTempRamDone.c @@ -0,0 +1,93 @@ +/** @file=0D + Provide SecTemporaryRamDone function.=0D +=0D +Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.
=0D +SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D +This interface disables temporary memory in SEC Phase.=0D +**/=0D +VOID=0D +EFIAPI=0D +SecPlatformDisableTemporaryMemory (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + VOID *TempRamExitParam;=0D + CONST EFI_PEI_SERVICES **PeiServices;=0D + FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi;=0D + PLATFORM_INIT_TEMP_RAM_EXIT_PPI *PlatformInitTempRamExitPpi;=0D +=0D + DEBUG ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n"));=0D + PeiServices =3D GetPeiServicesTablePointer ();=0D + ASSERT (PeiServices !=3D NULL);=0D + if (PeiServices =3D=3D NULL) {=0D + return;=0D + }=0D + ASSERT ((*PeiServices) !=3D NULL);=0D + if ((*PeiServices) =3D=3D NULL) {=0D + return;=0D + }=0D + Status =3D (*PeiServices)->LocatePpi (=0D + PeiServices,=0D + &gPlatformInitTempRamExitPpiGuid,=0D + 0,=0D + NULL,=0D + (VOID **) &PlatformInitTempRamExitPpi=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D + if (EFI_ERROR (Status)) {=0D + return;=0D + }=0D +=0D + Status =3D PlatformInitTempRamExitPpi->PlatformInitBeforeTempRamExit ();= =0D + ASSERT_EFI_ERROR (Status);=0D +=0D + if (PcdGet8 (PcdFspModeSelection) =3D=3D 1) {=0D + //=0D + // FSP API mode=0D + //=0D + TempRamExitParam =3D UpdateTempRamExitParam ();=0D + Status =3D CallTempRamExit (TempRamExitParam);=0D + DEBUG ((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status));=0D + ASSERT_EFI_ERROR (Status);=0D + } else {=0D + //=0D + // FSP Dispatch mode=0D + //=0D + Status =3D (*PeiServices)->LocatePpi (=0D + PeiServices,=0D + &gFspTempRamExitPpiGuid,=0D + 0,=0D + NULL,=0D + (VOID **) &TempRamExitPpi=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D + if (EFI_ERROR (Status)) {=0D + return;=0D + }=0D + TempRamExitPpi->TempRamExit (NULL);=0D + }=0D +=0D + Status =3D PlatformInitTempRamExitPpi->PlatformInitAfterTempRamExit ();= =0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return ;=0D +}=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashC= ommon.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashComm= on.h deleted file mode 100644 index 76ba3a80..00000000 --- a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h +++ /dev/null @@ -1,99 +0,0 @@ -/** @file=0D - The header file includes the common header files, defines=0D - internal structure and functions used by SpiFlashCommonLib.=0D -=0D - Copyright (c) 2022, Intel Corporation. All rights reserved.
=0D - SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -**/=0D -=0D -#ifndef __SPI_FLASH_COMMON_H__=0D -#define __SPI_FLASH_COMMON_H__=0D -=0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -=0D -#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size=0D -/**=0D - Enable block protection on the Serial Flash device.=0D -=0D - @retval EFI_SUCCESS Opertion is successful.=0D - @retval EFI_DEVICE_ERROR If there is any device errors.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -SpiFlashLock (=0D - VOID=0D - );=0D -=0D -/**=0D - Read NumBytes bytes of data from the address specified by=0D - PAddress into Buffer.=0D -=0D - @param[in] Address The starting physical address of the read.= =0D - @param[in,out] NumBytes On input, the number of bytes to read. On = output, the number=0D - of bytes actually read.=0D - @param[out] Buffer The destination data buffer for the read.= =0D -=0D - @retval EFI_SUCCESS Opertion is successful.=0D - @retval EFI_DEVICE_ERROR If there is any device errors.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -SpiFlashRead (=0D - IN UINTN Address,=0D - IN OUT UINT32 *NumBytes,=0D - OUT UINT8 *Buffer=0D - );=0D -=0D -/**=0D - Write NumBytes bytes of data from Buffer to the address specified by=0D - PAddresss.=0D -=0D - @param[in] Address The starting physical address of the wri= te.=0D - @param[in,out] NumBytes On input, the number of bytes to write. = On output,=0D - the actual number of bytes written.=0D - @param[in] Buffer The source data buffer for the write.=0D -=0D - @retval EFI_SUCCESS Opertion is successful.=0D - @retval EFI_DEVICE_ERROR If there is any device errors.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -SpiFlashWrite (=0D - IN UINTN Address,=0D - IN OUT UINT32 *NumBytes,=0D - IN UINT8 *Buffer=0D - );=0D -=0D -/**=0D - Erase the block starting at Address.=0D -=0D - @param[in] Address The starting physical address of the block t= o be erased.=0D - This library assume that caller garantee tha= t the PAddress=0D - is at the starting address of this block.=0D - @param[in] NumBytes On input, the number of bytes of the logical= block to be erased.=0D - On output, the actual number of bytes erased= .=0D -=0D - @retval EFI_SUCCESS. Opertion is successful.=0D - @retval EFI_DEVICE_ERROR If there is any device errors.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -SpiFlashBlockErase (=0D - IN UINTN Address,=0D - IN UINTN *NumBytes=0D - );=0D -=0D -#endif=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommon= Lib/SmmSpiFlashCommonLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library= /SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf deleted file mode 100644 index cf6ca0d0..00000000 --- a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/Smm= SpiFlashCommonLib.inf +++ /dev/null @@ -1,49 +0,0 @@ -### @file=0D -# SMM Library instance of Spi Flash Common Library Class=0D -#=0D -# Copyright (c) 2022, Intel Corporation. All rights reserved.
=0D -# SPDX-License-Identifier: BSD-2-Clause-Patent=0D -#=0D -###=0D -=0D -[Defines]=0D - INF_VERSION =3D 0x00010017=0D - BASE_NAME =3D SmmSpiFlashCommonLib=0D - FILE_GUID =3D 9632D96E-E849-4217-9217-DC500B8AAE47= =0D - VERSION_STRING =3D 1.0=0D - MODULE_TYPE =3D DXE_SMM_DRIVER=0D - LIBRARY_CLASS =3D SpiFlashCommonLib|DXE_SMM_DRIVER=0D - CONSTRUCTOR =3D SmmSpiFlashCommonLibConstructor=0D -#=0D -# The following information is for reference only and not required by the = build tools.=0D -#=0D -# VALID_ARCHITECTURES =3D IA32 X64=0D -#=0D -=0D -[LibraryClasses]=0D - IoLib=0D - MemoryAllocationLib=0D - BaseLib=0D - UefiLib=0D - SmmServicesTableLib=0D - BaseMemoryLib=0D - DebugLib=0D -=0D -[Packages]=0D - MdePkg/MdePkg.dec=0D - AlderlakeSiliconPkg/SiPkg.dec=0D - AlderlakeOpenBoardPkg/OpenBoardPkg.dec=0D -=0D -[Pcd]=0D - gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES=0D - gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES=0D -=0D -[Sources]=0D - SpiFlashCommonSmmLib.c=0D - SpiFlashCommon.c=0D -=0D -[Protocols]=0D - gPchSmmSpiProtocolGuid ## CONSUMES=0D -=0D -[Depex.X64.DXE_SMM_DRIVER]=0D - gPchSmmSpiProtocolGuid=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommon= Lib/SpiFlashCommon.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiF= lashCommonLib/SpiFlashCommon.c deleted file mode 100644 index 3f7c52ac..00000000 --- a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/Spi= FlashCommon.c +++ /dev/null @@ -1,215 +0,0 @@ -/** @file=0D - Wrap EFI_SPI_PROTOCOL to provide some library level interfaces=0D - for module use.=0D -=0D - Copyright (c) 2022, Intel Corporation. All rights reserved.
=0D - SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -=0D -**/=0D -=0D -#include =0D -#include =0D -=0D -PCH_SPI_PROTOCOL *mSpiProtocol;=0D -=0D -//=0D -// Variables for boottime and runtime usage.=0D -//=0D -UINTN mBiosAreaBaseAddress =3D 0;=0D -UINTN mBiosSize =3D 0;=0D -UINTN mBiosOffset =3D 0;=0D -=0D -/**=0D - Enable block protection on the Serial Flash device.=0D -=0D - @retval EFI_SUCCESS Operation is successful.=0D - @retval EFI_DEVICE_ERROR If there is any device errors.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -SpiFlashLock (=0D - VOID=0D - )=0D -{=0D - EFI_STATUS Status;=0D -=0D - Status =3D EFI_SUCCESS;=0D -=0D - return Status;=0D -}=0D -=0D -/**=0D - Read NumBytes bytes of data from the address specified by=0D - PAddress into Buffer.=0D -=0D - @param[in] Address The starting physical address of the read.= =0D - @param[in,out] NumBytes On input, the number of bytes to read. On = output, the number=0D - of bytes actually read.=0D - @param[out] Buffer The destination data buffer for the read.= =0D -=0D - @retval EFI_SUCCESS Operation is successful.=0D - @retval EFI_DEVICE_ERROR If there is any device errors.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -SpiFlashRead (=0D - IN UINTN Address,=0D - IN OUT UINT32 *NumBytes,=0D - OUT UINT8 *Buffer=0D - )=0D -{=0D - ASSERT ((NumBytes !=3D NULL) && (Buffer !=3D NULL));=0D - if ((NumBytes =3D=3D NULL) || (Buffer =3D=3D NULL)) {=0D - return EFI_INVALID_PARAMETER;=0D - }=0D -=0D - //=0D - // This function is implemented specifically for those platforms=0D - // at which the SPI device is memory mapped for read. So this=0D - // function just do a memory copy for Spi Flash Read.=0D - //=0D - CopyMem (Buffer, (VOID *) Address, *NumBytes);=0D -=0D - return EFI_SUCCESS;=0D -}=0D -=0D -/**=0D - Write NumBytes bytes of data from Buffer to the address specified by=0D - PAddresss.=0D -=0D - @param[in] Address The starting physical address of the wri= te.=0D - @param[in,out] NumBytes On input, the number of bytes to write. = On output,=0D - the actual number of bytes written.=0D - @param[in] Buffer The source data buffer for the write.=0D -=0D - @retval EFI_SUCCESS Operation is successful.=0D - @retval EFI_DEVICE_ERROR If there is any device errors.=0D - @retval EFI_INVALID_PARAMETER Invalid parameter.=0D - @retval EFI_BAD_BUFFER_SIZE DataSectionSize in BGUP header e= xceeds the=0D - size ofBIOS Guard script buffer= =0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -SpiFlashWrite (=0D - IN UINTN Address,=0D - IN OUT UINT32 *NumBytes,=0D - IN UINT8 *Buffer=0D - )=0D -{=0D - EFI_STATUS Status;=0D - UINTN Offset;=0D - UINT32 Length;=0D - UINT32 RemainingBytes;=0D -=0D - ASSERT ((NumBytes !=3D NULL) && (Buffer !=3D NULL));=0D - if ((NumBytes =3D=3D NULL) || (Buffer =3D=3D NULL)) {=0D - return EFI_INVALID_PARAMETER;=0D - }=0D -=0D - ASSERT (Address >=3D mBiosAreaBaseAddress);=0D - if (Address < mBiosAreaBaseAddress) {=0D - return EFI_INVALID_PARAMETER;=0D - }=0D -=0D - Offset =3D Address - mBiosAreaBaseAddress;=0D -=0D - ASSERT ((*NumBytes + Offset) <=3D mBiosSize);=0D - if ((*NumBytes + Offset) > mBiosSize) {=0D - return EFI_INVALID_PARAMETER;=0D - }=0D -=0D - Status =3D EFI_SUCCESS;=0D - RemainingBytes =3D *NumBytes;=0D -=0D - while (RemainingBytes > 0) {=0D - if (RemainingBytes > SECTOR_SIZE_4KB) {=0D - Length =3D SECTOR_SIZE_4KB;=0D - } else {=0D - Length =3D RemainingBytes;=0D - }=0D - Status =3D mSpiProtocol->FlashWrite (=0D - mSpiProtocol,=0D - FlashRegionBios,=0D - (UINT32) Offset,=0D - Length,=0D - Buffer=0D - );=0D - if (EFI_ERROR (Status)) {=0D - break;=0D - }=0D - RemainingBytes -=3D Length;=0D - Offset +=3D Length;=0D - Buffer +=3D Length;=0D - }=0D -=0D - //=0D - // Actual number of bytes written=0D - //=0D - *NumBytes -=3D RemainingBytes;=0D -=0D - return Status;=0D -}=0D -=0D -/**=0D - Erase the block starting at Address.=0D -=0D - @param[in] Address The starting physical address of the block t= o be erased.=0D - This library assume that caller garantee tha= t the PAddress=0D - is at the starting address of this block.=0D - @param[in] NumBytes On input, the number of bytes of the logical= block to be erased.=0D - On output, the actual number of bytes erased= .=0D -=0D - @retval EFI_SUCCESS. Operation is successful.=0D - @retval EFI_DEVICE_ERROR If there is any device errors.=0D - @retval EFI_INVALID_PARAMETER Invalid parameter.=0D -=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -SpiFlashBlockErase (=0D - IN UINTN Address,=0D - IN UINTN *NumBytes=0D - )=0D -{=0D - EFI_STATUS Status;=0D - UINTN Offset;=0D - UINTN RemainingBytes;=0D -=0D - ASSERT (NumBytes !=3D NULL);=0D - if (NumBytes =3D=3D NULL) {=0D - return EFI_INVALID_PARAMETER;=0D - }=0D -=0D - ASSERT (Address >=3D mBiosAreaBaseAddress);=0D - if (Address < mBiosAreaBaseAddress) {=0D - return EFI_INVALID_PARAMETER;=0D - }=0D -=0D - Offset =3D Address - mBiosAreaBaseAddress;=0D -=0D - ASSERT ((*NumBytes % SECTOR_SIZE_4KB) =3D=3D 0);=0D - if ((*NumBytes % SECTOR_SIZE_4KB) !=3D 0) {=0D - return EFI_INVALID_PARAMETER;=0D - }=0D -=0D - ASSERT ((*NumBytes + Offset) <=3D mBiosSize);=0D - if ((*NumBytes + Offset) > mBiosSize) {=0D - return EFI_INVALID_PARAMETER;=0D - }=0D -=0D - Status =3D EFI_SUCCESS;=0D - RemainingBytes =3D *NumBytes;=0D -=0D - Status =3D mSpiProtocol->FlashErase (=0D - mSpiProtocol,=0D - FlashRegionBios,=0D - (UINT32) Offset,=0D - (UINT32) RemainingBytes=0D - );=0D - return Status;=0D -}=0D -=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommon= Lib/SpiFlashCommonSmmLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/S= mmSpiFlashCommonLib/SpiFlashCommonSmmLib.c deleted file mode 100644 index 897d8574..00000000 --- a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/Spi= FlashCommonSmmLib.c +++ /dev/null @@ -1,60 +0,0 @@ -/** @file=0D - SMM Library instance of SPI Flash Common Library Class=0D -=0D - Copyright (c) 2022, Intel Corporation. All rights reserved.
=0D - SPDX-License-Identifier: BSD-2-Clause-Patent=0D -=0D -=0D -**/=0D -=0D -#include =0D -#include =0D -=0D -extern PCH_SPI_PROTOCOL *mSpiProtocol;=0D -=0D -extern UINTN mBiosAreaBaseAddress;=0D -extern UINTN mBiosSize;=0D -extern UINTN mBiosOffset;=0D -=0D -/**=0D - The library constructuor.=0D -=0D - The function does the necessary initialization work for this library=0D - instance.=0D -=0D - @param[in] ImageHandle The firmware allocated handle for the UEFI= image.=0D - @param[in] SystemTable A pointer to the EFI system table.=0D -=0D - @retval EFI_SUCCESS The function always return EFI_SUCCESS for= now.=0D - It will ASSERT on error for debug version.= =0D - @retval EFI_ERROR Please reference LocateProtocol for error = code details.=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -SmmSpiFlashCommonLibConstructor (=0D - IN EFI_HANDLE ImageHandle,=0D - IN EFI_SYSTEM_TABLE *SystemTable=0D - )=0D -{=0D - EFI_STATUS Status;=0D - UINT32 BaseAddr;=0D - UINT32 RegionSize;=0D -=0D - mBiosAreaBaseAddress =3D (UINTN) PcdGet32 (PcdBiosAreaBaseAddress);=0D - mBiosSize =3D (UINTN) PcdGet32 (PcdBiosSize);=0D -=0D - //=0D - // Locate the SMM SPI protocol.=0D - //=0D - Status =3D gSmst->SmmLocateProtocol (=0D - &gPchSmmSpiProtocolGuid,=0D - NULL,=0D - (VOID **) &mSpiProtocol=0D - );=0D - ASSERT_EFI_ERROR (Status);=0D -=0D - mSpiProtocol->GetRegionAddress (mSpiProtocol, FlashRegionBios, &BaseAddr= , &RegionSize);=0D - mBiosOffset =3D BaseAddr;=0D -=0D - return Status;=0D -}=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/Ope= nBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c b/Platform/Intel/Alder= lakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPl= atformInitPostMem.c index 4fab4ad8..fab53ed8 100644 --- a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardP= latformInitPei/OpenBoardPlatformInitPostMem.c +++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardP= latformInitPei/OpenBoardPlatformInitPostMem.c @@ -5,52 +5,14 @@ SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D -=0D -#include =0D -#include =0D -#include =0D #include =0D #include =0D -#include =0D #include =0D #include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D -#include =0D #include =0D -#include =0D #include =0D #include =0D =0D -=0D -EFI_STATUS=0D -EFIAPI=0D -OpenBoardPlatformInitEndOfPei (=0D - IN CONST EFI_PEI_SERVICES **PeiServices,=0D - IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,=0D - IN VOID *Ppi=0D - );=0D -=0D -static EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList =3D {=0D - (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST),=0D - &gEfiEndOfPeiSignalPpiGuid,=0D - (EFI_PEIM_NOTIFY_ENTRY_POINT) OpenBoardPlatformInitEndOfPei=0D -};=0D -=0D EFI_STATUS=0D EFIAPI=0D GetPeiPlatformLidStatus (=0D @@ -127,58 +89,10 @@ GetPeiPlatformLidStatus ( OUT LID_STATUS *CurrentLidStatus=0D )=0D {=0D - DEBUG ((DEBUG_INFO, "LidStatus Unsupported\n"));=0D - return EFI_UNSUPPORTED;=0D -}=0D -=0D -/**=0D - Configure PciHostBridge related PCDs=0D -**/=0D -VOID=0D -ConfigurePciHostBridgePcds (=0D - VOID=0D - )=0D -{=0D - //=0D - // Provide 256GB available above 4GB MMIO resource=0D - // limited to use single variable MTRR to cover this above 4GB MMIO regi= on.=0D - //=0D - PcdSet64S (PcdPciReservedMemAbove4GBBase, BASE_256GB);=0D - PcdSet64S (PcdPciReservedMemAbove4GBLimit, BASE_256GB + SIZE_256GB - 1);= =0D - if (PcdGet64 (PcdPciReservedMemAbove4GBBase) < PcdGet64 (PcdPciReservedM= emAbove4GBLimit)) {=0D - DEBUG ((DEBUG_INFO, " PCI space that above 4GB MMIO is from 0x%lX", Pc= dGet64 (PcdPciReservedMemAbove4GBBase)));=0D - DEBUG ((DEBUG_INFO, " to 0x%lX\n", PcdGet64 (PcdPciReservedMemAbove4GB= Limit)));=0D - }=0D -}=0D -=0D -/**=0D - This function handles PlatformInit task at the end of PEI=0D -=0D - @param[in] PeiServices Pointer to PEI Services Table.=0D - @param[in] NotifyDesc Pointer to the descriptor for the Notification = event that=0D - caused this function to execute.=0D - @param[in] Ppi Pointer to the PPI data associated with this fu= nction.=0D -=0D - @retval EFI_SUCCESS The function completes successfully=0D - @retval others=0D -**/=0D -EFI_STATUS=0D -EFIAPI=0D -OpenBoardPlatformInitEndOfPei (=0D - IN CONST EFI_PEI_SERVICES **PeiServices,=0D - IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,=0D - IN VOID *Ppi=0D - )=0D -{=0D - //=0D - // Configure PciHostBridge related PCDs before DXE phase=0D - //=0D - ConfigurePciHostBridgePcds ();=0D -=0D + *CurrentLidStatus =3D LidOpen;=0D return EFI_SUCCESS;=0D }=0D =0D -=0D /**=0D Platform Init PEI module entry point=0D =0D @@ -201,8 +115,6 @@ OpenBoardPlatformInitPostMemEntryPoint ( PEI_CORE_FV_HANDLE *CoreFvHandle;=0D VOID *HobData;=0D =0D - PostCode (PLATFORM_INIT_POSTMEM_ENTRY);=0D -=0D //=0D // Build a HOB to show current FV location for SA policy update code to = consume.=0D //=0D @@ -223,11 +135,5 @@ OpenBoardPlatformInitPostMemEntryPoint ( DEBUG ((DEBUG_INFO, "Install mPeiGraphicsPlatformPpi \n"));=0D Status =3D PeiServicesInstallPpi (&mPeiGraphicsPlatformPpi);=0D =0D - //=0D - // Performing PlatformInitEndOfPei after EndOfPei PPI produced=0D - //=0D - Status =3D PeiServicesNotifyPpi (&mEndOfPeiNotifyList);=0D - PostCode (PLATFORM_INIT_POSTMEM_EXIT);=0D -=0D return Status;=0D }=0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/Ope= nBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf b/Platform/Intel/Ald= erlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoard= PlatformInitPostMem.inf index b2bfd97f..31c01919 100644 --- a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardP= latformInitPei/OpenBoardPlatformInitPostMem.inf +++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardP= latformInitPei/OpenBoardPlatformInitPostMem.inf @@ -17,20 +17,11 @@ [LibraryClasses]=0D PeimEntryPoint=0D DebugLib=0D - IoLib=0D MemoryAllocationLib=0D BaseMemoryLib=0D HobLib=0D PeiServicesLib=0D - PciSegmentLib=0D - MtrrLib=0D - PchInfoLib=0D - PostCodeLib=0D - SiPolicyLib=0D - FspCommonLib=0D PcdLib=0D - PchPciBdfLib=0D - GpioLib=0D PeiGetFvInfoLib=0D =0D [Packages]=0D @@ -49,27 +40,16 @@ OpenBoardPlatformInitPostMem.c=0D =0D [Ppis]=0D - gEfiEndOfPeiSignalPpiGuid ## CONSUMES=0D - gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES=0D gPeiGraphicsPlatformPpiGuid ## PRODUCES=0D - gFspSiliconInitDonePpiGuid ## CONSUMES=0D =0D [Protocols]=0D =0D [Guids]=0D - gEfiSmmSmramMemoryGuid ## CONSUMES=0D gPlatformInitFvLocationGuid ## PRODUCES=0D =0D [Depex]=0D gEfiPeiMemoryDiscoveredPpiGuid=0D =0D [Pcd]=0D - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSU= MES=0D - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIobase ## CONSU= MES=0D - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIoLimit ## CONSU= MES=0D - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase ## CONSU= MES=0D - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit ## CONSU= MES=0D - gMinPlatformPkgTokenSpaceGuid.PcdPciSegmentCount ## CONSU= MES=0D -=0D gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSU= MES=0D =0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyU= pdateLib/PeiCpuPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/= Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c index b23e2cec..1139277f 100644 --- a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi= b/PeiCpuPolicyUpdatePreMem.c +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi= b/PeiCpuPolicyUpdatePreMem.c @@ -15,8 +15,6 @@ #include =0D #include =0D #include =0D -#include =0D -#include =0D #include =0D #include =0D #include =0D @@ -73,7 +71,6 @@ UpdatePeiCpuPolicyPreMem ( =0D UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SkipStopPbet, CpuSecur= ityPreMemConfig->SkipStopPbet, FALSE);=0D =0D - SpiServiceInit ();=0D DEBUG ((DEBUG_INFO, "BIOS Guard PCD and Policy are disabled\n"));=0D UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.BiosGuard, CpuSecurity= PreMemConfig->BiosGuard, CPU_FEATURE_DISABLE);=0D =0D diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyU= pdateLib/PeiPolicyUpdateLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Poli= cy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf index 844e4c99..d6bb07fa 100644 --- a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi= b/PeiPolicyUpdateLib.inf +++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi= b/PeiPolicyUpdateLib.inf @@ -32,7 +32,6 @@ SiPolicyLib=0D PeiServicesLib=0D FirmwareBootMediaLib=0D - SpiLib=0D BmpSupportLib=0D PeiGetFvInfoLib=0D TimerLib=0D @@ -205,4 +204,4 @@ gPchPcieConfigGuid ## CONSUMES=0D gSerialIoConfigGuid ## CONSUMES=0D gPcieRpPreMemConfigGuid ## CONSUMES=0D - gSaMiscPeiPreMemConfigGuid ## CONSUMES=0D + gSaMiscPeiPreMemConfigGuid ## CONSUMES \ No newline at end of file --=20 2.26.2.windows.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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