From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id BB7E27803CE for ; Thu, 30 Nov 2023 02:25:57 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=9HIohct74tIuvl8VEi5hMQXz00vPflFrkHuyULV0y/0=; c=relaxed/simple; d=groups.io; h=Message-ID:Date:MIME-Version:User-Agent:Subject:To:Cc:References:From:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type; s=20140610; t=1701311156; v=1; b=mW8ORre4E+zNmhpSYjDdMZsltQeyYdAE69qs8QQxf8f0Mkxgm7XOcFMb2gtfyi+wUZtIa8mB M+44bp4xmiQRbOCOol0TQUw7UrGkHEWdTQ4aMGZcFt7Y5P1tgjDvp5GDl6otdF8rzjKtsV3f3/y K9GX0570Bj1gu4DNgDDuSiDU= X-Received: by 127.0.0.2 with SMTP id 1WyXYY7687511xboia8BLDo6; Wed, 29 Nov 2023 18:25:56 -0800 X-Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web10.63207.1701311154420262523 for ; Wed, 29 Nov 2023 18:25:54 -0800 X-Received: from loongson.cn (unknown [10.40.24.149]) by gateway (Coremail) with SMTP id _____8Dx_+up8mdlYNA9AA--.56128S3; Thu, 30 Nov 2023 10:25:46 +0800 (CST) X-Received: from [10.40.24.149] (unknown [10.40.24.149]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxfS+k8mdlpFxQAA--.47026S3; Thu, 30 Nov 2023 10:25:40 +0800 (CST) Message-ID: Date: Thu, 30 Nov 2023 10:25:40 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [edk2-devel] [PATCH v3 13/39] UefiCpuPkg: Add CpuMmuLib.h to UefiCpuPkg To: devel@edk2.groups.io, ray.ni@intel.com Cc: "Dong, Eric" , "Kumar, Rahul R" , Gerd Hoffmann , Leif Lindholm , Ard Biesheuvel , Sami Mujawar , Sunil V L , "Warkentin, Andrei" References: <20231117095742.3605778-1-lichao@loongs> <20231117100026.3609206-1-lichao@loongson.cn> From: "Chao Li" In-Reply-To: X-CM-TRANSID: AQAAf8DxfS+k8mdlpFxQAA--.47026S3 X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQALCGVn8SsABgABsd X-Coremail-Antispam: 1Uk129KBj93XoWxtF1rtw4rJw48Cw1xXry5GFX_yoWftw4rpr yDCrW5Gw4UtrW3WrWxZa1I9F1ru3yrGa4UGrWqyrn5Cw45t3s7uFZxK34jqFZrZF1fu34U XF42gw17uFZ5G3gCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnRJUUUylb4IE77IF4wAF F20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r 1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAF wI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1l84ACjcxK6I8E87Iv67 AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4j6r4UJwAS0I0E0xvYzxvE52x0 82IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI0UMcIj6xIIjxv20xvE14v26r106r15Mc Ij6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IY64vIr41l7480 Y4vEI4kI2Ix0rVAqx4xJMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI 8I3I0E5I8CrVAFwI0_JrI_JrWlx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AK xVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI 8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280 aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVWUJVW8JbIYCTnIWIevJa73UjIFyT uYvjxUFrWrDUUUU Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lichao@loongson.cn List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: Pzm6IHKIFNGFWKjDe7jPFnRBx7686176AA= Content-Type: multipart/alternative; boundary="------------FrUuUbIw1Hw3x0LUAf0Sv6i5" X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=mW8ORre4; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io --------------FrUuUbIw1Hw3x0LUAf0Sv6i5 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Hi Ray, Thanks for review, here are some of my thoughts: Thanks, Chao On 2023/11/30 08:59, Ni, Ray wrote: > Chao, > Since the lib class is so general, I'd like to understand more details to= make sure it can properly fit into any CPU arch. > > In X86, cache setting is through MSRs and Page tables, and memory access = control (read-only, not-present, non-executable) is through page tables. Let me understand, 'cache setting' means does it access a certain=20 address(probably a memory address) via cache? If so, I'd say the 'cache=20 setting' should be a part of attributes. > > This CpuMmuLib is to provide both services. How does LoongArch64 manage t= he cache settings and memory access control? > Is it proper to combine both services into one lib? In LoongArch64, cache settings and memory access control are performed=20 via page tables. Please check the patch 14 of this series. > > If the backend silicon IP is the same one that supports the "one" lib des= ign, can we refine the lib API a bit? Yes, I think Attribute's instance family can be bear the memory access=20 and cache setting. So what are you suggestions if we improve the lib API? > > We have (Set|Get)MemoryRegionAttribute() and (Set|Clear)MemoryRegion(NoEx= ec|ReadOnly). Can we merge them together? Do you means the (Set|Get) merge together(differentiate Get or Set=20 operations by parameters)? If so, I think it's OK, but maybe some=20 existing instances will be modified together. > > And the API ConfigureMemoryManagementUint() accepts MEMORY_REGION_DESCRIP= TOR but none of other APIs helps to construct the descriptor. Yes, currently, no one helps construct MEMORY_REGION_DESCRIPTOR. I think=20 the construction of descriptors is not part of the API, it should be the=20 localized or private when I design them. Do I need to add an API to=20 construct descripters? > > It seems to me the MmuLib is simply a combination of different random API= s. > It's not a well-designed library class. > > We need more discussion to make it be able to be accommodated by other ar= chs in future, at least by figuring out the path of X86, ARM. Yes, the APIs looks like so fragmented and we should improve them. So we=20 should talk more about this API, thanks. > > Thanks, > Ray >> -----Original Message----- >> From: Chao Li >> Sent: Friday, November 17, 2023 6:00 PM >> To:devel@edk2.groups.io >> Cc: Dong, Eric; Ni, Ray; Kumar, >> Rahul R; Gerd Hoffmann; >> Leif Lindholm; Ard Biesheuvel >> ; Sami Mujawar; >> Sunil V L; Warkentin, Andrei >> >> Subject: [PATCH v3 13/39] UefiCpuPkg: Add CpuMmuLib.h to UefiCpuPkg >> >> Add a new header file CpuMmuLib.h, whitch is referenced from >> ArmPkg/Include/Library/ArmMmuLib.h. Currently, only support for >> LoongArch64 is added, and more architectures can be accommodated in the >> future. >> >> BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=3D4584 >> >> Cc: Eric Dong >> Cc: Ray Ni >> Cc: Rahul Kumar >> Cc: Gerd Hoffmann >> Cc: Leif Lindholm >> Cc: Ard Biesheuvel >> Cc: Sami Mujawar >> Cc: Sunil V L >> Cc: Andrei Warkentin >> Signed-off-by: Chao Li >> --- >> UefiCpuPkg/Include/Library/CpuMmuLib.h | 155 >> +++++++++++++++++++++++++ >> UefiCpuPkg/UefiCpuPkg.dec | 4 + >> 2 files changed, 159 insertions(+) >> create mode 100644 UefiCpuPkg/Include/Library/CpuMmuLib.h >> >> diff --git a/UefiCpuPkg/Include/Library/CpuMmuLib.h >> b/UefiCpuPkg/Include/Library/CpuMmuLib.h >> new file mode 100644 >> index 0000000000..23b2fe34ac >> --- /dev/null >> +++ b/UefiCpuPkg/Include/Library/CpuMmuLib.h >> @@ -0,0 +1,155 @@ >> +/** @file >> + >> + Copyright (c) 2023 Loongson Technology Corporation Limited. All right= s >> reserved.
>> + >> + SPDX-License-Identifier: BSD-2-Clause-Patent >> + >> +**/ >> + >> +#ifndef CPU_MMU_LIB_H_ >> +#define CPU_MMU_LIB_H_ >> + >> +#include >> + >> +#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | \ >> + EFI_MEMORY_WC | \ >> + EFI_MEMORY_WT | \ >> + EFI_MEMORY_WB | \ >> + EFI_MEMORY_UCE \ >> + ) >> + >> +typedef struct { >> + EFI_PHYSICAL_ADDRESS PhysicalBase; >> + EFI_VIRTUAL_ADDRESS VirtualBase; >> + UINTN Length; >> + UINTN Attributes; >> +} MEMORY_REGION_DESCRIPTOR; >> + >> +/** >> + Converts EFI Attributes to corresponding architecture Attributes. >> + >> + @param[in] EfiAttributes Efi Attributes. >> + >> + @retval Corresponding architecture attributes. >> +**/ >> +UINTN >> +EfiAttributeConverse ( >> + IN UINTN EfiAttributes >> + ); >> + >> +/** >> + Finds the length and memory properties of the memory region >> corresponding to the specified base address. >> + >> + @param[in] BaseAddress To find the base address of the memory >> region. >> + @param[in] EndAddress To find the end address of the memory >> region. >> + @param[out] RegionLength The length of the memory region >> found. >> + @param[out] RegionAttributes Properties of the memory region >> found. >> + >> + @retval EFI_SUCCESS The corresponding memory area was >> successfully found >> + EFI_NOT_FOUND No memory area found >> +**/ >> +EFI_STATUS >> +GetMemoryRegionAttribute ( >> + IN UINTN BaseAddress, >> + IN UINTN EndAddress, >> + OUT UINTN *RegionLength, >> + OUT UINTN *RegionAttributes >> + ); >> + >> +/** >> + Sets the Attributes of the specified memory region >> + >> + @param[in] BaseAddress The base address of the memory region >> to set the Attributes. >> + @param[in] Length The length of the memory region to set >> the Attributes. >> + @param[in] Attributes The Attributes to be set. >> + @param[in] AttributeMask Mask of memory attributes to take into >> account. >> + >> + @retval EFI_SUCCESS The Attributes was set successfully >> +**/ >> +EFI_STATUS >> +SetMemoryRegionAttributes ( >> + IN EFI_PHYSICAL_ADDRESS BaseAddress, >> + IN UINTN Length, >> + IN UINTN Attributes, >> + IN UINT64 AttributeMask >> + ); >> + >> +/** >> + Sets the non-executable Attributes for the specified memory region >> + >> + @param[in] BaseAddress The base address of the memory region to >> set the Attributes. >> + @param[in] Length The length of the memory region to set the >> Attributes. >> + >> + @retval EFI_SUCCESS The Attributes was set successfully >> +**/ >> +EFI_STATUS >> +SetMemoryRegionNoExec ( >> + IN EFI_PHYSICAL_ADDRESS BaseAddress, >> + IN UINTN Length >> + ); >> + >> +/** >> + Clears the non-executable Attributes for the specified memory region >> + >> + @param[in] BaseAddress The base address of the memory region to >> clear the Attributes. >> + @param[in] Length The length of the memory region to clear >> the Attributes. >> + >> + @retval EFI_SUCCESS The Attributes was clear successfully >> +**/ >> +EFI_STATUS >> +EFIAPI >> +ClearMemoryRegionNoExec ( >> + IN EFI_PHYSICAL_ADDRESS BaseAddress, >> + IN UINT64 Length >> + ); >> + >> +/** >> + Sets the read-only Attributes for the specified memory region >> + >> + @param[in] BaseAddress The base address of the memory region to >> set the Attributes. >> + @param[in] Length The length of the memory region to set the >> Attributes. >> + >> + @retval EFI_SUCCESS The Attributes was set successfully >> +**/ >> +EFI_STATUS >> +EFIAPI >> +SetMemoryRegionReadOnly ( >> + IN EFI_PHYSICAL_ADDRESS BaseAddress, >> + IN UINT64 Length >> + ); >> + >> +/** >> + Clears the read-only Attributes for the specified memory region >> + >> + @param[in] BaseAddress The base address of the memory region to >> clear the Attributes. >> + @param[in] Length The length of the memory region to clear >> the Attributes. >> + >> + @retval EFI_SUCCESS The Attributes was clear successfully >> +**/ >> +EFI_STATUS >> +EFIAPI >> +ClearMemoryRegionReadOnly ( >> + IN EFI_PHYSICAL_ADDRESS BaseAddress, >> + IN UINT64 Length >> + ); >> + >> +/** >> + Create a page table and initialize the memory management unit(MMU). >> + >> + @param[in] MemoryTable A pointer to a memory ragion >> table. >> + @param[out] TranslationTableBase A pointer to a translation table ba= se >> address. >> + @param[out] TranslationTableSize A pointer to a translation table ba= se >> size. >> + >> + @retval EFI_SUCCESS Configure MMU successfully. >> + EFI_INVALID_PARAMETER MemoryTable is NULL. >> + EFI_UNSUPPORTED Out of memory space or >> size not aligned. >> +**/ >> +EFI_STATUS >> +EFIAPI >> +ConfigureMemoryManagementUint ( >> + IN MEMORY_REGION_DESCRIPTOR *MemoryTable, >> + OUT VOID **TranslationTableBase OPTIONAL, >> + OUT UINTN *TranslationTableSize OPTIONAL >> + ); >> + >> +#endif // CPU_MMU_LIB_H_ >> diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec >> index 154b1d06fe..150beae981 100644 >> --- a/UefiCpuPkg/UefiCpuPkg.dec >> +++ b/UefiCpuPkg/UefiCpuPkg.dec >> @@ -62,6 +62,10 @@ >> ## @libraryclass Provides function for manipulating x86 paging >> structures. >> CpuPageTableLib|Include/Library/CpuPageTableLib.h >> >> +[LibraryClasses.LoongArch64] >> + ## @libraryclass Provides macros and functions for the memory >> management unit. >> + CpuMmuLib|Include/Library/CpuMmuLib.h >> + >> ## @libraryclass Provides functions for manipulating smram savesta= te >> registers. >> MmSaveStateLib|Include/Library/MmSaveStateLib.h >> >> -- >> 2.27.0 > > >=20 > -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#111882): https://edk2.groups.io/g/devel/message/111882 Mute This Topic: https://groups.io/mt/102644768/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --------------FrUuUbIw1Hw3x0LUAf0Sv6i5 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable

Hi Ray,

Thanks for review, here are some of my thoughts:


=
Thanks,
Chao
On 2023/11/30 08:59, Ni, Ray wrote:
Chao,
Since the lib class is so general, I'd like to understand more details to m=
ake sure it can properly fit into any CPU arch.

In X86, cache setting is through MSRs and Page tables, and memory access co=
ntrol (read-only, not-present, non-executable) is through page tables.
Let me understand, 'cache setting' means does it access a certain address(probably a memory address) via cache? If so, I'd say the 'cache setting' should be a part of attributes.

This CpuMmuLib is to provide both services. How does LoongArch64 manage the=
 cache settings and memory access control?
Is it proper to combine both services into one lib?
In LoongArch64, cache settings and memory access control are performed via page tables. Please check the patch 14 of this series. 

If the backend silicon IP is the same one that supports the "one" lib desig=
n, can we refine the lib API a bit?
Yes, I think Attribute's instance family can be bear the memory access and cache setting. So what are you suggestions if we improve the lib API?

We have (Set|Get)MemoryRegionAttribute() and (Set|Clear)MemoryRegion(NoExec=
|ReadOnly). Can we merge them together?
Do you means the (Set|Get) merge together(differentiate Get or Set operations by parameters)? If so, I think it's OK, but maybe some existing instances will be modified together.

And the API ConfigureMemoryManagementUint() accepts MEMORY_REGION_DESCRIPTO=
R but none of other APIs helps to construct the descriptor.
Yes, currently, no one helps construct MEMORY_REGION_DESCRIPTOR. I think the construction of descriptors is not part of the API, it should be the localized or private when I design them. Do I need to add an API to construct descripters?

It seems to me the MmuLib is simply a combination of different random APIs.
It's not a well-designed library class.

We need more discussion to make it be able to be accommodated by other arch=
s in future, at least by figuring out the path of X86, ARM.
Yes, the APIs looks like so fragmented and we should improve them. So we should talk more about this API, thanks.

Thanks,
Ray

-----Original Message-----
From: Chao Li <lichao@loongson.cn>
Sent: Friday, November 17, 2023 6:00 PM
To: devel@edk2.groups.io
Cc: Dong, Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; =
Kumar,
Rahul R <rahul.r.kumar@intel.com>; Gerd Hoffmann <kraxel@redhat.com&=
gt;;
Leif Lindholm <quic_llindhol@quicinc.com>; Ard Biesheuvel
<ardb+tianocore@kernel.org>; Sami Mujawar <sami.mujawar@arm.com=
>;
Sunil V L <sunilvl@ventanamicro.com>; Warkentin, Andrei
<andrei.warkentin@intel.com>
Subject: [PATCH v3 13/39] UefiCpuPkg: Add CpuMmuLib.h to UefiCpuPkg

Add a new header file CpuMmuLib.h, whitch is referenced from
ArmPkg/Include/Library/ArmMmuLib.h. Currently, only support for
LoongArch64 is added, and more architectures can be accommodated in the
future.

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=
=3D4584

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Sami Mujawar <sami.mujawar@arm.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Andrei Warkentin <andrei.warkentin@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
---
 UefiCpuPkg/Include/Library/CpuMmuLib.h | 155
+++++++++++++++++++++++++
 UefiCpuPkg/UefiCpuPkg.dec              |   4 +
 2 files changed, 159 insertions(+)
 create mode 100644 UefiCpuPkg/Include/Library/CpuMmuLib.h

diff --git a/UefiCpuPkg/Include/Library/CpuMmuLib.h
b/UefiCpuPkg/Include/Library/CpuMmuLib.h
new file mode 100644
index 0000000000..23b2fe34ac
--- /dev/null
+++ b/UefiCpuPkg/Include/Library/CpuMmuLib.h
@@ -0,0 +1,155 @@
+/** @file
+
+  Copyright (c) 2023 Loongson Technology Corporation Limited. All rights
reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef CPU_MMU_LIB_H_
+#define CPU_MMU_LIB_H_
+
+#include <Uefi/UefiBaseType.h>
+
+#define EFI_MEMORY_CACHETYPE_MASK  (EFI_MEMORY_UC  | \
+                                    EFI_MEMORY_WC  | \
+                                    EFI_MEMORY_WT  | \
+                                    EFI_MEMORY_WB  | \
+                                    EFI_MEMORY_UCE   \
+                                    )
+
+typedef struct {
+  EFI_PHYSICAL_ADDRESS    PhysicalBase;
+  EFI_VIRTUAL_ADDRESS     VirtualBase;
+  UINTN                   Length;
+  UINTN                   Attributes;
+} MEMORY_REGION_DESCRIPTOR;
+
+/**
+  Converts EFI Attributes to corresponding architecture Attributes.
+
+  @param[in]  EfiAttributes     Efi Attributes.
+
+  @retval  Corresponding architecture attributes.
+**/
+UINTN
+EfiAttributeConverse (
+  IN UINTN  EfiAttributes
+  );
+
+/**
+  Finds the length and memory properties of the memory region
corresponding to the specified base address.
+
+  @param[in]  BaseAddress    To find the base address of the memory
region.
+  @param[in]  EndAddress     To find the end address of the memory
region.
+  @param[out]  RegionLength    The length of the memory region
found.
+  @param[out]  RegionAttributes    Properties of the memory region
found.
+
+  @retval  EFI_SUCCESS    The corresponding memory area was
successfully found
+           EFI_NOT_FOUND    No memory area found
+**/
+EFI_STATUS
+GetMemoryRegionAttribute (
+  IN     UINTN  BaseAddress,
+  IN     UINTN  EndAddress,
+  OUT    UINTN  *RegionLength,
+  OUT    UINTN  *RegionAttributes
+  );
+
+/**
+  Sets the Attributes  of the specified memory region
+
+  @param[in]  BaseAddress    The base address of the memory region
to set the Attributes.
+  @param[in]  Length         The length of the memory region to set
the Attributes.
+  @param[in]  Attributes     The Attributes to be set.
+  @param[in]  AttributeMask  Mask of memory attributes to take into
account.
+
+  @retval  EFI_SUCCESS    The Attributes was set successfully
+**/
+EFI_STATUS
+SetMemoryRegionAttributes (
+  IN EFI_PHYSICAL_ADDRESS  BaseAddress,
+  IN UINTN                 Length,
+  IN UINTN                 Attributes,
+  IN UINT64                AttributeMask
+  );
+
+/**
+  Sets the non-executable Attributes for the specified memory region
+
+  @param[in]  BaseAddress  The base address of the memory region to
set the Attributes.
+  @param[in]  Length       The length of the memory region to set the
Attributes.
+
+  @retval  EFI_SUCCESS    The Attributes was set successfully
+**/
+EFI_STATUS
+SetMemoryRegionNoExec (
+  IN  EFI_PHYSICAL_ADDRESS  BaseAddress,
+  IN  UINTN                 Length
+  );
+
+/**
+  Clears the non-executable Attributes for the specified memory region
+
+  @param[in]  BaseAddress  The base address of the memory region to
clear the Attributes.
+  @param[in]  Length       The length of the memory region to clear
the Attributes.
+
+  @retval  EFI_SUCCESS    The Attributes was clear successfully
+**/
+EFI_STATUS
+EFIAPI
+ClearMemoryRegionNoExec (
+  IN  EFI_PHYSICAL_ADDRESS  BaseAddress,
+  IN  UINT64                Length
+  );
+
+/**
+  Sets the read-only Attributes for the specified memory region
+
+  @param[in]  BaseAddress  The base address of the memory region to
set the Attributes.
+  @param[in]  Length       The length of the memory region to set the
Attributes.
+
+  @retval  EFI_SUCCESS    The Attributes was set successfully
+**/
+EFI_STATUS
+EFIAPI
+SetMemoryRegionReadOnly (
+  IN  EFI_PHYSICAL_ADDRESS  BaseAddress,
+  IN  UINT64                Length
+  );
+
+/**
+  Clears the read-only Attributes for the specified memory region
+
+  @param[in]  BaseAddress  The base address of the memory region to
clear the Attributes.
+  @param[in]  Length       The length of the memory region to clear
the Attributes.
+
+  @retval  EFI_SUCCESS    The Attributes was clear successfully
+**/
+EFI_STATUS
+EFIAPI
+ClearMemoryRegionReadOnly (
+  IN  EFI_PHYSICAL_ADDRESS  BaseAddress,
+  IN  UINT64                Length
+  );
+
+/**
+  Create a page table and initialize the memory management unit(MMU).
+
+  @param[in]  MemoryTable           A pointer to a memory ragion
table.
+  @param[out] TranslationTableBase  A pointer to a translation table base
address.
+  @param[out] TranslationTableSize  A pointer to a translation table base
size.
+
+  @retval  EFI_SUCCESS                Configure MMU successfully.
+           EFI_INVALID_PARAMETER      MemoryTable is NULL.
+           EFI_UNSUPPORTED            Out of memory space or
size not aligned.
+**/
+EFI_STATUS
+EFIAPI
+ConfigureMemoryManagementUint (
+  IN  MEMORY_REGION_DESCRIPTOR  *MemoryTable,
+  OUT VOID                      **TranslationTableBase OPTIONAL,
+  OUT UINTN                     *TranslationTableSize  OPTIONAL
+  );
+
+#endif // CPU_MMU_LIB_H_
diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec
index 154b1d06fe..150beae981 100644
--- a/UefiCpuPkg/UefiCpuPkg.dec
+++ b/UefiCpuPkg/UefiCpuPkg.dec
@@ -62,6 +62,10 @@
   ##  @libraryclass  Provides function for manipulating x86 paging
structures.
   CpuPageTableLib|Include/Library/CpuPageTableLib.h

+[LibraryClasses.LoongArch64]
+  ##  @libraryclass  Provides macros and functions for the memory
management unit.
+  CpuMmuLib|Include/Library/CpuMmuLib.h
+
   ## @libraryclass   Provides functions for manipulating smram savestate
registers.
   MmSaveStateLib|Include/Library/MmSaveStateLib.h

--
2.27.0
_._,_._,_
Groups.io Links:

=20 You receive all messages sent to this group. =20 =20

View/Reply Online (#111882) | =20 | Mute= This Topic | New Topic
Your Subscriptio= n | Contact Group Owner | Unsubscribe [rebecca@openfw.io]

_._,_._,_
--------------FrUuUbIw1Hw3x0LUAf0Sv6i5--