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dkim=none (message not signed) header.d=none;redhat.com; dmarc=none action=none header.from=amd.com; Received: from SN6PR12MB2718.namprd12.prod.outlook.com (2603:10b6:805:6f::22) by SN1PR12MB2448.namprd12.prod.outlook.com (2603:10b6:802:28::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4478.21; Thu, 9 Sep 2021 10:51:11 +0000 Received: from SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::78b7:7336:d363:9be3]) by SN6PR12MB2718.namprd12.prod.outlook.com ([fe80::78b7:7336:d363:9be3%6]) with mapi id 15.20.4478.027; Thu, 9 Sep 2021 10:51:11 +0000 Subject: Re: [PATCH v6 00/29] Add AMD Secure Nested Paging (SEV-SNP) support To: "Xu, Min M" , "Yao, Jiewen" , "devel@edk2.groups.io" CC: James Bottomley , Tom Lendacky , "Justen, Jordan L" , Ard Biesheuvel , Erdem Aktas , Michael Roth , Gerd Hoffmann References: <20210901161646.24763-1-brijesh.singh@amd.com> <4da448de-5e1c-85cf-9471-bf2d77281ac9@amd.com> From: "Brijesh Singh" Message-ID: Date: Thu, 9 Sep 2021 05:51:08 -0500 User-Agent: Mozilla/5.0 (Macintosh; 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charset=utf-8 Content-Transfer-Encoding: quoted-printable Content-Language: en-US Hi Min, On 9/8/21 7:31 PM, Xu, Min M wrote: > On September 9, 2021 3:46 AM, Brijesh Singh wrote: >> Thank you so much Yao for reviewing the patches. Based on some comments >> from Gerd I may update code around the reset vector area (mainly use the >> metadata format etc). For your comments regarding the introducing a new >> PcdConfidentialComputingCategory I will look to see what I can come up w= ith >> and in UefiCpuPkg I will try to move all the SEV specific functions in n= ew files >> (where applicable). >> > Hi, Brijesh > if you are considering to introduce a new PcdConfidentialComputingCategor= y > as Jiewen suggested below: >>> 0008-UefiCpuPkg-Define-the-SEV-SNP-specific-dynamic-PCDs >>> I really don't like the idea to use BOOL PcdSevEsIsEnabled and >> PcdSevSnpIsEnabled. >>> Can we define *one* PCD - such as PcdConfidentialComputingCategory? >>> We can assign range 0x0000~0xFFFF to AMD SEV, 0x10000~0x1FFFF to Intel >> TDX. >>> Then SEV=3D0x0000, SEV-ES=3D0x0001, SEV-SNP=3D0x0002, and TDX=3D0x10000 >> later. >>> I really don't want to keep adding PCD endlessly in the future, like >> PcdSevXXXIsEnabled, PcdSevYYYIsEnabled, PcdTdxIsEnabled, >> PcdTdx20Enabled, PcdTdx30Enabled, ...... > I also have some suggestions. > > As we have below definition in WorkArea.h > typedef struct _CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER { > UINT8 GuestType; > UINT8 Reserved1[3]; > } CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER; > > Can we update above CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER to below: > typedef struct _CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER { > UINT8 GuestType; > UINT8 SubType; // subtype which indic= ates SEV-ES, SEV-NP, or TDX 1.0, TDX 2.0 etc. > UINT8 Reserved1[2]; > } CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER; > > The PcdConfidentialComputingCategory can be defined as UINT32, like below= : > ## This dynamic PCD indicates the Confidential Computing Category > # [7:0] Confidential Computing Category (0 - Non-Cc, 1 - AmdSev, 2 = - IntelTdx) > # [15:8] Sub-Category (defined by each vendor, SEV-ES, SEV-SNP, or TD= X-1.0, TDX-2.0, etc) > # [31:16] Reserved > # @Prompt Confidential Computing Category > gUefiCpuPkgTokenSpaceGuid.PcdConfidentialComputingCategory|0|UINT32|0x6= 0000018 > > So that we simply copy the CONFIDENTIAL_COMPUTING_WORK_AREA_HEADER to Pcd= ConfidentialComputingCategory. > What's your thought? I am not sure if its a good idea to pack a header like above in a 32-bit PCD. The caller need to unpack the 32-bit number and perform a bitshit etc. Additionally we also need to check for reserved bits being set to zero etc. I am more inclined toward something like this: enum { =C2=A0=C2=A0 /* The guest is running with memory encryption disabled. */ =C2=A0=C2=A0=C2=A0 CC_ATTR_UNDEF, =C2=A0 /* The guest is running with active AMD SEV memory encryption. */ =C2=A0=C2=A0 CC_ATTR_AMD_SEV, =C2=A0 /* The guest is running with active AMD SEV-ES memory encryption. */ =C2=A0 CC_ATTR_AMD_SEV_ES, =C2=A0 /* The guest is running with active AMD SEV-SNP memory encryption. *= / =C2=A0 CC_ATTR_AMD_SEV_SNP, =C2=A0/* The guest is running with active Intel TDX memory encryption. */ =C2=A0CC_ATTR_INTEL_TDX, =C2=A0/* The guest is running with active Intel SGX memory encryption. */ =C2=A0CC_ATTR_INTEL_SGX, } ConfidentialComputingAttr; The PcdConfidentialComputingAttr will be set to zero. The OVMF will set this dynamic PCD in PEI phase. The UefiCpuPkg will provide a new function that can be used by anyone to check the CC guest type. BOOLEAN CcPlatformHas(enum ConfidentialComputingAttr attr) { =C2=A0=C2=A0=C2=A0 UINT32 Val; =C2=A0=C2=A0=C2=A0 Val =3D PcdGet32 (PcdConfidentialComputingAttr); =C2=A0=C2=A0=C2=A0 return val =3D=3D attr; } > Thanks! > Min