From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 51938780091 for ; Tue, 16 Jan 2024 05:08:56 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=UgPBnxMiIwXExgT6BofXinuG6Nbe3edfaFjN+qFGynM=; c=relaxed/simple; d=groups.io; h=Message-ID:Date:MIME-Version:User-Agent:Subject:To:CC:References:From:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1705381735; v=1; b=wLdVS83edn+QEo0D5k16tqSlEPsKQT5roEd00o6EcCJR8Dx523wNvJ32rB+DfokV9QsWDNlL raynEhjcmM/xa9l++nTgftYUKAe+/jctrWdYMdGi274w/gRfysomdyUr9k0FDXJt0RdseEoHXNF sEKJM5XNtB751BluBlZICDmU= X-Received: by 127.0.0.2 with SMTP id t3t2YY7687511x7mzqY5Niww; Mon, 15 Jan 2024 21:08:55 -0800 X-Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by mx.groups.io with SMTP id smtpd.web10.90009.1705341734661925047 for ; Mon, 15 Jan 2024 10:02:14 -0800 X-Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40FHeEap030079; Mon, 15 Jan 2024 18:02:13 GMT X-Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3vmyhk18ap-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 15 Jan 2024 18:02:13 +0000 (GMT) X-Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40FI2C9c011485 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 15 Jan 2024 18:02:12 GMT X-Received: from [10.111.135.76] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 15 Jan 2024 10:02:10 -0800 Message-ID: Date: Mon, 15 Jan 2024 18:02:08 +0000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [edk2-devel] [PATCH edk2-platforms 1/1] SbsaQemu: get cpu information from TF-A To: Marcin Juszkiewicz , CC: Ard Biesheuvel , Graeme Gregory References: <20240115151140.1476758-1-marcin.juszkiewicz@linaro.org> <20240115151140.1476758-2-marcin.juszkiewicz@linaro.org> From: "Leif Lindholm" In-Reply-To: <20240115151140.1476758-2-marcin.juszkiewicz@linaro.org> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-ORIG-GUID: dBCCnUrEuEq7x9il0eF47-sxKOQqr1Of X-Proofpoint-GUID: dBCCnUrEuEq7x9il0eF47-sxKOQqr1Of Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,quic_llindhol@quicinc.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: wbJcEUa3KNQsvVGSsqFLpi6Ex7686176AA= Content-Language: en-GB Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=wLdVS83e; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=quicinc.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On 2024-01-15 15:11, Marcin Juszkiewicz wrote: > As part of removing DeviceTree use we moved cpu related parts to TF-A. > On EDK2 side we get values via SMC calls during platform initialization. Could you split this into three patches?: - Adding new Library (Library name should have a Lib suffix.) - Using this library to check whether SMCs are supported, falling back to FdtHelperLib if not. - Dropping FdtHelperLib and the fallback paths. ? / Leif > Handled are: > - get cpu cores count > - get MPIDR > - get NUMA node id >=20 > If too old TF-A is used then cpu count and MPIDR are read directly from > DeviceTree. >=20 > Signed-off-by: Marcin Juszkiewicz > --- > Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 4 +- > .../Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf | 6 +- > .../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 4 +- > .../SbsaQemuPlatformDxe.inf | 4 +- > .../Library/FdtHelperLib/FdtHelperLib.inf | 33 --- > .../Library/SbsaQemuSmc/SbsaQemuSmc.inf | 34 +++ > .../Include/IndustryStandard/SbsaQemuSmc.h | 2 + > .../SbsaQemu/Include/Library/FdtHelperLib.h | 36 ---- > .../SbsaQemu/Include/Library/SbsaQemuSmc.h | 45 ++++ > .../Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c | 10 +- > .../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 16 +- > .../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 9 +- > .../Library/FdtHelperLib/FdtHelperLib.c | 98 --------- > .../Library/SbsaQemuSmc/SbsaQemuSmc.c | 204 ++++++++++++++++++ > 14 files changed, 308 insertions(+), 197 deletions(-) > delete mode 100644 Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelper= Lib.inf > create mode 100644 Silicon/Qemu/SbsaQemu/Library/SbsaQemuSmc/SbsaQemuSm= c.inf > delete mode 100644 Silicon/Qemu/SbsaQemu/Include/Library/FdtHelperLib.h > create mode 100644 Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuSmc.h > delete mode 100644 Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelper= Lib.c > create mode 100644 Silicon/Qemu/SbsaQemu/Library/SbsaQemuSmc/SbsaQemuSm= c.c >=20 > diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc b/Platform/Qemu/SbsaQemu= /SbsaQemu.dsc > index 378600050df9..231db11cb07b 100644 > --- a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > +++ b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc > @@ -1,6 +1,6 @@ > # > # Copyright (c) 2021, NUVIA Inc. All rights reserved. > -# Copyright (c) 2019, Linaro Limited. All rights reserved. > +# Copyright (c) 2023, Linaro Ltd. All rights reserved. > # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -126,7 +126,7 @@ [LibraryClasses.common] > # ARM PL011 UART Driver > PL011UartLib|ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf > =20 > - FdtHelperLib|Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.i= nf > + SbsaQemuSmc|Silicon/Qemu/SbsaQemu/Library/SbsaQemuSmc/SbsaQemuSmc.inf > OemMiscLib|Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf > =20 > # Debug Support > diff --git a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf b/Platform/= Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf > index a34f54d431d4..8e2bf8c512f1 100644 > --- a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf > +++ b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf > @@ -3,7 +3,7 @@ > # > # Copyright (c) 2021, NUVIA Inc. All rights reserved. > # Copyright (c) 2018, Hisilicon Limited. All rights reserved. > -# Copyright (c) 2018, Linaro Limited. All rights reserved. > +# Copyright (c) 2023, Linaro Ltd. All rights reserved. > # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -29,8 +29,6 @@ [Packages] > =20 > [LibraryClasses] > BaseMemoryLib > - FdtLib > - FdtHelperLib > IoLib > PcdLib > =20 > @@ -40,7 +38,6 @@ [Guids] > [Pcd] > gArmTokenSpaceGuid.PcdEmbeddedControllerFirmwareRelease > gArmTokenSpaceGuid.PcdSystemBiosRelease > - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress > =20 > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemManufacturer > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdSystemSerialNumber > @@ -56,3 +53,4 @@ [Pcd] > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisManufacturer > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisAssetTag > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdChassisSKU > + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDx= e.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf > index 291743b19115..d23b53586cd3 100644 > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf > @@ -1,7 +1,7 @@ > ## @file > # This driver modifies ACPI tables for the Qemu SBSA platform > # > -# Copyright (c) 2020, Linaro Ltd. All rights reserved. > +# Copyright (c) Linaro Ltd. All rights reserved. > # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -35,9 +35,9 @@ [LibraryClasses] > BaseLib > DebugLib > DxeServicesLib > - FdtHelperLib > PcdLib > PrintLib > + SbsaQemuSmc > UefiDriverEntryPoint > UefiLib > UefiRuntimeServicesTableLib > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPl= atformDxe.inf b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuP= latformDxe.inf > index 19534b7a274a..c8203a6ffc47 100644 > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformD= xe.inf > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformD= xe.inf > @@ -1,7 +1,7 @@ > ## @file > # This driver effectuates SbsaQemu platform configuration settings > # > -# Copyright (c) 2019, Linaro Ltd. All rights reserved. > +# Copyright (c) Linaro Ltd. All rights reserved. > # > # SPDX-License-Identifier: BSD-2-Clause-Patent > # > @@ -32,6 +32,7 @@ [LibraryClasses] > PcdLib > DebugLib > NonDiscoverableDeviceRegistrationLib > + SbsaQemuSmc > UefiDriverEntryPoint > =20 > [Pcd] > @@ -46,6 +47,7 @@ [Pcd] > gArmTokenSpaceGuid.PcdGicDistributorBase > gArmTokenSpaceGuid.PcdGicRedistributorsBase > gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdGicItsBase > + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount > =20 > =20 > [Depex] > diff --git a/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf = b/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf > deleted file mode 100644 > index 9c059f3e5851..000000000000 > --- a/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.inf > +++ /dev/null > @@ -1,33 +0,0 @@ > -#/** @file > -# > -# Component description file for FdtHelperLib module > -# > -# Copyright (c) 2021, NUVIA Inc. All rights reserved. > -# > -# SPDX-License-Identifier: BSD-2-Clause-Patent > -# > -#**/ > - > -[Defines] > - INF_VERSION =3D 1.29 > - BASE_NAME =3D FdtHelperLib > - FILE_GUID =3D 34e4396f-c2fc-4f9e-ad58-0f98e99e387= 5 > - MODULE_TYPE =3D BASE > - VERSION_STRING =3D 1.0 > - LIBRARY_CLASS =3D FdtHelperLib > - > -[Sources.common] > - FdtHelperLib.c > - > -[Packages] > - EmbeddedPkg/EmbeddedPkg.dec > - MdePkg/MdePkg.dec > - Silicon/Qemu/SbsaQemu/SbsaQemu.dec > - > -[LibraryClasses] > - DebugLib > - FdtLib > - PcdLib > - > -[FixedPcd] > - gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress > diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuSmc/SbsaQemuSmc.inf b/= Silicon/Qemu/SbsaQemu/Library/SbsaQemuSmc/SbsaQemuSmc.inf > new file mode 100644 > index 000000000000..a9d51d8871b0 > --- /dev/null > +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuSmc/SbsaQemuSmc.inf > @@ -0,0 +1,34 @@ > +#/* @file > +# > +# Copyright (c) Linaro Ltd. All rights reserved. > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +#*/ > + > +[Defines] > + INF_VERSION =3D 0x0001001c > + BASE_NAME =3D SbsaQemuSmc > + FILE_GUID =3D 6454006f-6502-46e2-9be4-4bba8d4b29f= b > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D ArmPlatformLib > + > +[Sources] > + SbsaQemuSmc.c > + > +[Packages] > + ArmPkg/ArmPkg.dec > + EmbeddedPkg/EmbeddedPkg.dec > + MdePkg/MdePkg.dec > + Silicon/Qemu/SbsaQemu/SbsaQemu.dec > + > +[LibraryClasses] > + ArmSmcLib > + BaseMemoryLib > + DebugLib > + FdtLib > + > + [Pcd] > + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdDeviceTreeBaseAddress > + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount > diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h= b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h > index 7934875e4aba..e33648ee1462 100644 > --- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h > +++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h > @@ -14,5 +14,7 @@ > #define SIP_SVC_VERSION SMC_SIP_FUNCTION_ID(1) > #define SIP_SVC_GET_GIC SMC_SIP_FUNCTION_ID(100) > #define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101) > +#define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200) > +#define SIP_SVC_GET_CPU_NODE SMC_SIP_FUNCTION_ID(201) > =20 > #endif /* SBSA_QEMU_SMC_H_ */ > diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/FdtHelperLib.h b/Silic= on/Qemu/SbsaQemu/Include/Library/FdtHelperLib.h > deleted file mode 100644 > index ea9159857215..000000000000 > --- a/Silicon/Qemu/SbsaQemu/Include/Library/FdtHelperLib.h > +++ /dev/null > @@ -1,36 +0,0 @@ > -/** @file > -* FdtHelperLib.h > -* > -* Copyright (c) 2021, NUVIA Inc. All rights reserved. > -* > -* SPDX-License-Identifier: BSD-2-Clause-Patent > -* > -**/ > - > -#ifndef FDT_HELPER_LIB_ > -#define FDT_HELPER_LIB_ > - > -/** > - Get MPIDR for a given cpu from device tree passed by Qemu. > - > - @param [in] CpuId Index of cpu to retrieve MPIDR value for. > - > - @retval MPIDR value of CPU at index > -**/ > -UINT64 > -FdtHelperGetMpidr ( > - IN UINTN CpuId > - ); > - > -/** Walks through the Device Tree created by Qemu and counts the number > - of CPUs present in it. > - > - @return The number of CPUs present. > -**/ > -EFIAPI > -UINT32 > -FdtHelperCountCpus ( > - VOID > - ); > - > -#endif /* FDT_HELPER_LIB_ */ > diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuSmc.h b/Silico= n/Qemu/SbsaQemu/Include/Library/SbsaQemuSmc.h > new file mode 100644 > index 000000000000..883b8d0d0d17 > --- /dev/null > +++ b/Silicon/Qemu/SbsaQemu/Include/Library/SbsaQemuSmc.h > @@ -0,0 +1,45 @@ > +/** @file > +* > +* Copyright (c) Linaro Ltd. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > + > +#ifndef SBSA_QEMU_SMC_ > +#define SBSA_QEMU_SMC_ > + > +/** > + Get CPU count from information passed by Qemu. > + > +**/ > +VOID > +SbsaQemuGetCpuCount ( > + VOID > + ); > + > +/** > + Get MPIDR for a given cpu from device tree passed by Qemu. > + > + @param [in] CpuId Index of cpu to retrieve MPIDR value for. > + > + @retval MPIDR value of CPU at index > +**/ > +UINT64 > +SbsaQemuGetMpidr ( > + IN UINTN CpuId > + ); > + > +/** > + Get NUMA node id for a given cpu from device tree passed by Qemu. > + > + @param [in] CpuId Index of cpu to retrieve NUMA node id for. > + > + @retval NUMA node id for CPU at index > +**/ > +UINT64 > +SbsaQemuGetCpuNumaNode ( > + IN UINTN CpuId > + ); > + > +#endif /* SBSA_QEMU_SMC_ */ > diff --git a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c b/Platform/Qe= mu/SbsaQemu/OemMiscLib/OemMiscLib.c > index c38f2851904f..ab97768b5ddc 100644 > --- a/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c > +++ b/Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c > @@ -2,7 +2,7 @@ > * OemMiscLib.c > * > * Copyright (c) 2021, NUVIA Inc. All rights reserved. > -* Copyright (c) 2020, Linaro Ltd. All rights reserved. > +* Copyright (c) Linaro Ltd. All rights reserved. > * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > @@ -12,14 +12,12 @@ > #include > #include > #include > -#include > #include > #include > #include > #include > #include > #include > -#include > =20 > /** Returns whether the specified processor is present or not. > =20 > @@ -33,7 +31,7 @@ OemIsProcessorPresent ( > UINTN ProcessorIndex > ) > { > - if (ProcessorIndex < FdtHelperCountCpus ()) { > + if (ProcessorIndex < PcdGet32 (PcdCoreCount)) { > return TRUE; > } > =20 > @@ -76,7 +74,7 @@ OemGetProcessorInformation ( > { > UINT16 ProcessorCount; > =20 > - ProcessorCount =3D FdtHelperCountCpus (); > + ProcessorCount =3D PcdGet32 (PcdCoreCount); > =20 > if (ProcessorIndex < ProcessorCount) { > ProcessorStatus->Bits.CpuStatus =3D 1; // CPU enabled > @@ -121,7 +119,7 @@ OemGetMaxProcessors ( > VOID > ) > { > - return FdtHelperCountCpus (); > + return PcdGet32 (PcdCoreCount); > } > =20 > /** Gets information about the cache at the specified cache level. > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDx= e.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > index 9fb17151d7b8..fa9102194e84 100644 > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c > @@ -1,7 +1,7 @@ > /** @file > * This file is an ACPI driver for the Qemu SBSA platform. > * > -* Copyright (c) 2020, Linaro Ltd. All rights reserved. > +* Copyright (c) Linaro Ltd. All rights reserved. > * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > @@ -15,10 +15,10 @@ > #include > #include > #include > -#include > #include > #include > #include > +#include > #include > #include > #include > @@ -255,7 +255,7 @@ AddMadtTable ( > // Initialize GIC Redistributor Structure > EFI_ACPI_6_0_GICR_STRUCTURE Gicr =3D SBSAQEMU_MADT_GICR_INIT(); > =20 > - // Get CoreCount which was determined eariler after parsing device tre= e > + // Get CoreCount which was determined earlier from TF-A > NumCores =3D PcdGet32 (PcdCoreCount); > =20 > // Calculate the new table size based on the number of cores > @@ -291,13 +291,13 @@ AddMadtTable ( > New +=3D sizeof (EFI_ACPI_6_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER)= ; > =20 > // Add new GICC structures for the Cores > - for (CoreIndex =3D 0; CoreIndex < PcdGet32 (PcdCoreCount); CoreIndex++= ) { > + for (CoreIndex =3D 0; CoreIndex < NumCores; CoreIndex++) { > EFI_ACPI_6_0_GIC_STRUCTURE *GiccPtr; > =20 > CopyMem (New, &Gicc, sizeof (EFI_ACPI_6_0_GIC_STRUCTURE)); > GiccPtr =3D (EFI_ACPI_6_0_GIC_STRUCTURE *) New; > GiccPtr->AcpiProcessorUid =3D CoreIndex; > - GiccPtr->MPIDR =3D FdtHelperGetMpidr (CoreIndex); > + GiccPtr->MPIDR =3D SbsaQemuGetMpidr (CoreIndex); > New +=3D sizeof (EFI_ACPI_6_0_GIC_STRUCTURE); > } > =20 > @@ -758,12 +758,6 @@ InitializeSbsaQemuAcpiDxe ( > { > EFI_STATUS Status; > EFI_ACPI_TABLE_PROTOCOL *AcpiTable; > - UINT32 NumCores; > - > - // Parse the device tree and get the number of CPUs > - NumCores =3D FdtHelperCountCpus (); > - Status =3D PcdSet32S (PcdCoreCount, NumCores); > - ASSERT_RETURN_ERROR (Status); > =20 > // Check if ACPI Table Protocol has been installed > Status =3D gBS->LocateProtocol ( > diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPl= atformDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPla= tformDxe.c > index 4ebbe7c93a19..bc5545a272fe 100644 > --- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformD= xe.c > +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformD= xe.c > @@ -1,7 +1,7 @@ > /** @file > -* FDT client protocol driver for qemu,mach-virt-ahci DT node > +* SbsaQemu Platform Initialization > * > -* Copyright (c) 2019, Linaro Ltd. All rights reserved. > +* Copyright (c) Linaro Ltd. All rights reserved. > * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > @@ -12,13 +12,12 @@ > #include > #include > #include > +#include > #include > #include > #include > #include > =20 > -#include > - > EFI_STATUS > EFIAPI > InitializeSbsaQemuPlatformDxe ( > @@ -123,5 +122,7 @@ InitializeSbsaQemuPlatformDxe ( > } > } > =20 > + SbsaQemuGetCpuCount(); > + > return EFI_SUCCESS; > } > diff --git a/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c b/= Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c > deleted file mode 100644 > index 7fdfb055db76..000000000000 > --- a/Silicon/Qemu/SbsaQemu/Library/FdtHelperLib/FdtHelperLib.c > +++ /dev/null > @@ -1,98 +0,0 @@ > -/** @file > -* FdtHelperLib.c > -* > -* Copyright (c) 2021, NUVIA Inc. All rights reserved. > -* Copyright (c) 2020, Linaro Ltd. All rights reserved. > -* > -* SPDX-License-Identifier: BSD-2-Clause-Patent > -* > -**/ > - > -#include > -#include > -#include > -#include > -#include > - > -STATIC INT32 mFdtFirstCpuOffset; > -STATIC INT32 mFdtCpuNodeSize; > - > -/** > - Get MPIDR for a given cpu from device tree passed by Qemu. > - > - @param [in] CpuId Index of cpu to retrieve MPIDR value for. > - > - @retval MPIDR value of CPU at index > -**/ > -UINT64 > -FdtHelperGetMpidr ( > - IN UINTN CpuId > - ) > -{ > - VOID *DeviceTreeBase; > - CONST UINT64 *RegVal; > - INT32 Len; > - > - DeviceTreeBase =3D (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); > - ASSERT (DeviceTreeBase !=3D NULL); > - > - RegVal =3D fdt_getprop (DeviceTreeBase, > - mFdtFirstCpuOffset + (CpuId * mFdtCpuNodeSize), > - "reg", > - &Len); > - if (!RegVal) { > - DEBUG ((DEBUG_ERROR, "Couldn't find reg property for CPU:%d\n", CpuI= d)); > - return 0; > - } > - > - return (fdt64_to_cpu (ReadUnaligned64 (RegVal))); > -} > - > -/** Walks through the Device Tree created by Qemu and counts the number > - of CPUs present in it. > - > - @return The number of CPUs present. > -**/ > -EFIAPI > -UINT32 > -FdtHelperCountCpus ( > - VOID > - ) > -{ > - VOID *DeviceTreeBase; > - INT32 Node; > - INT32 Prev; > - INT32 CpuNode; > - UINT32 CpuCount; > - > - DeviceTreeBase =3D (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); > - ASSERT (DeviceTreeBase !=3D NULL); > - > - // Make sure we have a valid device tree blob > - ASSERT (fdt_check_header (DeviceTreeBase) =3D=3D 0); > - > - CpuNode =3D fdt_path_offset (DeviceTreeBase, "/cpus"); > - if (CpuNode <=3D 0) { > - DEBUG ((DEBUG_ERROR, "Unable to locate /cpus in device tree\n")); > - return 0; > - } > - > - CpuCount =3D 0; > - > - // Walk through /cpus node and count the number of subnodes. > - // The count of these subnodes corresponds to the number of > - // CPUs created by Qemu. > - Prev =3D fdt_first_subnode (DeviceTreeBase, CpuNode); > - mFdtFirstCpuOffset =3D Prev; > - while (1) { > - CpuCount++; > - Node =3D fdt_next_subnode (DeviceTreeBase, Prev); > - if (Node < 0) { > - break; > - } > - mFdtCpuNodeSize =3D Node - Prev; > - Prev =3D Node; > - } > - > - return CpuCount; > -} > diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuSmc/SbsaQemuSmc.c b/Si= licon/Qemu/SbsaQemu/Library/SbsaQemuSmc/SbsaQemuSmc.c > new file mode 100644 > index 000000000000..70bae6739fcb > --- /dev/null > +++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuSmc/SbsaQemuSmc.c > @@ -0,0 +1,204 @@ > +/** @file > +* > +* Copyright (c) 2021, NUVIA Inc. All rights reserved. > +* Copyright (c) Linaro Ltd. All rights reserved. > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + Get MPIDR for a given cpu from device tree passed by Qemu. > + > + @param [in] CpuId Index of cpu to retrieve MPIDR value for. > + > + @retval MPIDR value of CPU at index > +**/ > +UINT64 > +FdtHelperGetMpidr ( > + IN UINTN CpuId > + ) > +{ > + VOID *DeviceTreeBase; > + INT32 Node; > + INT32 Prev; > + UINT32 CpuCount; > + CONST UINT64 *RegVal; > + > + DeviceTreeBase =3D (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); > + ASSERT (DeviceTreeBase !=3D NULL); > + > + // Make sure we have a valid device tree blob > + ASSERT (fdt_check_header (DeviceTreeBase) =3D=3D 0); > + > + Node =3D fdt_path_offset (DeviceTreeBase, "/cpus"); > + if (Node <=3D 0) { > + DEBUG ((DEBUG_ERROR, "Unable to locate /cpus in device tree\n")); > + return 0; > + } > + > + CpuCount =3D 0; > + > + Prev =3D fdt_first_subnode (DeviceTreeBase, Node); > + while (1) { > + > + if (CpuCount =3D=3D CpuId) { > + RegVal =3D fdt_getprop (DeviceTreeBase, Prev, "reg", NULL); > + if (!RegVal) { > + DEBUG ((DEBUG_ERROR, "Couldn't find reg property for CPU:%d\n", = CpuId)); > + return 0; > + } > + return (fdt64_to_cpu (ReadUnaligned64 (RegVal))); > + } > + > + Node =3D fdt_next_subnode (DeviceTreeBase, Prev); > + if (Node < 0) { > + break; > + } > + Prev =3D Node; > + CpuCount++; > + } > + > + return 0; /* We did not found MPIDR */ > + > +} > + > +/** Walks through the Device Tree created by Qemu and counts the number > + of CPUs present in it. > + > + @return The number of CPUs present. > +**/ > +EFIAPI > +UINT32 > +FdtHelperCountCpus ( > + VOID > + ) > +{ > + VOID *DeviceTreeBase; > + INT32 Node; > + INT32 Prev; > + UINT32 CpuCount; > + > + DeviceTreeBase =3D (VOID *)(UINTN)PcdGet64 (PcdDeviceTreeBaseAddress); > + ASSERT (DeviceTreeBase !=3D NULL); > + > + // Make sure we have a valid device tree blob > + ASSERT (fdt_check_header (DeviceTreeBase) =3D=3D 0); > + > + Node =3D fdt_path_offset (DeviceTreeBase, "/cpus"); > + if (Node <=3D 0) { > + DEBUG ((DEBUG_ERROR, "Unable to locate /cpus in device tree\n")); > + return 0; > + } > + > + CpuCount =3D 0; > + > + // Walk through /cpus node and count the number of subnodes. > + // The count of these subnodes corresponds to the number of > + // CPUs created by Qemu. > + Prev =3D fdt_first_subnode (DeviceTreeBase, Node); > + while (1) { > + CpuCount++; > + Node =3D fdt_next_subnode (DeviceTreeBase, Prev); > + if (Node < 0) { > + break; > + } > + Prev =3D Node; > + } > + > + return CpuCount; > +} > + > + > +/** > + Get CPU count from information passed by Qemu. > + > +**/ > +VOID > +SbsaQemuGetCpuCount ( > + VOID > + ) > +{ > + UINTN Arg0; > + UINTN SmcResult; > + RETURN_STATUS Result; > + > + SmcResult =3D ArmCallSmc0 (SIP_SVC_GET_CPU_COUNT, &Arg0, NULL, NULL); > + if (SmcResult !=3D SMC_ARCH_CALL_SUCCESS) { > + DEBUG ((DEBUG_INFO, "Too old TF-A. We have to get cpu info from DT.\= n")); > + Arg0 =3D FdtHelperCountCpus(); > + } > + > + Result =3D PcdSet32S (PcdCoreCount, Arg0); > + ASSERT_RETURN_ERROR (Result); > + > + Arg0 =3D PcdGet32 (PcdCoreCount); > + > + DEBUG ((DEBUG_INFO, "We have %d cpus.\n", Arg0)); > +} > + > +/** > + Get MPIDR for a given cpu from device tree passed by Qemu. > + > + @param [in] CpuId Index of cpu to retrieve MPIDR value for. > + > + @retval MPIDR value of CPU at index > +**/ > +UINT64 > +SbsaQemuGetMpidr ( > + IN UINTN CpuId > + ) > +{ > + UINTN SmcResult; > + UINTN Arg0; > + UINTN Arg1; > + > + Arg0 =3D CpuId; > + > + SmcResult =3D ArmCallSmc0 (SIP_SVC_GET_CPU_NODE, &Arg0, &Arg1, NULL); > + if (SmcResult !=3D SMC_ARCH_CALL_SUCCESS) { > + DEBUG ((DEBUG_INFO, "Too old TF-A. We have to get cpu info from DT.\= n")); > + Arg1 =3D FdtHelperGetMpidr(CpuId); > +} > + > + DEBUG ((DEBUG_ERROR, "MPIDR for CPU:%d =3D %d\n", CpuId, Arg1)); > + > + return Arg1; > +} > + > +/** > + Get NUMA node id for a given cpu from device tree passed by Qemu. > + > + @param [in] CpuId Index of cpu to retrieve NUMA node id for. > + > + @retval NUMA node id for CPU at index > +**/ > +UINT64 > +SbsaQemuGetCpuNumaNode ( > + IN UINTN CpuId > + ) > +{ > + UINTN SmcResult; > + UINTN Arg0; > + UINTN Arg1; > + > + Arg0 =3D CpuId; > + > + SmcResult =3D ArmCallSmc0 (SIP_SVC_GET_CPU_NODE, &Arg0, &Arg1, NULL); > + if (SmcResult !=3D SMC_ARCH_CALL_SUCCESS) { > + /* No fallback to DeviceTree as we did not had that info earlier. */ > + DEBUG ((DEBUG_ERROR, "Couldn't find information for CPU:%d\n", CpuId= )); > + return 0; > + } > + > + DEBUG ((DEBUG_ERROR, "NUMA node for CPU:%d =3D %d\n", CpuId, Arg0)); > + > + return Arg0; > +} -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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