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kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.32 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.32; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.32) by DM6NAM11FT019.mail.protection.outlook.com (10.13.172.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4587.18 via Frontend Transport; Mon, 11 Oct 2021 21:40:52 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 11 Oct 2021 14:40:45 -0700 Received: from ashishsingha-lnx.nvidia.com (172.20.187.5) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 11 Oct 2021 21:40:44 +0000 From: "Ashish Singhal" To: , , CC: Ashish Singhal Subject: [PATCH v2] ArmPkg/TimerDxe: Delay End Of Interrupt Signal Date: Mon, 11 Oct 2021 15:40:42 -0600 Message-ID: X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public Return-Path: ashishsingha@nvidia.com MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 970b6f03-e9c8-49c4-2934-08d98cffccc2 X-MS-TrafficTypeDiagnostic: BN6PR12MB1362: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Oct 2021 21:40:52.8242 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 970b6f03-e9c8-49c4-2934-08d98cffccc2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.32];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1362 Content-Type: text/plain In an interrupt handler for the timers, it is important that software clears the interrupt before deactivating the interrupt in the GIC. Otherwise the GIC will re-signal the same interrupt again. Signed-off-by: Ashish Singhal --- ArmPkg/Drivers/TimerDxe/TimerDxe.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c index 0370620fae..46e5bbf287 100644 --- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c +++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c @@ -300,10 +300,6 @@ TimerInterruptHandler ( // OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL); - // Signal end of interrupt early to help avoid losing subsequent ticks - // from long duration handlers - gInterrupt->EndOfInterrupt (gInterrupt, Source); - // Check if the timer interrupt is active if ((ArmGenericTimerGetTimerCtrlReg () ) & ARM_ARCH_TIMER_ISTATUS) { @@ -335,6 +331,11 @@ TimerInterruptHandler ( ArmInstructionSynchronizationBarrier (); } + // In an interrupt handler for the timers, it is important that software clears the interrupt + // before deactivating the interrupt in the GIC. Otherwise the GIC will re-signal the same + // interrupt again. + gInterrupt->EndOfInterrupt (gInterrupt, Source); + gBS->RestoreTPL (OriginalTPL); } -- 2.17.1