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* [edk2-platforms][PATCH] ClevoOpenBoardPkg: Added OS boot support
@ 2019-06-14 20:00 Agyeman, Prince
  2019-06-25 22:16 ` [edk2-devel] " Sinha, Ankit
  2019-06-28 20:56 ` Nate DeSimone
  0 siblings, 2 replies; 3+ messages in thread
From: Agyeman, Prince @ 2019-06-14 20:00 UTC (permalink / raw)
  To: devel; +Cc: Liming Gao, David Y Wei, Michael Kubacki, Nate DeSimone,
	Chasel Chiu

These changes add OS boot support to N1xxWU platforms

Test: N1xxWU currently boots to windows 10

Cc: Liming Gao <liming.gao@intel.com>
Cc: David Y Wei <david.y.wei@intel.com>
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>

Co-authored-by: David Y Wei <david.y.wei@intel.com>
Signed-off-by: Agyeman <prince.agyeman@intel.com>
---
 .../Features/Tbt/TbtInit/Smm/TbtSmm.inf       |   2 +-
 .../PeiPreMemSiliconPolicyNotifyLib.c         | 103 +++
 .../PeiPreMemSiliconPolicyNotifyLib.inf       |  43 ++
 .../PeiSaPolicyUpdatePreMem.c                 |  11 +-
 .../PeiSiliconPolicyUpdateLibFsp.inf          |   3 +
 .../PeiMultiBoardInitPreMemLib.inf            |   3 +
 .../BoardInitLib/PeiN1xxWUInitPreMemLib.c     |  30 +-
 .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc |  13 +-
 .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf |   2 +-
 .../N1xxWU/OpenBoardPkgPcd.dsc                |   2 +-
 .../PlatformInitPei/PlatformInitPreMem.c      | 640 ++++++++++++++++++
 .../PlatformInitPei/PlatformInitPreMem.inf    |  67 ++
 12 files changed, 899 insertions(+), 20 deletions(-)
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
 create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf

diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
index 3826cf589b..c08608ae76 100644
--- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
+++ b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf
@@ -44,7 +44,7 @@
 
 [Pcd]
   gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES
-  gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength      ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength      ## CONSUMES
 
 [FixedPcd]
   gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress       ## CONSUMES
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c
new file mode 100644
index 0000000000..0fedd81cd0
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c
@@ -0,0 +1,103 @@
+/** @file
+  This library implements constructor function to register notify call back
+  when policy PPI installed.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/SiPolicyLib.h>
+
+/**
+  Callback function to update policy when policy PPI installed.
+
+  @param[in] PeiServices          General purpose services available to every PEIM.
+  @param[in] NotifyDescriptor     The notification structure this PEIM registered on install.
+  @param[in] Ppi                  The memory discovered PPI.  Not used.
+
+  @retval EFI_SUCCESS             Succeeds.
+  @retval Others                  Error code returned by sub-functions.
+**/
+EFI_STATUS
+EFIAPI
+SiPreMemPolicyPpiNotify (
+  IN  EFI_PEI_SERVICES             **PeiServices,
+  IN  EFI_PEI_NOTIFY_DESCRIPTOR    *NotifyDescriptor,
+  IN  VOID                         *Ppi
+  )
+{
+  EFI_STATUS                  Status;
+  SI_PREMEM_POLICY_PPI        *SiPreMemPolicyPpi;
+  SA_MISC_PEI_PREMEM_CONFIG   *MiscPeiPreMemConfig;
+
+  DEBUG ((DEBUG_INFO, "SiPreMemPolicyPpiNotify() Start\n"));
+
+  Status = PeiServicesLocatePpi (
+             &gSiPreMemPolicyPpiGuid,
+             0,
+             NULL,
+             (VOID **)&SiPreMemPolicyPpi
+             );
+  ASSERT_EFI_ERROR (Status);
+  if (SiPreMemPolicyPpi != NULL) {
+    //
+    // Get requisite IP Config Blocks which needs to be used here
+    //
+    Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
+    ASSERT_EFI_ERROR (Status);
+
+    //
+    // Update SpdAddressTable policy when it is installed.
+    //
+    if (MiscPeiPreMemConfig != NULL) {
+      MiscPeiPreMemConfig->SpdAddressTable[0] = PcdGet8 (PcdMrcSpdAddressTable0);
+      DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[0] 0x%x\n", MiscPeiPreMemConfig->SpdAddressTable[0]));
+      MiscPeiPreMemConfig->SpdAddressTable[1] = PcdGet8 (PcdMrcSpdAddressTable1);
+      DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[1] 0x%x\n", MiscPeiPreMemConfig->SpdAddressTable[1]));
+      MiscPeiPreMemConfig->SpdAddressTable[2] = PcdGet8 (PcdMrcSpdAddressTable2);
+      DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[2] 0x%x\n", MiscPeiPreMemConfig->SpdAddressTable[2]));
+      MiscPeiPreMemConfig->SpdAddressTable[3] = PcdGet8 (PcdMrcSpdAddressTable3);
+      DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[3] 0x%x\n", MiscPeiPreMemConfig->SpdAddressTable[3]));
+    }
+  }
+  return Status;
+}
+
+static EFI_PEI_NOTIFY_DESCRIPTOR  mSiPreMemPolicyPpiNotifyList[] = {
+  {
+    EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+    &gSiPreMemPolicyPpiGuid,
+    SiPreMemPolicyPpiNotify
+  }
+};
+
+/**
+  The library constructuor.
+  The function register a policy install notify callback.
+
+  @param[in]  ImageHandle       The firmware allocated handle for the UEFI image.
+  @param[in]  SystemTable       A pointer to the EFI system table.
+
+  @retval     EFI_SUCCESS       The function always return EFI_SUCCESS for now.
+                                It will ASSERT on error for debug version.
+**/
+EFI_STATUS
+EFIAPI
+PeiPreMemSiliconPolicyNotifyLibConstructor (
+  IN       EFI_PEI_FILE_HANDLE  FileHandle,
+  IN CONST EFI_PEI_SERVICES     **PeiServices
+  )
+{
+  EFI_STATUS                  Status;
+  //
+  // Register call back after PPI produced
+  //
+  Status = PeiServicesNotifyPpi (mSiPreMemPolicyPpiNotifyList);
+  ASSERT_EFI_ERROR (Status);
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf
new file mode 100644
index 0000000000..13c12655f6
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf
@@ -0,0 +1,43 @@
+## @file
+# Component information file for Silicon Policy Notify Library.
+# This library implements constructor function to register notify call back
+# when policy PPI installed.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PeiPreMemSiliconPolicyNotifyLib
+  FILE_GUID                      = 6D231E12-C088-47C8-8B16-61F07293EEF8
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = NULL
+  CONSTRUCTOR                    = PeiPreMemSiliconPolicyNotifyLibConstructor
+
+[LibraryClasses]
+  BaseLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  KabylakeOpenBoardPkg/OpenBoardPkg.dec
+  KabylakeSiliconPkg/SiPkg.dec
+
+[Sources]
+  PeiPreMemSiliconPolicyNotifyLib.c
+
+[Guids]
+  gSaMiscPeiPreMemConfigGuid
+
+[Ppis]
+  gSiPreMemPolicyPpiGuid
+
+[Pcd]
+  # SPD Address Table
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
index 12d2b2cdb2..93d79c2313 100644
--- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
@@ -39,8 +39,15 @@ PeiFspSaPolicyUpdatePreMem (
 {
   VOID                        *Buffer;
 
-  CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr00, (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize));
-  CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr10, (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize));
+//
+// Update UPD:DqPinsInterleaved
+//
+  FspmUpd->FspmConfig.DqPinsInterleaved = (UINT8)PcdGetBool(PcdMrcDqPinsInterleaved);
+
+  //
+  // Update UPD:DqPinsInterleaved
+  //
+  FspmUpd->FspmConfig.CaVrefConfig = PcdGet8(PcdMrcCaVrefConfig);
 
   DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n"));
   Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap);
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
index 25531d3d7f..b9b9232692 100644
--- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
@@ -96,6 +96,9 @@
   gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram      ## CONSUMES
   gBoardModuleTokenSpaceGuid.PcdMrcSpdData
   gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
+  gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig
+  gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl
+  gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved
 
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress      ## CONSUMES
   gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable        ## CONSUMES
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
index 8f73c2fa40..0f6be110c0 100644
--- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
@@ -64,6 +64,9 @@
   gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
   gBoardModuleTokenSpaceGuid.PcdMrcSpdData
   gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
+  gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig
+  gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl
+  gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved
 
   # PEG Reset By GPIO
   gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUInitPreMemLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUInitPreMemLib.c
index 10550baf8a..b8eb0e67c6 100644
--- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUInitPreMemLib.c
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxWUInitPreMemLib.c
@@ -44,6 +44,15 @@ GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp1[SA_MRC_MAX_RCOMP
 //
 GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23, 40 };
 
+//
+// Reference RCOMP resistors on motherboard - for SKL RVP2
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp2[SA_MRC_MAX_RCOMP] = { 121, 81, 100 };
+//
+// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SKL RVP2
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp2[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 20, 20, 26 };
+
 /**
   N 1XX WU board configuration init function for PEI pre-memory phase.
 
@@ -81,20 +90,17 @@ N1xxWUInitPreMem (
   //
   PcdSet8S (PcdSaMiscUserBd, 5);
 
-  PcdSet8S (PcdMrcSpdAddressTable0, 0xA2);
-  PcdSet8S (PcdMrcSpdAddressTable1, 0xA0);
-  PcdSet8S (PcdMrcSpdAddressTable2, 0xA2);
-  PcdSet8S (PcdMrcSpdAddressTable3, 0xA0);
+  PcdSet8S (PcdMrcSpdAddressTable0, 0xA0);
+  PcdSet8S (PcdMrcSpdAddressTable1, 0xA2);
+  PcdSet8S (PcdMrcSpdAddressTable2, 0xA4);
+  PcdSet8S (PcdMrcSpdAddressTable3, 0xA6);
 
-  PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3);
-  PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3));
-  PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramSklRvp3);
-  PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramSklRvp3));
-  PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1);
-  PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1);
 
-  PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd110);
-  PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3Spd110Size);
+  PcdSetBoolS(PcdMrcDqPinsInterleavedControl, TRUE);
+  PcdSetBoolS(PcdMrcDqPinsInterleaved, TRUE);
+  PcdSet32S(PcdMrcRcompResistor, (UINTN)RcompResistorSklRvp2);
+  PcdSet32S(PcdMrcRcompTarget, (UINTN)RcompTargetSklRvp2);
+  PcdSet8S(PcdMrcCaVrefConfig, 2); // DDR4 boards
 
   PcdSetBoolS (PcdIoExpanderPresent, TRUE);
 
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc
index 02ef06579b..f9deece846 100644
--- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc
@@ -120,7 +120,7 @@
   #
   # PEI phase common
   #
-  SerialPortLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.inf
+  SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
   DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
   FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf
 !if $(TARGET) == DEBUG
@@ -209,7 +209,7 @@
 # Platform
 #
   $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
-  $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
+  $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
     <LibraryClasses>
 !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
       BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
@@ -221,7 +221,14 @@
     <LibraryClasses>
       SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibDependency/PeiPreMemSiliconPolicyInitLibDependency.inf
   }
-  $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
+  $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf{
+    <LibraryClasses>
+  #  #
+    # Hook a library constructor to update some policy fields when policy installed.
+    #
+    NULL|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf
+  }
+
   $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf {
     <LibraryClasses>
 !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport == FALSE
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf
index b16bf0fe4e..7d76257671 100644
--- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf
@@ -234,7 +234,7 @@ INF  MdeModulePkg/Core/Pei/PeiMain.inf
 !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
 
 INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
-INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+INF $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
 INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
 INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
 
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc
index 7bb341a1dd..c6bce19856 100644
--- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc
@@ -43,7 +43,7 @@
   gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1
 
   gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
-  gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+  gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|0x10000000
   gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
   gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
new file mode 100644
index 0000000000..b784026c1b
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c
@@ -0,0 +1,640 @@
+/** @file
+  Source code file for Platform Init Pre-Memory PEI module
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <IndustryStandard/Pci30.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/TimerLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/MtrrLib.h>
+#include <Library/ReportFvLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Ppi/MemoryDiscovered.h>
+#include <Ppi/FirmwareVolumeInfo.h>
+#include <Ppi/BootInRecoveryMode.h>
+#include <Ppi/MasterBootMode.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/TestPointCheckLib.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Ppi/PlatformMemorySize.h>
+#include <Ppi/BaseMemoryTest.h>
+
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotifyCallback (
+  IN CONST EFI_PEI_SERVICES      **PeiServices,
+  IN EFI_PEI_NOTIFY_DESCRIPTOR   *NotifyDescriptor,
+  IN VOID                        *Ppi
+  );
+
+EFI_STATUS
+EFIAPI
+GetPlatformMemorySize (
+  IN      EFI_PEI_SERVICES                       **PeiServices,
+  IN      PEI_PLATFORM_MEMORY_SIZE_PPI           *This,
+  IN OUT  UINT64                                 *MemorySize
+  );
+
+/**
+
+  This function checks the memory range in PEI.
+
+  @param PeiServices     Pointer to PEI Services.
+  @param This            Pei memory test PPI pointer.
+  @param BeginAddress    Beginning of the memory address to be checked.
+  @param MemoryLength    Bytes of memory range to be checked.
+  @param Operation       Type of memory check operation to be performed.
+  @param ErrorAddress    Return the address of the error memory address.
+
+  @retval EFI_SUCCESS         The operation completed successfully.
+  @retval EFI_DEVICE_ERROR    Memory test failed. It's not safe to use this range of memory.
+
+**/
+EFI_STATUS
+EFIAPI
+BaseMemoryTest (
+  IN  EFI_PEI_SERVICES                   **PeiServices,
+  IN  PEI_BASE_MEMORY_TEST_PPI           *This,
+  IN  EFI_PHYSICAL_ADDRESS               BeginAddress,
+  IN  UINT64                             MemoryLength,
+  IN  PEI_MEMORY_TEST_OP                 Operation,
+  OUT EFI_PHYSICAL_ADDRESS               *ErrorAddress
+  );
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = {
+  (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  &gEfiPeiMemoryDiscoveredPpiGuid,
+  (EFI_PEIM_NOTIFY_ENTRY_POINT) MemoryDiscoveredPpiNotifyCallback
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPpiListRecoveryBootMode = {
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  &gEfiPeiBootInRecoveryModePpiGuid,
+  NULL
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPpiBootMode = {
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  &gEfiPeiMasterBootModePpiGuid,
+  NULL
+};
+
+static PEI_BASE_MEMORY_TEST_PPI     mPeiBaseMemoryTestPpi = { BaseMemoryTest };
+
+static PEI_PLATFORM_MEMORY_SIZE_PPI mMemoryMemorySizePpi  = { GetPlatformMemorySize };
+
+static EFI_PEI_PPI_DESCRIPTOR       mMemPpiList[] = {
+  {
+    EFI_PEI_PPI_DESCRIPTOR_PPI,
+    &gPeiBaseMemoryTestPpiGuid,
+    &mPeiBaseMemoryTestPpi
+  },
+  {
+    (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+    &gPeiPlatformMemorySizePpiGuid,
+    &mMemoryMemorySizePpi
+  },
+};
+
+///
+/// Memory Reserved should be between 125% to 150% of the Current required memory
+/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resume issues.
+///
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
+  { EfiACPIReclaimMemory,   FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemorySize) },  // ASL
+  { EfiACPIMemoryNVS,       FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize) },      // ACPI NVS (including S3 related)
+  { EfiReservedMemoryType,  FixedPcdGet32 (PcdPlatformEfiReservedMemorySize) },     // BIOS Reserved (including S3 related)
+  { EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize) },       // Runtime Service Data
+  { EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize) },       // Runtime Service Code
+  { EfiMaxMemoryType, 0 }
+};
+
+VOID
+BuildMemoryTypeInformation (
+  VOID
+  )
+{
+  EFI_STATUS                      Status;
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
+  UINTN                           DataSize;
+  EFI_MEMORY_TYPE_INFORMATION     MemoryData[EfiMaxMemoryType + 1];
+
+  //
+  // Locate system configuration variable
+  //
+  Status = PeiServicesLocatePpi(
+             &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
+             0,                                // INSTANCE
+             NULL,                             // EFI_PEI_PPI_DESCRIPTOR
+             (VOID **) &VariableServices       // PPI
+             );
+  ASSERT_EFI_ERROR(Status);
+
+  DataSize = sizeof (MemoryData);
+  Status = VariableServices->GetVariable (
+                               VariableServices,
+                               EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
+                               &gEfiMemoryTypeInformationGuid,
+                               NULL,
+                               &DataSize,
+                               &MemoryData
+                               );
+  if (EFI_ERROR(Status)) {
+    DataSize = sizeof (mDefaultMemoryTypeInformation);
+    CopyMem(MemoryData, mDefaultMemoryTypeInformation, DataSize);
+  }
+
+  ///
+  /// Build the GUID'd HOB for DXE
+  ///
+  BuildGuidDataHob (
+    &gEfiMemoryTypeInformationGuid,
+    MemoryData,
+    DataSize
+    );
+}
+
+EFI_STATUS
+EFIAPI
+GetPlatformMemorySize (
+  IN      EFI_PEI_SERVICES                       **PeiServices,
+  IN      PEI_PLATFORM_MEMORY_SIZE_PPI           *This,
+  IN OUT  UINT64                                 *MemorySize
+  )
+{
+  EFI_STATUS                      Status;
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
+  UINTN                           DataSize;
+  EFI_MEMORY_TYPE_INFORMATION     MemoryData[EfiMaxMemoryType + 1];
+  UINTN                           Index;
+  EFI_BOOT_MODE                   BootMode;
+  UINTN                           IndexNumber;
+
+#define PEI_MIN_MEMORY_SIZE             (EFI_PHYSICAL_ADDRESS) ((320 * 0x100000))
+
+  *MemorySize = PEI_MIN_MEMORY_SIZE;
+  Status = PeiServicesLocatePpi (
+             &gEfiPeiReadOnlyVariable2PpiGuid,
+             0,
+             NULL,
+             (VOID **)&Variable
+             );
+
+  ASSERT_EFI_ERROR (Status);
+
+  Status = PeiServicesGetBootMode (&BootMode);
+  ASSERT_EFI_ERROR (Status);
+
+  DataSize = sizeof (MemoryData);
+
+  Status = Variable->GetVariable (
+                      Variable,
+                      EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
+                      &gEfiMemoryTypeInformationGuid,
+                      NULL,
+                      &DataSize,
+                      &MemoryData
+                      );
+  IndexNumber = sizeof (mDefaultMemoryTypeInformation) / sizeof (EFI_MEMORY_TYPE_INFORMATION);
+
+  //
+  // Accumulate maximum amount of memory needed
+  //
+
+  DEBUG((DEBUG_ERROR, "PEI_MIN_MEMORY_SIZE:%dKB \n", DivU64x32(*MemorySize,1024)));
+  DEBUG((DEBUG_ERROR, "IndexNumber:%d MemoryDataNumber%d \n", IndexNumber,DataSize/ sizeof (EFI_MEMORY_TYPE_INFORMATION)));
+  if (EFI_ERROR (Status)) {
+    //
+    // Start with minimum memory
+    //
+    for (Index = 0; Index < IndexNumber; Index++) {
+      DEBUG((DEBUG_ERROR, "Index[%d].Type = %d .NumberOfPages=0x%x\n", Index,mDefaultMemoryTypeInformation[Index].Type,mDefaultMemoryTypeInformation[Index].NumberOfPages));
+      *MemorySize += mDefaultMemoryTypeInformation[Index].NumberOfPages * EFI_PAGE_SIZE;
+    }
+    DEBUG((DEBUG_ERROR, "No memory type,  Total platform memory:%dKB \n", DivU64x32(*MemorySize,1024)));
+  } else {
+    //
+    // Start with at least 0x200 pages of memory for the DXE Core and the DXE Stack
+    //
+    for (Index = 0; Index < IndexNumber; Index++) {
+      DEBUG((DEBUG_ERROR, "Index[%d].Type = %d .NumberOfPages=0x%x\n", Index,MemoryData[Index].Type,MemoryData[Index].NumberOfPages));
+      *MemorySize += MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE;
+
+    }
+    DEBUG((DEBUG_ERROR, "has memory type,  Total platform memory:%dKB \n", DivU64x32(*MemorySize,1024)));
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+
+  This function checks the memory range in PEI.
+
+  @param PeiServices     Pointer to PEI Services.
+  @param This            Pei memory test PPI pointer.
+  @param BeginAddress    Beginning of the memory address to be checked.
+  @param MemoryLength    Bytes of memory range to be checked.
+  @param Operation       Type of memory check operation to be performed.
+  @param ErrorAddress    Return the address of the error memory address.
+
+  @retval EFI_SUCCESS         The operation completed successfully.
+  @retval EFI_DEVICE_ERROR    Memory test failed. It's not safe to use this range of memory.
+
+**/
+EFI_STATUS
+EFIAPI
+BaseMemoryTest (
+  IN  EFI_PEI_SERVICES                   **PeiServices,
+  IN  PEI_BASE_MEMORY_TEST_PPI           *This,
+  IN  EFI_PHYSICAL_ADDRESS               BeginAddress,
+  IN  UINT64                             MemoryLength,
+  IN  PEI_MEMORY_TEST_OP                 Operation,
+  OUT EFI_PHYSICAL_ADDRESS               *ErrorAddress
+  )
+{
+  UINT32                TestPattern;
+  UINT32                SpanSize;
+  EFI_PHYSICAL_ADDRESS  TempAddress;
+
+#define MEMORY_TEST_PATTERN     0x5A5A5A5A
+#define MEMORY_TEST_COVER_SPAN  0x40000
+
+  TestPattern = MEMORY_TEST_PATTERN;
+  SpanSize    = 0;
+
+  //
+  // Make sure we don't try and test anything above the max physical address range
+  //
+  ASSERT (BeginAddress + MemoryLength < MAX_ADDRESS);
+
+  switch (Operation) {
+  case Extensive:
+    SpanSize = 0x4;
+    break;
+
+  case Sparse:
+  case Quick:
+    SpanSize = MEMORY_TEST_COVER_SPAN;
+    break;
+
+  case Ignore:
+    goto Done;
+    break;
+  }
+  //
+  // Write the test pattern into memory range
+  //
+  TempAddress = BeginAddress;
+  while (TempAddress < BeginAddress + MemoryLength) {
+    (*(UINT32 *) (UINTN) TempAddress) = TestPattern;
+    TempAddress += SpanSize;
+  }
+  //
+  // Read pattern from memory and compare it
+  //
+  TempAddress = BeginAddress;
+  while (TempAddress < BeginAddress + MemoryLength) {
+    if ((*(UINT32 *) (UINTN) TempAddress) != TestPattern) {
+      *ErrorAddress = TempAddress;
+      return EFI_DEVICE_ERROR;
+    }
+
+    TempAddress += SpanSize;
+  }
+
+Done:
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Set Cache Mtrr.
+**/
+VOID
+SetCacheMtrr (
+  VOID
+  )
+{
+  EFI_STATUS                  Status;
+  EFI_PEI_HOB_POINTERS        Hob;
+  MTRR_SETTINGS               MtrrSetting;
+  UINT64                      MemoryBase;
+  UINT64                      MemoryLength;
+  UINT64                      LowMemoryLength;
+  UINT64                      HighMemoryLength;
+  EFI_BOOT_MODE               BootMode;
+  EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;
+  UINT64                      CacheMemoryLength;
+
+  ///
+  /// Reset all MTRR setting.
+  ///
+  ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS));
+
+  ///
+  /// Cache the Flash area as WP to boost performance
+  ///
+  Status = MtrrSetMemoryAttributeInMtrrSettings (
+                &MtrrSetting,
+                (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
+                (UINTN) PcdGet32 (PcdFlashAreaSize),
+                CacheWriteProtected
+                );
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Update MTRR setting from MTRR buffer for Flash Region to be WP to boost performance
+  ///
+  MtrrSetAllMtrrs (&MtrrSetting);
+
+  ///
+  /// Set low to 1 MB. Since 1MB cacheability will always be set
+  /// until override by CSM.
+  /// Initialize high memory to 0.
+  ///
+  LowMemoryLength   = 0x100000;
+  HighMemoryLength  = 0;
+  ResourceAttribute = (
+                       EFI_RESOURCE_ATTRIBUTE_PRESENT |
+                       EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+                       EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
+                       EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
+                       EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
+                       EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
+                       );
+
+  Status = PeiServicesGetBootMode (&BootMode);
+  ASSERT_EFI_ERROR (Status);
+
+  if (BootMode != BOOT_ON_S3_RESUME) {
+    ResourceAttribute |= EFI_RESOURCE_ATTRIBUTE_TESTED;
+  }
+
+  Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
+  while (!END_OF_HOB_LIST (Hob)) {
+    if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {
+      if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) ||
+          ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) &&
+           (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute))
+         ) {
+        if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000000ULL) {
+          HighMemoryLength += Hob.ResourceDescriptor->ResourceLength;
+        } else if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000) {
+          LowMemoryLength += Hob.ResourceDescriptor->ResourceLength;
+        }
+      }
+    }
+
+    Hob.Raw = GET_NEXT_HOB (Hob);
+  }
+
+  DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) = %lx.\n", LowMemoryLength));
+  DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) = %lx.\n", HighMemoryLength));
+
+  ///
+  /// Assume size of main memory is multiple of 256MB
+  ///
+  MemoryLength = (LowMemoryLength + 0xFFFFFFF) & 0xF0000000;
+  MemoryBase = 0;
+
+  CacheMemoryLength = MemoryLength;
+  ///
+  /// Programming MTRRs to avoid override SPI region with UC when MAX TOLUD Length >= 3.5GB
+  ///
+  if (MemoryLength > 0xDC000000) {
+     CacheMemoryLength = 0xC0000000;
+     Status = MtrrSetMemoryAttributeInMtrrSettings (
+                &MtrrSetting,
+                MemoryBase,
+                CacheMemoryLength,
+                CacheWriteBack
+                );
+     ASSERT_EFI_ERROR (Status);
+
+     MemoryBase = 0xC0000000;
+     CacheMemoryLength = MemoryLength - 0xC0000000;
+     if (MemoryLength > 0xE0000000) {
+        CacheMemoryLength = 0x20000000;
+        Status = MtrrSetMemoryAttributeInMtrrSettings (
+                 &MtrrSetting,
+                 MemoryBase,
+                 CacheMemoryLength,
+                 CacheWriteBack
+                 );
+        ASSERT_EFI_ERROR (Status);
+
+        MemoryBase = 0xE0000000;
+        CacheMemoryLength = MemoryLength - 0xE0000000;
+     }
+  }
+
+  Status = MtrrSetMemoryAttributeInMtrrSettings (
+                &MtrrSetting,
+                MemoryBase,
+                CacheMemoryLength,
+                CacheWriteBack
+                );
+  ASSERT_EFI_ERROR (Status);
+
+  if (LowMemoryLength != MemoryLength) {
+     MemoryBase = LowMemoryLength;
+     MemoryLength -= LowMemoryLength;
+     Status = MtrrSetMemoryAttributeInMtrrSettings (
+                   &MtrrSetting,
+                   MemoryBase,
+                   MemoryLength,
+                   CacheUncacheable
+                   );
+      ASSERT_EFI_ERROR (Status);
+  }
+
+  ///
+  /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC
+  ///
+  Status = MtrrSetMemoryAttributeInMtrrSettings (
+                &MtrrSetting,
+                0xA0000,
+                0x20000,
+                CacheUncacheable
+                );
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Update MTRR setting from MTRR buffer
+  ///
+  MtrrSetAllMtrrs (&MtrrSetting);
+
+  return ;
+}
+
+VOID
+ReportCpuHob (
+  VOID
+  )
+{
+  UINT8                         PhysicalAddressBits;
+  UINT32                        RegEax;
+
+  AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
+  if (RegEax >= 0x80000008) {
+    AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
+    PhysicalAddressBits = (UINT8) RegEax;
+  } else {
+    PhysicalAddressBits = 36;
+  }
+
+  ///
+  /// Create a CPU hand-off information
+  ///
+  BuildCpuHob (PhysicalAddressBits, 16);
+}
+
+/**
+  Install Firmware Volume Hob's once there is main memory
+
+  @param[in]  PeiServices       General purpose services available to every PEIM.
+  @param[in]  NotifyDescriptor  Notify that this module published.
+  @param[in]  Ppi               PPI that was installed.
+
+  @retval     EFI_SUCCESS       The function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotifyCallback (
+  IN CONST EFI_PEI_SERVICES     **PeiServices,
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
+  IN VOID                       *Ppi
+  )
+{
+  EFI_STATUS                    Status;
+  EFI_BOOT_MODE                 BootMode;
+
+  Status = BoardInitAfterMemoryInit ();
+  ASSERT_EFI_ERROR (Status);
+
+  Status = PeiServicesGetBootMode (&BootMode);
+  ASSERT_EFI_ERROR (Status);
+
+
+  ReportCpuHob ();
+
+  TestPointMemoryDiscoveredMtrrFunctional ();
+
+  TestPointMemoryDiscoveredMemoryResourceFunctional ();
+
+  ///
+  /// If S3 resume, then we are done
+  ///
+  if (BootMode == BOOT_ON_S3_RESUME) {
+    return EFI_SUCCESS;
+  }
+
+  TestPointMemoryDiscoveredDmaProtectionEnabled ();
+
+  if (PcdGetBool (PcdStopAfterMemInit)) {
+    CpuDeadLoop ();
+  }
+
+  return Status;
+}
+
+
+/**
+  This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced
+
+  @param[in]  PeiServices  Pointer to PEI Services Table.
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     others
+**/
+EFI_STATUS
+EFIAPI
+PlatformInitPreMem (
+  IN CONST EFI_PEI_SERVICES     **PeiServices
+  )
+{
+  EFI_STATUS                        Status;
+  EFI_BOOT_MODE                     BootMode;
+
+  //
+  // Start board detection
+  //
+  BoardDetect ();
+
+  BoardDebugInit ();
+
+  TestPointDebugInitDone ();
+
+  if (PcdGetBool (PcdStopAfterDebugInit)) {
+    CpuDeadLoop ();
+  }
+
+  BootMode = BoardBootModeDetect ();
+  Status = PeiServicesSetBootMode (BootMode);
+  ASSERT_EFI_ERROR (Status);
+  if (BootMode == BOOT_IN_RECOVERY_MODE) {
+    Status = PeiServicesInstallPpi (&mPpiListRecoveryBootMode);
+  }
+  ///
+  /// Signal possible dependent modules that there has been a
+  /// final boot mode determination, it is used to build BIST
+  /// Hob for Dxe use.
+  ///
+  Status = PeiServicesInstallPpi (&mPpiBootMode);
+  ASSERT_EFI_ERROR (Status);
+
+  BuildMemoryTypeInformation ();
+
+  if (!PcdGetBool(PcdFspWrapperBootMode)) {
+    Status = PeiServicesInstallPpi (mMemPpiList);
+    ASSERT_EFI_ERROR (Status);
+  }
+
+  Status = BoardInitBeforeMemoryInit ();
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
+
+
+/**
+  Platform Init before memory PEI module entry point
+
+  @param[in]  FileHandle           Not used.
+  @param[in]  PeiServices          General purpose services available to every PEIM.
+
+  @retval     EFI_SUCCESS          The function completes successfully
+  @retval     EFI_OUT_OF_RESOURCES Insufficient resources to create database
+**/
+EFI_STATUS
+EFIAPI
+PlatformInitPreMemEntryPoint (
+  IN       EFI_PEI_FILE_HANDLE  FileHandle,
+  IN CONST EFI_PEI_SERVICES     **PeiServices
+  )
+{
+  EFI_STATUS Status;
+
+  Status = PlatformInitPreMem (PeiServices);
+
+  ///
+  /// After code reorangized, memorycallback will run because the PPI is already
+  /// installed when code run to here, it is supposed that the InstallEfiMemory is
+  /// done before.
+  ///
+  Status = PeiServicesNotifyPpi (&mMemDiscoveredNotifyList);
+
+  return Status;
+}
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
new file mode 100644
index 0000000000..76dd67d1a8
--- /dev/null
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
@@ -0,0 +1,67 @@
+### @file
+# Component information file for the Platform Init Pre-Memory PEI module.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = PlatformInitPreMem
+  FILE_GUID                      = EEEE611D-F78F-4FB9-B868-55907F169280
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = PEIM
+  ENTRY_POINT                    = PlatformInitPreMemEntryPoint
+
+[LibraryClasses]
+  BaseMemoryLib
+  BoardInitLib
+  DebugLib
+  HobLib
+  IoLib
+  MemoryAllocationLib
+  MtrrLib
+  PeimEntryPoint
+  PeiServicesLib
+  ReportFvLib
+  TestPointCheckLib
+  TimerLib
+
+[Packages]
+  MinPlatformPkg/MinPlatformPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[Pcd]
+  gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode          ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress        ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize               ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit          ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit            ## CONSUMES
+
+[FixedPcd]
+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize  ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize      ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize     ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize       ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize       ## CONSUMES
+
+[Sources]
+  PlatformInitPreMem.c
+
+[Ppis]
+  gEfiPeiMemoryDiscoveredPpiGuid
+  gEfiPeiMasterBootModePpiGuid                  ## PRODUCES
+  gEfiPeiBootInRecoveryModePpiGuid              ## PRODUCES
+  gEfiPeiReadOnlyVariable2PpiGuid
+  gPeiBaseMemoryTestPpiGuid
+  gPeiPlatformMemorySizePpiGuid
+
+[Guids]
+  gEfiMemoryTypeInformationGuid
+
+[Depex]
+  gEfiPeiReadOnlyVariable2PpiGuid
-- 
2.19.1.windows.1


^ permalink raw reply related	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2019-06-28 20:56 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-06-14 20:00 [edk2-platforms][PATCH] ClevoOpenBoardPkg: Added OS boot support Agyeman, Prince
2019-06-25 22:16 ` [edk2-devel] " Sinha, Ankit
2019-06-28 20:56 ` Nate DeSimone

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