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Received: from DM6PR12MB3163.namprd12.prod.outlook.com (20.179.71.154) by DM6PR12MB3930.namprd12.prod.outlook.com (10.255.174.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2686.29; Tue, 4 Feb 2020 23:02:25 +0000 Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::a0cd:463:f444:c270]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::a0cd:463:f444:c270%7]) with mapi id 15.20.2707.020; Tue, 4 Feb 2020 23:02:25 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [PATCH v4 22/40] UefiCpuPkg/CpuExceptionHandler: Add support for DR7 Read/Write NAE events Date: Tue, 4 Feb 2020 17:01:26 -0600 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-ClientProxiedBy: SN6PR16CA0062.namprd16.prod.outlook.com (2603:10b6:805:ca::39) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) Return-Path: thomas.lendacky@amd.com MIME-Version: 1.0 Received: from tlendack-t1.amd.com (165.204.77.1) by SN6PR16CA0062.namprd16.prod.outlook.com (2603:10b6:805:ca::39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2686.32 via Frontend Transport; Tue, 4 Feb 2020 23:02:24 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 6dd3ebcb-a132-4f3f-1b76-08d7a9c64c7a X-MS-TrafficTypeDiagnostic: DM6PR12MB3930:|DM6PR12MB3930: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-Forefront-PRVS: 03030B9493 X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10009020)(4636009)(39860400002)(366004)(376002)(136003)(396003)(346002)(199004)(189003)(4326008)(478600001)(6916009)(81156014)(2616005)(956004)(81166006)(8676002)(966005)(316002)(54906003)(19627235002)(2906002)(6486002)(66476007)(66556008)(52116002)(7696005)(186003)(26005)(16526019)(5660300002)(86362001)(36756003)(66946007)(8936002);DIR:OUT;SFP:1101;SCL:1;SRVR:DM6PR12MB3930;H:DM6PR12MB3163.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: IlRjHvg8+CMNLXB/U9mme9PI5yhbC75wKXLLIheHMDhuvqu6FQZFqTpmmfWvRtVkDKxsUHRgbLN39nxjPU4UxgFRtudO1rfKjJ8268fPuHhFfN8RTmpwXXrJuevs8Da4i6wNaJwanVGZCmIE5obJghQLY5+Hu8/eHL2GhhEN91luWh5PM2ykwDHkg0Ol3i0N7DB+cHAC/oVAPdd/KOocW2+Lx5agjfZTYIX8JlkAQ41vy95yAziAF+BoTX7vE/zBG4E2fgK8aWNltUQyy+Dh8FMRxxo6iux7PJQIWAD/S+9uVN/pMcnOERx1lC++SPnpAtC9t+DCymdq7xrSjaJwHAULfPbXSZ3rC761WZs0LnTz7GZbeSray6CZHh2XLY6bS34ZZlfYtLej2D2MNhoMVP2fGaJhkBwnaNBTLR2Ob1VHGvr0mXnlfhzry3pdWygFWo0LtQeb6sdQVgp9voOarHHjWEX+ICMnm/SvaKH+RJgz42aZdCsFRYA3slwCTRcLXeuQjYjnZYCSss/0P0jlmQ== X-MS-Exchange-AntiSpam-MessageData: aJERay7EBoZV4fO/WusI2LSeKTlTXYkQimYBbDVbEPjdtTSzJxkveJnAv0anUTGp2hWIZHpvvfk08mV5aCKPHJpRJYZOpNoD0DqWqF+d53Cf+vII/42GV5EFV4bgsnTihnAhWuORfCSsVaM2jHhyvw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6dd3ebcb-a132-4f3f-1b76-08d7a9c64c7a X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2020 23:02:25.2561 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: z4B9eJUzPBsPjdHWcDtlYVOmt6d0RqkGcDjE6q1hwp9cqTa3CjwxeN2GS9wdU6x/1AeFvsgyhkd3H136kJ6+dw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3930 Content-Type: text/plain BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 Under SEV-ES, a DR7 read or write intercept generates a #VC exception. The #VC handler must provide special support to the guest for this. On a DR7 write, the #VC handler must cache the value and issue a VMGEXIT to notify the hypervisor of the write. However, the #VC handler must not actually set the value of the DR7 register. On a DR7 read, the #VC handler must return the cached value of the DR7 register to the guest. VMGEXIT is not invoked for a DR7 register read. To avoid exception recursion, a #VC exception will not try to read and push the actual debug registers into the EFI_SYSTEM_CONTEXT_X64 struct and instead push zeroes. The #VC exception handler does not make use of the debug registers from saved context. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/AMDSevVcCommon.c | 68 +++++++++++++++++++ .../X64/ExceptionHandlerAsm.nasm | 17 +++++ 2 files changed, 85 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c index 4318014ceb45..2932e7341345 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c @@ -13,6 +13,12 @@ #define CR4_OSXSAVE (1 << 18) +#define DR7_RESET_VALUE 0x400 +typedef struct { + BOOLEAN Dr7Cached; + UINT64 Dr7; +} SEV_ES_PER_CPU_DATA; + typedef enum { LongMode64Bit = 0, LongModeCompat32Bit, @@ -1076,6 +1082,60 @@ RdtscExit ( return 0; } +STATIC +UINT64 +Dr7WriteExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_OPCODE_EXT *Ext = &InstructionData->Ext; + SEV_ES_PER_CPU_DATA *SevEsData = (SEV_ES_PER_CPU_DATA *) (Ghcb + 1); + INTN *Register; + UINT64 Status; + + DecodeModRm (Regs, InstructionData); + + /* MOV DRn always treats MOD == 3 no matter how encoded */ + Register = GetRegisterPointer (Regs, Ext->ModRm.Rm); + + /* Using a value of 0 for ExitInfo1 means RAX holds the value */ + Ghcb->SaveArea.Rax = *Register; + GhcbSetRegValid (Ghcb, GhcbRax); + + Status = VmgExit (Ghcb, SvmExitDr7Write, 0, 0); + if (Status) { + return Status; + } + + SevEsData->Dr7 = *Register; + SevEsData->Dr7Cached = TRUE; + + return 0; +} + +STATIC +UINT64 +Dr7ReadExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_OPCODE_EXT *Ext = &InstructionData->Ext; + SEV_ES_PER_CPU_DATA *SevEsData = (SEV_ES_PER_CPU_DATA *) (Ghcb + 1); + INTN *Register; + + DecodeModRm (Regs, InstructionData); + + /* MOV DRn always treats MOD == 3 no matter how encoded */ + Register = GetRegisterPointer (Regs, Ext->ModRm.Rm); + *Register = (SevEsData->Dr7Cached) ? SevEsData->Dr7 : DR7_RESET_VALUE; + + return 0; +} + UINTN DoVcCommon ( GHCB *Ghcb, @@ -1092,6 +1152,14 @@ DoVcCommon ( ExitCode = Regs->ExceptionData; switch (ExitCode) { + case SvmExitDr7Read: + NaeExit = Dr7ReadExit; + break; + + case SvmExitDr7Write: + NaeExit = Dr7WriteExit; + break; + case SvmExitRdtsc: NaeExit = RdtscExit; break; diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm index 19198f273137..26cae56cc5cf 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm @@ -18,6 +18,8 @@ ; CommonExceptionHandler() ; +%define VC_EXCEPTION 29 + extern ASM_PFX(mErrorCodeFlag) ; Error code flags for exceptions extern ASM_PFX(mDoFarReturnFlag) ; Do far return flag extern ASM_PFX(CommonExceptionHandler) @@ -225,6 +227,9 @@ HasErrorCode: push rax ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; + cmp qword [rbp + 8], VC_EXCEPTION + je VcDebugRegs ; For SEV-ES (#VC) Debug registers ignored + mov rax, dr7 push rax mov rax, dr6 @@ -237,7 +242,19 @@ HasErrorCode: push rax mov rax, dr0 push rax + jmp DrFinish +VcDebugRegs: +;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7 are skipped for #VC to avoid exception recursion + xor rax, rax + push rax + push rax + push rax + push rax + push rax + push rax + +DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; sub rsp, 512 mov rdi, rsp -- 2.17.1