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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT004.mail.protection.outlook.com (10.13.176.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5901.14 via Frontend Transport; Tue, 6 Dec 2022 13:23:56 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 6 Dec 2022 07:23:56 -0600 Received: from BLR-LAB-SFW01.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Tue, 6 Dec 2022 07:23:54 -0600 From: "Abdul Lateef Attar" To: CC: Abdul Lateef Attar , Paul Grimes , Garrett Kirkendall , "Abner Chang" , Eric Dong , Ray Ni , Rahul Kumar Subject: [PATCH v1 5/5] UefiCpuPkg/AmdSmmCpuFeaturesLib: Handles S3 save state Date: Tue, 6 Dec 2022 18:53:18 +0530 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Return-Path: AbdulLateef.Attar@amd.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT004:EE_|DM4PR12MB5889:EE_ X-MS-Office365-Filtering-Correlation-Id: 528d72a2-a71f-4e52-e45e-08dad78d20e8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Dec 2022 13:23:56.8528 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 528d72a2-a71f-4e52-e45e-08dad78d20e8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT004.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5889 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Abdul Lateef Attar BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4182 Handles S3 save state restore condition. Implements SmmCpuFeaturesCompleteSmmReadyToLock() to sync all processor and update S3 resume entry point. Cc: Paul Grimes Cc: Garrett Kirkendall Cc: Abner Chang Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Abdul Lateef Attar --- .../AmdSmmCpuFeaturesLib.inf | 1 + .../SmmCpuFeaturesLib/Amd/SmramSaveState.h | 19 +++++++++++ .../SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c | 32 +++++++++++++++++++ 3 files changed, 52 insertions(+) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf = b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf index 95eb31d16ead..7fd559e91ad8 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf @@ -27,6 +27,7 @@ [Sources] [Packages]=0D MdePkg/MdePkg.dec=0D UefiCpuPkg/UefiCpuPkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D =0D [LibraryClasses]=0D BaseLib=0D diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h b/Ue= fiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h index 290ebdbc9227..474a5dbd9765 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmramSaveState.h @@ -17,6 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =0D #include =0D #include =0D +#include =0D =0D // EFER register LMA bit=0D #define LMA BIT10=0D @@ -106,4 +107,22 @@ InternalSmmCpuFeaturesWriteSaveStateRegister ( IN CONST VOID *Buffer=0D );=0D =0D +/**=0D + Initialize MP synchronization data.=0D +**/=0D +VOID=0D +EFIAPI=0D +InitializeMpSyncData (=0D + VOID=0D + );=0D +=0D +/**=0D + Perform SMM MP sync Semaphores re-initialization in the S3 boot path.=0D +**/=0D +VOID=0D +EFIAPI=0D +SmmS3MpSemaphoreInit (=0D + VOID=0D + );=0D +=0D #endif=0D diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c b= /UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c index 10bed4116397..b855573d9401 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Amd/SmmCpuFeaturesLib.c @@ -14,6 +14,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // The mode of the CPU at the time an SMI occurs=0D extern UINT8 mSmmSaveStateRegisterLma;=0D =0D +// SMM S3 resume state Ptr=0D +extern SMM_S3_RESUME_STATE *mSmmS3ResumeState;=0D +=0D /**=0D Read an SMM Save State register on the target processor. If this functi= on=0D returns EFI_UNSUPPORTED, then the caller is responsible for reading the= =0D @@ -441,4 +444,33 @@ SmmCpuFeaturesCompleteSmmReadyToLock ( VOID=0D )=0D {=0D + if (mSmmS3ResumeState !=3D NULL ) {=0D + mSmmS3ResumeState->SmmS3ResumeEntryPoint =3D (EFI_PHYSICAL_ADDRESS)(UI= NTN)SmmS3MpSemaphoreInit;=0D + }=0D +}=0D +=0D +/**=0D + Perform SMM MP sync Semaphores re-initialization in the S3 boot path.=0D +**/=0D +VOID=0D +EFIAPI=0D +SmmS3MpSemaphoreInit (=0D + VOID=0D + )=0D +{=0D + InitializeMpSyncData ();=0D +=0D + DEBUG ((DEBUG_INFO, "SMM S3 Return CS =3D %x\n", mSmmS3Re= sumeState->ReturnCs));=0D + DEBUG ((DEBUG_INFO, "SMM S3 Return Entry Point =3D %x\n", mSmmS3Re= sumeState->ReturnEntryPoint));=0D + DEBUG ((DEBUG_INFO, "SMM S3 Return Context1 =3D %x\n", mSmmS3Re= sumeState->ReturnContext1));=0D + DEBUG ((DEBUG_INFO, "SMM S3 Return Context2 =3D %x\n", mSmmS3Re= sumeState->ReturnContext2));=0D + DEBUG ((DEBUG_INFO, "SMM S3 Return Stack Pointer =3D %x\n", mSmmS3Re= sumeState->ReturnStackPointer));=0D +=0D + AsmDisablePaging64 (=0D + mSmmS3ResumeState->ReturnCs,=0D + (UINT32)mSmmS3ResumeState->ReturnEntryPoint,=0D + (UINT32)mSmmS3ResumeState->ReturnContext1,=0D + (UINT32)mSmmS3ResumeState->ReturnContext2,=0D + (UINT32)mSmmS3ResumeState->ReturnStackPointer=0D + );=0D }=0D --=20 2.25.1