* [edk2-devel] [PATCH edk2-platforms v4 1/6] SbsaQemu: get the information of CPU topology via SMC calls
2024-07-10 17:52 [edk2-devel] [PATCH edk2-platforms v4 0/6] SbsaQemu: Align the PPTT tables with QEMU Marcin Juszkiewicz
@ 2024-07-10 17:52 ` Marcin Juszkiewicz
2024-07-10 17:52 ` [edk2-devel] [PATCH edk2-platforms v4 2/6] SbsaQemu: align the PPTT tables with QEMU Marcin Juszkiewicz
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Marcin Juszkiewicz @ 2024-07-10 17:52 UTC (permalink / raw)
To: devel
Cc: Xiong Yining, Marcin Juszkiewicz, Leif Lindholm, Ard Biesheuvel,
Graeme Gregory, Chen Baozi, Jonathan Cameron
Provide functions to check for CPU topology information:
- the number of sockets on sbsa-ref platform.
- the number of clusters in one socket.
- the number of cores in one cluster.
- the number of threads in one core.
As SMC calls can return up to 4 return values, the number of sockets,
clusters and cores are read from TF-A using platform specific SMC call.
Number of threads is caluculated using the cpu count and the number of
sockets, clusters and cores.
Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn>
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
.../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h | 1 +
.../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h | 26 ++++++++++++++
.../SbsaQemuHardwareInfoLib.c | 36 ++++++++++++++++++++
3 files changed, 63 insertions(+)
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
index af6b120561ad..b57573735ace 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h
@@ -16,6 +16,7 @@
#define SIP_SVC_GET_GIC_ITS SMC_SIP_FUNCTION_ID(101)
#define SIP_SVC_GET_CPU_COUNT SMC_SIP_FUNCTION_ID(200)
#define SIP_SVC_GET_CPU_NODE SMC_SIP_FUNCTION_ID(201)
+#define SIP_SVC_GET_CPU_TOPOLOGY SMC_SIP_FUNCTION_ID(202)
#define SIP_SVC_GET_MEMORY_NODE_COUNT SMC_SIP_FUNCTION_ID(300)
#define SIP_SVC_GET_MEMORY_NODE SMC_SIP_FUNCTION_ID(301)
diff --git a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
index e5076274fa0a..7e0bd962f8a9 100644
--- a/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
+++ b/Silicon/Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h
@@ -15,6 +15,19 @@ typedef struct {
UINT64 AddressSize;
} MemoryInfo;
+/**
+ Sockets: the number of sockets on sbsa-ref platform.
+ Clusters: the number of clusters in one socket.
+ Cores: the number of cores in one cluster.
+ Threads: the number of threads in one core.
+**/
+typedef struct {
+ UINT32 Sockets;
+ UINT32 Clusters;
+ UINT32 Cores;
+ UINT32 Threads;
+} CpuTopology;
+
/**
Get CPU count from information passed by Qemu.
@@ -83,4 +96,17 @@ GetNumaNodeCount (
VOID
);
+/**
+ Get cpu topology (sockets, clusters, cores, threads) from TF-A.
+
+ @param [out] CpuTopo A pointer to the cpu topology.
+
+
+ @retval the information of cpu topology.
+**/
+VOID
+GetCpuTopology (
+ OUT CpuTopology *CpuTopo
+ );
+
#endif /* HARDWARE_INFO_LIB */
diff --git a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
index 596a3453c70f..a2ea8a523625 100644
--- a/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
+++ b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c
@@ -181,3 +181,39 @@ GetNumaNodeCount (
return NumberNumaNodes;
}
+
+/**
+ Get CPU topology.
+**/
+VOID
+GetCpuTopology (
+ OUT CpuTopology *CpuTopo
+ )
+{
+ UINTN SmcResult;
+ UINTN Arg0;
+ UINTN Arg1;
+ UINTN Arg2;
+ UINT32 NumCores = GetCpuCount ();
+
+ SmcResult = ArmCallSmc0 (SIP_SVC_GET_CPU_TOPOLOGY, &Arg0, &Arg1, &Arg2);
+ if (SmcResult != SMC_SIP_CALL_SUCCESS) {
+ DEBUG ((DEBUG_ERROR, "%a: SIP_SVC_GET_CPU_TOPOLOGY call failed. We have no cpu topology information.\n", __FUNCTION__));
+ ResetShutdown ();
+ } else {
+ CpuTopo->Sockets = Arg0;
+ CpuTopo->Clusters = Arg1;
+ CpuTopo->Cores = Arg2;
+ CpuTopo->Threads = NumCores / (CpuTopo->Sockets * CpuTopo->Clusters * CpuTopo->Cores);
+ }
+
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: CPU Topology: sockets: %d, clusters: %d, cores: %d, threads: %d\n",
+ __FUNCTION__,
+ CpuTopo->Sockets,
+ CpuTopo->Clusters,
+ CpuTopo->Cores,
+ CpuTopo->Threads
+ ));
+}
--
2.45.2
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^ permalink raw reply related [flat|nested] 8+ messages in thread* [edk2-devel] [PATCH edk2-platforms v4 2/6] SbsaQemu: align the PPTT tables with QEMU
2024-07-10 17:52 [edk2-devel] [PATCH edk2-platforms v4 0/6] SbsaQemu: Align the PPTT tables with QEMU Marcin Juszkiewicz
2024-07-10 17:52 ` [edk2-devel] [PATCH edk2-platforms v4 1/6] SbsaQemu: get the information of CPU topology via SMC calls Marcin Juszkiewicz
@ 2024-07-10 17:52 ` Marcin Juszkiewicz
2024-07-10 17:52 ` [edk2-devel] [PATCH edk2-platforms v4 3/6] SbsaQemu: update PPTT to ACPI 6.5 Marcin Juszkiewicz
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Marcin Juszkiewicz @ 2024-07-10 17:52 UTC (permalink / raw)
To: devel
Cc: Xiong Yining, Marcin Juszkiewicz, Leif Lindholm, Ard Biesheuvel,
Graeme Gregory, Chen Baozi, Jonathan Cameron
From: Xiong Yining <xiongyining1480@phytium.com.cn>
To align the CPU topology information recognized by the operating system
with the CPU topology information configured by QEMU, we need to make
use of the CPU topology information to create complex PPTT tables
setups.
We can get the CPU topology information via SMC.
Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn>
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 11 ++
.../Include/IndustryStandard/SbsaQemuAcpi.h | 32 ----
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 195 ++++++++++++++++----
3 files changed, 166 insertions(+), 72 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
index e5f0748bb16e..085c681ba55f 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
@@ -88,4 +88,15 @@ typedef struct {
ClockDomain /* Clock Domain */ \
}
+#define SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT(Flags, Parent, ACPIProcessorID, NumberOfPrivateResources) \
+ { \
+ EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, /* Type */ \
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources * sizeof (UINT32), /* Length */ \
+ { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, /* Reserved */ \
+ Flags, /* Flags */ \
+ Parent, /* Parent */ \
+ ACPIProcessorID, /* ACPI Processor ID */ \
+ NumberOfPrivateResources /* Number of private resources */ \
+ }
+
#endif
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index ae151210c2c6..2f87591e737a 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -166,36 +166,4 @@ typedef struct {
64 /* LineSize */ \
}
-#define SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT { \
- EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR), \
- { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
- { \
- EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, /* PhysicalPackage */ \
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, /* AcpiProcessorIdValid */ \
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \
- EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, /* Not Leaf */ \
- EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ \
- }, \
- 0, /* Parent */ \
- 0, /* AcpiProcessorId */ \
- 0, /* NumberOfPrivateResources */ \
- }
-
-#define SBSAQEMU_ACPI_PPTT_CORE_STRUCT { \
- EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, \
- (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + (2 * sizeof (UINT32))), \
- { EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
- { \
- EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, /* PhysicalPackage */ \
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, /* AcpiProcessorValid */ \
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, /* Is not a Thread */ \
- EFI_ACPI_6_3_PPTT_NODE_IS_LEAF, /* Leaf */ \
- EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL, /* Identical Cores */ \
- }, \
- 0, /* Parent */ \
- 0, /* AcpiProcessorId */ \
- 2, /* NumberOfPrivateResources */ \
- }
-
#endif
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index e0eef54ff907..48cec24721d6 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -505,14 +505,61 @@ AddPpttTable (
EFI_PHYSICAL_ADDRESS PageAddress;
UINT8 *New;
UINT32 CpuId;
- UINT32 NumCores = GetCpuCount ();
+ CpuTopology CpuTopo;
+ UINT32 SocketIndex;
+ UINT32 ClusterIndex;
+ UINT32 CoreIndex;
+ UINT32 ThreadIndex;
+ UINT32 SocketOffset;
+ UINT32 ClusterOffset;
+ UINT32 CoreOffset;
+ UINT32 L1DCacheOffset;
+ UINT32 L1ICacheOffset;
+ UINT32 L2CacheOffset;
+
+ GetCpuTopology (&CpuTopo);
EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PPTT_CLUSTER_STRUCT;
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PPTT_CORE_STRUCT;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS SocketFlags = {
+ EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ };
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS ClusterFlags = {
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ };
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS CoreFlags = {
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ };
+
+ if (CpuTopo.Threads > 1) {
+ // The Thread structure is the leaf structure, adjust the value of CoreFlags.
+ CoreFlags.AcpiProcessorIdValid = EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID;
+ CoreFlags.NodeIsALeaf = EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF;
+ }
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS ThreadFlags = {
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD,
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ };
EFI_ACPI_DESCRIPTION_HEADER Header =
SBSAQEMU_ACPI_HEADER (
@@ -522,10 +569,16 @@ AddPpttTable (
);
TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
- (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3) +
- (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) * NumCores) +
- (sizeof (UINT32) * 2 * NumCores);
+ CpuTopo.Sockets * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
+ CpuTopo.Clusters * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3 +
+ CpuTopo.Cores * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
+ sizeof (UINT32) * 2)));
+
+ if (CpuTopo.Threads > 1) {
+ TableSize += CpuTopo.Sockets * CpuTopo.Clusters * CpuTopo.Cores * CpuTopo.Threads *
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ }
Status = gBS->AllocatePages (
AllocateAnyPages,
@@ -546,39 +599,101 @@ AddPpttTable (
((EFI_ACPI_DESCRIPTION_HEADER *)New)->Length = TableSize;
New += sizeof (EFI_ACPI_DESCRIPTION_HEADER);
- // Add the Cluster PPTT structure
- CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
-
- // Add L1 D Cache structure
- CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2_CACHE_INDEX;
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
-
- // Add L1 I Cache structure
- CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2_CACHE_INDEX;
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
-
- // Add L2 Cache structure
- CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = 0; /* L2 is LLC */
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
-
- for (CpuId = 0; CpuId < NumCores; CpuId++) {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *CorePtr;
- UINT32 *PrivateResourcePtr;
-
- CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
- CorePtr = (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *)New;
- CorePtr->Parent = CLUSTER_INDEX;
- CorePtr->AcpiProcessorId = CpuId;
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
-
- PrivateResourcePtr = (UINT32 *)New;
- PrivateResourcePtr[0] = L1_D_CACHE_INDEX;
- PrivateResourcePtr[1] = L1_I_CACHE_INDEX;
- New += (2 * sizeof (UINT32));
+ CpuId = 0;
+
+ SocketOffset = sizeof (EFI_ACPI_DESCRIPTION_HEADER);
+ for (SocketIndex = 0; SocketIndex < CpuTopo.Sockets; SocketIndex++) {
+ // Add the Socket PPTT structure
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Socket = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ SocketFlags,
+ 0,
+ 0,
+ 0
+ );
+ CopyMem (New, &Socket, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+
+ ClusterOffset = SocketOffset + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ for (ClusterIndex = 0; ClusterIndex < CpuTopo.Clusters; ClusterIndex++) {
+ L1DCacheOffset = ClusterOffset + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ L1ICacheOffset = L1DCacheOffset + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+ L2CacheOffset = L1ICacheOffset + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+ CoreOffset = L2CacheOffset + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+
+ // Add the Cluster PPTT structure
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ ClusterFlags,
+ SocketOffset,
+ 0,
+ 0
+ );
+ CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+
+ // Add L1 D Cache structure
+ CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+
+ // Add L1 I Cache structure
+ CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+
+ // Add L2 Cache structure
+ CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+
+ for (CoreIndex = 0; CoreIndex < CpuTopo.Cores; CoreIndex++) {
+ UINT32 *PrivateResourcePtr;
+ UINT32 CoreCpuId;
+
+ if (CpuTopo.Threads == 1) {
+ CoreCpuId = CpuId;
+ } else {
+ CoreCpuId = 0;
+ }
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ CoreFlags,
+ ClusterOffset,
+ CoreCpuId,
+ 2
+ );
+ CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+
+ PrivateResourcePtr = (UINT32 *)New;
+ PrivateResourcePtr[0] = L1DCacheOffset;
+ PrivateResourcePtr[1] = L1ICacheOffset;
+ New += (2 * sizeof (UINT32));
+
+ if (CpuTopo.Threads == 1) {
+ CpuId++;
+ } else {
+ // Add the Thread PPTT structure
+ for (ThreadIndex = 0; ThreadIndex < CpuTopo.Threads; ThreadIndex++) {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ ThreadFlags,
+ CoreOffset,
+ CpuId,
+ 0
+ );
+ CopyMem (New, &Thread, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ CpuId++;
+ }
+
+ CoreOffset += CpuTopo.Threads * sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ }
+
+ CoreOffset += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
+ }
+
+ ClusterOffset = CoreOffset;
+ }
+
+ SocketOffset = ClusterOffset;
}
// Perform Checksum
--
2.45.2
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^ permalink raw reply related [flat|nested] 8+ messages in thread* [edk2-devel] [PATCH edk2-platforms v4 3/6] SbsaQemu: update PPTT to ACPI 6.5
2024-07-10 17:52 [edk2-devel] [PATCH edk2-platforms v4 0/6] SbsaQemu: Align the PPTT tables with QEMU Marcin Juszkiewicz
2024-07-10 17:52 ` [edk2-devel] [PATCH edk2-platforms v4 1/6] SbsaQemu: get the information of CPU topology via SMC calls Marcin Juszkiewicz
2024-07-10 17:52 ` [edk2-devel] [PATCH edk2-platforms v4 2/6] SbsaQemu: align the PPTT tables with QEMU Marcin Juszkiewicz
@ 2024-07-10 17:52 ` Marcin Juszkiewicz
2024-07-10 17:52 ` [edk2-devel] [PATCH edk2-platforms v4 4/6] SbsaQemu: provide cache info per core in PPTT Marcin Juszkiewicz
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Marcin Juszkiewicz @ 2024-07-10 17:52 UTC (permalink / raw)
To: devel
Cc: Xiong Yining, Marcin Juszkiewicz, Leif Lindholm, Ard Biesheuvel,
Graeme Gregory, Chen Baozi, Jonathan Cameron
ACPI 6.5 is the newest version of specification so far. The only
functional change to make is handling of CacheId (has to be unique and
higher than zero).
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 4 +-
.../Include/IndustryStandard/SbsaQemuAcpi.h | 46 ++++---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 129 ++++++++++----------
3 files changed, 95 insertions(+), 84 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
index 085c681ba55f..5aaf02e3ca30 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h
@@ -90,8 +90,8 @@ typedef struct {
#define SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT(Flags, Parent, ACPIProcessorID, NumberOfPrivateResources) \
{ \
- EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, /* Type */ \
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources * sizeof (UINT32), /* Length */ \
+ EFI_ACPI_6_5_PPTT_TYPE_PROCESSOR, /* Type */ \
+ sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + NumberOfPrivateResources * sizeof (UINT32), /* Length */ \
{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, /* Reserved */ \
Flags, /* Flags */ \
Parent, /* Parent */ \
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index 2f87591e737a..fa2e2b30bb7d 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -87,13 +87,13 @@ typedef struct {
#define SBSAQEMU_L2_CACHE_ASSC 8
#define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER))
-#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR))
-#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
-#define L2_CACHE_INDEX (L1_I_CACHE_INDEX + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE))
+#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR))
+#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
+#define L2_CACHE_INDEX (L1_I_CACHE_INDEX + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
#define SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT { \
- EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
+ EFI_ACPI_6_5_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE), \
{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
{ \
1, /* SizePropertyValid */ \
@@ -103,22 +103,24 @@ typedef struct {
1, /* CacheTypeValid */ \
1, /* WritePolicyValid */ \
1, /* LineSizeValid */ \
+ 1, /* CacheIdValid */ \
}, \
0, /* NextLevelOfCache */ \
SBSAQEMU_L1_D_CACHE_SIZE, /* Size */ \
SBSAQEMU_L1_D_CACHE_SETS, /* NumberOfSets */ \
SBSAQEMU_L1_D_CACHE_ASSC, /* Associativity */ \
{ \
- EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
- EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
- EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
+ EFI_ACPI_6_5_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
}, \
- 64 /* LineSize */ \
+ 64, /* LineSize */ \
+ 0 /* CacheId */ \
}
#define SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT { \
- EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
+ EFI_ACPI_6_5_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE), \
{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
{ \
1, /* SizePropertyValid */ \
@@ -128,22 +130,24 @@ typedef struct {
1, /* CacheTypeValid */ \
1, /* WritePolicyValid */ \
1, /* LineSizeValid */ \
+ 1, /* CacheIdValid */ \
}, \
0, /* NextLevelOfCache */ \
SBSAQEMU_L1_I_CACHE_SIZE, /* Size */ \
SBSAQEMU_L1_I_CACHE_SETS, /* NumberOfSets */ \
SBSAQEMU_L1_I_CACHE_ASSC, /* Associativity */ \
{ \
- EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, \
- EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
+ EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ, \
+ EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
0, \
}, \
- 64 /* LineSize */ \
+ 64, /* LineSize */ \
+ 0 /* CacheId */ \
}
#define SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT { \
- EFI_ACPI_6_3_PPTT_TYPE_CACHE, \
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), \
+ EFI_ACPI_6_5_PPTT_TYPE_CACHE, \
+ sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE), \
{ EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE }, \
{ \
1, /* SizePropertyValid */ \
@@ -153,17 +157,19 @@ typedef struct {
1, /* CacheTypeValid */ \
1, /* WritePolicyValid */ \
1, /* LineSizeValid */ \
+ 1, /* CacheIdValid */ \
}, \
0, /* NextLevelOfCache */ \
SBSAQEMU_L2_CACHE_SIZE, /* Size */ \
SBSAQEMU_L2_CACHE_SETS, /* NumberOfSets */ \
SBSAQEMU_L2_CACHE_ASSC, /* Associativity */ \
{ \
- EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
- EFI_ACPI_6_2_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
- EFI_ACPI_6_2_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
+ EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
+ EFI_ACPI_6_5_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK, \
}, \
- 64 /* LineSize */ \
+ 64, /* LineSize */ \
+ 0 /* CacheId */ \
}
#endif
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 48cec24721d6..8770b2293b92 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -516,35 +516,36 @@ AddPpttTable (
UINT32 L1DCacheOffset;
UINT32 L1ICacheOffset;
UINT32 L2CacheOffset;
+ UINT32 CacheId;
GetCpuTopology (&CpuTopo);
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
+ EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
+ EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
+ EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS SocketFlags = {
- EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL,
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
- EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
- EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS SocketFlags = {
+ EFI_ACPI_6_5_PPTT_PACKAGE_PHYSICAL,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF,
+ EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
};
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS ClusterFlags = {
- EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID,
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
- EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF,
- EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS ClusterFlags = {
+ EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF,
+ EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
};
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS CoreFlags = {
- EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD,
- EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
- EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS CoreFlags = {
+ EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
};
if (CpuTopo.Threads > 1) {
@@ -553,31 +554,31 @@ AddPpttTable (
CoreFlags.NodeIsALeaf = EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF;
}
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_FLAGS ThreadFlags = {
- EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL,
- EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID,
- EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD,
- EFI_ACPI_6_3_PPTT_NODE_IS_LEAF,
- EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS ThreadFlags = {
+ EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_IS_THREAD,
+ EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
};
EFI_ACPI_DESCRIPTION_HEADER Header =
SBSAQEMU_ACPI_HEADER (
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
EFI_ACPI_DESCRIPTION_HEADER,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
);
TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
- CpuTopo.Sockets * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
- CpuTopo.Clusters * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) * 3 +
- CpuTopo.Cores * (sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
+ CpuTopo.Sockets * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
+ CpuTopo.Clusters * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
+ sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
+ CpuTopo.Cores * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
sizeof (UINT32) * 2)));
if (CpuTopo.Threads > 1) {
TableSize += CpuTopo.Sockets * CpuTopo.Clusters * CpuTopo.Cores * CpuTopo.Threads *
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
}
Status = gBS->AllocatePages (
@@ -599,50 +600,54 @@ AddPpttTable (
((EFI_ACPI_DESCRIPTION_HEADER *)New)->Length = TableSize;
New += sizeof (EFI_ACPI_DESCRIPTION_HEADER);
- CpuId = 0;
+ CpuId = 0;
+ CacheId = 1; // 0 is not a valid Cache ID.
SocketOffset = sizeof (EFI_ACPI_DESCRIPTION_HEADER);
for (SocketIndex = 0; SocketIndex < CpuTopo.Sockets; SocketIndex++) {
// Add the Socket PPTT structure
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Socket = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Socket = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
SocketFlags,
0,
0,
0
);
- CopyMem (New, &Socket, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ CopyMem (New, &Socket, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
- ClusterOffset = SocketOffset + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ ClusterOffset = SocketOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
for (ClusterIndex = 0; ClusterIndex < CpuTopo.Clusters; ClusterIndex++) {
- L1DCacheOffset = ClusterOffset + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
- L1ICacheOffset = L1DCacheOffset + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
- L2CacheOffset = L1ICacheOffset + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
- CoreOffset = L2CacheOffset + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+ L1DCacheOffset = ClusterOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+ L1ICacheOffset = L1DCacheOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+ L2CacheOffset = L1ICacheOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+ CoreOffset = L2CacheOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
// Add the Cluster PPTT structure
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
ClusterFlags,
SocketOffset,
0,
0
);
- CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
// Add L1 D Cache structure
- CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+ L1DCache.CacheId = CacheId++;
+ CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
// Add L1 I Cache structure
- CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+ L1ICache.CacheId = CacheId++;
+ CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
// Add L2 Cache structure
- CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE));
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+ L2Cache.CacheId = CacheId++;
+ CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
for (CoreIndex = 0; CoreIndex < CpuTopo.Cores; CoreIndex++) {
UINT32 *PrivateResourcePtr;
@@ -654,14 +659,14 @@ AddPpttTable (
CoreCpuId = 0;
}
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
CoreFlags,
ClusterOffset,
CoreCpuId,
2
);
- CopyMem (New, &Core, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ CopyMem (New, &Core, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
PrivateResourcePtr = (UINT32 *)New;
PrivateResourcePtr[0] = L1DCacheOffset;
@@ -673,21 +678,21 @@ AddPpttTable (
} else {
// Add the Thread PPTT structure
for (ThreadIndex = 0; ThreadIndex < CpuTopo.Threads; ThreadIndex++) {
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Thread = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
ThreadFlags,
CoreOffset,
CpuId,
0
);
- CopyMem (New, &Thread, sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
- New += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ CopyMem (New, &Thread, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
CpuId++;
}
- CoreOffset += CpuTopo.Threads * sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR);
+ CoreOffset += CpuTopo.Threads * sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
}
- CoreOffset += sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
+ CoreOffset += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
}
ClusterOffset = CoreOffset;
--
2.45.2
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^ permalink raw reply related [flat|nested] 8+ messages in thread* [edk2-devel] [PATCH edk2-platforms v4 4/6] SbsaQemu: provide cache info per core in PPTT
2024-07-10 17:52 [edk2-devel] [PATCH edk2-platforms v4 0/6] SbsaQemu: Align the PPTT tables with QEMU Marcin Juszkiewicz
` (2 preceding siblings ...)
2024-07-10 17:52 ` [edk2-devel] [PATCH edk2-platforms v4 3/6] SbsaQemu: update PPTT to ACPI 6.5 Marcin Juszkiewicz
@ 2024-07-10 17:52 ` Marcin Juszkiewicz
2024-07-10 17:52 ` [edk2-devel] [PATCH edk2-platforms v4 5/6] SbsaQemu: introduce helper in PPTT generation Marcin Juszkiewicz
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Marcin Juszkiewicz @ 2024-07-10 17:52 UTC (permalink / raw)
To: devel
Cc: Xiong Yining, Marcin Juszkiewicz, Leif Lindholm, Ard Biesheuvel,
Graeme Gregory, Chen Baozi, Jonathan Cameron
During Linaro Connect MAD24 I was asked to move cache information from
being 'per cluster' to be 'per core'. This is a move for implementing
MPAM support.
So topology moves from:
Socket -> Clusters -> Cores + Caches -> Threads (if exist)
to:
Socket -> Clusters -> Cores -> Caches + Threads (if exist)
Cache sizes are still 32+32+512KB (L1d, L1i, L2) as QEMU does not
implement them at all so we can tell whatever.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 50 ++++++++++----------
1 file changed, 26 insertions(+), 24 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 8770b2293b92..e4bdd5edbd95 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -572,8 +572,8 @@ AddPpttTable (
TableSize = sizeof (EFI_ACPI_DESCRIPTION_HEADER) +
CpuTopo.Sockets * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
CpuTopo.Clusters * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
- sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
CpuTopo.Cores * (sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) +
+ sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3 +
sizeof (UINT32) * 2)));
if (CpuTopo.Threads > 1) {
@@ -617,11 +617,6 @@ AddPpttTable (
ClusterOffset = SocketOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
for (ClusterIndex = 0; ClusterIndex < CpuTopo.Clusters; ClusterIndex++) {
- L1DCacheOffset = ClusterOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
- L1ICacheOffset = L1DCacheOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
- L2CacheOffset = L1ICacheOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
- CoreOffset = L2CacheOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
// Add the Cluster PPTT structure
EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Cluster = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
ClusterFlags,
@@ -632,27 +627,16 @@ AddPpttTable (
CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
- // Add L1 D Cache structure
- L1DCache.CacheId = CacheId++;
- CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
- New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
- // Add L1 I Cache structure
- L1ICache.CacheId = CacheId++;
- CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
- New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
- // Add L2 Cache structure
- L2Cache.CacheId = CacheId++;
- CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
- New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
+ CoreOffset = ClusterOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
for (CoreIndex = 0; CoreIndex < CpuTopo.Cores; CoreIndex++) {
UINT32 *PrivateResourcePtr;
UINT32 CoreCpuId;
+ // two UINT32s for PrivateResourcePtr data
+ L1DCacheOffset = CoreOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
+ L1ICacheOffset = L1DCacheOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+ L2CacheOffset = L1ICacheOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
if (CpuTopo.Threads == 1) {
CoreCpuId = CpuId;
} else {
@@ -673,6 +657,23 @@ AddPpttTable (
PrivateResourcePtr[1] = L1ICacheOffset;
New += (2 * sizeof (UINT32));
+ // Add L1 D Cache structure
+ L1DCache.CacheId = CacheId++;
+ CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+ // Add L1 I Cache structure
+ L1ICache.CacheId = CacheId++;
+ CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+ // Add L2 Cache structure
+ L2Cache.CacheId = CacheId++;
+ CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
if (CpuTopo.Threads == 1) {
CpuId++;
} else {
@@ -692,7 +693,8 @@ AddPpttTable (
CoreOffset += CpuTopo.Threads * sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
}
- CoreOffset += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
+ CoreOffset += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
+ CoreOffset += 3 * sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
}
ClusterOffset = CoreOffset;
--
2.45.2
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^ permalink raw reply related [flat|nested] 8+ messages in thread* [edk2-devel] [PATCH edk2-platforms v4 5/6] SbsaQemu: introduce helper in PPTT generation
2024-07-10 17:52 [edk2-devel] [PATCH edk2-platforms v4 0/6] SbsaQemu: Align the PPTT tables with QEMU Marcin Juszkiewicz
` (3 preceding siblings ...)
2024-07-10 17:52 ` [edk2-devel] [PATCH edk2-platforms v4 4/6] SbsaQemu: provide cache info per core in PPTT Marcin Juszkiewicz
@ 2024-07-10 17:52 ` Marcin Juszkiewicz
2024-07-10 17:52 ` [edk2-devel] [PATCH edk2-platforms v4 6/6] SbsaQemu: export proper cache values in PPTT Marcin Juszkiewicz
[not found] ` <17E0EB7A956FDF20.24858@groups.io>
6 siblings, 0 replies; 8+ messages in thread
From: Marcin Juszkiewicz @ 2024-07-10 17:52 UTC (permalink / raw)
To: devel
Cc: Xiong Yining, Marcin Juszkiewicz, Leif Lindholm, Ard Biesheuvel,
Graeme Gregory, Chen Baozi, Jonathan Cameron
Function AddPpttTable() adding PPTT got too long. This change moves part
of it into helper function AddCoresToPpttTable() which takes care of
generating entries for Core and below (Cache, Thread).
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 243 +++++++++++---------
1 file changed, 133 insertions(+), 110 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index e4bdd5edbd95..61f9de45d082 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -31,6 +31,9 @@ static UINTN GicItsBase;
#pragma pack ()
+static UINTN mCpuId;
+static UINTN mCacheId;
+
/*
* A Function to Compute the ACPI Table Checksum
*/
@@ -491,6 +494,127 @@ AddSsdtTable (
return Status;
}
+STATIC
+UINT32
+AddCoresToPpttTable (
+ UINT8 *New,
+ UINT32 ClusterOffset,
+ CpuTopology CpuTopo
+ )
+{
+ UINT32 L1DCacheOffset;
+ UINT32 L1ICacheOffset;
+ UINT32 L2CacheOffset;
+ UINT32 CoreOffset;
+ UINT32 Offset;
+ UINT32 CoreCpuId;
+ UINT32 CoreIndex;
+ UINT32 ThreadIndex;
+ UINT32 *PrivateResourcePtr;
+
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS CoreFlags = {
+ EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD,
+ EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
+ };
+
+ if (CpuTopo.Threads > 1) {
+ // The Thread structure is the leaf structure, adjust the value of CoreFlags.
+ CoreFlags.AcpiProcessorIdValid = EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID;
+ CoreFlags.NodeIsALeaf = EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF;
+ }
+
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS ThreadFlags = {
+ EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
+ EFI_ACPI_6_5_PPTT_PROCESSOR_IS_THREAD,
+ EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
+ EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
+ };
+
+ EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
+ EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
+ EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
+
+ CoreOffset = ClusterOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+ Offset = CoreOffset;
+
+ for (CoreIndex = 0; CoreIndex < CpuTopo.Cores; CoreIndex++) {
+ if (CpuTopo.Threads == 1) {
+ CoreCpuId = mCpuId;
+ } else {
+ CoreCpuId = 0;
+ }
+
+ // space for Core + PrivateResourcePtr
+ Offset += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+ Offset += sizeof (UINT32) * 2;
+
+ L1DCacheOffset = Offset;
+ L1ICacheOffset = L1DCacheOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+ L2CacheOffset = L1ICacheOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ CoreFlags,
+ ClusterOffset,
+ CoreCpuId,
+ 2
+ );
+
+ CopyMem (New, &Core, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+
+ PrivateResourcePtr = (UINT32 *)New;
+ PrivateResourcePtr[0] = L1DCacheOffset;
+ PrivateResourcePtr[1] = L1ICacheOffset;
+ New += (2 * sizeof (UINT32));
+
+ // Add L1 D Cache structure
+ L1DCache.CacheId = mCacheId++;
+ CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+ // Add L1 I Cache structure
+ L1ICache.CacheId = mCacheId++;
+ CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+ // Add L2 Cache structure
+ L2Cache.CacheId = mCacheId++;
+ CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
+
+ Offset += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE) * 3;
+
+ if (CpuTopo.Threads == 1) {
+ mCpuId++;
+ } else {
+ // Add the Thread PPTT structure
+ for (ThreadIndex = 0; ThreadIndex < CpuTopo.Threads; ThreadIndex++) {
+ EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Thread = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
+ ThreadFlags,
+ CoreOffset,
+ mCpuId,
+ 0
+ );
+ CopyMem (New, &Thread, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
+ New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+ mCpuId++;
+ }
+
+ Offset += CpuTopo.Threads * sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
+ }
+
+ CoreOffset = Offset;
+ }
+
+ return CoreOffset - ClusterOffset;
+}
+
/*
* A function that adds the PPTT ACPI table.
*/
@@ -502,28 +626,17 @@ AddPpttTable (
EFI_STATUS Status;
UINTN TableHandle;
UINT32 TableSize;
- EFI_PHYSICAL_ADDRESS PageAddress;
- UINT8 *New;
- UINT32 CpuId;
- CpuTopology CpuTopo;
+ UINT32 CoresPartSize;
UINT32 SocketIndex;
UINT32 ClusterIndex;
- UINT32 CoreIndex;
- UINT32 ThreadIndex;
UINT32 SocketOffset;
UINT32 ClusterOffset;
- UINT32 CoreOffset;
- UINT32 L1DCacheOffset;
- UINT32 L1ICacheOffset;
- UINT32 L2CacheOffset;
- UINT32 CacheId;
+ EFI_PHYSICAL_ADDRESS PageAddress;
+ UINT8 *New;
+ CpuTopology CpuTopo;
GetCpuTopology (&CpuTopo);
- EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1DCache = SBSAQEMU_ACPI_PPTT_L1_D_CACHE_STRUCT;
- EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
- EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
-
EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS SocketFlags = {
EFI_ACPI_6_5_PPTT_PACKAGE_PHYSICAL,
EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID,
@@ -540,28 +653,6 @@ AddPpttTable (
EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
};
- EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS CoreFlags = {
- EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
- EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
- EFI_ACPI_6_5_PPTT_PROCESSOR_IS_NOT_THREAD,
- EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
- EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
- };
-
- if (CpuTopo.Threads > 1) {
- // The Thread structure is the leaf structure, adjust the value of CoreFlags.
- CoreFlags.AcpiProcessorIdValid = EFI_ACPI_6_5_PPTT_PROCESSOR_ID_INVALID;
- CoreFlags.NodeIsALeaf = EFI_ACPI_6_5_PPTT_NODE_IS_NOT_LEAF;
- }
-
- EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR_FLAGS ThreadFlags = {
- EFI_ACPI_6_5_PPTT_PACKAGE_NOT_PHYSICAL,
- EFI_ACPI_6_5_PPTT_PROCESSOR_ID_VALID,
- EFI_ACPI_6_5_PPTT_PROCESSOR_IS_THREAD,
- EFI_ACPI_6_5_PPTT_NODE_IS_LEAF,
- EFI_ACPI_6_5_PPTT_IMPLEMENTATION_IDENTICAL
- };
-
EFI_ACPI_DESCRIPTION_HEADER Header =
SBSAQEMU_ACPI_HEADER (
EFI_ACPI_6_5_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
@@ -600,8 +691,8 @@ AddPpttTable (
((EFI_ACPI_DESCRIPTION_HEADER *)New)->Length = TableSize;
New += sizeof (EFI_ACPI_DESCRIPTION_HEADER);
- CpuId = 0;
- CacheId = 1; // 0 is not a valid Cache ID.
+ mCpuId = 0;
+ mCacheId = 1; // 0 is not a valid Cache ID.
SocketOffset = sizeof (EFI_ACPI_DESCRIPTION_HEADER);
for (SocketIndex = 0; SocketIndex < CpuTopo.Sockets; SocketIndex++) {
@@ -627,77 +718,9 @@ AddPpttTable (
CopyMem (New, &Cluster, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
- CoreOffset = ClusterOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
- for (CoreIndex = 0; CoreIndex < CpuTopo.Cores; CoreIndex++) {
- UINT32 *PrivateResourcePtr;
- UINT32 CoreCpuId;
-
- // two UINT32s for PrivateResourcePtr data
- L1DCacheOffset = CoreOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
- L1ICacheOffset = L1DCacheOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
- L2CacheOffset = L1ICacheOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
- if (CpuTopo.Threads == 1) {
- CoreCpuId = CpuId;
- } else {
- CoreCpuId = 0;
- }
-
- EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Core = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
- CoreFlags,
- ClusterOffset,
- CoreCpuId,
- 2
- );
- CopyMem (New, &Core, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
- New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
-
- PrivateResourcePtr = (UINT32 *)New;
- PrivateResourcePtr[0] = L1DCacheOffset;
- PrivateResourcePtr[1] = L1ICacheOffset;
- New += (2 * sizeof (UINT32));
-
- // Add L1 D Cache structure
- L1DCache.CacheId = CacheId++;
- CopyMem (New, &L1DCache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
- New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
- // Add L1 I Cache structure
- L1ICache.CacheId = CacheId++;
- CopyMem (New, &L1ICache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
- ((EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *)New)->NextLevelOfCache = L2CacheOffset;
- New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
- // Add L2 Cache structure
- L2Cache.CacheId = CacheId++;
- CopyMem (New, &L2Cache, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE));
- New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
-
- if (CpuTopo.Threads == 1) {
- CpuId++;
- } else {
- // Add the Thread PPTT structure
- for (ThreadIndex = 0; ThreadIndex < CpuTopo.Threads; ThreadIndex++) {
- EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR Thread = SBSAQEMU_ACPI_PROCESSOR_HIERARCHY_NODE_STRUCTURE_INIT (
- ThreadFlags,
- CoreOffset,
- CpuId,
- 0
- );
- CopyMem (New, &Thread, sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR));
- New += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
- CpuId++;
- }
-
- CoreOffset += CpuTopo.Threads * sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
- }
-
- CoreOffset += sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR) + sizeof (UINT32) * 2;
- CoreOffset += 3 * sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE);
- }
-
- ClusterOffset = CoreOffset;
+ CoresPartSize = AddCoresToPpttTable (New, ClusterOffset, CpuTopo);
+ ClusterOffset += CoresPartSize;
+ New += CoresPartSize - sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
}
SocketOffset = ClusterOffset;
--
2.45.2
-=-=-=-=-=-=-=-=-=-=-=-
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^ permalink raw reply related [flat|nested] 8+ messages in thread* [edk2-devel] [PATCH edk2-platforms v4 6/6] SbsaQemu: export proper cache values in PPTT
2024-07-10 17:52 [edk2-devel] [PATCH edk2-platforms v4 0/6] SbsaQemu: Align the PPTT tables with QEMU Marcin Juszkiewicz
` (4 preceding siblings ...)
2024-07-10 17:52 ` [edk2-devel] [PATCH edk2-platforms v4 5/6] SbsaQemu: introduce helper in PPTT generation Marcin Juszkiewicz
@ 2024-07-10 17:52 ` Marcin Juszkiewicz
[not found] ` <17E0EB7A956FDF20.24858@groups.io>
6 siblings, 0 replies; 8+ messages in thread
From: Marcin Juszkiewicz @ 2024-07-10 17:52 UTC (permalink / raw)
To: devel
Cc: Xiong Yining, Marcin Juszkiewicz, Leif Lindholm, Ard Biesheuvel,
Graeme Gregory, Chen Baozi, Jonathan Cameron
We were exporting fake cpu cache values instead of reading them from
CCSIDR registers.
This change gets rid of fake values in favour of existing ones.
Code taken from Ampere platform core.
Reported-by: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
---
.../SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 32 ++++++-----------
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 36 ++++++++++++++++++++
2 files changed, 46 insertions(+), 22 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
index fa2e2b30bb7d..9a7c96fc6970 100644
--- a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
+++ b/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h
@@ -74,18 +74,6 @@ typedef struct {
UINT8 uid[8];
} SBSAQEMU_ACPI_CPU_DEVICE;
-#define SBSAQEMU_L1_D_CACHE_SIZE SIZE_32KB
-#define SBSAQEMU_L1_D_CACHE_SETS 256
-#define SBSAQEMU_L1_D_CACHE_ASSC 2
-
-#define SBSAQEMU_L1_I_CACHE_SIZE SIZE_32KB
-#define SBSAQEMU_L1_I_CACHE_SETS 256
-#define SBSAQEMU_L1_I_CACHE_ASSC 2
-
-#define SBSAQEMU_L2_CACHE_SIZE SIZE_512KB
-#define SBSAQEMU_L2_CACHE_SETS 1024
-#define SBSAQEMU_L2_CACHE_ASSC 8
-
#define CLUSTER_INDEX (sizeof (EFI_ACPI_DESCRIPTION_HEADER))
#define L1_D_CACHE_INDEX (CLUSTER_INDEX + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR))
#define L1_I_CACHE_INDEX (L1_D_CACHE_INDEX + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE))
@@ -106,9 +94,9 @@ typedef struct {
1, /* CacheIdValid */ \
}, \
0, /* NextLevelOfCache */ \
- SBSAQEMU_L1_D_CACHE_SIZE, /* Size */ \
- SBSAQEMU_L1_D_CACHE_SETS, /* NumberOfSets */ \
- SBSAQEMU_L1_D_CACHE_ASSC, /* Associativity */ \
+ 0, /* Size */ \
+ 0, /* NumberOfSets */ \
+ 0, /* Associativity */ \
{ \
EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
@@ -133,9 +121,9 @@ typedef struct {
1, /* CacheIdValid */ \
}, \
0, /* NextLevelOfCache */ \
- SBSAQEMU_L1_I_CACHE_SIZE, /* Size */ \
- SBSAQEMU_L1_I_CACHE_SETS, /* NumberOfSets */ \
- SBSAQEMU_L1_I_CACHE_ASSC, /* Associativity */ \
+ 0, /* Size */ \
+ 0, /* NumberOfSets */ \
+ 0, /* Associativity */ \
{ \
EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ, \
EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
@@ -159,10 +147,10 @@ typedef struct {
1, /* LineSizeValid */ \
1, /* CacheIdValid */ \
}, \
- 0, /* NextLevelOfCache */ \
- SBSAQEMU_L2_CACHE_SIZE, /* Size */ \
- SBSAQEMU_L2_CACHE_SETS, /* NumberOfSets */ \
- SBSAQEMU_L2_CACHE_ASSC, /* Associativity */ \
+ 0, /* NextLevelOfCache */ \
+ 0, /* Size */ \
+ 0, /* NumberOfSets */ \
+ 0, /* Associativity */ \
{ \
EFI_ACPI_6_5_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
EFI_ACPI_6_5_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
diff --git a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
index 61f9de45d082..49f561e9bc2e 100644
--- a/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c
@@ -2,12 +2,14 @@
* This file is an ACPI driver for the Qemu SBSA platform.
*
* Copyright (c) 2020-2024, Linaro Ltd. All rights reserved.
+* Copyright (c) 2020-2021, Ampere Computing LLC. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
#include <IndustryStandard/Acpi.h>
#include <IndustryStandard/AcpiAml.h>
+#include <IndustryStandard/ArmCache.h>
#include <IndustryStandard/IoRemappingTable.h>
#include <IndustryStandard/SbsaQemuAcpi.h>
#include <IndustryStandard/SbsaQemuPlatformVersion.h>
@@ -494,6 +496,36 @@ AddSsdtTable (
return Status;
}
+STATIC VOID
+AcpiPpttFillCacheSizeInfo (
+ EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE *Node,
+ UINT32 Level,
+ BOOLEAN DataCache,
+ BOOLEAN UnifiedCache
+ )
+{
+ CSSELR_DATA CsselrData;
+ CCSIDR_DATA CcsidrData;
+
+ CsselrData.Data = 0;
+ CsselrData.Bits.Level = Level - 1;
+ CsselrData.Bits.InD = (!DataCache && !UnifiedCache);
+
+ CcsidrData.Data = ReadCCSIDR (CsselrData.Data);
+
+ Node->Flags.LineSizeValid = 1;
+ Node->Flags.NumberOfSetsValid = 1;
+ Node->Flags.AssociativityValid = 1;
+ Node->Flags.SizePropertyValid = 1;
+ Node->Flags.CacheTypeValid = 1;
+ Node->NumberOfSets = (UINT16)CcsidrData.BitsNonCcidx.NumSets + 1;
+ Node->Associativity = (UINT16)CcsidrData.BitsNonCcidx.Associativity + 1;
+ Node->LineSize = (UINT16)(1 << (CcsidrData.BitsNonCcidx.LineSize + 4));
+ Node->Size = Node->NumberOfSets *
+ Node->Associativity *
+ Node->LineSize;
+}
+
STATIC
UINT32
AddCoresToPpttTable (
@@ -538,6 +570,10 @@ AddCoresToPpttTable (
EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L1ICache = SBSAQEMU_ACPI_PPTT_L1_I_CACHE_STRUCT;
EFI_ACPI_6_5_PPTT_STRUCTURE_CACHE L2Cache = SBSAQEMU_ACPI_PPTT_L2_CACHE_STRUCT;
+ AcpiPpttFillCacheSizeInfo (&L1DCache, 1, TRUE, FALSE);
+ AcpiPpttFillCacheSizeInfo (&L1ICache, 1, FALSE, FALSE);
+ AcpiPpttFillCacheSizeInfo (&L2Cache, 2, FALSE, TRUE);
+
CoreOffset = ClusterOffset + sizeof (EFI_ACPI_6_5_PPTT_STRUCTURE_PROCESSOR);
Offset = CoreOffset;
--
2.45.2
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^ permalink raw reply related [flat|nested] 8+ messages in thread[parent not found: <17E0EB7A956FDF20.24858@groups.io>]
* Re: [edk2-devel] [PATCH edk2-platforms v4 6/6] SbsaQemu: export proper cache values in PPTT
[not found] ` <17E0EB7A956FDF20.24858@groups.io>
@ 2024-07-11 10:46 ` Marcin Juszkiewicz
0 siblings, 0 replies; 8+ messages in thread
From: Marcin Juszkiewicz @ 2024-07-11 10:46 UTC (permalink / raw)
To: devel
Cc: Xiong Yining, Leif Lindholm, Ard Biesheuvel, Graeme Gregory,
Chen Baozi, Jonathan Cameron
On 10.07.2024 19:52, Marcin Juszkiewicz via groups.io wrote:
> We were exporting fake cpu cache values instead of reading them from
> CCSIDR registers.
>
> This change gets rid of fake values in favour of existing ones.
>
> Code taken from Ampere platform core.
>
> Reported-by: Jonathan Cameron<Jonathan.Cameron@Huawei.com>
> Signed-off-by: Marcin Juszkiewicz<marcin.juszkiewicz@linaro.org>
This patch needs work. As this way only works for older cores (before
Neoverse-V1).
Need to check FEAT_CCIDX and if it present then calculate caches properly.
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