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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2022 15:40:26.7547 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9584a2ab-7727-4eb4-9ca8-08da07634afe X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT045.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR2PR08MB4764 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable Content-Language: en-GB Hi Rebecca, Thank you for this patch. These change look good to me. Reviewed-by: Sami Mujawar Regards, Sami Mujawar On 05/03/2022 04:19 AM, Rebecca Cran wrote: > Other .asl files in Platform/ARM/JunoPkg/AcpiTables use spaces, while > AcpiSsdtRootPci.asl uses tabs. To be consistent, convert it to spaces. > > Signed-off-by: Rebecca Cran > --- > Platform/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl | 288 ++++++++++---= ------- > 1 file changed, 144 insertions(+), 144 deletions(-) > > diff --git a/Platform/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl b/Platfo= rm/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl > index ba41a9586555..317b621e013e 100644 > --- a/Platform/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl > +++ b/Platform/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl > @@ -28,24 +28,24 @@ > interrupt type as PCI defaults (Level Triggered, Active Low) are not > compatible with GICv2. > */ > -#define LNK_DEVICE(Unique_Id, Link_Name, irq) = \ > - Device(Link_Name) { = \ > - Name(_HID, EISAID("PNP0C0F")) = \ > - Name(_UID, Unique_Id) = \ > - Name(_PRS, ResourceTemplate() { = \ > - Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) {= irq } \ > - }) = \ > - Method (_CRS, 0) { Return (_PRS) } = \ > - Method (_SRS, 1) { } = \ > - Method (_DIS) { } = \ > - } > +#define LNK_DEVICE(Unique_Id, Link_Name, irq) = \ > + Device(Link_Name) { = \ > + Name(_HID, EISAID("PNP0C0F")) = \ > + Name(_UID, Unique_Id) = \ > + Name(_PRS, ResourceTemplate() { = \ > + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { ir= q } \ > + }) = \ > + Method (_CRS, 0) { Return (_PRS) } = \ > + Method (_SRS, 1) { } = \ > + Method (_DIS) { } = \ > + } > > -#define PRT_ENTRY(Address, Pin, Link) = \ > +#define PRT_ENTRY(Address, Pin, Link) = \ > Package (4) { = \ > Address, /* uses the same format as _ADR */ = \ > Pin, /* The PCI pin number of the device (0-INTA, 1-= INTB, 2-INTC, 3-INTD). */ \ > - Link, /* Interrupt allocated via Link device. */ = \ > - Zero /* global system interrupt number (no used) */ = \ > + Link, /* Interrupt allocated via Link device. */ = \ > + Zero /* global system interrupt number (no used) */ = \ > } > > /* > @@ -59,155 +59,155 @@ > > DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACP= I_ARM_OEM_REVISION) { > Scope(_SB) { > - // > - // PCI Root Complex > - // > - LNK_DEVICE(1, LNKA, 168) > - LNK_DEVICE(2, LNKB, 169) > - LNK_DEVICE(3, LNKC, 170) > - LNK_DEVICE(4, LNKD, 171) > + // > + // PCI Root Complex > + // > + LNK_DEVICE(1, LNKA, 168) > + LNK_DEVICE(2, LNKB, 169) > + LNK_DEVICE(3, LNKC, 170) > + LNK_DEVICE(4, LNKD, 171) > > - Device(PCI0) > + Device(PCI0) > { > - Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge > - Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge > - Name(_SEG, Zero) // PCI Segment Group number > - Name(_BBN, Zero) // PCI Base Bus Number > - Name(_CCA, 1) // Initially mark the PCI coherent (for Ju= noR1) > + Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge > + Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge > + Name(_SEG, Zero) // PCI Segment Group number > + Name(_BBN, Zero) // PCI Base Bus Number > + Name(_CCA, 1) // Initially mark the PCI coherent (for JunoR1) > > - // Root Complex 0 > - Device (RP0) { > - Name(_ADR, 0xF0000000) // Dev 0, Func 0 > - } > + // Root Complex 0 > + Device (RP0) { > + Name(_ADR, 0xF0000000) // Dev 0, Func 0 > + } > > - // PCI Routing Table > - Name(_PRT, Package() { > - ROOT_PRT_ENTRY(0, LNKA), // INTA > - ROOT_PRT_ENTRY(1, LNKB), // INTB > - ROOT_PRT_ENTRY(2, LNKC), // INTC > - ROOT_PRT_ENTRY(3, LNKD), // INTD > - }) > - // Root complex resources > - Method (_CRS, 0, Serialized) { > - Name (RBUF, ResourceTemplate () { > - WordBusNumber ( // Bus numbers assigned to = this root > - ResourceProducer, > - MinFixed, MaxFixed, PosDecode, > - 0, // AddressGranularity > - 0, // AddressMinimum - Minimum Bu= s Number > - 255, // AddressMaximum - Maximum Bu= s Number > - 0, // AddressTranslation - Set to= 0 > - 256 // RangeLength - Number of Bus= ses > - ) > + // PCI Routing Table > + Name(_PRT, Package() { > + ROOT_PRT_ENTRY(0, LNKA), // INTA > + ROOT_PRT_ENTRY(1, LNKB), // INTB > + ROOT_PRT_ENTRY(2, LNKC), // INTC > + ROOT_PRT_ENTRY(3, LNKD), // INTD > + }) > + // Root complex resources > + Method (_CRS, 0, Serialized) { > + Name (RBUF, ResourceTemplate () { > + WordBusNumber ( // Bus numbers assigned to this root > + ResourceProducer, > + MinFixed, MaxFixed, PosDecode, > + 0, // AddressGranularity > + 0, // AddressMinimum - Minimum Bus Number > + 255, // AddressMaximum - Maximum Bus Number > + 0, // AddressTranslation - Set to 0 > + 256 // RangeLength - Number of Busses > + ) > > - DWordMemory ( // 32-bit BAR Windows > - ResourceProducer, PosDecode, > - MinFixed, MaxFixed, > - Cacheable, ReadWrite, > - 0x00000000, = // Granularity > - 0x50000000, = // Min Base Address > - 0x57FFFFFF, = // Max Base Address > - 0x00000000, = // Translate > - 0x08000000 = // Length > - ) > + DWordMemory ( // 32-bit BAR Windows > + ResourceProducer, PosDecode, > + MinFixed, MaxFixed, > + Cacheable, ReadWrite, > + 0x00000000, // Granularity > + 0x50000000, // Min Base Address > + 0x57FFFFFF, // Max Base Address > + 0x00000000, // Translate > + 0x08000000 // Length > + ) > > - QWordMemory ( // 64-bit BAR Windows > - ResourceProducer, PosDecode, > - MinFixed, MaxFixed, > - Cacheable, ReadWrite, > - 0x00000000, = // Granularity > - 0x4000000000, = // Min Base Address > - 0x40FFFFFFFF, = // Max Base Address > - 0x00000000, = // Translate > - 0x100000000 = // Length > - ) > + QWordMemory ( // 64-bit BAR Windows > + ResourceProducer, PosDecode, > + MinFixed, MaxFixed, > + Cacheable, ReadWrite, > + 0x00000000, // Granularity > + 0x4000000000, // Min Base Address > + 0x40FFFFFFFF, // Max Base Address > + 0x00000000, // Translate > + 0x100000000 // Length > + ) > > - DWordIo ( // IO window > - ResourceProducer, > - MinFixed, > - MaxFixed, > - PosDecode, > - EntireRange, > - 0x00000000, = // Granularity > - 0x00000000, = // Min Base Address > - 0x007fffff, = // Max Base Address > - 0x5f800000, = // Translate > - 0x00800000, = // Length > - ,,,TypeTranslation > - ) > - }) // Name(RBUF) > + DWordIo ( // IO window > + ResourceProducer, > + MinFixed, > + MaxFixed, > + PosDecode, > + EntireRange, > + 0x00000000, // Granularity > + 0x00000000, // Min Base Address > + 0x007fffff, // Max Base Address > + 0x5f800000, // Translate > + 0x00800000, // Length > + ,,,TypeTranslation > + ) > + }) // Name(RBUF) > > - Return (RBUF) > - } // Method(_CRS) > + Return (RBUF) > + } // Method(_CRS) > > - // > - // OS Control Handoff > - // > - Name(SUPP, Zero) // PCI _OSC Support Field value > - Name(CTRL, Zero) // PCI _OSC Control Field value > + // > + // OS Control Handoff > + // > + Name(SUPP, Zero) // PCI _OSC Support Field value > + Name(CTRL, Zero) // PCI _OSC Control Field value > > - /* > - See [1] 6.2.10, [2] 4.5 > - */ > - Method(_OSC,4) { > - // Check for proper UUID > - If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441= C03DD766"))) { > - // Create DWord-adressable fields from the = Capabilities Buffer > - CreateDWordField(Arg3,0,CDW1) > - CreateDWordField(Arg3,4,CDW2) > - CreateDWordField(Arg3,8,CDW3) > + /* > + See [1] 6.2.10, [2] 4.5 > + */ > + Method(_OSC,4) { > + // Check for proper UUID > + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) = { > + // Create DWord-adressable fields from the Capabilities Buffer > + CreateDWordField(Arg3,0,CDW1) > + CreateDWordField(Arg3,4,CDW2) > + CreateDWordField(Arg3,8,CDW3) > > - // Save Capabilities DWord2 & 3 > - Store(CDW2,SUPP) > - Store(CDW3,CTRL) > + // Save Capabilities DWord2 & 3 > + Store(CDW2,SUPP) > + Store(CDW3,CTRL) > > - // Only allow native hot plug control if OS= supports: > - // * ASPM > - // * Clock PM > - // * MSI/MSI-X > - If(LNotEqual(And(SUPP, 0x16), 0x16)) { > - And(CTRL,0x1E,CTRL) // Mask bit 0 (= and undefined bits) > - } > + // Only allow native hot plug control if OS supports: > + // * ASPM > + // * Clock PM > + // * MSI/MSI-X > + If(LNotEqual(And(SUPP, 0x16), 0x16)) { > + And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits) > + } > > - // Always allow native PME, AER (no depende= ncies) > + // Always allow native PME, AER (no dependencies) > > - // Never allow SHPC (no SHPC controller in = this system) > - And(CTRL,0x1D,CTRL) > + // Never allow SHPC (no SHPC controller in this system) > + And(CTRL,0x1D,CTRL) > > #if 0 > - If(LNot(And(CDW1,1))) { // Query fl= ag clear? > - // Disable GPEs for features grante= d native control. > - If(And(CTRL,0x01)) { // Hot plug= control granted? > - Store(0,HPCE) // = clear the hot plug SCI enable bit > - Store(1,HPCS) // = clear the hot plug SCI status bit > - } > - If(And(CTRL,0x04)) { // PME cont= rol granted? > - Store(0,PMCE) // = clear the PME SCI enable bit > - Store(1,PMCS) // = clear the PME SCI status bit > - } > - If(And(CTRL,0x10)) { // OS resto= ring PCIe cap structure? > - // Set status to not restor= e PCIe cap structure > - // upon resume from S3 > - Store(1,S3CR) > - } > - } > + If(LNot(And(CDW1,1))) { // Query flag clear? > + // Disable GPEs for features granted native control. > + If(And(CTRL,0x01)) { // Hot plug control granted? > + Store(0,HPCE) // clear the hot plug SCI enable bi= t > + Store(1,HPCS) // clear the hot plug SCI status bi= t > + } > + If(And(CTRL,0x04)) { // PME control granted? > + Store(0,PMCE) // clear the PME SCI enable bit > + Store(1,PMCS) // clear the PME SCI status bit > + } > + If(And(CTRL,0x10)) { // OS restoring PCIe cap structure? > + // Set status to not restore PCIe cap structure > + // upon resume from S3 > + Store(1,S3CR) > + } > + } > #endif > > - If(LNotEqual(Arg1,One)) { // Unknown = revision > - Or(CDW1,0x08,CDW1) > - } > + If(LNotEqual(Arg1,One)) { // Unknown revision > + Or(CDW1,0x08,CDW1) > + } > > - If(LNotEqual(CDW3,CTRL)) { // Capabili= ties bits were masked > - Or(CDW1,0x10,CDW1) > - } > - // Update DWORD3 in the buffer > - Store(CTRL,CDW3) > - Return(Arg3) > - } Else { > - Or(CDW1,4,CDW1) // Unrecognized UUID > - Return(Arg3) > - } > - } // End _OSC > + If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked > + Or(CDW1,0x10,CDW1) > + } > + // Update DWORD3 in the buffer > + Store(CTRL,CDW3) > + Return(Arg3) > + } Else { > + Or(CDW1,4,CDW1) // Unrecognized UUID > + Return(Arg3) > + } > + } // End _OSC > } // PCI0 > } > } IMPORTANT NOTICE: The contents of this email and any attachments are confid= ential and may also be privileged. If you are not the intended recipient, p= lease notify the sender immediately and do not disclose the contents to any= other person, use it for any purpose, or store or copy the information in = any medium. Thank you.