public inbox for devel@edk2.groups.io
 help / color / mirror / Atom feed
* Re: [edk2-devel] [edk2-platforms][PATCH V2 0/2] Enable SMMUv3 for Arm SGI/RD platforms
       [not found] <16697488855F3BC3.20367@groups.io>
@ 2021-03-05 13:21 ` Vivek Kumar Gautam
  2021-03-05 14:13   ` Sami Mujawar
  0 siblings, 1 reply; 4+ messages in thread
From: Vivek Kumar Gautam @ 2021-03-05 13:21 UTC (permalink / raw)
  To: devel; +Cc: ardb+tianocore, leif, Sami.Mujawar



On 3/5/21 6:44 PM, Vivek Kumar Gautam via groups.io wrote:
> Arm's SMMUv3 present in various SGI/RD platforms provides address
> translation support for devices such as the ones present over PCIe.
> SMMUv3 also supports Address Translation Service (ATS) and Page
> Request Interface (PRI) to work with PCIe devices.
> ATS allows PCIe devices to request translation from a translation
> agent such as SMMU, and then cache these translation in their private
> cache called as Address Translation Cache (ATC).
> Devices that support PRI can also enable the feature when ATS is
> enabled as ATS is a prerequisite for PRI.
>
> The I/O topology on SGI/RD platforms includes I/O devices (or PCIe
> devices) connected to a SMMU-v3, and an GIC ITS block that facilitates
> interrupt translations for message signaled interrupts. A typical view
> of this topology is as below -
>
>        ---------------       ------------       ------------
>       |  PCIe device  |---->|  SMMUv3    |---->|   ITS      |
>       | (RequesterID) |     | (StreamID) |     | (DeviceID) |
>        ---------------       ------------       ------------
>
> This patch series adds the SMMU-v3 node in iort table, and sets up the
> connection between these iort nodes to forward the traffic in the right
> manner.

After applying these patches, the resulting updated Iort Acpi table
looks like below:

====================================================================
Shell> Acpiview -s iort





  --------------- IORT Table ---------------



Address  : 0xF98DF598

Length   : 236



00000000 : 49 4F 52 54 EC 00 00 00 - 00 A5 41 52 4D 4C 54 44
IORT......ARMLTD

00000010 : 41 52 4D 53 47 49 20 20 - 27 07 14 20 41 52 4D 20   ARMSGI
'.. ARM

00000020 : 99 00 00 00 03 00 00 00 - 30 00 00 00 00 00 00 00
........0.......

00000030 : 00 18 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
................

00000040 : 01 00 00 00 00 00 00 00 - 04 6C 00 02 00 00 00 00
.........l......

00000050 : 02 00 00 00 44 00 00 00 - 00 00 00 4F 00 00 00 00
....D......O....

00000060 : 01 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
................

00000070 : 00 00 00 00 04 01 00 00 - 00 00 00 00 06 01 00 00
................

00000080 : 05 01 00 00 00 00 00 00 - 01 00 00 00 00 00 00 00
................

00000090 : FF FF 00 00 00 00 00 00 - 30 00 00 00 00 00 00 00
........0.......

000000A0 : 00 00 00 00 01 00 00 00 - 00 00 01 00 30 00 00 00
............0...

000000B0 : 01 00 00 00 02 38 00 00 - 00 00 00 00 01 00 00 00
.....8..........

000000C0 : 24 00 00 00 01 00 00 00 - 00 00 00 00 01 00 00 00
$...............

000000D0 : 00 00 00 00 00 00 00 00 - 00 00 00 00 FF FF 00 00
................

000000E0 : 00 00 00 00 48 00 00 00 - 00 00 00 00               ....H.......



Table Checksum : OK



IORT                                 :

   Signature                          : IORT

   Length                             : 236

   Revision                           : 0

   Checksum                           : 0xA5

   Oem ID                             : ARMLTD

   Oem Table ID                       : ARMSGI

   Oem Revision                       : 0x20140727

   Creator ID                         : ARM

   Creator Revision                   : 0x99

   Number of IORT Nodes               : 3

   Offset to Array of IORT Nodes      : 0x30

   Reserved                           : 0x0

   * Node Offset *                    : 0x30

   ITS Node                           :

     Type                             : 0

     Length                           : 24

     Revision                         : 0

     Reserved                         : 0x0

     Number of ID mappings            : 0

     Reference to ID Array            : 0x0

     Number of ITSs                   : 1

     GIC ITS Identifier Array [0]     :

       GIC ITS Identifier             : 0

   * Node Offset *                    : 0x48

   SMMUV3 Node                        :

     Type                             : 4

     Length                           : 108

     Revision                         : 2

     Reserved                         : 0x0

     Number of ID mappings            : 2

     Reference to ID Array            : 0x44

     Base Address                     : 0x4F000000

     Flags                            : 0x1

     Reserved                         : 0x0

     VATOS Address                    : 0x0

     Model                            : 0

     Event                            : 0x104

     PRI                              : 0x0

     GERR                             : 0x106

     Sync                             : 0x105

     Proximity domain                 : 0x0

     Device ID mapping index          : 1

     ID Mapping [0]                   :

       Input base                     : 0x0

       Number of IDs                  : 0xFFFF

       Output base                    : 0x0

       Output reference               : 0x30

       Flags                          : 0x0

     ID Mapping [1]                   :

       Input base                     : 0x0

       Number of IDs                  : 0x1

       Output base                    : 0x10000

       Output reference               : 0x30

       Flags                          : 0x1

   * Node Offset *                    : 0xB4

   Root Complex Node                  :

     Type                             : 2

     Length                           : 56

     Revision                         : 0

     Reserved                         : 0x0

     Number of ID mappings            : 1

     Reference to ID Array            : 0x24

     Memory access properties         : 0x1

     ATS Attribute                    : 0x1

     PCI Segment number               : 0x0

     Memory access size limit         : 0x0

     Reserved                         : 0 0 0

     ID Mapping [0]                   :

       Input base                     : 0x0

       Number of IDs                  : 0xFFFF

       Output base                    : 0x0

       Output reference               : 0x48

       Flags                          : 0x0



Table Statistics:

         0 Error(s)

         0 Warning(s)
====================================================================

Best regards
Vivek

[snip]
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [edk2-devel] [edk2-platforms][PATCH V2 0/2] Enable SMMUv3 for Arm SGI/RD platforms
  2021-03-05 13:21 ` [edk2-devel] [edk2-platforms][PATCH V2 0/2] Enable SMMUv3 for Arm SGI/RD platforms Vivek Kumar Gautam
@ 2021-03-05 14:13   ` Sami Mujawar
  2021-03-08 19:42     ` Vivek Kumar Gautam
  0 siblings, 1 reply; 4+ messages in thread
From: Sami Mujawar @ 2021-03-05 14:13 UTC (permalink / raw)
  To: Vivek Kumar Gautam, devel@edk2.groups.io
  Cc: ardb+tianocore@kernel.org, leif@nuviainc.com, nd

Hi Vivek,

Thank you for this patch.

For this series.
Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

I will merge this series once the merge window opens.

Regards,

Sami Mujawar

-----Original Message-----
From: Vivek Kumar Gautam <Vivek.Gautam@arm.com> 
Sent: 05 March 2021 01:21 PM
To: devel@edk2.groups.io
Cc: ardb+tianocore@kernel.org; leif@nuviainc.com; Sami Mujawar <Sami.Mujawar@arm.com>
Subject: Re: [edk2-devel] [edk2-platforms][PATCH V2 0/2] Enable SMMUv3 for Arm SGI/RD platforms



On 3/5/21 6:44 PM, Vivek Kumar Gautam via groups.io wrote:
> Arm's SMMUv3 present in various SGI/RD platforms provides address
> translation support for devices such as the ones present over PCIe.
> SMMUv3 also supports Address Translation Service (ATS) and Page
> Request Interface (PRI) to work with PCIe devices.
> ATS allows PCIe devices to request translation from a translation
> agent such as SMMU, and then cache these translation in their private
> cache called as Address Translation Cache (ATC).
> Devices that support PRI can also enable the feature when ATS is
> enabled as ATS is a prerequisite for PRI.
> 
> The I/O topology on SGI/RD platforms includes I/O devices (or PCIe
> devices) connected to a SMMU-v3, and an GIC ITS block that facilitates
> interrupt translations for message signaled interrupts. A typical view
> of this topology is as below -
> 
> 	 ---------------       ------------       ------------
> 	|  PCIe device  |---->|  SMMUv3    |---->|   ITS      |
> 	| (RequesterID) |     | (StreamID) |     | (DeviceID) |
> 	 ---------------       ------------       ------------
> 
> This patch series adds the SMMU-v3 node in iort table, and sets up the
> connection between these iort nodes to forward the traffic in the right
> manner.

After applying these patches, the resulting updated Iort Acpi table 
looks like below:

====================================================================
Shell> Acpiview -s iort





  --------------- IORT Table ---------------



Address  : 0xF98DF598

Length   : 236



00000000 : 49 4F 52 54 EC 00 00 00 - 00 A5 41 52 4D 4C 54 44 
IORT......ARMLTD

00000010 : 41 52 4D 53 47 49 20 20 - 27 07 14 20 41 52 4D 20   ARMSGI 
'.. ARM

00000020 : 99 00 00 00 03 00 00 00 - 30 00 00 00 00 00 00 00 
........0.......

00000030 : 00 18 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 
................

00000040 : 01 00 00 00 00 00 00 00 - 04 6C 00 02 00 00 00 00 
.........l......

00000050 : 02 00 00 00 44 00 00 00 - 00 00 00 4F 00 00 00 00 
....D......O....

00000060 : 01 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00 
................

00000070 : 00 00 00 00 04 01 00 00 - 00 00 00 00 06 01 00 00 
................

00000080 : 05 01 00 00 00 00 00 00 - 01 00 00 00 00 00 00 00 
................

00000090 : FF FF 00 00 00 00 00 00 - 30 00 00 00 00 00 00 00 
........0.......

000000A0 : 00 00 00 00 01 00 00 00 - 00 00 01 00 30 00 00 00 
............0...

000000B0 : 01 00 00 00 02 38 00 00 - 00 00 00 00 01 00 00 00 
.....8..........

000000C0 : 24 00 00 00 01 00 00 00 - 00 00 00 00 01 00 00 00 
$...............

000000D0 : 00 00 00 00 00 00 00 00 - 00 00 00 00 FF FF 00 00 
................

000000E0 : 00 00 00 00 48 00 00 00 - 00 00 00 00               ....H.......



Table Checksum : OK



IORT                                 :

   Signature                          : IORT

   Length                             : 236

   Revision                           : 0

   Checksum                           : 0xA5

   Oem ID                             : ARMLTD

   Oem Table ID                       : ARMSGI

   Oem Revision                       : 0x20140727

   Creator ID                         : ARM

   Creator Revision                   : 0x99

   Number of IORT Nodes               : 3

   Offset to Array of IORT Nodes      : 0x30

   Reserved                           : 0x0

   * Node Offset *                    : 0x30

   ITS Node                           :

     Type                             : 0

     Length                           : 24

     Revision                         : 0

     Reserved                         : 0x0

     Number of ID mappings            : 0

     Reference to ID Array            : 0x0

     Number of ITSs                   : 1

     GIC ITS Identifier Array [0]     :

       GIC ITS Identifier             : 0

   * Node Offset *                    : 0x48

   SMMUV3 Node                        :

     Type                             : 4

     Length                           : 108

     Revision                         : 2

     Reserved                         : 0x0

     Number of ID mappings            : 2

     Reference to ID Array            : 0x44

     Base Address                     : 0x4F000000

     Flags                            : 0x1

     Reserved                         : 0x0

     VATOS Address                    : 0x0

     Model                            : 0

     Event                            : 0x104

     PRI                              : 0x0

     GERR                             : 0x106

     Sync                             : 0x105

     Proximity domain                 : 0x0

     Device ID mapping index          : 1

     ID Mapping [0]                   :

       Input base                     : 0x0

       Number of IDs                  : 0xFFFF

       Output base                    : 0x0

       Output reference               : 0x30

       Flags                          : 0x0

     ID Mapping [1]                   :

       Input base                     : 0x0

       Number of IDs                  : 0x1

       Output base                    : 0x10000

       Output reference               : 0x30

       Flags                          : 0x1

   * Node Offset *                    : 0xB4

   Root Complex Node                  :

     Type                             : 2

     Length                           : 56

     Revision                         : 0

     Reserved                         : 0x0

     Number of ID mappings            : 1

     Reference to ID Array            : 0x24

     Memory access properties         : 0x1

     ATS Attribute                    : 0x1

     PCI Segment number               : 0x0

     Memory access size limit         : 0x0

     Reserved                         : 0 0 0

     ID Mapping [0]                   :

       Input base                     : 0x0

       Number of IDs                  : 0xFFFF

       Output base                    : 0x0

       Output reference               : 0x48

       Flags                          : 0x0



Table Statistics:

         0 Error(s)

         0 Warning(s)
====================================================================

Best regards
Vivek

[snip]

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [edk2-devel] [edk2-platforms][PATCH V2 0/2] Enable SMMUv3 for Arm SGI/RD platforms
  2021-03-05 14:13   ` Sami Mujawar
@ 2021-03-08 19:42     ` Vivek Kumar Gautam
  2021-04-06 12:21       ` Sami Mujawar
  0 siblings, 1 reply; 4+ messages in thread
From: Vivek Kumar Gautam @ 2021-03-08 19:42 UTC (permalink / raw)
  To: Sami Mujawar, devel@edk2.groups.io
  Cc: ardb+tianocore@kernel.org, leif@nuviainc.com, nd

Hi Sami,


On 3/5/21 7:43 PM, Sami Mujawar wrote:
> Hi Vivek,
> 
> Thank you for this patch.
> 
> For this series.
> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
> 
> I will merge this series once the merge window opens.

Thanks for reviewing the patches and taking them.

Best regards
Vivek

> 
> Regards,
> 
> Sami Mujawar
> 
> -----Original Message-----
> From: Vivek Kumar Gautam <Vivek.Gautam@arm.com>
> Sent: 05 March 2021 01:21 PM
> To: devel@edk2.groups.io
> Cc: ardb+tianocore@kernel.org; leif@nuviainc.com; Sami Mujawar <Sami.Mujawar@arm.com>
> Subject: Re: [edk2-devel] [edk2-platforms][PATCH V2 0/2] Enable SMMUv3 for Arm SGI/RD platforms
> 
> 
> 
> On 3/5/21 6:44 PM, Vivek Kumar Gautam via groups.io wrote:
>> Arm's SMMUv3 present in various SGI/RD platforms provides address
>> translation support for devices such as the ones present over PCIe.
>> SMMUv3 also supports Address Translation Service (ATS) and Page
>> Request Interface (PRI) to work with PCIe devices.
>> ATS allows PCIe devices to request translation from a translation
>> agent such as SMMU, and then cache these translation in their private
>> cache called as Address Translation Cache (ATC).
>> Devices that support PRI can also enable the feature when ATS is
>> enabled as ATS is a prerequisite for PRI.
>>
>> The I/O topology on SGI/RD platforms includes I/O devices (or PCIe
>> devices) connected to a SMMU-v3, and an GIC ITS block that facilitates
>> interrupt translations for message signaled interrupts. A typical view
>> of this topology is as below -
>>
>> 	 ---------------       ------------       ------------
>> 	|  PCIe device  |---->|  SMMUv3    |---->|   ITS      |
>> 	| (RequesterID) |     | (StreamID) |     | (DeviceID) |
>> 	 ---------------       ------------       ------------
>>
>> This patch series adds the SMMU-v3 node in iort table, and sets up the
>> connection between these iort nodes to forward the traffic in the right
>> manner.
> 
> After applying these patches, the resulting updated Iort Acpi table
> looks like below:
> 
> ====================================================================
> Shell> Acpiview -s iort
> 
> 
> 
> 
> 
>    --------------- IORT Table ---------------
> 
> 
> 
> Address  : 0xF98DF598
> 
> Length   : 236
> 
> 
> 
> 00000000 : 49 4F 52 54 EC 00 00 00 - 00 A5 41 52 4D 4C 54 44
> IORT......ARMLTD
> 
> 00000010 : 41 52 4D 53 47 49 20 20 - 27 07 14 20 41 52 4D 20   ARMSGI
> '.. ARM
> 
> 00000020 : 99 00 00 00 03 00 00 00 - 30 00 00 00 00 00 00 00
> ........0.......
> 
> 00000030 : 00 18 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
> ................
> 
> 00000040 : 01 00 00 00 00 00 00 00 - 04 6C 00 02 00 00 00 00
> .........l......
> 
> 00000050 : 02 00 00 00 44 00 00 00 - 00 00 00 4F 00 00 00 00
> ....D......O....
> 
> 00000060 : 01 00 00 00 00 00 00 00 - 00 00 00 00 00 00 00 00
> ................
> 
> 00000070 : 00 00 00 00 04 01 00 00 - 00 00 00 00 06 01 00 00
> ................
> 
> 00000080 : 05 01 00 00 00 00 00 00 - 01 00 00 00 00 00 00 00
> ................
> 
> 00000090 : FF FF 00 00 00 00 00 00 - 30 00 00 00 00 00 00 00
> ........0.......
> 
> 000000A0 : 00 00 00 00 01 00 00 00 - 00 00 01 00 30 00 00 00
> ............0...
> 
> 000000B0 : 01 00 00 00 02 38 00 00 - 00 00 00 00 01 00 00 00
> .....8..........
> 
> 000000C0 : 24 00 00 00 01 00 00 00 - 00 00 00 00 01 00 00 00
> $...............
> 
> 000000D0 : 00 00 00 00 00 00 00 00 - 00 00 00 00 FF FF 00 00
> ................
> 
> 000000E0 : 00 00 00 00 48 00 00 00 - 00 00 00 00               ....H.......
> 
> 
> 
> Table Checksum : OK
> 
> 
> 
> IORT                                 :
> 
>     Signature                          : IORT
> 
>     Length                             : 236
> 
>     Revision                           : 0
> 
>     Checksum                           : 0xA5
> 
>     Oem ID                             : ARMLTD
> 
>     Oem Table ID                       : ARMSGI
> 
>     Oem Revision                       : 0x20140727
> 
>     Creator ID                         : ARM
> 
>     Creator Revision                   : 0x99
> 
>     Number of IORT Nodes               : 3
> 
>     Offset to Array of IORT Nodes      : 0x30
> 
>     Reserved                           : 0x0
> 
>     * Node Offset *                    : 0x30
> 
>     ITS Node                           :
> 
>       Type                             : 0
> 
>       Length                           : 24
> 
>       Revision                         : 0
> 
>       Reserved                         : 0x0
> 
>       Number of ID mappings            : 0
> 
>       Reference to ID Array            : 0x0
> 
>       Number of ITSs                   : 1
> 
>       GIC ITS Identifier Array [0]     :
> 
>         GIC ITS Identifier             : 0
> 
>     * Node Offset *                    : 0x48
> 
>     SMMUV3 Node                        :
> 
>       Type                             : 4
> 
>       Length                           : 108
> 
>       Revision                         : 2
> 
>       Reserved                         : 0x0
> 
>       Number of ID mappings            : 2
> 
>       Reference to ID Array            : 0x44
> 
>       Base Address                     : 0x4F000000
> 
>       Flags                            : 0x1
> 
>       Reserved                         : 0x0
> 
>       VATOS Address                    : 0x0
> 
>       Model                            : 0
> 
>       Event                            : 0x104
> 
>       PRI                              : 0x0
> 
>       GERR                             : 0x106
> 
>       Sync                             : 0x105
> 
>       Proximity domain                 : 0x0
> 
>       Device ID mapping index          : 1
> 
>       ID Mapping [0]                   :
> 
>         Input base                     : 0x0
> 
>         Number of IDs                  : 0xFFFF
> 
>         Output base                    : 0x0
> 
>         Output reference               : 0x30
> 
>         Flags                          : 0x0
> 
>       ID Mapping [1]                   :
> 
>         Input base                     : 0x0
> 
>         Number of IDs                  : 0x1
> 
>         Output base                    : 0x10000
> 
>         Output reference               : 0x30
> 
>         Flags                          : 0x1
> 
>     * Node Offset *                    : 0xB4
> 
>     Root Complex Node                  :
> 
>       Type                             : 2
> 
>       Length                           : 56
> 
>       Revision                         : 0
> 
>       Reserved                         : 0x0
> 
>       Number of ID mappings            : 1
> 
>       Reference to ID Array            : 0x24
> 
>       Memory access properties         : 0x1
> 
>       ATS Attribute                    : 0x1
> 
>       PCI Segment number               : 0x0
> 
>       Memory access size limit         : 0x0
> 
>       Reserved                         : 0 0 0
> 
>       ID Mapping [0]                   :
> 
>         Input base                     : 0x0
> 
>         Number of IDs                  : 0xFFFF
> 
>         Output base                    : 0x0
> 
>         Output reference               : 0x48
> 
>         Flags                          : 0x0
> 
> 
> 
> Table Statistics:
> 
>           0 Error(s)
> 
>           0 Warning(s)
> ====================================================================
> 
> Best regards
> Vivek
> 
> [snip]
> 

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [edk2-devel] [edk2-platforms][PATCH V2 0/2] Enable SMMUv3 for Arm SGI/RD platforms
  2021-03-08 19:42     ` Vivek Kumar Gautam
@ 2021-04-06 12:21       ` Sami Mujawar
  0 siblings, 0 replies; 4+ messages in thread
From: Sami Mujawar @ 2021-04-06 12:21 UTC (permalink / raw)
  To: Vivek Kumar Gautam, devel

[-- Attachment #1: Type: text/plain, Size: 111 bytes --]

Hi Vivek,

Thanks for this patch series.
Pushed as: bc8a8b16bd4b..7fe9704893f1

Regards,

Sami Mujawar

[-- Attachment #2: Type: text/html, Size: 139 bytes --]

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2021-04-06 12:21 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
     [not found] <16697488855F3BC3.20367@groups.io>
2021-03-05 13:21 ` [edk2-devel] [edk2-platforms][PATCH V2 0/2] Enable SMMUv3 for Arm SGI/RD platforms Vivek Kumar Gautam
2021-03-05 14:13   ` Sami Mujawar
2021-03-08 19:42     ` Vivek Kumar Gautam
2021-04-06 12:21       ` Sami Mujawar

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox