From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=216.228.121.143; helo=hqemgate14.nvidia.com; envelope-from=jbrasen@nvidia.com; receiver=edk2-devel@lists.01.org Received: from hqemgate14.nvidia.com (hqemgate14.nvidia.com [216.228.121.143]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 47AD121959CB2 for ; Fri, 5 Oct 2018 10:13:44 -0700 (PDT) Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 05 Oct 2018 10:13:40 -0700 Received: from HQMAIL106.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 05 Oct 2018 10:13:43 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 05 Oct 2018 10:13:43 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 5 Oct 2018 17:13:43 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 5 Oct 2018 17:13:42 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Fri, 5 Oct 2018 17:13:42 +0000 Received: from jbrasen-ux.nvidia.com (Not Verified[10.28.48.113]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 05 Oct 2018 10:13:42 -0700 From: Jeff Brasen To: CC: Jeff Brasen Date: Fri, 5 Oct 2018 11:13:24 -0600 Message-ID: X-Mailer: git-send-email 2.7.4 In-Reply-To: <09d9d3505f508b5d565ac909d50efe3d056b85f6.1538757814.git.jbrasen@nvidia.com> References: <09d9d3505f508b5d565ac909d50efe3d056b85f6.1538757814.git.jbrasen@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1538759620; bh=NvUCDlFYWmXKBDBzntSfT8Mt61OnisR6NRN1E2FtCtM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=NClGpYWQWY2u1QTHu8f25qsgD0vKZ0wlCbyROCwh+5fFNmPVj8ON5pkdGSR+aX9IS LwPKTGkBHlvIX9x75Du+yx2GxsgWvvqsSz7D+mUz28ZWPt/3XG53hC09vykt2YGSDN MX8O4U7BL0DeeneBWJhoHyW3ZoXWDzdwWsVyDTBcOhG6Imni8ChKjDJup5Joh/zC1V 7mFd9w6xLiKacdhvZL7CBvaEy7QmRZNtznyAUBQpGSdsFwRqwtLBpOrJYBPg376I5V btG2iMRhN9yh/Octd09QeHngbuVxK8P5WNsmoODx7VTabbZKxbQkzQcu85Uy85gKH1 uI8cgG1xfQs7Q== Subject: [PATCH 2/2] MdeModulePkg/SdMmcPciHcDxe: Allow additional SDHCI versions X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 05 Oct 2018 17:13:44 -0000 Content-Type: text/plain Clock control is similar in SDHCI versions greater then version 3. Add support for more recent versions of the controller specification. SD card support for 1.8V is also present in controller versions 3 and greater. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jeff Brasen --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 2 +- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c index d3f77ed..12b4659 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c @@ -978,7 +978,7 @@ SdCardIdentification ( return Status; } - if ((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_300) { + if ((ControllerVer & 0xFF) >= SD_MMC_HC_CTRL_VER_300) { S18r = TRUE; } else if (((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_100) || ((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_200)) { S18r = FALSE; diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index 3b9a184..de282bf 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -782,7 +782,7 @@ SdMmcHcClockSupply ( // // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register. // - if ((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_300) { + if ((ControllerVer & 0xFF) >= SD_MMC_HC_CTRL_VER_300) { ASSERT (Divisor <= 0x3FF); ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2); } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) { -- 2.7.4 ----------------------------------------------------------------------------------- This email message is for the sole use of the intended recipient(s) and may contain confidential information. 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