From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web12.5143.1628258781905588759 for ; Fri, 06 Aug 2021 07:06:22 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: jeremy.linton@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7C2CC31B; Fri, 6 Aug 2021 07:06:20 -0700 (PDT) Received: from [192.168.122.166] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2EC5D3F719; Fri, 6 Aug 2021 07:06:20 -0700 (PDT) Subject: Re: [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4 To: Ard Biesheuvel Cc: edk2-devel-groups-io , Peter Batard , Ard Biesheuvel , Andrei Warkentin , Sunny Wang , Samer El-Haj-Mahmoud , =?UTF-8?Q?Ren=c3=a9_Treffer?= References: <20210805163551.488035-1-jeremy.linton@arm.com> <20210805163551.488035-5-jeremy.linton@arm.com> From: "Jeremy Linton" Message-ID: Date: Fri, 6 Aug 2021 09:06:14 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: quoted-printable Hi, On 8/6/21 8:42 AM, Ard Biesheuvel wrote: > On Thu, 5 Aug 2021 at 18:36, Jeremy Linton wrot= e: >> >> The CM4 has an actual pcie slot, so we need to move the linkup >> check to the configuration probe logic. Further the device >> restriction logic needs to be relaxed to support downstream >> PCIe switches. >> >> Suggested-by: Ren=C3=A9 Treffer >> Signed-off-by: Jeremy Linton >=20 > Please split this into two patches. Your talking about the linkup move, vs expanding the dev<0 check? Ok. >=20 >> --- >> .../Bcm2711PciHostBridgeLibConstructor.c | 5 ----- >> .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 24 ++++++++++++= +++------- >> 2 files changed, 17 insertions(+), 12 deletions(-) >> >> diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/= Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/B= cm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c >> index 8587d2d36d..4d4c584726 100644 >> --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711= PciHostBridgeLibConstructor.c >> +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711= PciHostBridgeLibConstructor.c >> @@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor ( >> } while (((Data & 0x30) !=3D 0x030) && (Timeout)); >> DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=3D%x) Timeout=3D%d= \n", Data, Timeout)); >> >> - if ((Data & 0x30) !=3D 0x30) { >> - DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=3D%x)\n", Data)= ); >> - return EFI_DEVICE_ERROR; >> - } >> - >> if ((Data & 0x80) !=3D 0x80) { >> DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=3D%x)\n",= Data)); >> return EFI_UNSUPPORTED; >> diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/Pci= SegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciS= egmentLib.c >> index 44ce3b4b99..3ccc131eab 100644 >> --- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegment= Lib.c >> +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegment= Lib.c >> @@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase ( >> UINT64 Base; >> UINT64 Offset; >> UINT32 Dev; >> + UINT32 Bus; >> + UINT32 Data; >> >> Base =3D PCIE_REG_BASE; >> Offset =3D Address & 0xFFF; /* Pick off the 4k register of= fset */ >> @@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase ( >> Base +=3D PCIE_EXT_CFG_DATA; >> if (mPciSegmentLastAccess !=3D Address) { >> Dev =3D EFI_PCI_ADDR_DEV (Address); >> + Bus =3D EFI_PCI_ADDR_BUS (Address); >> + >> /* >> - * Scan things out directly rather than translating the "bus" t= o a device, etc.. >> - * only we need to limit each bus to a single device. >> + * There can only be a single device on bus 1 (downstream of ro= ot). >> + * Subsequent busses (behind a PCIe switch) can have more. >> */ >> - if (Dev < 1) { >> - MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); >> - mPciSegmentLastAccess =3D Address; >> - } else { >> - mPciSegmentLastAccess =3D 0; >> + if (Dev > 0 && (Bus < 2)) { >> return 0xFFFFFFFF; >> } >> + >> + /* Don't probe slots if the link is down */ >> + Data =3D MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS); >> + if ((Data & 0x30) !=3D 0x30) { >> + DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=3D%x)\n",= Data)); >> + return 0xFFFFFFFF; >> + } >> + >> + MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address); >> + mPciSegmentLastAccess =3D Address; >> } >> } >> return Base + Offset; >> -- >> 2.13.7 >>