From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.115; helo=mga14.intel.com; envelope-from=star.zeng@intel.com; receiver=edk2-devel@lists.01.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E562C2117D77E for ; Wed, 24 Oct 2018 19:56:21 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Oct 2018 19:56:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,422,1534834800"; d="scan'208";a="85395036" Received: from shzintpr02.sh.intel.com (HELO [10.7.209.51]) ([10.239.4.160]) by orsmga006.jf.intel.com with ESMTP; 24 Oct 2018 19:56:18 -0700 To: Jian J Wang , edk2-devel@lists.01.org Cc: Michael D Kinney , Ruiyu Ni , Jiewen Yao , Laszlo Ersek , star.zeng@intel.com References: <20181024052620.4088-1-jian.j.wang@intel.com> <20181024052620.4088-2-jian.j.wang@intel.com> From: "Zeng, Star" Message-ID: Date: Thu, 25 Oct 2018 10:55:48 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20181024052620.4088-2-jian.j.wang@intel.com> Subject: Re: [PATCH v3 1/6] MdeModulePkg: cleanup Heap Guard pool/page type PCD documentation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 25 Oct 2018 02:56:22 -0000 Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit On 2018/10/24 13:26, Jian J Wang wrote: >> v3 changes: >> a. split from #1 patch of v2 >> b. update title > > This cleanup is meant for avoiding misuse of newly introduced BIT4 > (UAF detection) of PCD PcdHeapGuardPropertyMask, because it applies > to all types of physical memory. In another words, > PcdHeapGuardPoolType and PcdHeapGuardPageType don't have effect to > the BIT4 of PcdHeapGuardPropertyMask. > > Cc: Star Zeng > Cc: Michael D Kinney > Cc: Jiewen Yao > Cc: Ruiyu Ni > Cc: Laszlo Ersek > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Jian J Wang Reviewed-by: Star Zeng You may can add Laszlo's RB and even Suggested-by according to Laszlo's feedback to V2 patch series. Thanks, Star > --- > MdeModulePkg/MdeModulePkg.dec | 4 ++++ > MdeModulePkg/MdeModulePkg.uni | 2 ++ > 2 files changed, 6 insertions(+) > > diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec > index 6037504fa7..2009dbc5fd 100644 > --- a/MdeModulePkg/MdeModulePkg.dec > +++ b/MdeModulePkg/MdeModulePkg.dec > @@ -955,6 +955,8 @@ > # free pages for all of them. The page allocation for the type related to > # cleared bits keeps the same as ususal. > # > + # This PCD is only valid if BIT0 and/or BIT2 are set in PcdHeapGuardPropertyMask. > + # > # Below is bit mask for this PCD: (Order is same as UEFI spec)
> # EfiReservedMemoryType 0x0000000000000001
> # EfiLoaderCode 0x0000000000000002
> @@ -984,6 +986,8 @@ > # if there's enough free memory for all of them. The pool allocation for the > # type related to cleared bits keeps the same as ususal. > # > + # This PCD is only valid if BIT1 and/or BIT3 are set in PcdHeapGuardPropertyMask. > + # > # Below is bit mask for this PCD: (Order is same as UEFI spec)
> # EfiReservedMemoryType 0x0000000000000001
> # EfiLoaderCode 0x0000000000000002
> diff --git a/MdeModulePkg/MdeModulePkg.uni b/MdeModulePkg/MdeModulePkg.uni > index a6bcb627cf..9d2e473fa9 100644 > --- a/MdeModulePkg/MdeModulePkg.uni > +++ b/MdeModulePkg/MdeModulePkg.uni > @@ -1171,6 +1171,7 @@ > " before and after corresponding type of pages allocated if there's enough\n" > " free pages for all of them. The page allocation for the type related to\n" > " cleared bits keeps the same as ususal.\n\n" > + " This PCD is only valid if BIT0 and/or BIT2 are set in PcdHeapGuardPropertyMask.\n\n" > " Below is bit mask for this PCD: (Order is same as UEFI spec)
\n" > " EfiReservedMemoryType 0x0000000000000001\n" > " EfiLoaderCode 0x0000000000000002\n" > @@ -1198,6 +1199,7 @@ > " before and after corresponding type of pages which the allocated pool occupies,\n" > " if there's enough free memory for all of them. The pool allocation for the\n" > " type related to cleared bits keeps the same as ususal.\n\n" > + " This PCD is only valid if BIT1 and/or BIT3 are set in PcdHeapGuardPropertyMask.\n\n" > " Below is bit mask for this PCD: (Order is same as UEFI spec)
\n" > " EfiReservedMemoryType 0x0000000000000001\n" > " EfiLoaderCode 0x0000000000000002\n" >