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Wed, 22 Apr 2020 17:42:45 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: bcdc4360-fbb2-4f7c-efcf-08d7e6e4916a X-MS-TrafficTypeDiagnostic: DM6PR12MB3673:|DM6PR12MB3673: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-Forefront-PRVS: 03818C953D X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM6PR12MB3163.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFTY:;SFS:(10009020)(4636009)(346002)(136003)(396003)(366004)(39860400002)(376002)(16526019)(186003)(8936002)(8676002)(956004)(4326008)(316002)(6916009)(86362001)(2616005)(36756003)(26005)(52116002)(7696005)(5660300002)(19627235002)(2906002)(478600001)(81156014)(966005)(66556008)(66946007)(66476007)(6486002)(54906003)(136400200001);DIR:OUT;SFP:1101; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DfflVnYkTxJCzSUPgYUpY2OqLcrzRoBX4D23uXSCHk1AbzD31Bm5xZJNjoEGHd2Cgn9l+IzyMSM95bD8ypwgwfS4ZMqTUVxEqeRXBfs0sB2qeYNI7xEI/Go6TzzWOivOjApken2vhAU6AeIyN5z9mQ32d1JcTuko5oeg1/b4OXCjp4LGCHSv1ulFnt3MIkSWtXKeKRaTLAbLNvoZrVAg1j+uuJmcpMpzuUAcQ/G6wPQ5mPiJ5TAdogUZWiG7A/bYPI7LjMBe94ZJ/aT/I60WMsM47bb/FO3W4SzXe3hd9qmi9P2QERT4zxD5JWGTGt8DOnIy6bP1jywpFSuuqLViSHaQCO78JxV072xKcdUEVMMST0YVBu+0DvEs9eGHSRJzE1Uo/9f9jc+5Ss0Hj+mfLHUGtnQ+l8VaDzIBPqGO8Og15KHvqCIX1Lua4ohLMXiR3a5mK8Cr6oZutJLd/g5EAefym3tG/AgtIQ/7zmogi4Bti2JQpSa3EQDmG7w55Cvz8sfeDaw6Bqh1cA+JjNLG/scHq+Deap+HHpuKtFLB2dtvMCQ1E2bAkCH3rpSN1kA05wNOBSBlGkSes5TB1ZOX5w== X-MS-Exchange-AntiSpam-MessageData: pe/3oTI+ALkP44sS3geIRTKXV0TXD015u3RQn0Aa7DvFxQx76gE0T+DVHeSey4ctsfoQTAq3QbxdBoc5ntp4WyypLrTYRV2KOEf2shfAw32VVOn84L4F3e3hogy1pgMejQuGeyp7tEh2l8+53UKwSA== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: bcdc4360-fbb2-4f7c-efcf-08d7e6e4916a X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Apr 2020 17:42:46.4420 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: WJs/DtwEg4dRciRg66uOhWC6LKiY0VIRKKJsn6fVlBJDNzeU/qI4Oa2T3TXlL+oHneUa3FubIueYZkJ6Js19lw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3673 Content-Type: text/plain BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 Allocate memory for the GHCB pages and the per-CPU variable pages during SEV initialization for use during Pei and Dxe phases. The GHCB page(s) must be shared pages, so clear the encryption mask from the current page table entries. Upon successful allocation, set the GHCB PCDs (PcdGhcbBase and PcdGhcbSize). The per-CPU variable page needs to be unique per AP. Using the page after the GHCB ensures that it is unique per AP. Only the GHCB page is marked as shared, keeping the per-CPU variable page encyrpted. The same logic is used in DXE using CreateIdentityMappingPageTables() before switching to the DXE pagetables. The GHCB pages (one per vCPU) will be used by the PEI and DXE #VC exception handlers. The #VC exception handler will fill in the necessary fields of the GHCB and exit to the hypervisor using the VMGEXIT instruction. The hypervisor then accesses the GHCB associated with the vCPU in order to perform the requested function. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/OvmfPkgIa32.dsc | 2 ++ OvmfPkg/OvmfPkgIa32X64.dsc | 2 ++ OvmfPkg/OvmfPkgX64.dsc | 2 ++ OvmfPkg/PlatformPei/PlatformPei.inf | 2 ++ OvmfPkg/PlatformPei/AmdSev.c | 45 ++++++++++++++++++++++++++++- 5 files changed, 52 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 95423942101f..dfe8f0210b92 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -587,6 +587,8 @@ [PcdsDynamicDefault] gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0 # Set SEV-ES defaults + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0 gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 !if $(SMM_REQUIRE) == TRUE diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 37bbf2073494..b0ee4413581a 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -598,6 +598,8 @@ [PcdsDynamicDefault] gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0 # Set SEV-ES defaults + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0 gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 !if $(SMM_REQUIRE) == TRUE diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 5248e6fd92a8..39eceb422f42 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -597,6 +597,8 @@ [PcdsDynamicDefault] gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0 # Set SEV-ES defaults + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0 gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 !if $(SMM_REQUIRE) == TRUE diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/PlatformPei.inf index c5b92ab4afd8..fcab78e3d20c 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -100,6 +100,8 @@ [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber diff --git a/OvmfPkg/PlatformPei/AmdSev.c b/OvmfPkg/PlatformPei/AmdSev.c index 4dc5340caa7a..4fd4534cabea 100644 --- a/OvmfPkg/PlatformPei/AmdSev.c +++ b/OvmfPkg/PlatformPei/AmdSev.c @@ -10,12 +10,15 @@ // The package level header files this module uses // #include +#include #include #include #include +#include #include #include #include +#include #include #include @@ -32,7 +35,10 @@ AmdSevEsInitialize ( VOID ) { - RETURN_STATUS PcdStatus; + VOID *GhcbBase; + PHYSICAL_ADDRESS GhcbBasePa; + UINTN GhcbPageCount, PageCount; + RETURN_STATUS PcdStatus, DecryptStatus; if (!MemEncryptSevEsIsEnabled ()) { return; @@ -40,6 +46,43 @@ AmdSevEsInitialize ( PcdStatus = PcdSetBoolS (PcdSevEsIsEnabled, TRUE); ASSERT_RETURN_ERROR (PcdStatus); + + // + // Allocate GHCB and per-CPU variable pages. + // + GhcbPageCount = mMaxCpuCount * 2; + GhcbBase = AllocatePages (GhcbPageCount); + ASSERT (GhcbBase != NULL); + + GhcbBasePa = (PHYSICAL_ADDRESS)(UINTN) GhcbBase; + + // + // Each vCPU gets two consecutive pages, the first is the GHCB and the + // second is the per-CPU variable page. Loop through the allocation and + // only clear the encryption mask for the GHCB pages. + // + for (PageCount = 0; PageCount < GhcbPageCount; PageCount += 2) { + DecryptStatus = MemEncryptSevClearPageEncMask ( + 0, + GhcbBasePa + EFI_PAGES_TO_SIZE (PageCount), + 1, + TRUE + ); + ASSERT_RETURN_ERROR (DecryptStatus); + } + + ZeroMem (GhcbBase, EFI_PAGES_TO_SIZE (GhcbPageCount)); + + PcdStatus = PcdSet64S (PcdGhcbBase, GhcbBasePa); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus = PcdSet64S (PcdGhcbSize, EFI_PAGES_TO_SIZE (GhcbPageCount)); + ASSERT_RETURN_ERROR (PcdStatus); + + DEBUG ((DEBUG_INFO, + "SEV-ES is enabled, %lu GHCB pages allocated starting at 0x%p\n", + (UINT64)GhcbPageCount, GhcbBase)); + + AsmWriteMsr64 (MSR_SEV_ES_GHCB, GhcbBasePa); } /** -- 2.17.1