* [edk2-staging/RISC-V-V2 PATCH v3 01/39] RiscVPkg: RISC-V processor package.
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 02/39] RiscVPkg/Include: Add header files of RISC-V CPU package Abner Chang
` (37 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
- Add RiscVPkg package which provides RISC-V processor related
drivers and libraries.
- Support RISC-V OpenSBI and RISC-V platforms
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
RiscVPkg/RiscVPkg.dec | 26 +++++++++++++
RiscVPkg/RiscVPkg.dsc | 92 ++++++++++++++++++++++++++++++++++++++++++++++
RiscVPkg/RiscVPkg.uni | 13 +++++++
| 13 +++++++
4 files changed, 144 insertions(+)
create mode 100644 RiscVPkg/RiscVPkg.dec
create mode 100644 RiscVPkg/RiscVPkg.dsc
create mode 100644 RiscVPkg/RiscVPkg.uni
create mode 100644 RiscVPkg/RiscVPkgExtra.uni
diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec
new file mode 100644
index 0000000..d01d76f
--- /dev/null
+++ b/RiscVPkg/RiscVPkg.dec
@@ -0,0 +1,26 @@
+## @file RiscVPkg.dec
+# This Package provides UEFI RISC-V modules and libraries.
+#
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001b
+ PACKAGE_NAME = RiscVPkg
+ PACKAGE_UNI_FILE = RiscVPkg.uni
+ PACKAGE_GUID = 993C7CAC-C87C-4F08-A2CF-AD3AABA859D1
+ PACKAGE_VERSION = 1.0
+
+[Includes]
+ Include
+ Library/RiscVOpensbiLib/opensbi # OpenSBI header file reference ("include/sbi/...")
+ Library/RiscVOpensbiLib/opensbi/include # Header file reference from opensbi files, ("sbi/...")
+
+[Guids]
+ gUefiRiscVPkgTokenSpaceGuid = { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ RiscVPkgExtra.uni
diff --git a/RiscVPkg/RiscVPkg.dsc b/RiscVPkg/RiscVPkg.dsc
new file mode 100644
index 0000000..307d17b
--- /dev/null
+++ b/RiscVPkg/RiscVPkg.dsc
@@ -0,0 +1,92 @@
+#/** @file
+# RISC-V package.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+################################################################################
+#
+# Defines Section
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = RiscV
+ PLATFORM_GUID = 55D77916-B270-41B4-9325-2CE9DCE0926E
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001c
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = RISCV64
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+
+[BuildOptions]
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ GCC:*_*_RISCV64_GENFW_FLAGS = --keepexceptiontable
+!endif
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this Platform.
+#
+################################################################################
+[SkuIds]
+ 0|DEFAULT
+
+[LibraryClasses.common]
+ CpuExceptionHandlerLib|RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
+ RiscVCpuLib|RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
+ RiscVOpensbiLib|RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
+ TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
+ RiscVPlatformTimerLib|RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
+
+[LibraryClasses.common.PEI_CORE]
+ PeiServicesTablePointerLib|RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+
+[LibraryClasses.common.PEIM]
+ PeiServicesTablePointerLib|RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
+ RiscVPlatformDxeIplLib|RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+
+[LibraryClasses.common.DXE_CORE]
+ TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ PlatformBootManagerLib|RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
+
+[Components]
+ RiscVPkg/Universal/CpuDxe/CpuDxe.inf
+ RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
+
diff --git a/RiscVPkg/RiscVPkg.uni b/RiscVPkg/RiscVPkg.uni
new file mode 100644
index 0000000..5ec7a99
--- /dev/null
+++ b/RiscVPkg/RiscVPkg.uni
@@ -0,0 +1,13 @@
+// /** @file
+// RISC-V Package Localized Strings and Content.
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PACKAGE_ABSTRACT #language en-US "Provides UEFI compatible RISC-V modules and libraries"
+
+#string STR_PACKAGE_DESCRIPTION #language en-US "This Package provides UEFI compatible RISC-V modules and libraries."
+
--git a/RiscVPkg/RiscVPkgExtra.uni b/RiscVPkg/RiscVPkgExtra.uni
new file mode 100644
index 0000000..b50a6b4
--- /dev/null
+++ b/RiscVPkg/RiscVPkgExtra.uni
@@ -0,0 +1,13 @@
+// /** @file
+// RISC-V Package Localized Strings and Content.
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PROPERTIES_PACKAGE_NAME
+#language en-US
+"RiscV package"
+
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 02/39] RiscVPkg/Include: Add header files of RISC-V CPU package
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 01/39] RiscVPkg: RISC-V processor package Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 03/39] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support Abner Chang
` (36 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
RISC-V package library definitions.
IndustryStandard/RiscV.h
-Add RiscV.h which conform with RISC-V Privilege Spec v1.10.
RiscVImpl.h
-Definition of EDK2 RISC-V implementation.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
RiscVPkg/Include/IndustryStandard/RiscV.h | 118 ++++++++++++++++++++++++++++++
RiscVPkg/Include/RiscVImpl.h | 72 ++++++++++++++++++
2 files changed, 190 insertions(+)
create mode 100644 RiscVPkg/Include/IndustryStandard/RiscV.h
create mode 100644 RiscVPkg/Include/RiscVImpl.h
diff --git a/RiscVPkg/Include/IndustryStandard/RiscV.h b/RiscVPkg/Include/IndustryStandard/RiscV.h
new file mode 100644
index 0000000..56aed81
--- /dev/null
+++ b/RiscVPkg/Include/IndustryStandard/RiscV.h
@@ -0,0 +1,118 @@
+/** @file
+ RISC-V package definitions.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_INDUSTRY_STANDARD_H_
+#define RISCV_INDUSTRY_STANDARD_H_
+
+#if defined (MDE_CPU_RISCV64)
+#define RISC_V_XLEN_BITS 64
+#else
+#endif
+
+#define RISC_V_ISA_ATOMIC_EXTENSION (0x00000001 << 0)
+#define RISC_V_ISA_BIT_OPERATION_EXTENSION (0x00000001 << 1)
+#define RISC_V_ISA_COMPRESSED_EXTENSION (0x00000001 << 2)
+#define RISC_V_ISA_DOUBLE_PRECISION_FP_EXTENSION (0x00000001 << 3)
+#define RISC_V_ISA_RV32E_ISA (0x00000001 << 4)
+#define RISC_V_ISA_SINGLE_PRECISION_FP_EXTENSION (0x00000001 << 5)
+#define RISC_V_ISA_ADDITIONAL_STANDARD_EXTENSION (0x00000001 << 6)
+#define RISC_V_ISA_RESERVED_1 (0x00000001 << 7)
+#define RISC_V_ISA_INTEGER_ISA_EXTENSION (0x00000001 << 8)
+#define RISC_V_ISA_DYNAMICALLY_TRANSLATED_LANGUAGE_EXTENSION (0x00000001 << 9)
+#define RISC_V_ISA_RESERVED_2 (0x00000001 << 10)
+#define RISC_V_ISA_DECIMAL_FP_EXTENSION (0x00000001 << 11)
+#define RISC_V_ISA_INTEGER_MUL_DIV_EXTENSION (0x00000001 << 12)
+#define RISC_V_ISA_USER_LEVEL_INTERRUPT_SUPPORTED (0x00000001 << 13)
+#define RISC_V_ISA_RESERVED_3 (0x00000001 << 14)
+#define RISC_V_ISA_PACKED_SIMD_EXTENSION (0x00000001 << 15)
+#define RISC_V_ISA_QUAD_PRECISION_FP_EXTENSION (0x00000001 << 16)
+#define RISC_V_ISA_RESERVED_4 (0x00000001 << 17)
+#define RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED (0x00000001 << 18)
+#define RISC_V_ISA_TRANSATIONAL_MEMORY_EXTENSION (0x00000001 << 19)
+#define RISC_V_ISA_USER_MODE_IMPLEMENTED (0x00000001 << 20)
+#define RISC_V_ISA_VECTOR_EXTENSION (0x00000001 << 21)
+#define RISC_V_ISA_RESERVED_5 (0x00000001 << 22)
+#define RISC_V_ISA_NON_STANDARD_EXTENSION (0x00000001 << 23)
+#define RISC_V_ISA_RESERVED_6 (0x00000001 << 24)
+#define RISC_V_ISA_RESERVED_7 (0x00000001 << 25)
+
+//
+// RISC-V CSR definitions.
+//
+//
+// Machine information
+//
+#define RISCV_CSR_MACHINE_MVENDORID 0xF11
+#define RISCV_CSR_MACHINE_MARCHID 0xF12
+#define RISCV_CSR_MACHINE_MIMPID 0xF13
+#define RISCV_CSR_MACHINE_HARRID 0xF14
+//
+// Machine Trap Setup.
+//
+#define RISCV_CSR_MACHINE_MSTATUS 0x300
+#define RISCV_CSR_MACHINE_MISA 0x301
+#define RISCV_CSR_MACHINE_MEDELEG 0x302
+#define RISCV_CSR_MACHINE_MIDELEG 0x303
+#define RISCV_CSR_MACHINE_MIE 0x304
+#define RISCV_CSR_MACHINE_MTVEC 0x305
+
+#define RISCV_TIMER_COMPARE_BITS 32
+//
+// Machine Timer and Counter.
+//
+//#define RISCV_CSR_MACHINE_MTIME 0x701
+//#define RISCV_CSR_MACHINE_MTIMEH 0x741
+//
+// Machine Trap Handling.
+//
+#define RISCV_CSR_MACHINE_MSCRATCH 0x340
+#define RISCV_CSR_MACHINE_MEPC 0x341
+#define RISCV_CSR_MACHINE_MCAUSE 0x342
+ #define MACHINE_MCAUSE_EXCEPTION_ MASK 0x0f
+ #define MACHINE_MCAUSE_INTERRUPT (RISC_V_XLEN_BITS - 1)
+#define RISCV_CSR_MACHINE_MBADADDR 0x343
+#define RISCV_CSR_MACHINE_MIP 0x344
+
+//
+// Machine Protection and Translation.
+//
+#define RISCV_CSR_MACHINE_MBASE 0x380
+#define RISCV_CSR_MACHINE_MBOUND 0x381
+#define RISCV_CSR_MACHINE_MIBASE 0x382
+#define RISCV_CSR_MACHINE_MIBOUND 0x383
+#define RISCV_CSR_MACHINE_MDBASE 0x384
+#define RISCV_CSR_MACHINE_MDBOUND 0x385
+
+//
+// Supervisor mode CSR.
+//
+#define RISCV_CSR_SUPERVISOR_SSCRATCH 0x140
+#define RISCV_CSR_SUPERVISOR_SEPC 0x141
+#define RISCV_CSR_SUPERVISOR_SCAUSE 0x142
+ #define SCAUSE_USER_SOFTWARE_INT 0
+ #define SCAUSE_SUPERVISOR_SOFTWARE_INT 1
+ #define SCAUSE_USER_TIMER_INT 4
+ #define SCAUSE_SUPERVISOR_TIMER_INT 5
+ #define SCAUSE_USER_EXTERNAL_INT 8
+ #define SCAUSE_SUPERVISOR_EXTERNAL_INT 9
+#define RISCV_CSR_SUPERVISOR_STVAL 0x143
+#define RISCV_CSR_SUPERVISOR_SIP 0x144
+
+//
+// Machine Read-Write Shadow of Hypervisor Read-Only Registers
+//
+#define RISCV_CSR_HTIMEW 0xB01
+#define RISCV_CSR_HTIMEHW 0xB81
+//
+// Machine Host-Target Interface (Non-Standard Berkeley Extension)
+//
+#define RISCV_CSR_MTOHOST 0x780
+#define RISCV_CSR_MFROMHOST 0x781
+
+#endif
diff --git a/RiscVPkg/Include/RiscVImpl.h b/RiscVPkg/Include/RiscVImpl.h
new file mode 100644
index 0000000..1629266
--- /dev/null
+++ b/RiscVPkg/Include/RiscVImpl.h
@@ -0,0 +1,72 @@
+/** @file
+ RISC-V package definitions.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_H_
+#define RISCV_H_
+
+#include <IndustryStandard/RiscV.h>
+
+//
+// Structure for 128-bit value
+//
+typedef struct {
+ UINT64 Value64_L;
+ UINT64 Value64_H;
+} RISCV_UINT128;
+
+#define RISCV_MACHINE_CONTEXT_SIZE 0x1000
+typedef struct _RISCV_MACHINE_MODE_CONTEXT RISCV_MACHINE_MODE_CONTEXT;
+
+///
+/// Exception handlers in context.
+///
+typedef struct _EXCEPTION_HANDLER_CONTEXT {
+ EFI_PHYSICAL_ADDRESS InstAddressMisalignedHander;
+ EFI_PHYSICAL_ADDRESS InstAccessFaultHander;
+ EFI_PHYSICAL_ADDRESS IllegalInstHander;
+ EFI_PHYSICAL_ADDRESS BreakpointHander;
+ EFI_PHYSICAL_ADDRESS LoadAddrMisalignedHander;
+ EFI_PHYSICAL_ADDRESS LoadAccessFaultHander;
+ EFI_PHYSICAL_ADDRESS StoreAmoAddrMisalignedHander;
+ EFI_PHYSICAL_ADDRESS StoreAmoAccessFaultHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromUModeHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromSModeHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromHModeHander;
+ EFI_PHYSICAL_ADDRESS EnvCallFromMModeHander;
+} EXCEPTION_HANDLER_CONTEXT;
+
+///
+/// Exception handlers in context.
+///
+typedef struct _INTERRUPT_HANDLER_CONTEXT {
+ EFI_PHYSICAL_ADDRESS SoftwareIntHandler;
+ EFI_PHYSICAL_ADDRESS TimerIntHandler;
+} INTERRUPT_HANDLER_CONTEXT;
+
+///
+/// Interrupt handlers in context.
+///
+typedef struct _TRAP_HANDLER_CONTEXT {
+ EXCEPTION_HANDLER_CONTEXT ExceptionHandlerContext;
+ INTERRUPT_HANDLER_CONTEXT IntHandlerContext;
+} TRAP_HANDLER_CONTEXT;
+
+///
+/// Machine mode context used for saveing hart-local context.
+///
+typedef struct _RISCV_MACHINE_MODE_CONTEXT {
+ EFI_PHYSICAL_ADDRESS PeiService; /// PEI service.
+ EFI_PHYSICAL_ADDRESS MachineModeTrapHandler; /// Machine mode trap handler.
+ EFI_PHYSICAL_ADDRESS HypervisorModeTrapHandler; /// Hypervisor mode trap handler.
+ EFI_PHYSICAL_ADDRESS SupervisorModeTrapHandler; /// Supervisor mode trap handler.
+ EFI_PHYSICAL_ADDRESS UserModeTrapHandler; /// USer mode trap handler.
+ TRAP_HANDLER_CONTEXT MModeHandler; /// Handler for machine mode.
+} RISCV_MACHINE_MODE_CONTEXT;
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 03/39] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 01/39] RiscVPkg: RISC-V processor package Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 02/39] RiscVPkg/Include: Add header files of RISC-V CPU package Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-11-21 16:24 ` Leif Lindholm
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 04/39] MdePkg: RISC-V RV64 binding in MdePkg Abner Chang
` (35 subsequent siblings)
38 siblings, 1 reply; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
Add EDK2 RISC-V OpenSBI header files.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
RiscVPkg/Include/sbi/SbiFirmwareContext.h | 33 ++++++++++++++++++++
RiscVPkg/Include/sbi/sbi.h | 52 +++++++++++++++++++++++++++++++
RiscVPkg/Include/sbi/sbi_bits.h | 17 ++++++++++
RiscVPkg/Include/sbi/sbi_types.h | 45 ++++++++++++++++++++++++++
4 files changed, 147 insertions(+)
create mode 100644 RiscVPkg/Include/sbi/SbiFirmwareContext.h
create mode 100644 RiscVPkg/Include/sbi/sbi.h
create mode 100644 RiscVPkg/Include/sbi/sbi_bits.h
create mode 100644 RiscVPkg/Include/sbi/sbi_types.h
diff --git a/RiscVPkg/Include/sbi/SbiFirmwareContext.h b/RiscVPkg/Include/sbi/SbiFirmwareContext.h
new file mode 100644
index 0000000..c3d3489
--- /dev/null
+++ b/RiscVPkg/Include/sbi/SbiFirmwareContext.h
@@ -0,0 +1,33 @@
+/** @file
+ RISC-V OpesbSBI Platform Firmware context definition
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SBI_FIRMWARE_CONTEXT_H_
+#define SBI_FIRMWARE_CONTEXT_H_
+
+#include <RiscVImpl.h>
+
+#define RISC_V_MAX_HART_SUPPORTED 16
+
+//
+// keep the structure member in 64-bit alignment.
+//
+typedef struct {
+ UINT64 IsaExtensionSupported; // The ISA extension this core supported.
+ RISCV_UINT128 MachineVendorId; // Machine vendor ID
+ RISCV_UINT128 MachineArchId; // Machine Architecture ID
+ RISCV_UINT128 MachineImplId; // Machine Implementation ID
+} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC;
+
+#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 7)
+
+typedef struct {
+ VOID *PeiServiceTable; // PEI Service table
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_SUPPORTED];
+} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;
+#endif
+
diff --git a/RiscVPkg/Include/sbi/sbi.h b/RiscVPkg/Include/sbi/sbi.h
new file mode 100644
index 0000000..04e7f18
--- /dev/null
+++ b/RiscVPkg/Include/sbi/sbi.h
@@ -0,0 +1,52 @@
+/** @file
+ SBI inline function calls.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef EDK2_SBI_H_
+#define EDK2_SBI_H_
+
+#include <sbi/sbi_types.h> // Reference to header file wrapper
+#include <include/sbi/riscv_asm.h> // Reference to header file in opensbi
+
+#define SBI_SET_TIMER 0
+#define SBI_CONSOLE_PUTCHAR 1
+#define SBI_CONSOLE_GETCHAR 2
+#define SBI_CLEAR_IPI 3
+#define SBI_SEND_IPI 4
+#define SBI_REMOTE_FENCE_I 5
+#define SBI_REMOTE_SFENCE_VMA 6
+#define SBI_REMOTE_SFENCE_VMA_ASID 7
+#define SBI_SHUTDOWN 8
+
+#define SBI_CALL(which, arg0, arg1, arg2) ({ \
+ register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
+ register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
+ register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
+ register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \
+ asm volatile ("ecall" \
+ : "+r" (a0) \
+ : "r" (a1), "r" (a2), "r" (a7) \
+ : "memory"); \
+ a0; \
+})
+
+#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0)
+#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0)
+#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0)
+
+#define sbi_console_putchar(ch) SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch)
+#define sbi_console_getchar() SBI_CALL_0(SBI_CONSOLE_GETCHAR)
+#define sbi_set_timer(stime_value) SBI_CALL_1(SBI_SET_TIMER, stime_value)
+#define sbi_shutdown() SBI_CALL_0(SBI_SHUTDOWN)
+#define sbi_clear_ipi() SBI_CALL_0(SBI_CLEAR_IPI)
+#define sbi_send_ipi(hart_mask) SBI_CALL_1(SBI_SEND_IPI, hart_mask)
+#define sbi_remote_fence_i(hart_mask) SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask)
+#define sbi_remote_sfence_vma(hart_mask, start, size) SBI_CALL_1(SBI_REMOTE_SFENCE_VMA, hart_mask)
+#define sbi_remote_sfence_vma_asid(hart_mask, start, size, asid) SBI_CALL_1(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask)
+
+#endif
diff --git a/RiscVPkg/Include/sbi/sbi_bits.h b/RiscVPkg/Include/sbi/sbi_bits.h
new file mode 100644
index 0000000..c935547
--- /dev/null
+++ b/RiscVPkg/Include/sbi/sbi_bits.h
@@ -0,0 +1,17 @@
+/** @file
+ RISC-V OpesbSBI header file reference.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef EDK2_SBI_BITS_H_
+#define EDK2_SBI_BITS_H_
+
+#undef MAX
+#undef MIN
+
+#include "include/sbi/sbi_bits.h" // Reference to header file in opensbi
+
+#endif
diff --git a/RiscVPkg/Include/sbi/sbi_types.h b/RiscVPkg/Include/sbi/sbi_types.h
new file mode 100644
index 0000000..95ee213
--- /dev/null
+++ b/RiscVPkg/Include/sbi/sbi_types.h
@@ -0,0 +1,45 @@
+/** @file
+ RISC-V OpesbSBI header file reference.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef EDK2_SBI_TYPES_H_
+#define EDK2_SBI_TYPES_H_
+
+typedef INT8 s8;
+typedef UINT8 u8;
+typedef UINT8 uint8_t;
+
+typedef INT16 s16;
+typedef UINT16 u16;
+typedef INT16 int16_t;
+typedef UINT16 uint16_t;
+
+typedef INT32 s32;
+typedef UINT32 u32;
+typedef INT32 int32_t;
+typedef UINT32 uint32_t;
+
+typedef INT64 s64;
+typedef UINT64 u64;
+typedef INT64 int64_t;
+typedef UINT64 uint64_t;
+
+#define PRILX "016lx"
+
+typedef INT32 bool;
+typedef unsigned long ulong;
+typedef UINT64 uintptr_t;
+typedef UINT64 size_t;
+typedef INT64 ssize_t;
+typedef UINT64 virtual_addr_t;
+typedef UINT64 virtual_size_t;
+typedef UINT64 physical_addr_t;
+typedef UINT64 physical_size_t;
+
+#define __packed __attribute__((packed))
+#define __noreturn __attribute__((noreturn))
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* Re: [edk2-staging/RISC-V-V2 PATCH v3 03/39] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 03/39] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support Abner Chang
@ 2019-11-21 16:24 ` Leif Lindholm
2019-12-19 4:09 ` [edk2-devel] " Abner Chang
0 siblings, 1 reply; 77+ messages in thread
From: Leif Lindholm @ 2019-11-21 16:24 UTC (permalink / raw)
To: Abner Chang; +Cc: devel, Gilbert Chen, Palmer Dabbelt, Kinney, Michael D
On Mon, Oct 28, 2019 at 09:58:41 +0800, Abner Chang wrote:
> Add EDK2 RISC-V OpenSBI header files.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Gilbert Chen <gilbert.chen@hpe.com>
> ---
> RiscVPkg/Include/sbi/SbiFirmwareContext.h | 33 ++++++++++++++++++++
> RiscVPkg/Include/sbi/sbi.h | 52 +++++++++++++++++++++++++++++++
> RiscVPkg/Include/sbi/sbi_bits.h | 17 ++++++++++
> RiscVPkg/Include/sbi/sbi_types.h | 45 ++++++++++++++++++++++++++
> 4 files changed, 147 insertions(+)
> create mode 100644 RiscVPkg/Include/sbi/SbiFirmwareContext.h
> create mode 100644 RiscVPkg/Include/sbi/sbi.h
> create mode 100644 RiscVPkg/Include/sbi/sbi_bits.h
> create mode 100644 RiscVPkg/Include/sbi/sbi_types.h
>
> diff --git a/RiscVPkg/Include/sbi/SbiFirmwareContext.h b/RiscVPkg/Include/sbi/SbiFirmwareContext.h
> new file mode 100644
> index 0000000..c3d3489
> --- /dev/null
> +++ b/RiscVPkg/Include/sbi/SbiFirmwareContext.h
> @@ -0,0 +1,33 @@
> +/** @file
> + RISC-V OpesbSBI Platform Firmware context definition
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#ifndef SBI_FIRMWARE_CONTEXT_H_
> +#define SBI_FIRMWARE_CONTEXT_H_
> +
> +#include <RiscVImpl.h>
> +
> +#define RISC_V_MAX_HART_SUPPORTED 16
> +
> +//
> +// keep the structure member in 64-bit alignment.
> +//
> +typedef struct {
> + UINT64 IsaExtensionSupported; // The ISA extension this core supported.
> + RISCV_UINT128 MachineVendorId; // Machine vendor ID
> + RISCV_UINT128 MachineArchId; // Machine Architecture ID
> + RISCV_UINT128 MachineImplId; // Machine Implementation ID
> +} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC;
> +
> +#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 7)
> +
> +typedef struct {
> + VOID *PeiServiceTable; // PEI Service table
> + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartSpecific[RISC_V_MAX_HART_SUPPORTED];
> +} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;
> +#endif
> +
> diff --git a/RiscVPkg/Include/sbi/sbi.h b/RiscVPkg/Include/sbi/sbi.h
> new file mode 100644
> index 0000000..04e7f18
> --- /dev/null
> +++ b/RiscVPkg/Include/sbi/sbi.h
> @@ -0,0 +1,52 @@
> +/** @file
> + SBI inline function calls.
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef EDK2_SBI_H_
> +#define EDK2_SBI_H_
> +
> +#include <sbi/sbi_types.h> // Reference to header file wrapper
> +#include <include/sbi/riscv_asm.h> // Reference to header file in opensbi
This whole sbi situation is too much of a hornets' nest, and really
does need to get sorted before we even push this to -staging.
(But I do think is is one of the last things we need to address.)
And I think the starting point to untangle it is to rename the wrapper
include files in RiscVPkg/Include/sbi (and indeed the directory
itself) to conform with the TianoCore standard.
That means:
RiscVPkg/Include/IndustryStandard/Sbi/Sbi.h
RiscVPkg/Include/IndustryStandard/Sbi/SbiBits.h
RiscVPkg/Include/IndustryStandard/Sbi/SbiTypes.h
Unless all of the wrappers can be combined into a single
RiscVPkg/Include/IndustryStandard/Sbi.h
...and then tested on a case-sensitive filesystem.
For the record, doing that immediately results in the non-wrapper
versions being pulled in and then the build failing.
/
Leif
> +
> +#define SBI_SET_TIMER 0
> +#define SBI_CONSOLE_PUTCHAR 1
> +#define SBI_CONSOLE_GETCHAR 2
> +#define SBI_CLEAR_IPI 3
> +#define SBI_SEND_IPI 4
> +#define SBI_REMOTE_FENCE_I 5
> +#define SBI_REMOTE_SFENCE_VMA 6
> +#define SBI_REMOTE_SFENCE_VMA_ASID 7
> +#define SBI_SHUTDOWN 8
> +
> +#define SBI_CALL(which, arg0, arg1, arg2) ({ \
> + register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
> + register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
> + register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
> + register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \
> + asm volatile ("ecall" \
> + : "+r" (a0) \
> + : "r" (a1), "r" (a2), "r" (a7) \
> + : "memory"); \
> + a0; \
> +})
> +
> +#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0)
> +#define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0)
> +#define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0)
> +
> +#define sbi_console_putchar(ch) SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch)
> +#define sbi_console_getchar() SBI_CALL_0(SBI_CONSOLE_GETCHAR)
> +#define sbi_set_timer(stime_value) SBI_CALL_1(SBI_SET_TIMER, stime_value)
> +#define sbi_shutdown() SBI_CALL_0(SBI_SHUTDOWN)
> +#define sbi_clear_ipi() SBI_CALL_0(SBI_CLEAR_IPI)
> +#define sbi_send_ipi(hart_mask) SBI_CALL_1(SBI_SEND_IPI, hart_mask)
> +#define sbi_remote_fence_i(hart_mask) SBI_CALL_1(SBI_REMOTE_FENCE_I, hart_mask)
> +#define sbi_remote_sfence_vma(hart_mask, start, size) SBI_CALL_1(SBI_REMOTE_SFENCE_VMA, hart_mask)
> +#define sbi_remote_sfence_vma_asid(hart_mask, start, size, asid) SBI_CALL_1(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask)
> +
> +#endif
> diff --git a/RiscVPkg/Include/sbi/sbi_bits.h b/RiscVPkg/Include/sbi/sbi_bits.h
> new file mode 100644
> index 0000000..c935547
> --- /dev/null
> +++ b/RiscVPkg/Include/sbi/sbi_bits.h
> @@ -0,0 +1,17 @@
> +/** @file
> + RISC-V OpesbSBI header file reference.
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#ifndef EDK2_SBI_BITS_H_
> +#define EDK2_SBI_BITS_H_
> +
> +#undef MAX
> +#undef MIN
> +
> +#include "include/sbi/sbi_bits.h" // Reference to header file in opensbi
> +
> +#endif
> diff --git a/RiscVPkg/Include/sbi/sbi_types.h b/RiscVPkg/Include/sbi/sbi_types.h
> new file mode 100644
> index 0000000..95ee213
> --- /dev/null
> +++ b/RiscVPkg/Include/sbi/sbi_types.h
> @@ -0,0 +1,45 @@
> +/** @file
> + RISC-V OpesbSBI header file reference.
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +#ifndef EDK2_SBI_TYPES_H_
> +#define EDK2_SBI_TYPES_H_
> +
> +typedef INT8 s8;
> +typedef UINT8 u8;
> +typedef UINT8 uint8_t;
> +
> +typedef INT16 s16;
> +typedef UINT16 u16;
> +typedef INT16 int16_t;
> +typedef UINT16 uint16_t;
> +
> +typedef INT32 s32;
> +typedef UINT32 u32;
> +typedef INT32 int32_t;
> +typedef UINT32 uint32_t;
> +
> +typedef INT64 s64;
> +typedef UINT64 u64;
> +typedef INT64 int64_t;
> +typedef UINT64 uint64_t;
> +
> +#define PRILX "016lx"
> +
> +typedef INT32 bool;
> +typedef unsigned long ulong;
> +typedef UINT64 uintptr_t;
> +typedef UINT64 size_t;
> +typedef INT64 ssize_t;
> +typedef UINT64 virtual_addr_t;
> +typedef UINT64 virtual_size_t;
> +typedef UINT64 physical_addr_t;
> +typedef UINT64 physical_size_t;
> +
> +#define __packed __attribute__((packed))
> +#define __noreturn __attribute__((noreturn))
> +#endif
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 77+ messages in thread* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 03/39] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support
2019-11-21 16:24 ` Leif Lindholm
@ 2019-12-19 4:09 ` Abner Chang
2019-12-19 13:21 ` Leif Lindholm
0 siblings, 1 reply; 77+ messages in thread
From: Abner Chang @ 2019-12-19 4:09 UTC (permalink / raw)
To: devel@edk2.groups.io, leif.lindholm@linaro.org
Cc: Chen, Gilbert, Palmer Dabbelt, Kinney, Michael D
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Friday, November 22, 2019 12:24 AM
> To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Cc: devel@edk2.groups.io; Chen, Gilbert <gilbert.chen@hpe.com>; Palmer
> Dabbelt <palmer@sifive.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 03/39]
> RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support
>
> On Mon, Oct 28, 2019 at 09:58:41 +0800, Abner Chang wrote:
> > Add EDK2 RISC-V OpenSBI header files.
> >
> > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> >
> > Cc: Leif Lindholm <leif.lindholm@linaro.org>
> > Cc: Gilbert Chen <gilbert.chen@hpe.com>
> > ---
> > RiscVPkg/Include/sbi/SbiFirmwareContext.h | 33
> ++++++++++++++++++++
> > RiscVPkg/Include/sbi/sbi.h | 52
> +++++++++++++++++++++++++++++++
> > RiscVPkg/Include/sbi/sbi_bits.h | 17 ++++++++++
> > RiscVPkg/Include/sbi/sbi_types.h | 45
> ++++++++++++++++++++++++++
> > 4 files changed, 147 insertions(+)
> > create mode 100644 RiscVPkg/Include/sbi/SbiFirmwareContext.h
> > create mode 100644 RiscVPkg/Include/sbi/sbi.h create mode 100644
> > RiscVPkg/Include/sbi/sbi_bits.h create mode 100644
> > RiscVPkg/Include/sbi/sbi_types.h
> >
> > diff --git a/RiscVPkg/Include/sbi/SbiFirmwareContext.h
> > b/RiscVPkg/Include/sbi/SbiFirmwareContext.h
> > new file mode 100644
> > index 0000000..c3d3489
> > --- /dev/null
> > +++ b/RiscVPkg/Include/sbi/SbiFirmwareContext.h
> > @@ -0,0 +1,33 @@
> > +/** @file
> > + RISC-V OpesbSBI Platform Firmware context definition
> > +
> > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> > + rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +#ifndef SBI_FIRMWARE_CONTEXT_H_
> > +#define SBI_FIRMWARE_CONTEXT_H_
> > +
> > +#include <RiscVImpl.h>
> > +
> > +#define RISC_V_MAX_HART_SUPPORTED 16
> > +
> > +//
> > +// keep the structure member in 64-bit alignment.
> > +//
> > +typedef struct {
> > + UINT64 IsaExtensionSupported; // The ISA extension this core
> supported.
> > + RISCV_UINT128 MachineVendorId; // Machine vendor ID
> > + RISCV_UINT128 MachineArchId; // Machine Architecture ID
> > + RISCV_UINT128 MachineImplId; // Machine Implementation ID
> > +} EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC;
> > +
> > +#define FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE (64 * 7)
> > +
> > +typedef struct {
> > + VOID *PeiServiceTable; // PEI Service table
> > + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
> > +*HartSpecific[RISC_V_MAX_HART_SUPPORTED];
> > +} EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT;
> > +#endif
> > +
> > diff --git a/RiscVPkg/Include/sbi/sbi.h b/RiscVPkg/Include/sbi/sbi.h
> > new file mode 100644 index 0000000..04e7f18
> > --- /dev/null
> > +++ b/RiscVPkg/Include/sbi/sbi.h
> > @@ -0,0 +1,52 @@
> > +/** @file
> > + SBI inline function calls.
> > +
> > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> > + rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +#ifndef EDK2_SBI_H_
> > +#define EDK2_SBI_H_
> > +
> > +#include <sbi/sbi_types.h> // Reference to header file wrapper
> > +#include <include/sbi/riscv_asm.h> // Reference to header file in
> > +opensbi
>
> This whole sbi situation is too much of a hornets' nest, and really does need
> to get sorted before we even push this to -staging.
> (But I do think is is one of the last things we need to address.)
>
> And I think the starting point to untangle it is to rename the wrapper include
> files in RiscVPkg/Include/sbi (and indeed the directory
> itself) to conform with the TianoCore standard.
>
> That means:
>
> RiscVPkg/Include/IndustryStandard/Sbi/Sbi.h
> RiscVPkg/Include/IndustryStandard/Sbi/SbiBits.h
> RiscVPkg/Include/IndustryStandard/Sbi/SbiTypes.h
>
> Unless all of the wrappers can be combined into a single
> RiscVPkg/Include/IndustryStandard/Sbi.h
>
> ...and then tested on a case-sensitive filesystem.
>
> For the record, doing that immediately results in the non-wrapper versions
> being pulled in and then the build failing.
Leif,
We can't change the naming of those header files under RiscVPkg/Include/sbi. We build opensbi source code in edk2 and those source files refer to those header file. And we are not going to change opensbi code as we discussed before.
The only file we can change is sbi.h -> Sbi.h because this header file is created for edk2 RISC-V related drivers.
I think we can make it this way,
Rename sbi.h to RiscVOpensbi.h and move it to under RiscVPkg/Include/IndustryStandard, no need "/Sbi" subdirectory.
Keep the naming of sbi_bits.h and sbi_types.h and still leave those under RiscVPkg/Include/sbi. No naming changes in order to build opensbi source file. Can't even change "/sbi" subdirectory to "/Sbi". sbi_bits.h and sbi_types.h are the binding files for edk2 framework BTW.
>
> /
> Leif
>
> > +
> > +#define SBI_SET_TIMER 0
> > +#define SBI_CONSOLE_PUTCHAR 1
> > +#define SBI_CONSOLE_GETCHAR 2
> > +#define SBI_CLEAR_IPI 3
> > +#define SBI_SEND_IPI 4
> > +#define SBI_REMOTE_FENCE_I 5
> > +#define SBI_REMOTE_SFENCE_VMA 6
> > +#define SBI_REMOTE_SFENCE_VMA_ASID 7
> > +#define SBI_SHUTDOWN 8
> > +
> > +#define SBI_CALL(which, arg0, arg1, arg2) ({ \
> > + register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \
> > + register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \
> > + register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2); \
> > + register uintptr_t a7 asm ("a7") = (uintptr_t)(which); \
> > + asm volatile ("ecall" \
> > + : "+r" (a0) \
> > + : "r" (a1), "r" (a2), "r" (a7) \
> > + : "memory"); \
> > + a0; \
> > +})
> > +
> > +#define SBI_CALL_0(which) SBI_CALL(which, 0, 0, 0) #define
> > +SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0) #define
> > +SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0)
> > +
> > +#define sbi_console_putchar(ch) SBI_CALL_1(SBI_CONSOLE_PUTCHAR,
> ch)
> > +#define sbi_console_getchar() SBI_CALL_0(SBI_CONSOLE_GETCHAR)
> > +#define sbi_set_timer(stime_value) SBI_CALL_1(SBI_SET_TIMER,
> stime_value)
> > +#define sbi_shutdown() SBI_CALL_0(SBI_SHUTDOWN)
> > +#define sbi_clear_ipi() SBI_CALL_0(SBI_CLEAR_IPI)
> > +#define sbi_send_ipi(hart_mask) SBI_CALL_1(SBI_SEND_IPI,
> hart_mask)
> > +#define sbi_remote_fence_i(hart_mask)
> SBI_CALL_1(SBI_REMOTE_FENCE_I,
> > +hart_mask) #define sbi_remote_sfence_vma(hart_mask, start, size)
> > +SBI_CALL_1(SBI_REMOTE_SFENCE_VMA, hart_mask) #define
> > +sbi_remote_sfence_vma_asid(hart_mask, start, size, asid)
> > +SBI_CALL_1(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask)
> > +
> > +#endif
> > diff --git a/RiscVPkg/Include/sbi/sbi_bits.h
> > b/RiscVPkg/Include/sbi/sbi_bits.h new file mode 100644 index
> > 0000000..c935547
> > --- /dev/null
> > +++ b/RiscVPkg/Include/sbi/sbi_bits.h
> > @@ -0,0 +1,17 @@
> > +/** @file
> > + RISC-V OpesbSBI header file reference.
> > +
> > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> > + rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +#ifndef EDK2_SBI_BITS_H_
> > +#define EDK2_SBI_BITS_H_
> > +
> > +#undef MAX
> > +#undef MIN
> > +
> > +#include "include/sbi/sbi_bits.h" // Reference to header file in
> > +opensbi
> > +
> > +#endif
> > diff --git a/RiscVPkg/Include/sbi/sbi_types.h
> > b/RiscVPkg/Include/sbi/sbi_types.h
> > new file mode 100644
> > index 0000000..95ee213
> > --- /dev/null
> > +++ b/RiscVPkg/Include/sbi/sbi_types.h
> > @@ -0,0 +1,45 @@
> > +/** @file
> > + RISC-V OpesbSBI header file reference.
> > +
> > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> > + rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +#ifndef EDK2_SBI_TYPES_H_
> > +#define EDK2_SBI_TYPES_H_
> > +
> > +typedef INT8 s8;
> > +typedef UINT8 u8;
> > +typedef UINT8 uint8_t;
> > +
> > +typedef INT16 s16;
> > +typedef UINT16 u16;
> > +typedef INT16 int16_t;
> > +typedef UINT16 uint16_t;
> > +
> > +typedef INT32 s32;
> > +typedef UINT32 u32;
> > +typedef INT32 int32_t;
> > +typedef UINT32 uint32_t;
> > +
> > +typedef INT64 s64;
> > +typedef UINT64 u64;
> > +typedef INT64 int64_t;
> > +typedef UINT64 uint64_t;
> > +
> > +#define PRILX "016lx"
> > +
> > +typedef INT32 bool;
> > +typedef unsigned long ulong;
> > +typedef UINT64 uintptr_t;
> > +typedef UINT64 size_t;
> > +typedef INT64 ssize_t;
> > +typedef UINT64 virtual_addr_t;
> > +typedef UINT64 virtual_size_t;
> > +typedef UINT64 physical_addr_t;
> > +typedef UINT64 physical_size_t;
> > +
> > +#define __packed __attribute__((packed))
> > +#define __noreturn __attribute__((noreturn))
> > +#endif
> > --
> > 2.7.4
> >
>
>
^ permalink raw reply [flat|nested] 77+ messages in thread* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 03/39] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support
2019-12-19 4:09 ` [edk2-devel] " Abner Chang
@ 2019-12-19 13:21 ` Leif Lindholm
2019-12-19 14:48 ` Abner Chang
[not found] ` <15E1CD20DD2FE7F1.29030@groups.io>
0 siblings, 2 replies; 77+ messages in thread
From: Leif Lindholm @ 2019-12-19 13:21 UTC (permalink / raw)
To: devel, abner.chang; +Cc: Chen, Gilbert, Kinney, Michael D
On Thu, Dec 19, 2019 at 04:09:22 +0000, Abner Chang wrote:
> > > diff --git a/RiscVPkg/Include/sbi/sbi.h b/RiscVPkg/Include/sbi/sbi.h
> > > new file mode 100644 index 0000000..04e7f18
> > > --- /dev/null
> > > +++ b/RiscVPkg/Include/sbi/sbi.h
> > > @@ -0,0 +1,52 @@
> > > +/** @file
> > > + SBI inline function calls.
> > > +
> > > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> > > + rights reserved.<BR>
> > > +
> > > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > > +
> > > +**/
> > > +
> > > +#ifndef EDK2_SBI_H_
> > > +#define EDK2_SBI_H_
> > > +
> > > +#include <sbi/sbi_types.h> // Reference to header file wrapper
> > > +#include <include/sbi/riscv_asm.h> // Reference to header file in
> > > +opensbi
> >
> > This whole sbi situation is too much of a hornets' nest, and really does need
> > to get sorted before we even push this to -staging.
> > (But I do think is is one of the last things we need to address.)
> >
> > And I think the starting point to untangle it is to rename the wrapper include
> > files in RiscVPkg/Include/sbi (and indeed the directory
> > itself) to conform with the TianoCore standard.
> >
> > That means:
> >
> > RiscVPkg/Include/IndustryStandard/Sbi/Sbi.h
> > RiscVPkg/Include/IndustryStandard/Sbi/SbiBits.h
> > RiscVPkg/Include/IndustryStandard/Sbi/SbiTypes.h
> >
> > Unless all of the wrappers can be combined into a single
> > RiscVPkg/Include/IndustryStandard/Sbi.h
> >
> > ...and then tested on a case-sensitive filesystem.
> >
> > For the record, doing that immediately results in the non-wrapper versions
> > being pulled in and then the build failing.
>
> Leif,
> We can't change the naming of those header files under
> RiscVPkg/Include/sbi. We build opensbi source code in edk2 and those
> source files refer to those header file. And we are not going to
> change opensbi code as we discussed before.
>
> The only file we can change is sbi.h -> Sbi.h because this header
> file is created for edk2 RISC-V related drivers.
>
> I think we can make it this way,
> Rename sbi.h to RiscVOpensbi.h and move it to under
> RiscVPkg/Include/IndustryStandard, no need "/Sbi" subdirectory.
That sounds good to me.
> Keep the naming of sbi_bits.h and sbi_types.h and still leave those
> under RiscVPkg/Include/sbi.
>
> No naming changes in order to build opensbi source file. Can't even
> change "/sbi" subdirectory to "/Sbi". sbi_bits.h and sbi_types.h are
> the binding files for edk2 framework BTW.
Sure, if we separate interface for EDK2 apps from binding, it becomes
less bad. Plus sbi_bits.h needs to just go, but we'll fix that in
opensbi before merging Risc-V to edk2 master.
I think the proper fix for sbi_types.h also involves a change to
opensbi.
But if you can
- do those changes
- move/rename SbiFirmwareContext.h to live with RiscVOpensbi.h
- add a (short) Readme.md to RiscVPkg/Include/sbi explaining what
these files are and why
I think that resolves my final reservations against bringing this set
onto a staging branch.
Regards,
Leif
^ permalink raw reply [flat|nested] 77+ messages in thread* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 03/39] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support
2019-12-19 13:21 ` Leif Lindholm
@ 2019-12-19 14:48 ` Abner Chang
[not found] ` <15E1CD20DD2FE7F1.29030@groups.io>
1 sibling, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-12-19 14:48 UTC (permalink / raw)
To: Leif Lindholm, devel@edk2.groups.io; +Cc: Chen, Gilbert, Kinney, Michael D
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Thursday, December 19, 2019 9:22 PM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Cc: Chen, Gilbert <gilbert.chen@hpe.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 03/39]
> RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support
>
> On Thu, Dec 19, 2019 at 04:09:22 +0000, Abner Chang wrote:
> > > > diff --git a/RiscVPkg/Include/sbi/sbi.h
> > > > b/RiscVPkg/Include/sbi/sbi.h new file mode 100644 index
> > > > 0000000..04e7f18
> > > > --- /dev/null
> > > > +++ b/RiscVPkg/Include/sbi/sbi.h
> > > > @@ -0,0 +1,52 @@
> > > > +/** @file
> > > > + SBI inline function calls.
> > > > +
> > > > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP.
> > > > + All rights reserved.<BR>
> > > > +
> > > > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > > > +
> > > > +**/
> > > > +
> > > > +#ifndef EDK2_SBI_H_
> > > > +#define EDK2_SBI_H_
> > > > +
> > > > +#include <sbi/sbi_types.h> // Reference to header file wrapper
> > > > +#include <include/sbi/riscv_asm.h> // Reference to header file in
> > > > +opensbi
> > >
> > > This whole sbi situation is too much of a hornets' nest, and really
> > > does need to get sorted before we even push this to -staging.
> > > (But I do think is is one of the last things we need to address.)
> > >
> > > And I think the starting point to untangle it is to rename the
> > > wrapper include files in RiscVPkg/Include/sbi (and indeed the
> > > directory
> > > itself) to conform with the TianoCore standard.
> > >
> > > That means:
> > >
> > > RiscVPkg/Include/IndustryStandard/Sbi/Sbi.h
> > > RiscVPkg/Include/IndustryStandard/Sbi/SbiBits.h
> > > RiscVPkg/Include/IndustryStandard/Sbi/SbiTypes.h
> > >
> > > Unless all of the wrappers can be combined into a single
> > > RiscVPkg/Include/IndustryStandard/Sbi.h
> > >
> > > ...and then tested on a case-sensitive filesystem.
> > >
> > > For the record, doing that immediately results in the non-wrapper
> > > versions being pulled in and then the build failing.
> >
> > Leif,
> > We can't change the naming of those header files under
> > RiscVPkg/Include/sbi. We build opensbi source code in edk2 and those
> > source files refer to those header file. And we are not going to
> > change opensbi code as we discussed before.
> >
> > The only file we can change is sbi.h -> Sbi.h because this header file
> > is created for edk2 RISC-V related drivers.
> >
> > I think we can make it this way,
> > Rename sbi.h to RiscVOpensbi.h and move it to under
> > RiscVPkg/Include/IndustryStandard, no need "/Sbi" subdirectory.
>
> That sounds good to me.
>
> > Keep the naming of sbi_bits.h and sbi_types.h and still leave those
> > under RiscVPkg/Include/sbi.
> >
> > No naming changes in order to build opensbi source file. Can't even
> > change "/sbi" subdirectory to "/Sbi". sbi_bits.h and sbi_types.h are
> > the binding files for edk2 framework BTW.
>
> Sure, if we separate interface for EDK2 apps from binding, it becomes less
> bad. Plus sbi_bits.h needs to just go, but we'll fix that in opensbi before
> merging Risc-V to edk2 master.
I am not sure this one. That may take some time to fix that in opensbi. I would rather merge our code to edk2 master first and deal with opensbi in parallel. Some people they approach to me and ask for edk2 RISC-V port. Currently they can just go to our private Github to retrieve code. More people will join edk2 RISC-V port if we can merge it to edk2 master earlier.
> I think the proper fix for sbi_types.h also involves a change to opensbi.
This has to ask opensbi to have binging mechanism for different frameworks, however I agree with you in this part.
>
> But if you can
> - do those changes
> - move/rename SbiFirmwareContext.h to live with RiscVOpensbi.h
Hehe already. I know you :). I already moved this file to under RiscVPkg/Include/IndustryStandard just a separate file.
> - add a (short) Readme.md to RiscVPkg/Include/sbi explaining what
> these files are and why
> I think that resolves my final reservations against bringing this set onto a
> staging branch.
sure
>
> Regards,
>
> Leif
^ permalink raw reply [flat|nested] 77+ messages in thread[parent not found: <15E1CD20DD2FE7F1.29030@groups.io>]
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 03/39] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support
[not found] ` <15E1CD20DD2FE7F1.29030@groups.io>
@ 2019-12-20 3:04 ` Abner Chang
0 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-12-20 3:04 UTC (permalink / raw)
To: devel@edk2.groups.io, Chang, Abner (HPS SW/FW Technologist),
Leif Lindholm
Cc: Chen, Gilbert, Kinney, Michael D
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Abner Chang
> Sent: Thursday, December 19, 2019 10:48 PM
> To: Leif Lindholm <leif.lindholm@linaro.org>; devel@edk2.groups.io
> Cc: Chen, Gilbert <gilbert.chen@hpe.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 03/39]
> RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support
>
>
>
> > -----Original Message-----
> > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > Sent: Thursday, December 19, 2019 9:22 PM
> > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> > <abner.chang@hpe.com>
> > Cc: Chen, Gilbert <gilbert.chen@hpe.com>; Kinney, Michael D
> > <michael.d.kinney@intel.com>
> > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 03/39]
> > RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support
> >
> > On Thu, Dec 19, 2019 at 04:09:22 +0000, Abner Chang wrote:
> > > > > diff --git a/RiscVPkg/Include/sbi/sbi.h
> > > > > b/RiscVPkg/Include/sbi/sbi.h new file mode 100644 index
> > > > > 0000000..04e7f18
> > > > > --- /dev/null
> > > > > +++ b/RiscVPkg/Include/sbi/sbi.h
> > > > > @@ -0,0 +1,52 @@
> > > > > +/** @file
> > > > > + SBI inline function calls.
> > > > > +
> > > > > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP.
> > > > > + All rights reserved.<BR>
> > > > > +
> > > > > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > > > > +
> > > > > +**/
> > > > > +
> > > > > +#ifndef EDK2_SBI_H_
> > > > > +#define EDK2_SBI_H_
> > > > > +
> > > > > +#include <sbi/sbi_types.h> // Reference to header file wrapper
> > > > > +#include <include/sbi/riscv_asm.h> // Reference to header file
> > > > > +in opensbi
> > > >
> > > > This whole sbi situation is too much of a hornets' nest, and
> > > > really does need to get sorted before we even push this to -staging.
> > > > (But I do think is is one of the last things we need to address.)
> > > >
> > > > And I think the starting point to untangle it is to rename the
> > > > wrapper include files in RiscVPkg/Include/sbi (and indeed the
> > > > directory
> > > > itself) to conform with the TianoCore standard.
> > > >
> > > > That means:
> > > >
> > > > RiscVPkg/Include/IndustryStandard/Sbi/Sbi.h
> > > > RiscVPkg/Include/IndustryStandard/Sbi/SbiBits.h
> > > > RiscVPkg/Include/IndustryStandard/Sbi/SbiTypes.h
> > > >
> > > > Unless all of the wrappers can be combined into a single
> > > > RiscVPkg/Include/IndustryStandard/Sbi.h
> > > >
> > > > ...and then tested on a case-sensitive filesystem.
> > > >
> > > > For the record, doing that immediately results in the non-wrapper
> > > > versions being pulled in and then the build failing.
> > >
> > > Leif,
> > > We can't change the naming of those header files under
> > > RiscVPkg/Include/sbi. We build opensbi source code in edk2 and those
> > > source files refer to those header file. And we are not going to
> > > change opensbi code as we discussed before.
> > >
> > > The only file we can change is sbi.h -> Sbi.h because this header
> > > file is created for edk2 RISC-V related drivers.
> > >
> > > I think we can make it this way,
> > > Rename sbi.h to RiscVOpensbi.h and move it to under
> > > RiscVPkg/Include/IndustryStandard, no need "/Sbi" subdirectory.
> >
> > That sounds good to me.
> >
> > > Keep the naming of sbi_bits.h and sbi_types.h and still leave those
> > > under RiscVPkg/Include/sbi.
> > >
> > > No naming changes in order to build opensbi source file. Can't even
> > > change "/sbi" subdirectory to "/Sbi". sbi_bits.h and sbi_types.h are
> > > the binding files for edk2 framework BTW.
> >
> > Sure, if we separate interface for EDK2 apps from binding, it becomes
> > less bad. Plus sbi_bits.h needs to just go, but we'll fix that in
> > opensbi before merging Risc-V to edk2 master.
> I am not sure this one. That may take some time to fix that in opensbi. I
> would rather merge our code to edk2 master first and deal with opensbi in
> parallel. Some people they approach to me and ask for edk2 RISC-V port.
> Currently they can just go to our private Github to retrieve code. More
> people will join edk2 RISC-V port if we can merge it to edk2 master earlier.
>
>
> > I think the proper fix for sbi_types.h also involves a change to opensbi.
> This has to ask opensbi to have binging mechanism for different frameworks,
> however I agree with you in this part.
>
> >
> > But if you can
> > - do those changes
> > - move/rename SbiFirmwareContext.h to live with RiscVOpensbi.h
> Hehe already. I know you :). I already moved this file to under
> RiscVPkg/Include/IndustryStandard just a separate file.
Just merged SbiFirmwareContext.h to RiscVOpensbi.h.
Now we only have two header files under Include/sbi/. I will start the conversation with opensbi people to fix the duplicate definitions issue when other firmware frameworks leverage opensbi. This helps to remove sbi_bits.h from edk2 RISC-V port.
Also consult with them regard with the binding mechanism in opensbi for different firmware frameworks.
Lefi, most of comments for RISC-V edk2 port are done and I will clean up the commits on the private github repo we are working on. The next will be edk2-platforms.
Abner
>
> > - add a (short) Readme.md to RiscVPkg/Include/sbi explaining what
> > these files are and why
> > I think that resolves my final reservations against bringing this set
> > onto a staging branch.
> sure
>
> >
> > Regards,
> >
> > Leif
>
>
^ permalink raw reply [flat|nested] 77+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v3 04/39] MdePkg: RISC-V RV64 binding in MdePkg
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (2 preceding siblings ...)
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 03/39] RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 05/39] MdePkg/Include: RISC-V definitions Abner Chang
` (34 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Liming Gao, Leif Lindholm,
Gilbert Chen
Add RISCV64 sections in MdePkg.dec and RISCV64 ProcessorBind.h
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
MdePkg/MdePkg.dec | 5 +-
MdePkg/Include/RiscV64/ProcessorBind.h | 173 +++++++++++++++++++++++++++++++++
2 files changed, 177 insertions(+), 1 deletion(-)
create mode 100644 MdePkg/Include/RiscV64/ProcessorBind.h
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index 3fd7d16..1aaa97d 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -6,7 +6,7 @@
#
# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-# (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
+# (C) Copyright 2016 - 2019 Hewlett Packard Enterprise Development LP<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -39,6 +39,9 @@
[Includes.AARCH64]
Include/AArch64
+[Includes.RISCV64]
+ Include/RiscV64
+
[LibraryClasses]
## @libraryclass Provides most usb APIs to support the Hid requests defined in Usb Hid 1.1 spec
# and the standard requests defined in Usb 1.1 spec.
diff --git a/MdePkg/Include/RiscV64/ProcessorBind.h b/MdePkg/Include/RiscV64/ProcessorBind.h
new file mode 100644
index 0000000..b887250
--- /dev/null
+++ b/MdePkg/Include/RiscV64/ProcessorBind.h
@@ -0,0 +1,173 @@
+/** @file
+ Processor or Compiler specific defines and types for RISC-V
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PROCESSOR_BIND_H__
+#define PROCESSOR_BIND_H__
+
+///
+/// Define the processor type so other code can make processor based choices
+///
+#define MDE_CPU_RISCV64
+
+//
+// Make sure we are using the correct packing rules per EFI specification
+//
+#if !defined(__GNUC__)
+#pragma pack()
+#endif
+
+///
+/// 8-byte unsigned value
+///
+typedef unsigned long long UINT64 __attribute__ ((aligned (8)));
+///
+/// 8-byte signed value
+///
+typedef long long INT64 __attribute__ ((aligned (8)));
+///
+/// 4-byte unsigned value
+///
+typedef unsigned int UINT32 __attribute__ ((aligned (4)));
+///
+/// 4-byte signed value
+///
+typedef int INT32 __attribute__ ((aligned (4)));
+///
+/// 2-byte unsigned value
+///
+typedef unsigned short UINT16 __attribute__ ((aligned (2)));
+///
+/// 2-byte Character. Unless otherwise specified all strings are stored in the
+/// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
+///
+typedef unsigned short CHAR16 __attribute__ ((aligned (2)));
+///
+/// 2-byte signed value
+///
+typedef short INT16 __attribute__ ((aligned (2)));
+///
+/// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
+/// values are undefined.
+///
+typedef unsigned char BOOLEAN;
+///
+/// 1-byte unsigned value
+///
+typedef unsigned char UINT8;
+///
+/// 1-byte Character
+///
+typedef char CHAR8;
+///
+/// 1-byte signed value
+///
+typedef signed char INT8;
+///
+/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
+/// 8 bytes on supported 64-bit processor instructions)
+///
+typedef UINT64 UINTN __attribute__ ((aligned (8)));
+///
+/// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
+/// 8 bytes on supported 64-bit processor instructions)
+///
+typedef INT64 INTN __attribute__ ((aligned (8)));
+
+//
+// Processor specific defines
+//
+
+///
+/// A value of native width with the highest bit set.
+///
+#define MAX_BIT 0x8000000000000000ULL
+///
+/// A value of native width with the two highest bits set.
+///
+#define MAX_2_BITS 0xC000000000000000ULL
+
+///
+/// Maximum legal RV64 address
+///
+#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL
+
+///
+/// Maximum usable address at boot time (48 bits using 4 KB pages in Supervisor mode)
+///
+#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL
+
+///
+/// Maximum legal RISC-V INTN and UINTN values.
+///
+#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL)
+#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL)
+
+///
+/// The stack alignment required for RISC-V
+///
+#define CPU_STACK_ALIGNMENT 16
+
+///
+/// Page allocation granularity for RISC-V
+///
+#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
+#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x1000)
+
+//
+// Modifier to ensure that all protocol member functions and EFI intrinsics
+// use the correct C calling convention. All protocol member functions and
+// EFI intrinsics are required to modify their member functions with EFIAPI.
+//
+#ifdef EFIAPI
+ ///
+ /// If EFIAPI is already defined, then we use that definition.
+ ///
+#elif defined(__GNUC__)
+ ///
+ /// Define the standard calling convention regardless of optimization level
+ /// The GCC support assumes a GCC compiler that supports the EFI ABI. The EFI
+ /// ABI is much closer to the x64 Microsoft* ABI than standard x64 (x86-64)
+ /// GCC ABI. Thus a standard x64 (x86-64) GCC compiler can not be used for
+ /// x64. Warning the assembly code in the MDE x64 does not follow the correct
+ /// ABI for the standard x64 (x86-64) GCC.
+ ///
+ #define EFIAPI
+#else
+ ///
+ /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI
+ /// is the standard.
+ ///
+ #define EFIAPI
+#endif
+
+#if defined(__GNUC__)
+ ///
+ /// For GNU assembly code, .global or .globl can declare global symbols.
+ /// Define this macro to unify the usage.
+ ///
+ #define ASM_GLOBAL .globl
+#endif
+
+/**
+ Return the pointer to the first instruction of a function given a function pointer.
+ On x64 CPU architectures, these two pointer values are the same,
+ so the implementation of this macro is very simple.
+
+ @param FunctionPointer A pointer to a function.
+
+ @return The pointer to the first instruction of a function given a function pointer.
+
+**/
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
+
+#ifndef __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__
+#endif
+
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 05/39] MdePkg/Include: RISC-V definitions.
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (3 preceding siblings ...)
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 04/39] MdePkg: RISC-V RV64 binding in MdePkg Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 06/39] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch Abner Chang
` (33 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Liming Gao, Leif Lindholm,
Gilbert Chen
Add RISC-V processor related definitions.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
MdePkg/Include/IndustryStandard/PeImage.h | 12 +++++++
MdePkg/Include/Protocol/DebugSupport.h | 55 +++++++++++++++++++++++++++++++
MdePkg/Include/Protocol/PxeBaseCode.h | 4 +++
MdePkg/Include/Uefi/UefiBaseType.h | 13 ++++++++
MdePkg/Include/Uefi/UefiSpec.h | 5 +++
5 files changed, 89 insertions(+)
diff --git a/MdePkg/Include/IndustryStandard/PeImage.h b/MdePkg/Include/IndustryStandard/PeImage.h
index 720bb08..ca3fd0b 100644
--- a/MdePkg/Include/IndustryStandard/PeImage.h
+++ b/MdePkg/Include/IndustryStandard/PeImage.h
@@ -9,6 +9,8 @@
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -34,6 +36,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define IMAGE_FILE_MACHINE_X64 0x8664
#define IMAGE_FILE_MACHINE_ARMTHUMB_MIXED 0x01c2
#define IMAGE_FILE_MACHINE_ARM64 0xAA64
+#define IMAGE_FILE_MACHINE_RISCV32 0x5032
+#define IMAGE_FILE_MACHINE_RISCV64 0x5064
+#define IMAGE_FILE_MACHINE_RISCV128 0x5128
//
// EXE file formats
@@ -494,6 +499,13 @@ typedef struct {
#define EFI_IMAGE_REL_BASED_DIR64 10
///
+/// Relocation types of RISC-V processor.
+///
+#define EFI_IMAGE_REL_BASED_RISCV_HI20 5
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
+
+///
/// Line number format.
///
typedef struct {
diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protocol/DebugSupport.h
index 800e771..1a29cc0 100644
--- a/MdePkg/Include/Protocol/DebugSupport.h
+++ b/MdePkg/Include/Protocol/DebugSupport.h
@@ -7,6 +7,7 @@
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -603,6 +604,59 @@ typedef struct {
UINT64 FAR; // Fault Address Register
} EFI_SYSTEM_CONTEXT_AARCH64;
+///
+/// RISC-V processor exception types.
+///
+#define EXCEPT_RISCV_INST_MISALIGNED 0
+#define EXCEPT_RISCV_INST_ACCESS_FAULT 1
+#define EXCEPT_RISCV_ILLEGAL_INST 2
+#define EXCEPT_RISCV_BREAKPOINT 3
+#define EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED 4
+#define EXCEPT_RISCV_LOAD_ACCESS_FAULT 5
+#define EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED 6
+#define EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT 7
+#define EXCEPT_RISCV_ENV_CALL_FROM_UMODE 8
+#define EXCEPT_RISCV_ENV_CALL_FROM_SMODE 9
+#define EXCEPT_RISCV_ENV_CALL_FROM_HMODE 10
+#define EXCEPT_RISCV_ENV_CALL_FROM_MMODE 11
+
+#define EXCEPT_RISCV_SOFTWARE_INT 0x0
+#define EXCEPT_RISCV_TIMER_INT 0x1
+
+typedef struct {
+ UINT64 X0;
+ UINT64 X1;
+ UINT64 X2;
+ UINT64 X3;
+ UINT64 X4;
+ UINT64 X5;
+ UINT64 X6;
+ UINT64 X7;
+ UINT64 X8;
+ UINT64 X9;
+ UINT64 X10;
+ UINT64 X11;
+ UINT64 X12;
+ UINT64 X13;
+ UINT64 X14;
+ UINT64 X15;
+ UINT64 X16;
+ UINT64 X17;
+ UINT64 X18;
+ UINT64 X19;
+ UINT64 X20;
+ UINT64 X21;
+ UINT64 X22;
+ UINT64 X23;
+ UINT64 X24;
+ UINT64 X25;
+ UINT64 X26;
+ UINT64 X27;
+ UINT64 X28;
+ UINT64 X29;
+ UINT64 X30;
+ UINT64 X31;
+} EFI_SYSTEM_CONTEXT_RISCV64;
///
/// Universal EFI_SYSTEM_CONTEXT definition.
@@ -614,6 +668,7 @@ typedef union {
EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;
EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;
EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;
+ EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;
} EFI_SYSTEM_CONTEXT;
//
diff --git a/MdePkg/Include/Protocol/PxeBaseCode.h b/MdePkg/Include/Protocol/PxeBaseCode.h
index b02d270..8a9e4a1 100644
--- a/MdePkg/Include/Protocol/PxeBaseCode.h
+++ b/MdePkg/Include/Protocol/PxeBaseCode.h
@@ -3,6 +3,8 @@
devices for network access and network booting.
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Revision Reference:
@@ -153,6 +155,8 @@ typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT;
#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000A
#elif defined (MDE_CPU_AARCH64)
#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000B
+#elif defined (MDE_CPU_RISCV64)
+#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x001B
#endif
diff --git a/MdePkg/Include/Uefi/UefiBaseType.h b/MdePkg/Include/Uefi/UefiBaseType.h
index a62f13d..d979412 100644
--- a/MdePkg/Include/Uefi/UefiBaseType.h
+++ b/MdePkg/Include/Uefi/UefiBaseType.h
@@ -3,6 +3,7 @@
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
+Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -240,6 +241,12 @@ typedef union {
///
#define EFI_IMAGE_MACHINE_AARCH64 0xAA64
+///
+/// PE32+ Machine type for RISC-V 32/64/128
+///
+#define EFI_IMAGE_MACHINE_RISCV32 0x5032
+#define EFI_IMAGE_MACHINE_RISCV64 0x5064
+#define EFI_IMAGE_MACHINE_RISCV128 0x5128
#if defined (MDE_CPU_IA32)
@@ -268,6 +275,12 @@ typedef union {
#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
+#elif defined (MDE_CPU_RISCV64)
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
+ ((Machine) == EFI_IMAGE_MACHINE_RISCV64)
+
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
+
#elif defined (MDE_CPU_EBC)
///
diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiSpec.h
index 44a0a6a..e2d4539 100644
--- a/MdePkg/Include/Uefi/UefiSpec.h
+++ b/MdePkg/Include/Uefi/UefiSpec.h
@@ -6,6 +6,8 @@
by this include file.
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+Portions Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -2178,6 +2180,7 @@ typedef struct {
#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI"
#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI"
#define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.EFI"
#if defined (MDE_CPU_IA32)
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA32
@@ -2188,6 +2191,8 @@ typedef struct {
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_ARM
#elif defined (MDE_CPU_AARCH64)
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64
+#elif defined (MDE_CPU_RISCV64)
+ #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64
#else
#error Unknown Processor Type
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 06/39] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch.
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (4 preceding siblings ...)
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 05/39] MdePkg/Include: RISC-V definitions Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 07/39] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor Abner Chang
` (32 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Hao A Wu, Liming Gao, Leif Lindholm, Gilbert Chen
Add RISC-V in INF for building CapsuleRuntimeDxe RISCV64 image.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
index 9da4507..84f3688 100644
--- a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+++ b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
@@ -5,6 +5,7 @@
# the capsule runtime services are ready.
#
# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -21,20 +22,20 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
#
[Sources]
CapsuleService.c
CapsuleService.h
-[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64]
+[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64, Sources.RISCV64]
SaveLongModeContext.c
-[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64]
+[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64, Sources.RISCV64]
CapsuleCache.c
-[Sources.Ia32, Sources.X64, Sources.EBC]
+[Sources.Ia32, Sources.X64, Sources.EBC, Sources.RISCV64]
CapsuleReset.c
[Sources.ARM, Sources.AARCH64]
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 07/39] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor.
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (5 preceding siblings ...)
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 06/39] MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 08/39] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
` (31 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Liming Gao, Leif Lindholm,
Gilbert Chen
Add RISC-V RV64 BaseLib functions.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
MdePkg/Library/BaseLib/BaseLib.inf | 18 ++++++-
MdePkg/Include/Library/BaseLib.h | 26 ++++++++++
MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c | 27 +++++++++++
MdePkg/Library/BaseLib/RiscV64/CpuPause.c | 29 ++++++++++++
MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c | 24 ++++++++++
MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c | 25 ++++++++++
MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c | 35 ++++++++++++++
.../Library/BaseLib/RiscV64/InternalSwitchStack.c | 55 ++++++++++++++++++++++
MdePkg/Library/BaseLib/RiscV64/LongJump.c | 32 +++++++++++++
MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 +++++++++
.../Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S | 14 ++++++
MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S | 14 ++++++
MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 32 +++++++++++++
.../Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S | 55 ++++++++++++++++++++++
14 files changed, 406 insertions(+), 1 deletion(-)
create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuPause.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/LongJump.c
create mode 100644 MdePkg/Library/BaseLib/RiscV64/FlushCache.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 3586beb..053911e 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -4,6 +4,7 @@
# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -20,7 +21,7 @@
LIBRARY_CLASS = BaseLib
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
#
[Sources]
@@ -381,6 +382,21 @@
AArch64/CpuBreakpoint.asm | MSFT
AArch64/SpeculationBarrier.asm | MSFT
+[Sources.RISCV64]
+ Math64.c
+ Unaligned.c
+ RiscV64/InternalSwitchStack.c
+ RiscV64/CpuBreakpoint.c
+ RiscV64/GetInterruptState.c
+ RiscV64/DisableInterrupts.c
+ RiscV64/EnableInterrupts.c
+ RiscV64/CpuPause.c
+ RiscV64/RiscVSetJumpLongJump.S | GCC
+ RiscV64/RiscVCpuBreakpoint.S | GCC
+ RiscV64/RiscVCpuPause.S | GCC
+ RiscV64/RiscVInterrupt.S | GCC
+ RiscV64/FlushCache.S | GCC
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 2a75bc0..b8c8512 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -4,6 +4,8 @@
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -124,6 +126,30 @@ typedef struct {
#endif // defined (MDE_CPU_AARCH64)
+#if defined (MDE_CPU_RISCV64)
+///
+/// The RISC-V architecture context buffer used by SetJump() and LongJump().
+///
+typedef struct {
+ UINT64 RA;
+ UINT64 S0;
+ UINT64 S1;
+ UINT64 S2;
+ UINT64 S3;
+ UINT64 S4;
+ UINT64 S5;
+ UINT64 S6;
+ UINT64 S7;
+ UINT64 S8;
+ UINT64 S9;
+ UINT64 S10;
+ UINT64 S11;
+ UINT64 SP;
+} BASE_LIBRARY_JUMP_BUFFER;
+
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+
+#endif // defined (MDE_CPU_RISCV64)
//
// String Services
diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c b/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
new file mode 100644
index 0000000..d82b1d5
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
@@ -0,0 +1,27 @@
+/** @file
+ CPU breakpoint for RISC-V
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+extern VOID RiscVCpuBreakpoint (VOID);
+
+/**
+ Generates a breakpoint on the CPU.
+
+ Generates a breakpoint on the CPU. The breakpoint must be implemented such
+ that code can resume normal execution after the breakpoint.
+
+**/
+VOID
+EFIAPI
+CpuBreakpoint (
+ VOID
+ )
+{
+ RiscVCpuBreakpoint ();
+}
diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuPause.c b/MdePkg/Library/BaseLib/RiscV64/CpuPause.c
new file mode 100644
index 0000000..8eb6b65
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/CpuPause.c
@@ -0,0 +1,29 @@
+/** @file
+ CPU pause for RISC-V
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+extern VOID RiscVCpuPause (VOID);
+
+
+/**
+ Requests CPU to pause for a short period of time.
+
+ Requests CPU to pause for a short period of time. Typically used in MP
+ systems to prevent memory starvation while waiting for a spin lock.
+
+**/
+VOID
+EFIAPI
+CpuPause (
+ VOID
+ )
+{
+ RiscVCpuPause ();
+}
+
diff --git a/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c b/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
new file mode 100644
index 0000000..7ee5eb1
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
@@ -0,0 +1,24 @@
+/** @file
+ CPU disable interrupt function for RISC-V
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "BaseLibInternals.h"
+
+extern VOID RiscVDisableSupervisorModeInterrupts (VOID);
+
+/**
+ Disables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+DisableInterrupts (
+ VOID
+ )
+{
+ RiscVDisableSupervisorModeInterrupts ();
+}
+
diff --git a/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c b/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
new file mode 100644
index 0000000..9aa0d9a
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
@@ -0,0 +1,25 @@
+/** @file
+ CPU enable interrupt function for RISC-V
+
+ Copyright (c) 2016-2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+extern VOID RiscVEnableSupervisorModeInterrupt (VOID);
+
+/**
+ Enables CPU interrupts.
+
+**/
+VOID
+EFIAPI
+EnableInterrupts (
+ VOID
+ )
+{
+ RiscVEnableSupervisorModeInterrupt ();
+}
+
diff --git a/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c b/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
new file mode 100644
index 0000000..8f764fb
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
@@ -0,0 +1,35 @@
+/** @file
+ CPU get interrupt state function for RISC-V
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+extern UINT32 RiscVGetSupervisorModeInterrupts (VOID);
+
+/**
+ Retrieves the current CPU interrupt state.
+
+ Returns TRUE is interrupts are currently enabled. Otherwise
+ returns FALSE.
+
+ @retval TRUE CPU interrupts are enabled.
+ @retval FALSE CPU interrupts are disabled.
+
+**/
+BOOLEAN
+EFIAPI
+GetInterruptState (
+ VOID
+ )
+{
+ unsigned long RetValue;
+
+ RetValue = RiscVGetSupervisorModeInterrupts ();
+ return RetValue? TRUE: FALSE;
+}
+
+
diff --git a/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
new file mode 100644
index 0000000..1082d4e
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
@@ -0,0 +1,55 @@
+/** @file
+ Switch stack function for RISC-V
+
+ Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+/**
+ Transfers control to a function starting with a new stack.
+
+ Transfers control to the function specified by EntryPoint using the
+ new stack specified by NewStack and passing in the parameters specified
+ by Context1 and Context2. Context1 and Context2 are optional and may
+ be NULL. The function EntryPoint must never return.
+ Marker will be ignored on IA-32, x64, and EBC.
+ IPF CPUs expect one additional parameter of type VOID * that specifies
+ the new backing store pointer.
+
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ @param EntryPoint A pointer to function to call with the new stack.
+ @param Context1 A pointer to the context to pass into the EntryPoint
+ function.
+ @param Context2 A pointer to the context to pass into the EntryPoint
+ function.
+ @param NewStack A pointer to the new stack to use for the EntryPoint
+ function.
+ @param Marker VA_LIST marker for the variable argument list.
+
+**/
+VOID
+EFIAPI
+InternalSwitchStack (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *NewStack,
+ IN VA_LIST Marker
+ )
+{
+ BASE_LIBRARY_JUMP_BUFFER JumpBuffer;
+
+ DEBUG ((DEBUG_INFO, "RISC-V InternalSwitchStack Entry:%x Context1:%x Context2:%x NewStack%x\n", \
+ EntryPoint, Context1, Context2, NewStack));
+ JumpBuffer.RA = (UINTN)EntryPoint;
+ JumpBuffer.SP = (UINTN)NewStack - sizeof (VOID *);
+ JumpBuffer.S0 = (UINT64)(UINTN)Context1;
+ JumpBuffer.S1 = (UINT64)(UINTN)Context2;
+ LongJump (&JumpBuffer, (UINTN)-1);
+ ASSERT(FALSE);
+}
diff --git a/MdePkg/Library/BaseLib/RiscV64/LongJump.c b/MdePkg/Library/BaseLib/RiscV64/LongJump.c
new file mode 100644
index 0000000..a62b882
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/LongJump.c
@@ -0,0 +1,32 @@
+/** @file
+ Long jump implementation of RISC-V
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+
+/**
+ Restores the CPU context that was saved with SetJump().
+
+ Restores the CPU context from the buffer specified by JumpBuffer.
+ This function never returns to the caller.
+ Instead is resumes execution based on the state of JumpBuffer.
+
+ @param JumpBuffer A pointer to CPU context buffer.
+ @param Value The value to return when the SetJump() context is restored.
+
+**/
+VOID
+EFIAPI
+InternalLongJump (
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,
+ IN UINTN Value
+ )
+{
+ ASSERT (FALSE);
+}
+
diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
new file mode 100644
index 0000000..0ef0213
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
@@ -0,0 +1,21 @@
+//------------------------------------------------------------------------------
+//
+// RISC-V cache operation.
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+.align 3
+ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)
+ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)
+
+ASM_PFX(RiscVInvalidateInstCacheAsm):
+ fence.i
+ ret
+
+ASM_PFX(RiscVInvalidateDataCacheAsm):
+ fence
+ ret
diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
new file mode 100644
index 0000000..1a45e2a
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
@@ -0,0 +1,14 @@
+//------------------------------------------------------------------------------
+//
+// CpuBreakpoint for RISC-V
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(RiscVCpuBreakpoint)
+ASM_PFX(RiscVCpuBreakpoint):
+ ebreak
+ ret
diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
new file mode 100644
index 0000000..ceba0c0
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
@@ -0,0 +1,14 @@
+//------------------------------------------------------------------------------
+//
+// CpuPause for RISC-V
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(RiscVCpuPause)
+ASM_PFX(RiscVCpuPause):
+ nop
+ ret
diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
new file mode 100644
index 0000000..8fdb544
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
@@ -0,0 +1,32 @@
+//------------------------------------------------------------------------------
+//
+// RISC-V Supervisor Mode interrupt enable/disable
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts)
+ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt)
+ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts)
+
+# define MSTATUS_SIE 0x00000002
+# define CSR_SSTATUS 0x100
+
+ASM_PFX(RiscVDisableSupervisorModeInterrupts):
+ li a1, MSTATUS_SIE
+ csrc CSR_SSTATUS, a1
+ ret
+
+ASM_PFX(RiscVEnableSupervisorModeInterrupt):
+ li a1, MSTATUS_SIE
+ csrs CSR_SSTATUS, a1
+ ret
+
+ASM_PFX(RiscVGetSupervisorModeInterrupts):
+ csrr a0, CSR_SSTATUS
+ andi a0, a0, MSTATUS_SIE
+ ret
+
diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S b/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
new file mode 100644
index 0000000..a915f69
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
@@ -0,0 +1,55 @@
+//------------------------------------------------------------------------------
+//
+// Set/Long jump for RISC-V
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+# define REG_S sd
+# define REG_L ld
+# define SZREG 8
+.align 3
+ .globl SetJump
+
+SetJump:
+ REG_S ra, 0*SZREG(a0)
+ REG_S s0, 1*SZREG(a0)
+ REG_S s1, 2*SZREG(a0)
+ REG_S s2, 3*SZREG(a0)
+ REG_S s3, 4*SZREG(a0)
+ REG_S s4, 5*SZREG(a0)
+ REG_S s5, 6*SZREG(a0)
+ REG_S s6, 7*SZREG(a0)
+ REG_S s7, 8*SZREG(a0)
+ REG_S s8, 9*SZREG(a0)
+ REG_S s9, 10*SZREG(a0)
+ REG_S s10, 11*SZREG(a0)
+ REG_S s11, 12*SZREG(a0)
+ REG_S sp, 13*SZREG(a0)
+ li a0, 0
+ ret
+
+ .globl InternalLongJump
+InternalLongJump:
+ REG_L ra, 0*SZREG(a0)
+ REG_L s0, 1*SZREG(a0)
+ REG_L s1, 2*SZREG(a0)
+ REG_L s2, 3*SZREG(a0)
+ REG_L s3, 4*SZREG(a0)
+ REG_L s4, 5*SZREG(a0)
+ REG_L s5, 6*SZREG(a0)
+ REG_L s6, 7*SZREG(a0)
+ REG_L s7, 8*SZREG(a0)
+ REG_L s8, 9*SZREG(a0)
+ REG_L s9, 10*SZREG(a0)
+ REG_L s10, 11*SZREG(a0)
+ REG_L s11, 12*SZREG(a0)
+ REG_L sp, 13*SZREG(a0)
+
+ add a0, s0, 0
+ add a1, s1, 0
+ add a2, s2, 0
+ add a3, s3, 0
+ ret
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 08/39] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation.
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (6 preceding siblings ...)
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 07/39] MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 09/39] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions Abner Chang
` (30 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Liming Gao, Leif Lindholm,
Gilbert Chen
Implement RISC-V cache maintenance functions in
BaseCacheMaintenanceLib.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../BaseCacheMaintenanceLib.inf | 4 +
.../Library/BaseCacheMaintenanceLib/RiscVCache.c | 250 +++++++++++++++++++++
2 files changed, 254 insertions(+)
create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
index ec7feec..d9bfa04 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
@@ -6,6 +6,7 @@
#
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -41,6 +42,9 @@
[Sources.AARCH64]
ArmCache.c
+[Sources.RISCV64]
+ RiscVCache.c
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
new file mode 100644
index 0000000..b51ae42
--- /dev/null
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/RiscVCache.c
@@ -0,0 +1,250 @@
+/** @file
+ RISC-V specific functionality for cache.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ RISC-V invalidate instruction cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateInstCacheAsm (
+ VOID
+ );
+
+/**
+ RISC-V invalidate data cache.
+
+**/
+VOID
+EFIAPI
+RiscVInvalidateDataCacheAsm (
+ VOID
+ );
+
+/**
+ Invalidates the entire instruction cache in cache coherency domain of the
+ calling CPU.
+
+**/
+VOID
+EFIAPI
+InvalidateInstructionCache (
+ VOID
+ )
+{
+ RiscVInvalidateInstCacheAsm ();
+}
+
+/**
+ Invalidates a range of instruction cache lines in the cache coherency domain
+ of the calling CPU.
+
+ Invalidates the instruction cache lines specified by Address and Length. If
+ Address is not aligned on a cache line boundary, then entire instruction
+ cache line containing Address is invalidated. If Address + Length is not
+ aligned on a cache line boundary, then the entire instruction cache line
+ containing Address + Length -1 is invalidated. This function may choose to
+ invalidate the entire instruction cache if that is more efficient than
+ invalidating the specified range. If Length is 0, then no instruction cache
+ lines are invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the instruction cache lines to
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+
+ @param Length The number of bytes to invalidate from the instruction cache.
+
+ @return Address.
+
+**/
+VOID *
+EFIAPI
+InvalidateInstructionCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
+ return Address;
+}
+
+/**
+ Writes back and invalidates the entire data cache in cache coherency domain
+ of the calling CPU.
+
+ Writes back and invalidates the entire data cache in cache coherency domain
+ of the calling CPU. This function guarantees that all dirty cache lines are
+ written back to system memory, and also invalidates all the data cache lines
+ in the cache coherency domain of the calling CPU.
+
+**/
+VOID
+EFIAPI
+WriteBackInvalidateDataCache (
+ VOID
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
+}
+
+/**
+ Writes back and invalidates a range of data cache lines in the cache
+ coherency domain of the calling CPU.
+
+ Writes back and invalidates the data cache lines specified by Address and
+ Length. If Address is not aligned on a cache line boundary, then entire data
+ cache line containing Address is written back and invalidated. If Address +
+ Length is not aligned on a cache line boundary, then the entire data cache
+ line containing Address + Length -1 is written back and invalidated. This
+ function may choose to write back and invalidate the entire data cache if
+ that is more efficient than writing back and invalidating the specified
+ range. If Length is 0, then no data cache lines are written back and
+ invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back and
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+ @param Length The number of bytes to write back and invalidate from the
+ data cache.
+
+ @return Address of cache invalidation.
+
+**/
+VOID *
+EFIAPI
+WriteBackInvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
+ return Address;
+}
+
+/**
+ Writes back the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Writes back the entire data cache in cache coherency domain of the calling
+ CPU. This function guarantees that all dirty cache lines are written back to
+ system memory. This function may also invalidate all the data cache lines in
+ the cache coherency domain of the calling CPU.
+
+**/
+VOID
+EFIAPI
+WriteBackDataCache (
+ VOID
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
+}
+
+/**
+ Writes back a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Writes back the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is written back. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is written back. This function may choose to write back the entire
+ data cache if that is more efficient than writing back the specified range.
+ If Length is 0, then no data cache lines are written back. This function may
+ also invalidate all the data cache lines in the specified range of the cache
+ coherency domain of the calling CPU. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to write back. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing
+ mode, then Address is a virtual address.
+ @param Length The number of bytes to write back from the data cache.
+
+ @return Address of cache written in main memory.
+
+**/
+VOID *
+EFIAPI
+WriteBackDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
+ return Address;
+}
+
+/**
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU. This function must be used with care because dirty cache lines are not
+ written back to system memory. It is typically used for cache diagnostics. If
+ the CPU does not support invalidation of the entire data cache, then a write
+ back and invalidate operation should be performed on the entire data cache.
+
+**/
+VOID
+EFIAPI
+InvalidateDataCache (
+ VOID
+ )
+{
+ RiscVInvalidateDataCacheAsm ();
+}
+
+/**
+ Invalidates a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Invalidates the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is invalidated. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is invalidated. This function must never invalidate any cache lines
+ outside the specified range. If Length is 0, then no data cache lines are
+ invalidated. Address is returned. This function must be used with care
+ because dirty cache lines are not written back to system memory. It is
+ typically used for cache diagnostics. If the CPU does not support
+ invalidation of a data cache range, then a write back and invalidate
+ operation should be performed on the data cache range.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param Address The base address of the data cache lines to invalidate. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing mode,
+ then Address is a virtual address.
+ @param Length The number of bytes to invalidate from the data cache.
+
+ @return Address.
+
+**/
+VOID *
+EFIAPI
+InvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ DEBUG((DEBUG_ERROR, "%a:RISC-V unsupported function.\n", __FUNCTION__));
+ return Address;
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 09/39] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (7 preceding siblings ...)
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 08/39] MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance implementation Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-11-21 16:36 ` Leif Lindholm
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 10/39] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code Abner Chang
` (29 subsequent siblings)
38 siblings, 1 reply; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Liming Gao, Leif Lindholm,
Gilbert Chen
RISC-V MMIO library instance.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 12 +-
MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c | 593 ---------------------
MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c | 593 +++++++++++++++++++++
3 files changed, 601 insertions(+), 597 deletions(-)
delete mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c
create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
index 457cce9..db349c2 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
@@ -4,11 +4,12 @@
# I/O Library that uses compiler intrinsics to perform IN and OUT instructions
# for IA-32 and x64. On IPF, I/O port requests are translated into MMIO requests.
# MMIO requests are forwarded directly to memory. For EBC, I/O port requests
-# ASSERT().
+# ASSERT(). For ARM and RISC-V, I/O library only provides non I/O read and write.
#
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+# Portinos Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -25,7 +26,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
#
[Sources]
@@ -50,10 +51,13 @@
IoLib.c
[Sources.ARM]
- IoLibArm.c
+ IoLibNoIo.c
[Sources.AARCH64]
- IoLibArm.c
+ IoLibNoIo.c
+
+[Sources.RISCV64]
+ IoLibNoIo.c
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c b/MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c
deleted file mode 100644
index c6b8224..0000000
--- a/MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c
+++ /dev/null
@@ -1,593 +0,0 @@
-/** @file
- I/O Library for ARM.
-
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
- Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
- Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-
-//
-// Include common header file for this module.
-//
-#include "BaseIoLibIntrinsicInternal.h"
-
-/**
- Reads an 8-bit I/O port.
-
- Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
-
- @return The value read.
-
-**/
-UINT8
-EFIAPI
-IoRead8 (
- IN UINTN Port
- )
-{
- ASSERT (FALSE);
- return 0;
-}
-
-/**
- Writes an 8-bit I/O port.
-
- Writes the 8-bit I/O port specified by Port with the value specified by Value
- and returns Value. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Value The value to write to the I/O port.
-
- @return The value written the I/O port.
-
-**/
-UINT8
-EFIAPI
-IoWrite8 (
- IN UINTN Port,
- IN UINT8 Value
- )
-{
- ASSERT (FALSE);
- return Value;
-}
-
-/**
- Reads a 16-bit I/O port.
-
- Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
-
- @return The value read.
-
-**/
-UINT16
-EFIAPI
-IoRead16 (
- IN UINTN Port
- )
-{
- ASSERT (FALSE);
- return 0;
-}
-
-/**
- Writes a 16-bit I/O port.
-
- Writes the 16-bit I/O port specified by Port with the value specified by Value
- and returns Value. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Value The value to write to the I/O port.
-
- @return The value written the I/O port.
-
-**/
-UINT16
-EFIAPI
-IoWrite16 (
- IN UINTN Port,
- IN UINT16 Value
- )
-{
- ASSERT (FALSE);
- return Value;
-}
-
-/**
- Reads a 32-bit I/O port.
-
- Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
-
- @return The value read.
-
-**/
-UINT32
-EFIAPI
-IoRead32 (
- IN UINTN Port
- )
-{
- ASSERT (FALSE);
- return 0;
-}
-
-/**
- Writes a 32-bit I/O port.
-
- Writes the 32-bit I/O port specified by Port with the value specified by Value
- and returns Value. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Value The value to write to the I/O port.
-
- @return The value written the I/O port.
-
-**/
-UINT32
-EFIAPI
-IoWrite32 (
- IN UINTN Port,
- IN UINT32 Value
- )
-{
- ASSERT (FALSE);
- return Value;
-}
-
-/**
- Reads a 64-bit I/O port.
-
- Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 64-bit I/O port operations are not supported, then ASSERT().
- If Port is not aligned on a 64-bit boundary, then ASSERT().
-
- @param Port The I/O port to read.
-
- @return The value read.
-
-**/
-UINT64
-EFIAPI
-IoRead64 (
- IN UINTN Port
- )
-{
- ASSERT (FALSE);
- return 0;
-}
-
-/**
- Writes a 64-bit I/O port.
-
- Writes the 64-bit I/O port specified by Port with the value specified by Value
- and returns Value. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 64-bit I/O port operations are not supported, then ASSERT().
- If Port is not aligned on a 64-bit boundary, then ASSERT().
-
- @param Port The I/O port to write.
- @param Value The value to write to the I/O port.
-
- @return The value written to the I/O port.
-
-**/
-UINT64
-EFIAPI
-IoWrite64 (
- IN UINTN Port,
- IN UINT64 Value
- )
-{
- ASSERT (FALSE);
- return 0;
-}
-
-/**
- Reads an 8-bit I/O port fifo into a block of memory.
-
- Reads the 8-bit I/O fifo port specified by Port.
- The port is read Count times, and the read data is
- stored in the provided Buffer.
-
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
- @param Count The number of times to read I/O port.
- @param Buffer The buffer to store the read data into.
-
-**/
-VOID
-EFIAPI
-IoReadFifo8 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
- )
-{
- ASSERT (FALSE);
-}
-
-/**
- Writes a block of memory into an 8-bit I/O port fifo.
-
- Writes the 8-bit I/O fifo port specified by Port.
- The port is written Count times, and the write data is
- retrieved from the provided Buffer.
-
- This function must guarantee that all I/O write and write operations are
- serialized.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Count The number of times to write I/O port.
- @param Buffer The buffer to retrieve the write data from.
-
-**/
-VOID
-EFIAPI
-IoWriteFifo8 (
- IN UINTN Port,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- ASSERT (FALSE);
-}
-
-/**
- Reads a 16-bit I/O port fifo into a block of memory.
-
- Reads the 16-bit I/O fifo port specified by Port.
- The port is read Count times, and the read data is
- stored in the provided Buffer.
-
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
- @param Count The number of times to read I/O port.
- @param Buffer The buffer to store the read data into.
-
-**/
-VOID
-EFIAPI
-IoReadFifo16 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
- )
-{
- ASSERT (FALSE);
-}
-
-/**
- Writes a block of memory into a 16-bit I/O port fifo.
-
- Writes the 16-bit I/O fifo port specified by Port.
- The port is written Count times, and the write data is
- retrieved from the provided Buffer.
-
- This function must guarantee that all I/O write and write operations are
- serialized.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Count The number of times to write I/O port.
- @param Buffer The buffer to retrieve the write data from.
-
-**/
-VOID
-EFIAPI
-IoWriteFifo16 (
- IN UINTN Port,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- ASSERT (FALSE);
-}
-
-/**
- Reads a 32-bit I/O port fifo into a block of memory.
-
- Reads the 32-bit I/O fifo port specified by Port.
- The port is read Count times, and the read data is
- stored in the provided Buffer.
-
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
- @param Count The number of times to read I/O port.
- @param Buffer The buffer to store the read data into.
-
-**/
-VOID
-EFIAPI
-IoReadFifo32 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
- )
-{
- ASSERT (FALSE);
-}
-
-/**
- Writes a block of memory into a 32-bit I/O port fifo.
-
- Writes the 32-bit I/O fifo port specified by Port.
- The port is written Count times, and the write data is
- retrieved from the provided Buffer.
-
- This function must guarantee that all I/O write and write operations are
- serialized.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Count The number of times to write I/O port.
- @param Buffer The buffer to retrieve the write data from.
-
-**/
-VOID
-EFIAPI
-IoWriteFifo32 (
- IN UINTN Port,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- ASSERT (FALSE);
-}
-
-/**
- Reads an 8-bit MMIO register.
-
- Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 8-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT8
-EFIAPI
-MmioRead8 (
- IN UINTN Address
- )
-{
- UINT8 Value;
-
- Value = *(volatile UINT8*)Address;
- return Value;
-}
-
-/**
- Writes an 8-bit MMIO register.
-
- Writes the 8-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 8-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
-**/
-UINT8
-EFIAPI
-MmioWrite8 (
- IN UINTN Address,
- IN UINT8 Value
- )
-{
- *(volatile UINT8*)Address = Value;
- return Value;
-}
-
-/**
- Reads a 16-bit MMIO register.
-
- Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT16
-EFIAPI
-MmioRead16 (
- IN UINTN Address
- )
-{
- UINT16 Value;
-
- ASSERT ((Address & 1) == 0);
- Value = *(volatile UINT16*)Address;
- return Value;
-}
-
-/**
- Writes a 16-bit MMIO register.
-
- Writes the 16-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
-**/
-UINT16
-EFIAPI
-MmioWrite16 (
- IN UINTN Address,
- IN UINT16 Value
- )
-{
- ASSERT ((Address & 1) == 0);
- *(volatile UINT16*)Address = Value;
- return Value;
-}
-
-/**
- Reads a 32-bit MMIO register.
-
- Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT32
-EFIAPI
-MmioRead32 (
- IN UINTN Address
- )
-{
- UINT32 Value;
-
- ASSERT ((Address & 3) == 0);
- Value = *(volatile UINT32*)Address;
- return Value;
-}
-
-/**
- Writes a 32-bit MMIO register.
-
- Writes the 32-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
-**/
-UINT32
-EFIAPI
-MmioWrite32 (
- IN UINTN Address,
- IN UINT32 Value
- )
-{
- ASSERT ((Address & 3) == 0);
- *(volatile UINT32*)Address = Value;
- return Value;
-}
-
-/**
- Reads a 64-bit MMIO register.
-
- Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 64-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT64
-EFIAPI
-MmioRead64 (
- IN UINTN Address
- )
-{
- UINT64 Value;
-
- ASSERT ((Address & 7) == 0);
- Value = *(volatile UINT64*)Address;
- return Value;
-}
-
-/**
- Writes a 64-bit MMIO register.
-
- Writes the 64-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 64-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
-**/
-UINT64
-EFIAPI
-MmioWrite64 (
- IN UINTN Address,
- IN UINT64 Value
- )
-{
- ASSERT ((Address & 7) == 0);
- *(volatile UINT64*)Address = Value;
- return Value;
-}
-
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c b/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c
new file mode 100644
index 0000000..c6b8224
--- /dev/null
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c
@@ -0,0 +1,593 @@
+/** @file
+ I/O Library for ARM.
+
+ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+ Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+//
+// Include common header file for this module.
+//
+#include "BaseIoLibIntrinsicInternal.h"
+
+/**
+ Reads an 8-bit I/O port.
+
+ Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+IoRead8 (
+ IN UINTN Port
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes an 8-bit I/O port.
+
+ Writes the 8-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT8
+EFIAPI
+IoWrite8 (
+ IN UINTN Port,
+ IN UINT8 Value
+ )
+{
+ ASSERT (FALSE);
+ return Value;
+}
+
+/**
+ Reads a 16-bit I/O port.
+
+ Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+IoRead16 (
+ IN UINTN Port
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes a 16-bit I/O port.
+
+ Writes the 16-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT16
+EFIAPI
+IoWrite16 (
+ IN UINTN Port,
+ IN UINT16 Value
+ )
+{
+ ASSERT (FALSE);
+ return Value;
+}
+
+/**
+ Reads a 32-bit I/O port.
+
+ Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+IoRead32 (
+ IN UINTN Port
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes a 32-bit I/O port.
+
+ Writes the 32-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written the I/O port.
+
+**/
+UINT32
+EFIAPI
+IoWrite32 (
+ IN UINTN Port,
+ IN UINT32 Value
+ )
+{
+ ASSERT (FALSE);
+ return Value;
+}
+
+/**
+ Reads a 64-bit I/O port.
+
+ Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Port The I/O port to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+IoRead64 (
+ IN UINTN Port
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Writes a 64-bit I/O port.
+
+ Writes the 64-bit I/O port specified by Port with the value specified by Value
+ and returns Value. This function must guarantee that all I/O read and write
+ operations are serialized.
+
+ If 64-bit I/O port operations are not supported, then ASSERT().
+ If Port is not aligned on a 64-bit boundary, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Value The value to write to the I/O port.
+
+ @return The value written to the I/O port.
+
+**/
+UINT64
+EFIAPI
+IoWrite64 (
+ IN UINTN Port,
+ IN UINT64 Value
+ )
+{
+ ASSERT (FALSE);
+ return 0;
+}
+
+/**
+ Reads an 8-bit I/O port fifo into a block of memory.
+
+ Reads the 8-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Writes a block of memory into an 8-bit I/O port fifo.
+
+ Writes the 8-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 8-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+IoWriteFifo8 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Reads a 16-bit I/O port fifo into a block of memory.
+
+ Reads the 16-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Writes a block of memory into a 16-bit I/O port fifo.
+
+ Writes the 16-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 16-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+IoWriteFifo16 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Reads a 32-bit I/O port fifo into a block of memory.
+
+ Reads the 32-bit I/O fifo port specified by Port.
+ The port is read Count times, and the read data is
+ stored in the provided Buffer.
+
+ This function must guarantee that all I/O read and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to read.
+ @param Count The number of times to read I/O port.
+ @param Buffer The buffer to store the read data into.
+
+**/
+VOID
+EFIAPI
+IoReadFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ OUT VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Writes a block of memory into a 32-bit I/O port fifo.
+
+ Writes the 32-bit I/O fifo port specified by Port.
+ The port is written Count times, and the write data is
+ retrieved from the provided Buffer.
+
+ This function must guarantee that all I/O write and write operations are
+ serialized.
+
+ If 32-bit I/O port operations are not supported, then ASSERT().
+
+ @param Port The I/O port to write.
+ @param Count The number of times to write I/O port.
+ @param Buffer The buffer to retrieve the write data from.
+
+**/
+VOID
+EFIAPI
+IoWriteFifo32 (
+ IN UINTN Port,
+ IN UINTN Count,
+ IN VOID *Buffer
+ )
+{
+ ASSERT (FALSE);
+}
+
+/**
+ Reads an 8-bit MMIO register.
+
+ Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT8
+EFIAPI
+MmioRead8 (
+ IN UINTN Address
+ )
+{
+ UINT8 Value;
+
+ Value = *(volatile UINT8*)Address;
+ return Value;
+}
+
+/**
+ Writes an 8-bit MMIO register.
+
+ Writes the 8-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 8-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT8
+EFIAPI
+MmioWrite8 (
+ IN UINTN Address,
+ IN UINT8 Value
+ )
+{
+ *(volatile UINT8*)Address = Value;
+ return Value;
+}
+
+/**
+ Reads a 16-bit MMIO register.
+
+ Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT16
+EFIAPI
+MmioRead16 (
+ IN UINTN Address
+ )
+{
+ UINT16 Value;
+
+ ASSERT ((Address & 1) == 0);
+ Value = *(volatile UINT16*)Address;
+ return Value;
+}
+
+/**
+ Writes a 16-bit MMIO register.
+
+ Writes the 16-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 16-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT16
+EFIAPI
+MmioWrite16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ )
+{
+ ASSERT ((Address & 1) == 0);
+ *(volatile UINT16*)Address = Value;
+ return Value;
+}
+
+/**
+ Reads a 32-bit MMIO register.
+
+ Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT32
+EFIAPI
+MmioRead32 (
+ IN UINTN Address
+ )
+{
+ UINT32 Value;
+
+ ASSERT ((Address & 3) == 0);
+ Value = *(volatile UINT32*)Address;
+ return Value;
+}
+
+/**
+ Writes a 32-bit MMIO register.
+
+ Writes the 32-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 32-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT32
+EFIAPI
+MmioWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ ASSERT ((Address & 3) == 0);
+ *(volatile UINT32*)Address = Value;
+ return Value;
+}
+
+/**
+ Reads a 64-bit MMIO register.
+
+ Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
+ returned. This function must guarantee that all MMIO read and write
+ operations are serialized.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to read.
+
+ @return The value read.
+
+**/
+UINT64
+EFIAPI
+MmioRead64 (
+ IN UINTN Address
+ )
+{
+ UINT64 Value;
+
+ ASSERT ((Address & 7) == 0);
+ Value = *(volatile UINT64*)Address;
+ return Value;
+}
+
+/**
+ Writes a 64-bit MMIO register.
+
+ Writes the 64-bit MMIO register specified by Address with the value specified
+ by Value and returns Value. This function must guarantee that all MMIO read
+ and write operations are serialized.
+
+ If 64-bit MMIO register operations are not supported, then ASSERT().
+
+ @param Address The MMIO register to write.
+ @param Value The value to write to the MMIO register.
+
+**/
+UINT64
+EFIAPI
+MmioWrite64 (
+ IN UINTN Address,
+ IN UINT64 Value
+ )
+{
+ ASSERT ((Address & 7) == 0);
+ *(volatile UINT64*)Address = Value;
+ return Value;
+}
+
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* Re: [edk2-staging/RISC-V-V2 PATCH v3 09/39] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 09/39] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions Abner Chang
@ 2019-11-21 16:36 ` Leif Lindholm
0 siblings, 0 replies; 77+ messages in thread
From: Leif Lindholm @ 2019-11-21 16:36 UTC (permalink / raw)
To: Abner Chang; +Cc: devel, Michael D Kinney, Liming Gao, Gilbert Chen
On Mon, Oct 28, 2019 at 09:58:47 +0800, Abner Chang wrote:
> RISC-V MMIO library instance.
Need to remember to fix subject and description.
Something like
"MdePkg/BaseIoLibIntrinsic: rename IoLibArm.c => IoLibNoIo.c"
and
"IoLibArm.c in fact implements a generic Mmio-only (and ANSI C
compliant), so rename it to better reflect this."
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Gilbert Chen <gilbert.chen@hpe.com>
> ---
> .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 12 +-
> MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c | 593 ---------------------
> MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c | 593 +++++++++++++++++++++
> 3 files changed, 601 insertions(+), 597 deletions(-)
> delete mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c
> create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c
>
> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> index 457cce9..db349c2 100644
> --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> @@ -4,11 +4,12 @@
> # I/O Library that uses compiler intrinsics to perform IN and OUT instructions
> # for IA-32 and x64. On IPF, I/O port requests are translated into MMIO requests.
> # MMIO requests are forwarded directly to memory. For EBC, I/O port requests
> -# ASSERT().
> +# ASSERT(). For ARM and RISC-V, I/O library only provides non I/O read and write.
The ARM and RISC-V bit is beside the point, please drop that and start
with "I/O library..."
/
Leif
> #
> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> # Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> +# Portinos Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -25,7 +26,7 @@
>
>
> #
> -# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> +# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
> #
>
> [Sources]
> @@ -50,10 +51,13 @@
> IoLib.c
>
> [Sources.ARM]
> - IoLibArm.c
> + IoLibNoIo.c
>
> [Sources.AARCH64]
> - IoLibArm.c
> + IoLibNoIo.c
> +
> +[Sources.RISCV64]
> + IoLibNoIo.c
>
> [Packages]
> MdePkg/MdePkg.dec
> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c b/MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c
> deleted file mode 100644
> index c6b8224..0000000
> --- a/MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c
> +++ /dev/null
> @@ -1,593 +0,0 @@
> -/** @file
> - I/O Library for ARM.
> -
> - Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> - Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> - Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> -
> - SPDX-License-Identifier: BSD-2-Clause-Patent
> -
> -**/
> -
> -
> -//
> -// Include common header file for this module.
> -//
> -#include "BaseIoLibIntrinsicInternal.h"
> -
> -/**
> - Reads an 8-bit I/O port.
> -
> - Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
> - This function must guarantee that all I/O read and write operations are
> - serialized.
> -
> - If 8-bit I/O port operations are not supported, then ASSERT().
> -
> - @param Port The I/O port to read.
> -
> - @return The value read.
> -
> -**/
> -UINT8
> -EFIAPI
> -IoRead8 (
> - IN UINTN Port
> - )
> -{
> - ASSERT (FALSE);
> - return 0;
> -}
> -
> -/**
> - Writes an 8-bit I/O port.
> -
> - Writes the 8-bit I/O port specified by Port with the value specified by Value
> - and returns Value. This function must guarantee that all I/O read and write
> - operations are serialized.
> -
> - If 8-bit I/O port operations are not supported, then ASSERT().
> -
> - @param Port The I/O port to write.
> - @param Value The value to write to the I/O port.
> -
> - @return The value written the I/O port.
> -
> -**/
> -UINT8
> -EFIAPI
> -IoWrite8 (
> - IN UINTN Port,
> - IN UINT8 Value
> - )
> -{
> - ASSERT (FALSE);
> - return Value;
> -}
> -
> -/**
> - Reads a 16-bit I/O port.
> -
> - Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
> - This function must guarantee that all I/O read and write operations are
> - serialized.
> -
> - If 16-bit I/O port operations are not supported, then ASSERT().
> -
> - @param Port The I/O port to read.
> -
> - @return The value read.
> -
> -**/
> -UINT16
> -EFIAPI
> -IoRead16 (
> - IN UINTN Port
> - )
> -{
> - ASSERT (FALSE);
> - return 0;
> -}
> -
> -/**
> - Writes a 16-bit I/O port.
> -
> - Writes the 16-bit I/O port specified by Port with the value specified by Value
> - and returns Value. This function must guarantee that all I/O read and write
> - operations are serialized.
> -
> - If 16-bit I/O port operations are not supported, then ASSERT().
> -
> - @param Port The I/O port to write.
> - @param Value The value to write to the I/O port.
> -
> - @return The value written the I/O port.
> -
> -**/
> -UINT16
> -EFIAPI
> -IoWrite16 (
> - IN UINTN Port,
> - IN UINT16 Value
> - )
> -{
> - ASSERT (FALSE);
> - return Value;
> -}
> -
> -/**
> - Reads a 32-bit I/O port.
> -
> - Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
> - This function must guarantee that all I/O read and write operations are
> - serialized.
> -
> - If 32-bit I/O port operations are not supported, then ASSERT().
> -
> - @param Port The I/O port to read.
> -
> - @return The value read.
> -
> -**/
> -UINT32
> -EFIAPI
> -IoRead32 (
> - IN UINTN Port
> - )
> -{
> - ASSERT (FALSE);
> - return 0;
> -}
> -
> -/**
> - Writes a 32-bit I/O port.
> -
> - Writes the 32-bit I/O port specified by Port with the value specified by Value
> - and returns Value. This function must guarantee that all I/O read and write
> - operations are serialized.
> -
> - If 32-bit I/O port operations are not supported, then ASSERT().
> -
> - @param Port The I/O port to write.
> - @param Value The value to write to the I/O port.
> -
> - @return The value written the I/O port.
> -
> -**/
> -UINT32
> -EFIAPI
> -IoWrite32 (
> - IN UINTN Port,
> - IN UINT32 Value
> - )
> -{
> - ASSERT (FALSE);
> - return Value;
> -}
> -
> -/**
> - Reads a 64-bit I/O port.
> -
> - Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
> - This function must guarantee that all I/O read and write operations are
> - serialized.
> -
> - If 64-bit I/O port operations are not supported, then ASSERT().
> - If Port is not aligned on a 64-bit boundary, then ASSERT().
> -
> - @param Port The I/O port to read.
> -
> - @return The value read.
> -
> -**/
> -UINT64
> -EFIAPI
> -IoRead64 (
> - IN UINTN Port
> - )
> -{
> - ASSERT (FALSE);
> - return 0;
> -}
> -
> -/**
> - Writes a 64-bit I/O port.
> -
> - Writes the 64-bit I/O port specified by Port with the value specified by Value
> - and returns Value. This function must guarantee that all I/O read and write
> - operations are serialized.
> -
> - If 64-bit I/O port operations are not supported, then ASSERT().
> - If Port is not aligned on a 64-bit boundary, then ASSERT().
> -
> - @param Port The I/O port to write.
> - @param Value The value to write to the I/O port.
> -
> - @return The value written to the I/O port.
> -
> -**/
> -UINT64
> -EFIAPI
> -IoWrite64 (
> - IN UINTN Port,
> - IN UINT64 Value
> - )
> -{
> - ASSERT (FALSE);
> - return 0;
> -}
> -
> -/**
> - Reads an 8-bit I/O port fifo into a block of memory.
> -
> - Reads the 8-bit I/O fifo port specified by Port.
> - The port is read Count times, and the read data is
> - stored in the provided Buffer.
> -
> - This function must guarantee that all I/O read and write operations are
> - serialized.
> -
> - If 8-bit I/O port operations are not supported, then ASSERT().
> -
> - @param Port The I/O port to read.
> - @param Count The number of times to read I/O port.
> - @param Buffer The buffer to store the read data into.
> -
> -**/
> -VOID
> -EFIAPI
> -IoReadFifo8 (
> - IN UINTN Port,
> - IN UINTN Count,
> - OUT VOID *Buffer
> - )
> -{
> - ASSERT (FALSE);
> -}
> -
> -/**
> - Writes a block of memory into an 8-bit I/O port fifo.
> -
> - Writes the 8-bit I/O fifo port specified by Port.
> - The port is written Count times, and the write data is
> - retrieved from the provided Buffer.
> -
> - This function must guarantee that all I/O write and write operations are
> - serialized.
> -
> - If 8-bit I/O port operations are not supported, then ASSERT().
> -
> - @param Port The I/O port to write.
> - @param Count The number of times to write I/O port.
> - @param Buffer The buffer to retrieve the write data from.
> -
> -**/
> -VOID
> -EFIAPI
> -IoWriteFifo8 (
> - IN UINTN Port,
> - IN UINTN Count,
> - IN VOID *Buffer
> - )
> -{
> - ASSERT (FALSE);
> -}
> -
> -/**
> - Reads a 16-bit I/O port fifo into a block of memory.
> -
> - Reads the 16-bit I/O fifo port specified by Port.
> - The port is read Count times, and the read data is
> - stored in the provided Buffer.
> -
> - This function must guarantee that all I/O read and write operations are
> - serialized.
> -
> - If 16-bit I/O port operations are not supported, then ASSERT().
> -
> - @param Port The I/O port to read.
> - @param Count The number of times to read I/O port.
> - @param Buffer The buffer to store the read data into.
> -
> -**/
> -VOID
> -EFIAPI
> -IoReadFifo16 (
> - IN UINTN Port,
> - IN UINTN Count,
> - OUT VOID *Buffer
> - )
> -{
> - ASSERT (FALSE);
> -}
> -
> -/**
> - Writes a block of memory into a 16-bit I/O port fifo.
> -
> - Writes the 16-bit I/O fifo port specified by Port.
> - The port is written Count times, and the write data is
> - retrieved from the provided Buffer.
> -
> - This function must guarantee that all I/O write and write operations are
> - serialized.
> -
> - If 16-bit I/O port operations are not supported, then ASSERT().
> -
> - @param Port The I/O port to write.
> - @param Count The number of times to write I/O port.
> - @param Buffer The buffer to retrieve the write data from.
> -
> -**/
> -VOID
> -EFIAPI
> -IoWriteFifo16 (
> - IN UINTN Port,
> - IN UINTN Count,
> - IN VOID *Buffer
> - )
> -{
> - ASSERT (FALSE);
> -}
> -
> -/**
> - Reads a 32-bit I/O port fifo into a block of memory.
> -
> - Reads the 32-bit I/O fifo port specified by Port.
> - The port is read Count times, and the read data is
> - stored in the provided Buffer.
> -
> - This function must guarantee that all I/O read and write operations are
> - serialized.
> -
> - If 32-bit I/O port operations are not supported, then ASSERT().
> -
> - @param Port The I/O port to read.
> - @param Count The number of times to read I/O port.
> - @param Buffer The buffer to store the read data into.
> -
> -**/
> -VOID
> -EFIAPI
> -IoReadFifo32 (
> - IN UINTN Port,
> - IN UINTN Count,
> - OUT VOID *Buffer
> - )
> -{
> - ASSERT (FALSE);
> -}
> -
> -/**
> - Writes a block of memory into a 32-bit I/O port fifo.
> -
> - Writes the 32-bit I/O fifo port specified by Port.
> - The port is written Count times, and the write data is
> - retrieved from the provided Buffer.
> -
> - This function must guarantee that all I/O write and write operations are
> - serialized.
> -
> - If 32-bit I/O port operations are not supported, then ASSERT().
> -
> - @param Port The I/O port to write.
> - @param Count The number of times to write I/O port.
> - @param Buffer The buffer to retrieve the write data from.
> -
> -**/
> -VOID
> -EFIAPI
> -IoWriteFifo32 (
> - IN UINTN Port,
> - IN UINTN Count,
> - IN VOID *Buffer
> - )
> -{
> - ASSERT (FALSE);
> -}
> -
> -/**
> - Reads an 8-bit MMIO register.
> -
> - Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
> - returned. This function must guarantee that all MMIO read and write
> - operations are serialized.
> -
> - If 8-bit MMIO register operations are not supported, then ASSERT().
> -
> - @param Address The MMIO register to read.
> -
> - @return The value read.
> -
> -**/
> -UINT8
> -EFIAPI
> -MmioRead8 (
> - IN UINTN Address
> - )
> -{
> - UINT8 Value;
> -
> - Value = *(volatile UINT8*)Address;
> - return Value;
> -}
> -
> -/**
> - Writes an 8-bit MMIO register.
> -
> - Writes the 8-bit MMIO register specified by Address with the value specified
> - by Value and returns Value. This function must guarantee that all MMIO read
> - and write operations are serialized.
> -
> - If 8-bit MMIO register operations are not supported, then ASSERT().
> -
> - @param Address The MMIO register to write.
> - @param Value The value to write to the MMIO register.
> -
> -**/
> -UINT8
> -EFIAPI
> -MmioWrite8 (
> - IN UINTN Address,
> - IN UINT8 Value
> - )
> -{
> - *(volatile UINT8*)Address = Value;
> - return Value;
> -}
> -
> -/**
> - Reads a 16-bit MMIO register.
> -
> - Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
> - returned. This function must guarantee that all MMIO read and write
> - operations are serialized.
> -
> - If 16-bit MMIO register operations are not supported, then ASSERT().
> -
> - @param Address The MMIO register to read.
> -
> - @return The value read.
> -
> -**/
> -UINT16
> -EFIAPI
> -MmioRead16 (
> - IN UINTN Address
> - )
> -{
> - UINT16 Value;
> -
> - ASSERT ((Address & 1) == 0);
> - Value = *(volatile UINT16*)Address;
> - return Value;
> -}
> -
> -/**
> - Writes a 16-bit MMIO register.
> -
> - Writes the 16-bit MMIO register specified by Address with the value specified
> - by Value and returns Value. This function must guarantee that all MMIO read
> - and write operations are serialized.
> -
> - If 16-bit MMIO register operations are not supported, then ASSERT().
> -
> - @param Address The MMIO register to write.
> - @param Value The value to write to the MMIO register.
> -
> -**/
> -UINT16
> -EFIAPI
> -MmioWrite16 (
> - IN UINTN Address,
> - IN UINT16 Value
> - )
> -{
> - ASSERT ((Address & 1) == 0);
> - *(volatile UINT16*)Address = Value;
> - return Value;
> -}
> -
> -/**
> - Reads a 32-bit MMIO register.
> -
> - Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
> - returned. This function must guarantee that all MMIO read and write
> - operations are serialized.
> -
> - If 32-bit MMIO register operations are not supported, then ASSERT().
> -
> - @param Address The MMIO register to read.
> -
> - @return The value read.
> -
> -**/
> -UINT32
> -EFIAPI
> -MmioRead32 (
> - IN UINTN Address
> - )
> -{
> - UINT32 Value;
> -
> - ASSERT ((Address & 3) == 0);
> - Value = *(volatile UINT32*)Address;
> - return Value;
> -}
> -
> -/**
> - Writes a 32-bit MMIO register.
> -
> - Writes the 32-bit MMIO register specified by Address with the value specified
> - by Value and returns Value. This function must guarantee that all MMIO read
> - and write operations are serialized.
> -
> - If 32-bit MMIO register operations are not supported, then ASSERT().
> -
> - @param Address The MMIO register to write.
> - @param Value The value to write to the MMIO register.
> -
> -**/
> -UINT32
> -EFIAPI
> -MmioWrite32 (
> - IN UINTN Address,
> - IN UINT32 Value
> - )
> -{
> - ASSERT ((Address & 3) == 0);
> - *(volatile UINT32*)Address = Value;
> - return Value;
> -}
> -
> -/**
> - Reads a 64-bit MMIO register.
> -
> - Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
> - returned. This function must guarantee that all MMIO read and write
> - operations are serialized.
> -
> - If 64-bit MMIO register operations are not supported, then ASSERT().
> -
> - @param Address The MMIO register to read.
> -
> - @return The value read.
> -
> -**/
> -UINT64
> -EFIAPI
> -MmioRead64 (
> - IN UINTN Address
> - )
> -{
> - UINT64 Value;
> -
> - ASSERT ((Address & 7) == 0);
> - Value = *(volatile UINT64*)Address;
> - return Value;
> -}
> -
> -/**
> - Writes a 64-bit MMIO register.
> -
> - Writes the 64-bit MMIO register specified by Address with the value specified
> - by Value and returns Value. This function must guarantee that all MMIO read
> - and write operations are serialized.
> -
> - If 64-bit MMIO register operations are not supported, then ASSERT().
> -
> - @param Address The MMIO register to write.
> - @param Value The value to write to the MMIO register.
> -
> -**/
> -UINT64
> -EFIAPI
> -MmioWrite64 (
> - IN UINTN Address,
> - IN UINT64 Value
> - )
> -{
> - ASSERT ((Address & 7) == 0);
> - *(volatile UINT64*)Address = Value;
> - return Value;
> -}
> -
> diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c b/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c
> new file mode 100644
> index 0000000..c6b8224
> --- /dev/null
> +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c
> @@ -0,0 +1,593 @@
> +/** @file
> + I/O Library for ARM.
> +
> + Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> + Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +
> +//
> +// Include common header file for this module.
> +//
> +#include "BaseIoLibIntrinsicInternal.h"
> +
> +/**
> + Reads an 8-bit I/O port.
> +
> + Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
> + This function must guarantee that all I/O read and write operations are
> + serialized.
> +
> + If 8-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to read.
> +
> + @return The value read.
> +
> +**/
> +UINT8
> +EFIAPI
> +IoRead8 (
> + IN UINTN Port
> + )
> +{
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Writes an 8-bit I/O port.
> +
> + Writes the 8-bit I/O port specified by Port with the value specified by Value
> + and returns Value. This function must guarantee that all I/O read and write
> + operations are serialized.
> +
> + If 8-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Value The value to write to the I/O port.
> +
> + @return The value written the I/O port.
> +
> +**/
> +UINT8
> +EFIAPI
> +IoWrite8 (
> + IN UINTN Port,
> + IN UINT8 Value
> + )
> +{
> + ASSERT (FALSE);
> + return Value;
> +}
> +
> +/**
> + Reads a 16-bit I/O port.
> +
> + Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
> + This function must guarantee that all I/O read and write operations are
> + serialized.
> +
> + If 16-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to read.
> +
> + @return The value read.
> +
> +**/
> +UINT16
> +EFIAPI
> +IoRead16 (
> + IN UINTN Port
> + )
> +{
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Writes a 16-bit I/O port.
> +
> + Writes the 16-bit I/O port specified by Port with the value specified by Value
> + and returns Value. This function must guarantee that all I/O read and write
> + operations are serialized.
> +
> + If 16-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Value The value to write to the I/O port.
> +
> + @return The value written the I/O port.
> +
> +**/
> +UINT16
> +EFIAPI
> +IoWrite16 (
> + IN UINTN Port,
> + IN UINT16 Value
> + )
> +{
> + ASSERT (FALSE);
> + return Value;
> +}
> +
> +/**
> + Reads a 32-bit I/O port.
> +
> + Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
> + This function must guarantee that all I/O read and write operations are
> + serialized.
> +
> + If 32-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to read.
> +
> + @return The value read.
> +
> +**/
> +UINT32
> +EFIAPI
> +IoRead32 (
> + IN UINTN Port
> + )
> +{
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Writes a 32-bit I/O port.
> +
> + Writes the 32-bit I/O port specified by Port with the value specified by Value
> + and returns Value. This function must guarantee that all I/O read and write
> + operations are serialized.
> +
> + If 32-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Value The value to write to the I/O port.
> +
> + @return The value written the I/O port.
> +
> +**/
> +UINT32
> +EFIAPI
> +IoWrite32 (
> + IN UINTN Port,
> + IN UINT32 Value
> + )
> +{
> + ASSERT (FALSE);
> + return Value;
> +}
> +
> +/**
> + Reads a 64-bit I/O port.
> +
> + Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
> + This function must guarantee that all I/O read and write operations are
> + serialized.
> +
> + If 64-bit I/O port operations are not supported, then ASSERT().
> + If Port is not aligned on a 64-bit boundary, then ASSERT().
> +
> + @param Port The I/O port to read.
> +
> + @return The value read.
> +
> +**/
> +UINT64
> +EFIAPI
> +IoRead64 (
> + IN UINTN Port
> + )
> +{
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Writes a 64-bit I/O port.
> +
> + Writes the 64-bit I/O port specified by Port with the value specified by Value
> + and returns Value. This function must guarantee that all I/O read and write
> + operations are serialized.
> +
> + If 64-bit I/O port operations are not supported, then ASSERT().
> + If Port is not aligned on a 64-bit boundary, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Value The value to write to the I/O port.
> +
> + @return The value written to the I/O port.
> +
> +**/
> +UINT64
> +EFIAPI
> +IoWrite64 (
> + IN UINTN Port,
> + IN UINT64 Value
> + )
> +{
> + ASSERT (FALSE);
> + return 0;
> +}
> +
> +/**
> + Reads an 8-bit I/O port fifo into a block of memory.
> +
> + Reads the 8-bit I/O fifo port specified by Port.
> + The port is read Count times, and the read data is
> + stored in the provided Buffer.
> +
> + This function must guarantee that all I/O read and write operations are
> + serialized.
> +
> + If 8-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to read.
> + @param Count The number of times to read I/O port.
> + @param Buffer The buffer to store the read data into.
> +
> +**/
> +VOID
> +EFIAPI
> +IoReadFifo8 (
> + IN UINTN Port,
> + IN UINTN Count,
> + OUT VOID *Buffer
> + )
> +{
> + ASSERT (FALSE);
> +}
> +
> +/**
> + Writes a block of memory into an 8-bit I/O port fifo.
> +
> + Writes the 8-bit I/O fifo port specified by Port.
> + The port is written Count times, and the write data is
> + retrieved from the provided Buffer.
> +
> + This function must guarantee that all I/O write and write operations are
> + serialized.
> +
> + If 8-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Count The number of times to write I/O port.
> + @param Buffer The buffer to retrieve the write data from.
> +
> +**/
> +VOID
> +EFIAPI
> +IoWriteFifo8 (
> + IN UINTN Port,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + ASSERT (FALSE);
> +}
> +
> +/**
> + Reads a 16-bit I/O port fifo into a block of memory.
> +
> + Reads the 16-bit I/O fifo port specified by Port.
> + The port is read Count times, and the read data is
> + stored in the provided Buffer.
> +
> + This function must guarantee that all I/O read and write operations are
> + serialized.
> +
> + If 16-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to read.
> + @param Count The number of times to read I/O port.
> + @param Buffer The buffer to store the read data into.
> +
> +**/
> +VOID
> +EFIAPI
> +IoReadFifo16 (
> + IN UINTN Port,
> + IN UINTN Count,
> + OUT VOID *Buffer
> + )
> +{
> + ASSERT (FALSE);
> +}
> +
> +/**
> + Writes a block of memory into a 16-bit I/O port fifo.
> +
> + Writes the 16-bit I/O fifo port specified by Port.
> + The port is written Count times, and the write data is
> + retrieved from the provided Buffer.
> +
> + This function must guarantee that all I/O write and write operations are
> + serialized.
> +
> + If 16-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Count The number of times to write I/O port.
> + @param Buffer The buffer to retrieve the write data from.
> +
> +**/
> +VOID
> +EFIAPI
> +IoWriteFifo16 (
> + IN UINTN Port,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + ASSERT (FALSE);
> +}
> +
> +/**
> + Reads a 32-bit I/O port fifo into a block of memory.
> +
> + Reads the 32-bit I/O fifo port specified by Port.
> + The port is read Count times, and the read data is
> + stored in the provided Buffer.
> +
> + This function must guarantee that all I/O read and write operations are
> + serialized.
> +
> + If 32-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to read.
> + @param Count The number of times to read I/O port.
> + @param Buffer The buffer to store the read data into.
> +
> +**/
> +VOID
> +EFIAPI
> +IoReadFifo32 (
> + IN UINTN Port,
> + IN UINTN Count,
> + OUT VOID *Buffer
> + )
> +{
> + ASSERT (FALSE);
> +}
> +
> +/**
> + Writes a block of memory into a 32-bit I/O port fifo.
> +
> + Writes the 32-bit I/O fifo port specified by Port.
> + The port is written Count times, and the write data is
> + retrieved from the provided Buffer.
> +
> + This function must guarantee that all I/O write and write operations are
> + serialized.
> +
> + If 32-bit I/O port operations are not supported, then ASSERT().
> +
> + @param Port The I/O port to write.
> + @param Count The number of times to write I/O port.
> + @param Buffer The buffer to retrieve the write data from.
> +
> +**/
> +VOID
> +EFIAPI
> +IoWriteFifo32 (
> + IN UINTN Port,
> + IN UINTN Count,
> + IN VOID *Buffer
> + )
> +{
> + ASSERT (FALSE);
> +}
> +
> +/**
> + Reads an 8-bit MMIO register.
> +
> + Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
> + returned. This function must guarantee that all MMIO read and write
> + operations are serialized.
> +
> + If 8-bit MMIO register operations are not supported, then ASSERT().
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT8
> +EFIAPI
> +MmioRead8 (
> + IN UINTN Address
> + )
> +{
> + UINT8 Value;
> +
> + Value = *(volatile UINT8*)Address;
> + return Value;
> +}
> +
> +/**
> + Writes an 8-bit MMIO register.
> +
> + Writes the 8-bit MMIO register specified by Address with the value specified
> + by Value and returns Value. This function must guarantee that all MMIO read
> + and write operations are serialized.
> +
> + If 8-bit MMIO register operations are not supported, then ASSERT().
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT8
> +EFIAPI
> +MmioWrite8 (
> + IN UINTN Address,
> + IN UINT8 Value
> + )
> +{
> + *(volatile UINT8*)Address = Value;
> + return Value;
> +}
> +
> +/**
> + Reads a 16-bit MMIO register.
> +
> + Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
> + returned. This function must guarantee that all MMIO read and write
> + operations are serialized.
> +
> + If 16-bit MMIO register operations are not supported, then ASSERT().
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT16
> +EFIAPI
> +MmioRead16 (
> + IN UINTN Address
> + )
> +{
> + UINT16 Value;
> +
> + ASSERT ((Address & 1) == 0);
> + Value = *(volatile UINT16*)Address;
> + return Value;
> +}
> +
> +/**
> + Writes a 16-bit MMIO register.
> +
> + Writes the 16-bit MMIO register specified by Address with the value specified
> + by Value and returns Value. This function must guarantee that all MMIO read
> + and write operations are serialized.
> +
> + If 16-bit MMIO register operations are not supported, then ASSERT().
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT16
> +EFIAPI
> +MmioWrite16 (
> + IN UINTN Address,
> + IN UINT16 Value
> + )
> +{
> + ASSERT ((Address & 1) == 0);
> + *(volatile UINT16*)Address = Value;
> + return Value;
> +}
> +
> +/**
> + Reads a 32-bit MMIO register.
> +
> + Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
> + returned. This function must guarantee that all MMIO read and write
> + operations are serialized.
> +
> + If 32-bit MMIO register operations are not supported, then ASSERT().
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT32
> +EFIAPI
> +MmioRead32 (
> + IN UINTN Address
> + )
> +{
> + UINT32 Value;
> +
> + ASSERT ((Address & 3) == 0);
> + Value = *(volatile UINT32*)Address;
> + return Value;
> +}
> +
> +/**
> + Writes a 32-bit MMIO register.
> +
> + Writes the 32-bit MMIO register specified by Address with the value specified
> + by Value and returns Value. This function must guarantee that all MMIO read
> + and write operations are serialized.
> +
> + If 32-bit MMIO register operations are not supported, then ASSERT().
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT32
> +EFIAPI
> +MmioWrite32 (
> + IN UINTN Address,
> + IN UINT32 Value
> + )
> +{
> + ASSERT ((Address & 3) == 0);
> + *(volatile UINT32*)Address = Value;
> + return Value;
> +}
> +
> +/**
> + Reads a 64-bit MMIO register.
> +
> + Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
> + returned. This function must guarantee that all MMIO read and write
> + operations are serialized.
> +
> + If 64-bit MMIO register operations are not supported, then ASSERT().
> +
> + @param Address The MMIO register to read.
> +
> + @return The value read.
> +
> +**/
> +UINT64
> +EFIAPI
> +MmioRead64 (
> + IN UINTN Address
> + )
> +{
> + UINT64 Value;
> +
> + ASSERT ((Address & 7) == 0);
> + Value = *(volatile UINT64*)Address;
> + return Value;
> +}
> +
> +/**
> + Writes a 64-bit MMIO register.
> +
> + Writes the 64-bit MMIO register specified by Address with the value specified
> + by Value and returns Value. This function must guarantee that all MMIO read
> + and write operations are serialized.
> +
> + If 64-bit MMIO register operations are not supported, then ASSERT().
> +
> + @param Address The MMIO register to write.
> + @param Value The value to write to the MMIO register.
> +
> +**/
> +UINT64
> +EFIAPI
> +MmioWrite64 (
> + IN UINTN Address,
> + IN UINT64 Value
> + )
> +{
> + ASSERT ((Address & 7) == 0);
> + *(volatile UINT64*)Address = Value;
> + return Value;
> +}
> +
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 77+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v3 10/39] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (8 preceding siblings ...)
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 09/39] MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 11/39] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation Abner Chang
` (28 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Liming Gao, Leif Lindholm,
Gilbert Chen
Support RISC-V image relocation.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
.../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 9 ++
MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
.../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 133 +++++++++++++++++++++
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +
5 files changed, 151 insertions(+), 1 deletion(-)
create mode 100644 MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
index 395c140..50546eb 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
@@ -3,6 +3,7 @@
# The IPF version library supports loading IPF and EBC PE/COFF image.
# The IA32 version library support loading IA32, X64 and EBC PE/COFF images.
# The X64 version library support loading IA32, X64 and EBC PE/COFF images.
+# The RISC-V version library support loading RISC-V images.
#
# Caution: This module requires additional review when modified.
# This library will have external input - PE/COFF image.
@@ -11,6 +12,7 @@
#
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -41,6 +43,9 @@
[Sources.ARM]
Arm/PeCoffLoaderEx.c
+[Sources.RISCV64]
+ RiscV/PeCoffLoaderEx.c
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
index b74277f..f8eea65 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLibInternals.h
@@ -2,6 +2,7 @@
Declaration of internal functions in PE/COFF Lib.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -16,6 +17,14 @@
#include <Library/PeCoffExtraActionLib.h>
#include <IndustryStandard/PeImage.h>
+//
+// Macro definitions for RISC-V architecture.
+//
+#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
+#define RISCV_IMM_BITS 12
+#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
+#define RISCV_CONST_HIGH_PART(VALUE) \
+ (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
/**
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
index 07bb62f..25ffcb1 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
@@ -1,6 +1,6 @@
/** @file
Base PE/COFF loader supports loading any PE32/PE32+ or TE image, but
- only supports relocating IA32, x64, IPF, and EBC images.
+ only supports relocating IA32, x64, IPF, ARM, RISC-V and EBC images.
Caution: This file requires additional review when modified.
This library will have external input - PE/COFF image.
@@ -17,6 +17,7 @@
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
new file mode 100644
index 0000000..e4aba4c
--- /dev/null
+++ b/MdePkg/Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c
@@ -0,0 +1,133 @@
+/** @file
+ PE/Coff loader for RISC-V PE image
+
+ Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "BasePeCoffLibInternals.h"
+#include <Library/BaseLib.h>
+
+/**
+ Performs an RISC-V specific relocation fixup and is a no-op on
+ other instruction sets.
+ RISC-V splits 32-bit fixup into 20bit and 12-bit with two relocation
+ types. We have to know the lower 12-bit fixup first then we can deal
+ carry over on high 20-bit fixup. So we log the high 20-bit in
+ FixupData.
+
+ @param Reloc The pointer to the relocation record.
+ @param Fixup The pointer to the address to fix up.
+ @param FixupData The pointer to a buffer to log the fixups.
+ @param Adjust The offset to adjust the fixup.
+
+ @return Status code.
+
+**/
+RETURN_STATUS
+PeCoffLoaderRelocateImageEx (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ )
+{
+ UINT32 Value;
+ UINT32 Value2;
+ UINT32 *RiscVHi20Fixup;
+
+ switch ((*Reloc) >> 12) {
+ case EFI_IMAGE_REL_BASED_RISCV_HI20:
+ *(UINT64 *)(*FixupData) = (UINT64)(UINTN)Fixup;
+ break;
+
+ case EFI_IMAGE_REL_BASED_RISCV_LOW12I:
+ RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));
+ if (RiscVHi20Fixup != NULL) {
+
+ Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
+ Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12));
+ if (Value2 & (RISCV_IMM_REACH/2)) {
+ Value2 |= ~(RISCV_IMM_REACH-1);
+ }
+ Value += Value2;
+ Value += (UINT32)Adjust;
+ Value2 = RISCV_CONST_HIGH_PART (Value);
+ *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) |\
+ (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
+ *(UINT32 *)Fixup = (RV_X (Value, 0, 12) << 20) |\
+ (RV_X (*(UINT32 *)Fixup, 0, 20));
+ }
+ break;
+
+ case EFI_IMAGE_REL_BASED_RISCV_LOW12S:
+ RiscVHi20Fixup = (UINT32 *)(*(UINT64 *)(*FixupData));
+ if (RiscVHi20Fixup != NULL) {
+ Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
+ Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 *)Fixup, 25, 7) << 5));
+ if (Value2 & (RISCV_IMM_REACH/2)) {
+ Value2 |= ~(RISCV_IMM_REACH-1);
+ }
+ Value += Value2;
+ Value += (UINT32)Adjust;
+ Value2 = RISCV_CONST_HIGH_PART (Value);
+ *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
+ (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
+ Value2 = *(UINT32 *)Fixup & 0x01fff07f;
+ Value &= RISCV_IMM_REACH - 1;
+ *(UINT32 *)Fixup = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) | (RV_X(Value, 5, 7) << 25)));
+ }
+ break;
+
+ default:
+ return RETURN_UNSUPPORTED;
+
+ }
+ return RETURN_SUCCESS;
+}
+
+/**
+ Returns TRUE if the machine type of PE/COFF image is supported. Supported
+ does not mean the image can be executed it means the PE/COFF loader supports
+ loading and relocating of the image type. It's up to the caller to support
+ the entry point.
+
+ @param Machine Machine type from the PE Header.
+
+ @return TRUE if this PE/COFF loader can load the image
+
+**/
+BOOLEAN
+PeCoffLoaderImageFormatSupported (
+ IN UINT16 Machine
+ )
+{
+ if (Machine == IMAGE_FILE_MACHINE_RISCV64) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+/**
+ Performs an Itanium-based specific re-relocation fixup and is a no-op on other
+ instruction sets. This is used to re-relocated the image into the EFI virtual
+ space for runtime calls.
+
+ @param Reloc The pointer to the relocation record.
+ @param Fixup The pointer to the address to fix up.
+ @param FixupData The pointer to a buffer to log the fixups.
+ @param Adjust The offset to adjust the fixup.
+
+ @return Status code.
+
+**/
+RETURN_STATUS
+PeHotRelocateImageEx (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ )
+{
+ return RETURN_UNSUPPORTED;
+}
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
index b0ea702..cf45f1d 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
@@ -4,6 +4,7 @@
// The IPF version library supports loading IPF and EBC PE/COFF image.
// The IA32 version library support loading IA32, X64 and EBC PE/COFF images.
// The X64 version library support loading IA32, X64 and EBC PE/COFF images.
+// The RISC-V version library support loading RISC-V32 and RISC-V64 PE/COFF images.
//
// Caution: This module requires additional review when modified.
// This library will have external input - PE/COFF image.
@@ -12,6 +13,7 @@
//
// Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+// Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 11/39] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation.
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (9 preceding siblings ...)
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 10/39] MdePkg/BasePeCoff: Add RISC-V PE/Coff related code Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 12/39] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
` (27 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Liming Gao, Leif Lindholm,
Gilbert Chen
Implement RISC-V CPU related functions in BaseCpuLib.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 +++++-
MdePkg/Library/BaseCpuLib/BaseCpuLib.uni | 5 +++--
MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | 19 +++++++++++++++++++
3 files changed, 27 insertions(+), 3 deletions(-)
create mode 100644 MdePkg/Library/BaseCpuLib/RiscV/Cpu.S
diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
index a7cb381..a95d8a0 100644
--- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
@@ -7,6 +7,7 @@
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -24,7 +25,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
#
[Sources.IA32]
@@ -59,6 +60,9 @@
AArch64/CpuFlushTlb.asm | MSFT
AArch64/CpuSleep.asm | MSFT
+[Sources.RISCV64]
+ RiscV/Cpu.S
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
index fc95cda..85d56ce 100644
--- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
+++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
@@ -1,12 +1,13 @@
// /** @file
// Instance of CPU Library for various architecture.
//
-// CPU Library implemented using ASM functions for IA-32 and X64,
+// CPU Library implemented using ASM functions for IA-32, X64 and RISCV64,
// PAL CALLs for IPF, and empty functions for EBC.
//
// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
// Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -15,5 +16,5 @@
#string STR_MODULE_ABSTRACT #language en-US "Instance of CPU Library for various architectures"
-#string STR_MODULE_DESCRIPTION #language en-US "CPU Library implemented using ASM functions for IA-32 and X64, PAL CALLs for IPF, and empty functions for EBC."
+#string STR_MODULE_DESCRIPTION #language en-US "CPU Library implemented using ASM functions for IA-32, X64 and RISCV64, PAL CALLs for IPF, and empty functions for EBC."
diff --git a/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S
new file mode 100644
index 0000000..703b1e8
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/RiscV/Cpu.S
@@ -0,0 +1,19 @@
+//------------------------------------------------------------------------------
+//
+// CpuSleep for RISC-V
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+.data
+.align 3
+.section .text
+
+.global ASM_PFX(_CpuSleep)
+
+ASM_PFX(_CpuSleep):
+ wfi
+ ret
+
+
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 12/39] MdePkg/BaseSynchronizationLib: RISC-V cache related code.
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (10 preceding siblings ...)
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 11/39] MdePkg/BaseCpuLib: RISC-V Base CPU library implementation Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 13/39] MdeModulePkg/Logo Abner Chang
` (26 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel
Cc: abner.chang, Michael D Kinney, Liming Gao, Leif Lindholm,
Gilbert Chen
Support RISC-V cache related functions.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../BaseSynchronizationLib.inf | 5 ++
.../RiscV64/SynchronizationAsm.S | 78 ++++++++++++++++++++++
2 files changed, 83 insertions(+)
create mode 100644 MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
index 446bc19..c227f0c 100755
--- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
@@ -3,6 +3,7 @@
#
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -78,6 +79,10 @@
AArch64/Synchronization.S | GCC
AArch64/Synchronization.asm | MSFT
+[Sources.RISCV64]
+ Synchronization.c
+ RiscV64/SynchronizationAsm.S
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
new file mode 100644
index 0000000..40a9f1e
--- /dev/null
+++ b/MdePkg/Library/BaseSynchronizationLib/RiscV64/SynchronizationAsm.S
@@ -0,0 +1,78 @@
+//------------------------------------------------------------------------------
+//
+// RISC-V synchronization functions.
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <Base.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(InternalSyncCompareExchange32)
+.global ASM_PFX(InternalSyncCompareExchange64)
+.global ASM_PFX(InternalSyncIncrement)
+.global ASM_PFX(InternalSyncDecrement)
+
+//
+// ompare and xchange a 32-bit value.
+//
+// @param a0 : Pointer to 32-bit value.
+// @param a1 : Compare value.
+// @param a2 : Exchange value.
+//
+ASM_PFX (InternalSyncCompareExchange32):
+ lr.w a3, (a0) // Load the value from a0 and make
+ // the reservation of address.
+ bne a3, a1, exit
+ sc.w a3, a2, (a0) // Write the value back to the address.
+ mv a3, a1
+exit:
+ mv a0, a3
+ ret
+
+.global ASM_PFX(InternalSyncCompareExchange64)
+
+//
+// Compare and xchange a 64-bit value.
+//
+// @param a0 : Pointer to 64-bit value.
+// @param a1 : Compare value.
+// @param a2 : Exchange value.
+//
+ASM_PFX (SyncCompareExchange64):
+ lr.d a3, (a0) // Load the value from a0 and make
+ // the reservation of address.
+ bne a3, a1, exit
+ sc.d a3, a2, (a0) // Write the value back to the address.
+ mv a3, a1
+exit2:
+ mv a0, a3
+ ret
+
+//
+// Performs an atomic increment of an 32-bit unsigned integer.
+//
+// @param a0 : Pointer to 32-bit value.
+//
+ASM_PFX (InternalSyncIncrement):
+ li a1, 1
+ amoadd.w a2, a1, (a0)
+ mv a0, a2
+ ret
+
+//
+// Performs an atomic decrement of an 32-bit unsigned integer.
+//
+// @param a0 : Pointer to 32-bit value.
+//
+ASM_PFX (InternalSyncDecrement):
+ li a1, -1
+ amoadd.w a2, a1, (a0)
+ mv a0, a2
+ ret
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 13/39] MdeModulePkg/Logo
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (11 preceding siblings ...)
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 12/39] MdePkg/BaseSynchronizationLib: RISC-V cache related code Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 14/39] NetworkPkg Abner Chang
` (25 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Zhichao Gao, Ray Ni, Leif Lindholm, Gilbert Chen
Add RISCV64 Arch.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
MdeModulePkg/Logo/Logo.inf | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MdeModulePkg/Logo/Logo.inf b/MdeModulePkg/Logo/Logo.inf
index 0182025..243748c 100644
--- a/MdeModulePkg/Logo/Logo.inf
+++ b/MdeModulePkg/Logo/Logo.inf
@@ -19,7 +19,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
#
[Binaries]
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 14/39] NetworkPkg
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (12 preceding siblings ...)
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 13/39] MdeModulePkg/Logo Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 15/39] RiscVPkg/Library: RISC-V CPU library Abner Chang
` (24 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Siyuan Fu, Jiaxin Wu, Leif Lindholm, Gilbert Chen
Add RISCV64 Arch.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
NetworkPkg/Network.dsc.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/NetworkPkg/Network.dsc.inc b/NetworkPkg/Network.dsc.inc
index c7f4328..b484f9b 100644
--- a/NetworkPkg/Network.dsc.inc
+++ b/NetworkPkg/Network.dsc.inc
@@ -34,7 +34,7 @@
!include NetworkPkg/NetworkComponents.dsc.inc
!else
-[Components.IA32, Components.X64, Components.ARM, Components.AARCH64]
+[Components.IA32, Components.X64, Components.ARM, Components.AARCH64, Components.RISCV64]
!include NetworkPkg/NetworkComponents.dsc.inc
!endif
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 15/39] RiscVPkg/Library: RISC-V CPU library
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (13 preceding siblings ...)
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 14/39] NetworkPkg Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 16/39] RiscVPkg/Library: Add RISC-V exception library Abner Chang
` (23 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
This library provides CSR assembly functions to read/write RISC-V
specific Control and Status registers.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf | 34 ++++++++
RiscVPkg/Include/Library/RiscVCpuLib.h | 68 ++++++++++++++++
RiscVPkg/Library/RiscVCpuLib/Cpu.S | 115 +++++++++++++++++++++++++++
3 files changed, 217 insertions(+)
create mode 100644 RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
create mode 100644 RiscVPkg/Include/Library/RiscVCpuLib.h
create mode 100644 RiscVPkg/Library/RiscVCpuLib/Cpu.S
diff --git a/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf b/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
new file mode 100644
index 0000000..fc9131b
--- /dev/null
+++ b/RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
@@ -0,0 +1,34 @@
+## @file
+# RISC-V RV64 CPU library
+#
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVCpuLib
+ FILE_GUID = 8C6CFB0D-A0EE-40D5-90DA-2E51EAE0583F
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVCpuLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+
+[Sources.RISCV64]
+ Cpu.S
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+
diff --git a/RiscVPkg/Include/Library/RiscVCpuLib.h b/RiscVPkg/Include/Library/RiscVCpuLib.h
new file mode 100644
index 0000000..58c763a
--- /dev/null
+++ b/RiscVPkg/Include/Library/RiscVCpuLib.h
@@ -0,0 +1,68 @@
+/** @file
+ RISC-V CPU library definitions.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef RISCV_CPU_LIB_H_
+#define RISCV_CPU_LIB_H_
+
+#include "RiscVImpl.h"
+
+/**
+ RISCV_TRAP_HANDLER
+**/
+typedef
+VOID
+(EFIAPI *RISCV_TRAP_HANDLER)(
+ VOID
+ );
+
+VOID
+RiscVSetScratch (RISCV_MACHINE_MODE_CONTEXT *RiscvContext);
+
+UINT32
+RiscVGetScratch (VOID);
+
+UINT32
+RiscVGetTrapCause (VOID);
+
+UINT64
+RiscVReadMachineTimer (VOID);
+
+VOID
+RiscVSetMachineTimerCmp (UINT64);
+
+UINT64
+RiscVReadMachineTimerCmp(VOID);
+
+UINT64
+RiscVReadMachineIE(VOID);
+
+UINT64
+RiscVReadMachineIP(VOID);
+
+UINT64
+RiscVReadMachineStatus(VOID);
+
+VOID
+RiscVWriteMachineStatus(UINT64);
+
+UINT64
+RiscVReadMachineTvec(VOID);
+
+UINT64
+RiscVReadMisa (VOID);
+
+UINT64
+RiscVReadMVendorId (VOID);
+
+UINT64
+RiscVReadMArchId (VOID);
+
+UINT64
+RiscVReadMImplId (VOID);
+
+#endif
diff --git a/RiscVPkg/Library/RiscVCpuLib/Cpu.S b/RiscVPkg/Library/RiscVCpuLib/Cpu.S
new file mode 100644
index 0000000..2b68b9d
--- /dev/null
+++ b/RiscVPkg/Library/RiscVCpuLib/Cpu.S
@@ -0,0 +1,115 @@
+//------------------------------------------------------------------------------
+//
+// RISC-V CPU functions.
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <Base.h>
+#include <RiscVImpl.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(RiscVSetScratch)
+.global ASM_PFX(RiscVGetScratch)
+.global ASM_PFX(RiscVGetMachineTrapCause)
+.global ASM_PFX(RiscVReadMachineIE)
+.global ASM_PFX(RiscVReadMachineIP)
+.global ASM_PFX(RiscVReadMachineStatus)
+.global ASM_PFX(RiscVWriteMachineStatus)
+.global ASM_PFX(RiscVReadMachineTvec)
+.global ASM_PFX(RiscVReadMisa)
+.global ASM_PFX(RiscVReadMVendorId)
+.global ASM_PFX(RiscVReadMArchId)
+.global ASM_PFX(RiscVReadMImplId)
+//
+// Set machine mode scratch.
+// @param a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
+//
+ASM_PFX (RiscVSetScratch):
+ csrrw a1, RISCV_CSR_MACHINE_MSCRATCH, a0
+ ret
+
+//
+// Get machine mode scratch.
+// @retval a0 : Pointer to RISCV_MACHINE_MODE_CONTEXT.
+//
+ASM_PFX (RiscVGetScratch):
+ csrrs a0, RISCV_CSR_MACHINE_MSCRATCH, 0
+ ret
+
+//
+// Get machine trap cause CSR.
+//
+ASM_PFX (RiscVGetMachineTrapCause):
+ csrrs a0, RISCV_CSR_MACHINE_MCAUSE, 0
+ ret
+
+//
+// Get machine interrupt enable
+//
+ASM_PFX (RiscVReadMachineIE):
+ csrr a0, RISCV_CSR_MACHINE_MIE
+ ret
+
+//
+// Get machine interrupt pending
+//
+ASM_PFX (RiscVReadMachineIP):
+ csrr a0, RISCV_CSR_MACHINE_MIP
+ ret
+
+//
+// Get machine status
+//
+ASM_PFX(RiscVReadMachineStatus):
+ csrr a0, RISCV_CSR_MACHINE_MSTATUS
+ ret
+
+//
+// Set machine status
+//
+ASM_PFX(RiscVWriteMachineStatus):
+ csrw RISCV_CSR_MACHINE_MSTATUS, a0
+ ret
+
+//
+// Get machine trap vector
+//
+ASM_PFX(RiscVReadMachineTvec):
+ csrr a0, RISCV_CSR_MACHINE_MTVEC
+ ret
+
+//
+// Read machine ISA
+//
+ASM_PFX(RiscVReadMisa):
+ csrr a0, RISCV_CSR_MACHINE_MISA
+ ret
+
+//
+// Read machine vendor ID
+//
+ASM_PFX(RiscVReadMVendorId):
+ csrr a0, RISCV_CSR_MACHINE_MVENDORID
+ ret
+
+//
+// Read machine architecture ID
+//
+ASM_PFX(RiscVReadMArchId):
+ csrr a0, RISCV_CSR_MACHINE_MARCHID
+ ret
+
+//
+// Read machine implementation ID
+//
+ASM_PFX(RiscVReadMImplId):
+ csrr a0, RISCV_CSR_MACHINE_MIMPID
+ ret
+
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 16/39] RiscVPkg/Library: Add RISC-V exception library
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (14 preceding siblings ...)
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 15/39] RiscVPkg/Library: RISC-V CPU library Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 17/39] RiscVPkg/Library: Add RISC-V timer library Abner Chang
` (22 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
Initial RISC-V Supervisor Mode trap handler.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../CpuExceptionHandlerDxeLib.inf | 43 +++++
.../RiscVExceptionLib/CpuExceptionHandlerLib.h | 16 ++
.../RiscVExceptionLib/CpuExceptionHandlerLib.c | 191 +++++++++++++++++++++
.../RiscVExceptionLib/CpuExceptionHandlerLib.uni | 13 ++
.../RiscVExceptionLib/SupervisorTrapHandler.S | 88 ++++++++++
5 files changed, 351 insertions(+)
create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
create mode 100644 RiscVPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S
diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
new file mode 100644
index 0000000..2463bac
--- /dev/null
+++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
@@ -0,0 +1,43 @@
+## @file
+# RISC-V CPU Exception Handler Library
+#
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = CpuExceptionHandlerLib
+ MODULE_UNI_FILE = CpuExceptionHandlerLib.uni
+ FILE_GUID = 16309FCF-E900-459C-B071-052118394D11
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = CpuExceptionHandlerLib
+ CONSTRUCTOR = CpuExceptionHandlerLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources.RISCV64]
+ SupervisorTrapHandler.S
+
+[Sources.common]
+ CpuExceptionHandlerLib.c
+ CpuExceptionHandlerLib.h
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ RiscVCpuLib
+ UefiBootServicesTableLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
new file mode 100644
index 0000000..1d141d1
--- /dev/null
+++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.h
@@ -0,0 +1,16 @@
+/**@file
+
+ RISC-V Exception Handler library definition file.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISCV_CPU_EXECPTION_HANDLER_LIB_H_
+#define RISCV_CPU_EXECPTION_HANDLER_LIB_H_
+
+extern void SupervisorModeTrap(void);
+
+#endif
diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
new file mode 100644
index 0000000..e25ce3a
--- /dev/null
+++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.c
@@ -0,0 +1,191 @@
+/** @file
+ RISC-V Exception Handler library implementition.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/CpuExceptionHandlerLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_types.h>
+
+#include "CpuExceptionHandlerLib.h"
+
+STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2];
+
+/**
+ Initializes all CPU exceptions entries and provides the default exception handlers.
+
+ Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
+ persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
+ If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
+ If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
+
+ @param[in] VectorInfo Pointer to reserved vector list.
+
+ @retval EFI_SUCCESS CPU Exception Entries have been successfully initialized
+ with default exception handlers.
+ @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
+ @retval EFI_UNSUPPORTED This function is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuExceptionHandlers (
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.
+
+ Caller should try to get an array of interrupt and/or exception vectors that are in use and need to
+ persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.
+ If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL.
+ If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.
+
+ @param[in] VectorInfo Pointer to reserved vector list.
+
+ @retval EFI_SUCCESS All CPU interrupt/exception entries have been successfully initialized
+ with default interrupt/exception handlers.
+ @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
+ @retval EFI_UNSUPPORTED This function is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuInterruptHandlers (
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Registers a function to be called from the processor interrupt handler.
+
+ This function registers and enables the handler specified by InterruptHandler for a processor
+ interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
+ handler for the processor interrupt or exception type specified by InterruptType is uninstalled.
+ The installed handler is called once for each processor interrupt or exception.
+ NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or
+ InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED returned.
+
+ @param[in] InterruptType Defines which interrupt or exception to hook.
+ @param[in] InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called
+ when a processor interrupt occurs. If this parameter is NULL, then the handler
+ will be uninstalled.
+
+ @retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was
+ previously installed.
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not
+ previously installed.
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported,
+ or this function is not supported.
+**/
+EFI_STATUS
+EFIAPI
+RegisterCpuInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ )
+{
+
+ DEBUG ((DEBUG_INFO, "%a: Type:%x Handler: %x\n", __FUNCTION__, InterruptType, InterruptHandler));
+ mInterruptHandlers[InterruptType] = InterruptHandler;
+ return EFI_SUCCESS;
+}
+/**
+ Machine mode trap handler.
+
+**/
+VOID
+RiscVSupervisorModeTrapHandler (
+ VOID
+ )
+{
+ EFI_SYSTEM_CONTEXT RiscVSystemContext;
+ UINTN SCause;
+
+ //
+ // Check scasue register.
+ //
+ SCause = (UINTN)csr_read(RISCV_CSR_SUPERVISOR_SCAUSE);
+ if ((SCause & (1UL << (sizeof (UINTN) * 8- 1))) != 0) {
+ //
+ // This is interrupt event.
+ //
+ SCause &= ~(1UL << (sizeof (UINTN) * 8- 1));
+ if((SCause == SCAUSE_SUPERVISOR_TIMER_INT) && (mInterruptHandlers[EXCEPT_RISCV_TIMER_INT] != NULL)) {
+ mInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, (CONST EFI_SYSTEM_CONTEXT)RiscVSystemContext);
+ }
+ }
+}
+
+/**
+ Initializes all CPU exceptions entries with optional extra initializations.
+
+ By default, this method should include all functionalities implemented by
+ InitializeCpuExceptionHandlers(), plus extra initialization works, if any.
+ This could be done by calling InitializeCpuExceptionHandlers() directly
+ in this method besides the extra works.
+
+ InitData is optional and its use and content are processor arch dependent.
+ The typical usage of it is to convey resources which have to be reserved
+ elsewhere and are necessary for the extra initializations of exception.
+
+ @param[in] VectorInfo Pointer to reserved vector list.
+ @param[in] InitData Pointer to data optional for extra initializations
+ of exception.
+
+ @retval EFI_SUCCESS The exceptions have been successfully
+ initialized.
+ @retval EFI_INVALID_PARAMETER VectorInfo or InitData contains invalid
+ content.
+ @retval EFI_UNSUPPORTED This function is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpuExceptionHandlersEx (
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
+ IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
+ )
+{
+ return InitializeCpuExceptionHandlers (VectorInfo);
+}
+
+/**
+ The constructor function to initial interrupt handlers in
+ RISCV_MACHINE_MODE_CONTEXT.
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The destructor completed successfully.
+ @retval Other value The destructor did not complete successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuExceptionHandlerLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ //
+ // Set Superviosr mode trap handler.
+ //
+ csr_write(CSR_STVEC, SupervisorModeTrap);
+
+ return EFI_SUCCESS;
+}
diff --git a/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
new file mode 100644
index 0000000..00cca22
--- /dev/null
+++ b/RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
@@ -0,0 +1,13 @@
+// /** @file
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "RISC-V CPU Exception Handler Librarys."
+
+#string STR_MODULE_DESCRIPTION #language en-US "RISC-V CPU Exception Handler Librarys."
+
diff --git a/RiscVPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S b/RiscVPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S
new file mode 100644
index 0000000..7d3cdd8
--- /dev/null
+++ b/RiscVPkg/Library/RiscVExceptionLib/SupervisorTrapHandler.S
@@ -0,0 +1,88 @@
+/** @file
+ RISC-V Processor supervisor mode trap handler
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <RiscVImpl.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_trap.h>
+
+ .align 3
+ .section .entry, "ax", %progbits
+ .globl SupervisorModeTrap
+SupervisorModeTrap:
+ addi sp, sp, -34 * 8
+ /* Save all general regisers except SP and T0 */
+ sd ra, 1 * 8(sp)
+ sd gp, 2 * 8(sp)
+ sd tp, 3 * 8(sp)
+ sd t1, 4 * 8(sp)
+ sd t2, 5 * 8(sp)
+ sd s0, 6 * 8(sp)
+ sd s1, 7 * 8(sp)
+ sd a0, 8 * 8(sp)
+ sd a1, 9 * 8(sp)
+ sd a2, 10 * 8(sp)
+ sd a3, 11 * 8(sp)
+ sd a4, 12 * 8(sp)
+ sd a5, 13 * 8(sp)
+ sd a6, 14 * 8(sp)
+ sd a7, 15 * 8(sp)
+ sd s2, 16 * 8(sp)
+ sd s3, 17 * 8(sp)
+ sd s4, 18 * 8(sp)
+ sd s5, 19 * 8(sp)
+ sd s6, 20 * 8(sp)
+ sd s7, 21 * 8(sp)
+ sd s8, 22 * 8(sp)
+ sd s9, 23 * 8(sp)
+ sd s10, 24 * 8(sp)
+ sd s11, 25 * 8(sp)
+ sd t3, 26 * 8(sp)
+ sd t4, 27 * 8(sp)
+ sd t5, 28 * 8(sp)
+ sd t6, 29 * 8(sp)
+
+ /* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */
+ call RiscVSupervisorModeTrapHandler
+
+ /* Restore all general regisers except SP and T0 */
+ ld ra, 1 * 8(sp)
+ ld gp, 2 * 8(sp)
+ ld tp, 3 * 8(sp)
+ ld t1, 4 * 8(sp)
+ ld t2, 5 * 8(sp)
+ ld s0, 6 * 8(sp)
+ ld s1, 7 * 8(sp)
+ ld a0, 8 * 8(sp)
+ ld a1, 9 * 8(sp)
+ ld a2, 10 * 8(sp)
+ ld a3, 11 * 8(sp)
+ ld a4, 12 * 8(sp)
+ ld a5, 13 * 8(sp)
+ ld a6, 14 * 8(sp)
+ ld a7, 15 * 8(sp)
+ ld s2, 16 * 8(sp)
+ ld s3, 17 * 8(sp)
+ ld s4, 18 * 8(sp)
+ ld s5, 19 * 8(sp)
+ ld s6, 20 * 8(sp)
+ ld s7, 21 * 8(sp)
+ ld s8, 22 * 8(sp)
+ ld s9, 23 * 8(sp)
+ ld s10, 24 * 8(sp)
+ ld s11, 25 * 8(sp)
+ ld t3, 26 * 8(sp)
+ ld t4, 27 * 8(sp)
+ ld t5, 28 * 8(sp)
+ ld t6, 29 * 8(sp)
+ addi sp, sp, 34 * 8
+ sret
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 17/39] RiscVPkg/Library: Add RISC-V timer library
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (15 preceding siblings ...)
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 16/39] RiscVPkg/Library: Add RISC-V exception library Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 18/39] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library Abner Chang
` (21 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
Timer library for RISC-V.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
RiscVPkg/RiscVPkg.dec | 9 +
.../Library/RiscVTimerLib/BaseRiscVTimerLib.inf | 34 ++++
RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c | 199 +++++++++++++++++++++
3 files changed, 242 insertions(+)
create mode 100644 RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
create mode 100644 RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c
diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec
index d01d76f..3542185 100644
--- a/RiscVPkg/RiscVPkg.dec
+++ b/RiscVPkg/RiscVPkg.dec
@@ -22,5 +22,14 @@
[Guids]
gUefiRiscVPkgTokenSpaceGuid = { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}
+[PcdsFixedAtBuild]
+ #
+ # 1000000000
+ # PcdRiscVMachineTimerTickInNanoSecond = ---------------------------------------
+ # PcdRiscVMachineTimerFrequencyInHerz
+ #
+ gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond|100|UINT64|0x00001010
+ gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz|10000000|UINT64|0x00001011
+
[UserExtensions.TianoCore."ExtraFiles"]
RiscVPkgExtra.uni
diff --git a/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
new file mode 100644
index 0000000..af27049
--- /dev/null
+++ b/RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
@@ -0,0 +1,34 @@
+## @file
+# RISC-V Timer Library Instance.
+#
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = BaseRiscVTimerLib
+ FILE_GUID = FB648CF5-91BE-4737-9023-FD807AC6D96D
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = TimerLib
+
+[Sources]
+ RiscVTimerLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[Pcd]
+ gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerTickInNanoSecond
+ gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ RiscVCpuLib
+ RiscVPlatformTimerLib
+
diff --git a/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c
new file mode 100644
index 0000000..97fe2ae
--- /dev/null
+++ b/RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c
@@ -0,0 +1,199 @@
+/** @file
+ RISC-V instance of Timer Library.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/RiscVCpuLib.h>
+
+/**
+ Stalls the CPU for at least the given number of ticks.
+
+ Stalls the CPU for at least the given number of ticks. It's invoked by
+ MicroSecondDelay() and NanoSecondDelay().
+
+ @param Delay A period of time to delay in ticks.
+
+**/
+VOID
+InternalRiscVTimerDelay (
+ IN UINT32 Delay
+ )
+{
+ UINT32 Ticks;
+ UINT32 Times;
+
+ Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
+ Delay &= (( 1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
+ do {
+ //
+ // The target timer count is calculated here
+ //
+ Ticks = RiscVReadMachineTimer () + Delay;
+ Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
+ while (((Ticks - RiscVReadMachineTimer ()) & ( 1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
+ CpuPause ();
+ }
+ } while (Times-- > 0);
+}
+
+/**
+ Stalls the CPU for at least the given number of microseconds.
+
+ Stalls the CPU for the number of microseconds specified by MicroSeconds.
+
+ @param MicroSeconds The minimum number of microseconds to delay.
+
+ @return MicroSeconds
+
+**/
+UINTN
+EFIAPI
+MicroSecondDelay (
+ IN UINTN MicroSeconds
+ )
+{
+ InternalRiscVTimerDelay (
+ (UINT32)DivU64x32 (
+ MultU64x32 (
+ MicroSeconds,
+ PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)
+ ),
+ 1000000u
+ )
+ );
+ return MicroSeconds;
+}
+
+/**
+ Stalls the CPU for at least the given number of nanoseconds.
+
+ Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
+
+ @param NanoSeconds The minimum number of nanoseconds to delay.
+
+ @return NanoSeconds
+
+**/
+UINTN
+EFIAPI
+NanoSecondDelay (
+ IN UINTN NanoSeconds
+ )
+{
+ InternalRiscVTimerDelay (
+ (UINT32)DivU64x32 (
+ MultU64x32 (
+ NanoSeconds,
+ PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)
+ ),
+ 1000000000u
+ )
+ );
+ return NanoSeconds;
+}
+
+/**
+ Retrieves the current value of a 64-bit free running performance counter.
+
+ Retrieves the current value of a 64-bit free running performance counter. The
+ counter can either count up by 1 or count down by 1. If the physical
+ performance counter counts by a larger increment, then the counter values
+ must be translated. The properties of the counter can be retrieved from
+ GetPerformanceCounterProperties().
+
+ @return The current value of the free running performance counter.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounter (
+ VOID
+ )
+{
+ return (UINT64)RiscVReadMachineTimer ();
+}
+
+/**return
+ Retrieves the 64-bit frequency in Hz and the range of performance counter
+ values.
+
+ If StartValue is not NULL, then the value that the performance counter starts
+ with immediately after is it rolls over is returned in StartValue. If
+ EndValue is not NULL, then the value that the performance counter end with
+ immediately before it rolls over is returned in EndValue. The 64-bit
+ frequency of the performance counter in Hz is always returned. If StartValue
+ is less than EndValue, then the performance counter counts up. If StartValue
+ is greater than EndValue, then the performance counter counts down. For
+ example, a 64-bit free running counter that counts up would have a StartValue
+ of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
+ that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
+
+ @param StartValue The value the performance counter starts with when it
+ rolls over.
+ @param EndValue The value that the performance counter ends with before
+ it rolls over.
+
+ @return The frequency in Hz.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounterProperties (
+ OUT UINT64 *StartValue, OPTIONAL
+ OUT UINT64 *EndValue OPTIONAL
+ )
+{
+ if (StartValue != NULL) {
+ *StartValue = 0;
+ }
+
+ if (EndValue != NULL) {
+ *EndValue = 32 - 1;
+ }
+
+ return PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz);
+}
+
+/**
+ Converts elapsed ticks of performance counter to time in nanoseconds.
+
+ This function converts the elapsed ticks of running performance counter to
+ time value in unit of nanoseconds.
+
+ @param Ticks The number of elapsed ticks of running performance counter.
+
+ @return The elapsed time in nanoseconds.
+
+**/
+UINT64
+EFIAPI
+GetTimeInNanoSecond (
+ IN UINT64 Ticks
+ )
+{
+ UINT64 NanoSeconds;
+ UINT32 Remainder;
+
+ //
+ // Ticks
+ // Time = --------- x 1,000,000,000
+ // Frequency
+ //
+ NanoSeconds = MultU64x32 (DivU64x32Remainder (Ticks, PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz), &Remainder), 1000000000u);
+
+ //
+ // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder * 1,000,000,000)
+ // will not overflow 64-bit.
+ //
+ NanoSeconds += DivU64x32 (MultU64x32 ((UINT64) Remainder, 1000000000u), PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz));
+
+ return NanoSeconds;
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 18/39] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library.
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (16 preceding siblings ...)
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 17/39] RiscVPkg/Library: Add RISC-V timer library Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-11-21 16:48 ` [edk2-devel] " Leif Lindholm
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 19/39] RiscVPkg/Library: RISC-V platform level DxeIPL libraries Abner Chang
` (20 subsequent siblings)
38 siblings, 1 reply; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
EDK2 RISC-V OpenSBI library which pull in external source files under
RiscVPkg/Library/RiscVOpensbiLib/opensbi to the build process.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | 53 ++++++++++++++++++++++
1 file changed, 53 insertions(+)
create mode 100644 RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
diff --git a/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
new file mode 100644
index 0000000..3e7f0fb
--- /dev/null
+++ b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
@@ -0,0 +1,53 @@
+## @file
+# RISC-V Opensbi Library Instance.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVOpensbiLib
+ FILE_GUID = 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVOpensbiLib
+
+[Sources]
+ opensbi/lib/sbi/riscv_asm.c
+ opensbi/lib/sbi/riscv_atomic.c
+ opensbi/lib/sbi/riscv_hardfp.S
+ opensbi/lib/sbi/riscv_locks.c
+ opensbi/lib/sbi/riscv_unpriv.c
+ opensbi/lib/sbi/sbi_console.c
+ opensbi/lib/sbi/sbi_ecall.c
+ opensbi/lib/sbi/sbi_emulate_csr.c
+ opensbi/lib/sbi/sbi_fifo.c
+ opensbi/lib/sbi/sbi_hart.c
+ opensbi/lib/sbi/sbi_illegal_insn.c
+ opensbi/lib/sbi/sbi_init.c
+ opensbi/lib/sbi/sbi_ipi.c
+ opensbi/lib/sbi/sbi_misaligned_ldst.c
+ opensbi/lib/sbi/sbi_scratch.c
+ opensbi/lib/sbi/sbi_string.c
+ opensbi/lib/sbi/sbi_system.c
+ opensbi/lib/sbi/sbi_timer.c
+ opensbi/lib/sbi/sbi_tlb.c
+ opensbi/lib/sbi/sbi_trap.c
+ opensbi/lib/utils/sys/clint.c
+ opensbi/lib/utils/irqchip/plic.c
+ opensbi/lib/utils/serial/sifive-uart.c
+ opensbi/lib/utils/serial/uart8250.c
+
+[Packages]
+ EmbeddedPkg/EmbeddedPkg.dec # For libfdt.
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ RiscVCpuLib
+
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 18/39] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library.
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 18/39] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library Abner Chang
@ 2019-11-21 16:48 ` Leif Lindholm
2019-12-19 6:00 ` Abner Chang
0 siblings, 1 reply; 77+ messages in thread
From: Leif Lindholm @ 2019-11-21 16:48 UTC (permalink / raw)
To: devel, abner.chang; +Cc: Gilbert Chen
On Mon, Oct 28, 2019 at 09:58:56 +0800, Abner Chang wrote:
> EDK2 RISC-V OpenSBI library which pull in external source files under
> RiscVPkg/Library/RiscVOpensbiLib/opensbi to the build process.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
>
Could this be reordered to appear immediately after the Sbi wrapper
headers are added (or even squashed with it)?
/
Leif
> Cc: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Gilbert Chen <gilbert.chen@hpe.com>
> ---
> .../Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | 53 ++++++++++++++++++++++
> 1 file changed, 53 insertions(+)
> create mode 100644 RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
>
> diff --git a/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> new file mode 100644
> index 0000000..3e7f0fb
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> @@ -0,0 +1,53 @@
> +## @file
> +# RISC-V Opensbi Library Instance.
> +#
> +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x0001001b
> + BASE_NAME = RiscVOpensbiLib
> + FILE_GUID = 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = RiscVOpensbiLib
> +
> +[Sources]
> + opensbi/lib/sbi/riscv_asm.c
> + opensbi/lib/sbi/riscv_atomic.c
> + opensbi/lib/sbi/riscv_hardfp.S
> + opensbi/lib/sbi/riscv_locks.c
> + opensbi/lib/sbi/riscv_unpriv.c
> + opensbi/lib/sbi/sbi_console.c
> + opensbi/lib/sbi/sbi_ecall.c
> + opensbi/lib/sbi/sbi_emulate_csr.c
> + opensbi/lib/sbi/sbi_fifo.c
> + opensbi/lib/sbi/sbi_hart.c
> + opensbi/lib/sbi/sbi_illegal_insn.c
> + opensbi/lib/sbi/sbi_init.c
> + opensbi/lib/sbi/sbi_ipi.c
> + opensbi/lib/sbi/sbi_misaligned_ldst.c
> + opensbi/lib/sbi/sbi_scratch.c
> + opensbi/lib/sbi/sbi_string.c
> + opensbi/lib/sbi/sbi_system.c
> + opensbi/lib/sbi/sbi_timer.c
> + opensbi/lib/sbi/sbi_tlb.c
> + opensbi/lib/sbi/sbi_trap.c
> + opensbi/lib/utils/sys/clint.c
> + opensbi/lib/utils/irqchip/plic.c
> + opensbi/lib/utils/serial/sifive-uart.c
> + opensbi/lib/utils/serial/uart8250.c
> +
> +[Packages]
> + EmbeddedPkg/EmbeddedPkg.dec # For libfdt.
> + MdePkg/MdePkg.dec
> + RiscVPkg/RiscVPkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + PcdLib
> + RiscVCpuLib
> +
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 77+ messages in thread* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 18/39] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library.
2019-11-21 16:48 ` [edk2-devel] " Leif Lindholm
@ 2019-12-19 6:00 ` Abner Chang
2019-12-20 15:04 ` Abner Chang
0 siblings, 1 reply; 77+ messages in thread
From: Abner Chang @ 2019-12-19 6:00 UTC (permalink / raw)
To: devel@edk2.groups.io, leif.lindholm@linaro.org; +Cc: Chen, Gilbert
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Friday, November 22, 2019 12:49 AM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Cc: Chen, Gilbert <gilbert.chen@hpe.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 18/39]
> RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library.
>
> On Mon, Oct 28, 2019 at 09:58:56 +0800, Abner Chang wrote:
> > EDK2 RISC-V OpenSBI library which pull in external source files under
> > RiscVPkg/Library/RiscVOpensbiLib/opensbi to the build process.
> >
> > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> >
>
> Could this be reordered to appear immediately after the Sbi wrapper
> headers are added (or even squashed with it)?
Yes. will see if I can squash it.
>
> /
> Leif
>
> > Cc: Leif Lindholm <leif.lindholm@linaro.org>
> > Cc: Gilbert Chen <gilbert.chen@hpe.com>
> > ---
> > .../Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | 53
> ++++++++++++++++++++++
> > 1 file changed, 53 insertions(+)
> > create mode 100644
> > RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> >
> > diff --git a/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> > b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> > new file mode 100644
> > index 0000000..3e7f0fb
> > --- /dev/null
> > +++ b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> > @@ -0,0 +1,53 @@
> > +## @file
> > +# RISC-V Opensbi Library Instance.
> > +#
> > +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> > +rights reserved.<BR> # # SPDX-License-Identifier:
> > +BSD-2-Clause-Patent # ##
> > +
> > +[Defines]
> > + INF_VERSION = 0x0001001b
> > + BASE_NAME = RiscVOpensbiLib
> > + FILE_GUID = 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = RiscVOpensbiLib
> > +
> > +[Sources]
> > + opensbi/lib/sbi/riscv_asm.c
> > + opensbi/lib/sbi/riscv_atomic.c
> > + opensbi/lib/sbi/riscv_hardfp.S
> > + opensbi/lib/sbi/riscv_locks.c
> > + opensbi/lib/sbi/riscv_unpriv.c
> > + opensbi/lib/sbi/sbi_console.c
> > + opensbi/lib/sbi/sbi_ecall.c
> > + opensbi/lib/sbi/sbi_emulate_csr.c
> > + opensbi/lib/sbi/sbi_fifo.c
> > + opensbi/lib/sbi/sbi_hart.c
> > + opensbi/lib/sbi/sbi_illegal_insn.c
> > + opensbi/lib/sbi/sbi_init.c
> > + opensbi/lib/sbi/sbi_ipi.c
> > + opensbi/lib/sbi/sbi_misaligned_ldst.c
> > + opensbi/lib/sbi/sbi_scratch.c
> > + opensbi/lib/sbi/sbi_string.c
> > + opensbi/lib/sbi/sbi_system.c
> > + opensbi/lib/sbi/sbi_timer.c
> > + opensbi/lib/sbi/sbi_tlb.c
> > + opensbi/lib/sbi/sbi_trap.c
> > + opensbi/lib/utils/sys/clint.c
> > + opensbi/lib/utils/irqchip/plic.c
> > + opensbi/lib/utils/serial/sifive-uart.c
> > + opensbi/lib/utils/serial/uart8250.c
> > +
> > +[Packages]
> > + EmbeddedPkg/EmbeddedPkg.dec # For libfdt.
> > + MdePkg/MdePkg.dec
> > + RiscVPkg/RiscVPkg.dec
> > +
> > +[LibraryClasses]
> > + BaseLib
> > + PcdLib
> > + RiscVCpuLib
> > +
> > --
> > 2.7.4
> >
> >
> >
> >
>
>
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 18/39] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library.
2019-12-19 6:00 ` Abner Chang
@ 2019-12-20 15:04 ` Abner Chang
0 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-12-20 15:04 UTC (permalink / raw)
To: devel@edk2.groups.io, leif.lindholm@linaro.org; +Cc: Chen, Gilbert
> -----Original Message-----
> From: Chang, Abner (HPS SW/FW Technologist)
> Sent: Thursday, December 19, 2019 2:00 PM
> To: devel@edk2.groups.io; leif.lindholm@linaro.org
> Cc: Chen, Gilbert <gilbert.chen@hpe.com>
> Subject: RE: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 18/39]
> RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library.
>
>
>
> > -----Original Message-----
> > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> > Leif Lindholm
> > Sent: Friday, November 22, 2019 12:49 AM
> > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> > <abner.chang@hpe.com>
> > Cc: Chen, Gilbert <gilbert.chen@hpe.com>
> > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 18/39]
> > RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library.
> >
> > On Mon, Oct 28, 2019 at 09:58:56 +0800, Abner Chang wrote:
> > > EDK2 RISC-V OpenSBI library which pull in external source files
> > > under RiscVPkg/Library/RiscVOpensbiLib/opensbi to the build process.
> > >
> > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > >
> >
> > Could this be reordered to appear immediately after the Sbi wrapper
> > headers are added (or even squashed with it)?
>
> Yes. will see if I can squash it.
Done
> >
> > /
> > Leif
> >
> > > Cc: Leif Lindholm <leif.lindholm@linaro.org>
> > > Cc: Gilbert Chen <gilbert.chen@hpe.com>
> > > ---
> > > .../Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | 53
> > ++++++++++++++++++++++
> > > 1 file changed, 53 insertions(+)
> > > create mode 100644
> > > RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> > >
> > > diff --git a/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> > > b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> > > new file mode 100644
> > > index 0000000..3e7f0fb
> > > --- /dev/null
> > > +++ b/RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
> > > @@ -0,0 +1,53 @@
> > > +## @file
> > > +# RISC-V Opensbi Library Instance.
> > > +#
> > > +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP.
> > > +All rights reserved.<BR> # # SPDX-License-Identifier:
> > > +BSD-2-Clause-Patent # ##
> > > +
> > > +[Defines]
> > > + INF_VERSION = 0x0001001b
> > > + BASE_NAME = RiscVOpensbiLib
> > > + FILE_GUID = 6EF0C812-66F6-11E9-93CE-3F5D5F0DF0A7
> > > + MODULE_TYPE = BASE
> > > + VERSION_STRING = 1.0
> > > + LIBRARY_CLASS = RiscVOpensbiLib
> > > +
> > > +[Sources]
> > > + opensbi/lib/sbi/riscv_asm.c
> > > + opensbi/lib/sbi/riscv_atomic.c
> > > + opensbi/lib/sbi/riscv_hardfp.S
> > > + opensbi/lib/sbi/riscv_locks.c
> > > + opensbi/lib/sbi/riscv_unpriv.c
> > > + opensbi/lib/sbi/sbi_console.c
> > > + opensbi/lib/sbi/sbi_ecall.c
> > > + opensbi/lib/sbi/sbi_emulate_csr.c
> > > + opensbi/lib/sbi/sbi_fifo.c
> > > + opensbi/lib/sbi/sbi_hart.c
> > > + opensbi/lib/sbi/sbi_illegal_insn.c
> > > + opensbi/lib/sbi/sbi_init.c
> > > + opensbi/lib/sbi/sbi_ipi.c
> > > + opensbi/lib/sbi/sbi_misaligned_ldst.c
> > > + opensbi/lib/sbi/sbi_scratch.c
> > > + opensbi/lib/sbi/sbi_string.c
> > > + opensbi/lib/sbi/sbi_system.c
> > > + opensbi/lib/sbi/sbi_timer.c
> > > + opensbi/lib/sbi/sbi_tlb.c
> > > + opensbi/lib/sbi/sbi_trap.c
> > > + opensbi/lib/utils/sys/clint.c
> > > + opensbi/lib/utils/irqchip/plic.c
> > > + opensbi/lib/utils/serial/sifive-uart.c
> > > + opensbi/lib/utils/serial/uart8250.c
> > > +
> > > +[Packages]
> > > + EmbeddedPkg/EmbeddedPkg.dec # For libfdt.
> > > + MdePkg/MdePkg.dec
> > > + RiscVPkg/RiscVPkg.dec
> > > +
> > > +[LibraryClasses]
> > > + BaseLib
> > > + PcdLib
> > > + RiscVCpuLib
> > > +
> > > --
> > > 2.7.4
> > >
> > >
> > >
> > >
> >
> >
^ permalink raw reply [flat|nested] 77+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v3 19/39] RiscVPkg/Library: RISC-V platform level DxeIPL libraries.
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (17 preceding siblings ...)
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 18/39] RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 20/39] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Abner Chang
` (19 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
RiscVDxeIplHandoffLib.inf: Simply use stack switch to hand off to DXE
phase.
RiscVDxeIplHandoffOpenSbiLib.inf: Hand off to DXE phase using OpenSBI
interface.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../RiscVDxeIplHandoffLib.inf | 32 +++++++
.../RiscVDxeIplHandoffOpenSbiLib.inf | 33 +++++++
.../RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c | 41 +++++++++
.../RiscVDxeIplHandoffOpenSbiLib.c | 101 +++++++++++++++++++++
4 files changed, 207 insertions(+)
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
new file mode 100644
index 0000000..986db1d
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
@@ -0,0 +1,32 @@
+## @file
+# Instance of RISC-V DXE IPL to DXE core handoff platform library
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVPlatformDxeIplLib
+ FILE_GUID = 2A77EE71-9F55-43F9-8773-7854A5B56086
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVPlatformDxeIplLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ RiscVDxeIplHandoffLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+ RiscVOpensbiLib
+
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
new file mode 100644
index 0000000..262071d
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
@@ -0,0 +1,33 @@
+## @file
+# Instance of RISC-V DXE IPL to DXE core handoff platform library using OpenSBI
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVPlatformDxeIplLib
+ FILE_GUID = 906A4BB9-8DE2-4CE0-A609-23818A8FF514
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVPlatformDxeIplLib|PEIM PEI_CORE
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ RiscVDxeIplHandoffOpenSbiLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+ RiscVOpensbiLib
+
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
new file mode 100644
index 0000000..211b4e8
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c
@@ -0,0 +1,41 @@
+/** @file
+ RISC-V platform level DXE core hand off library
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+/**
+ RISC-V platform DXE IPL to DXE core handoff process.
+
+ This function performs a CPU architecture specific operations to execute
+ the entry point of DxeCore with the parameters of HobList.
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+
+ @param BaseOfStack Base address of stack
+ @param TopOfStack Top address of stack
+ @param DxeCoreEntryPoint The entry point of DxeCore.
+ @param HobList The start of HobList passed to DxeCore.
+
+**/
+
+VOID
+RiscVPlatformHandOffToDxeCore (
+ IN VOID *BaseOfStack,
+ IN VOID *TopOfStack,
+ IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
+ IN EFI_PEI_HOB_POINTERS HobList
+ )
+{
+
+ //
+ // Transfer the control to the entry point of DxeCore.
+ //
+ SwitchStack (
+ (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
+ HobList.Raw,
+ NULL,
+ TopOfStack
+ );
+}
diff --git a/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
new file mode 100644
index 0000000..26975c0
--- /dev/null
+++ b/RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.c
@@ -0,0 +1,101 @@
+/** @file
+ RISC-V DXE IPL to DXE core handoff platform library using OpenSBI
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_init.h>
+#include <sbi/sbi_scratch.h>
+#include <Library/RiscVCpuLib.h>
+#include <Library/RiscVPlatformDxeIpl.h>
+
+/**
+ RISC-V platform DXE IPL to DXE OpenSBI mdoe switch handler.
+ This function is executed in RISC-V Supervisor mode.
+
+ This function performs a CPU architecture specific operations to execute
+ the entry point of DxeCore with the parameters of HobList.
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+
+ @param BaseOfStack Base address of stack
+ @param TopOfStack Top address of stack
+ @param DxeCoreEntryPoint The entry point of DxeCore.
+ @param HobList The start of HobList passed to DxeCore.
+
+**/
+VOID
+RiscVDxeIplHandoffOpenSbiHandler (
+ IN UINTN HardId,
+ IN OPENSBI_SWITCH_MODE_CONTEXT *ThisSwitchContext
+ )
+{
+ DEBUG ((DEBUG_INFO, "OpenSBI mode switch DXE IPL Handoff handler entry\n"));
+
+ SwitchStack (
+ (SWITCH_STACK_ENTRY_POINT)(UINTN)ThisSwitchContext->DxeCoreEntryPoint,
+ ThisSwitchContext->HobList.Raw,
+ NULL,
+ ThisSwitchContext->TopOfStack
+ );
+
+ //
+ // Shold never came back.
+ //
+ UNREACHABLE();
+}
+
+
+/**
+ RISC-V platform DXE IPL to DXE core handoff process.
+
+ This function performs a CPU architecture specific operations to execute
+ the entry point of DxeCore with the parameters of HobList.
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+
+ @param BaseOfStack Base address of stack
+ @param TopOfStack Top address of stack
+ @param DxeCoreEntryPoint The entry point of DxeCore.
+ @param HobList The start of HobList passed to DxeCore.
+
+**/
+VOID
+RiscVPlatformHandOffToDxeCore (
+ IN VOID *BaseOfStack,
+ IN VOID *TopOfStack,
+ IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
+ IN EFI_PEI_HOB_POINTERS HobList
+ )
+{
+ struct sbi_scratch *ThisScratch;
+ OPENSBI_SWITCH_MODE_CONTEXT OpenSbiSwitchModeContext;
+
+ DEBUG ((DEBUG_INFO, "DXE IPL to DXE Core using OpenSBI\n"));
+ //
+ // Setup next address in OpenSBI scratch
+ //
+ OpenSbiSwitchModeContext.BaseOfStack = BaseOfStack;
+ OpenSbiSwitchModeContext.TopOfStack = TopOfStack;
+ OpenSbiSwitchModeContext.HobList = HobList;
+ OpenSbiSwitchModeContext.DxeCoreEntryPoint = DxeCoreEntryPoint;
+ ThisScratch = sbi_scratch_thishart_ptr ();
+ ThisScratch->next_arg1 = (UINTN)&OpenSbiSwitchModeContext;
+ ThisScratch->next_addr = (UINTN)RiscVDxeIplHandoffOpenSbiHandler;
+ ThisScratch->next_mode = PRV_S;
+
+ DEBUG ((DEBUG_INFO, " Base address of satck: 0x%x\n", BaseOfStack));
+ DEBUG ((DEBUG_INFO, " Top address of satck: 0x%x\n", TopOfStack));
+ DEBUG ((DEBUG_INFO, " HOB list address: 0x%x\n", &HobList));
+ DEBUG ((DEBUG_INFO, " DXE core entry pointer: 0x%x\n", DxeCoreEntryPoint));
+ DEBUG ((DEBUG_INFO, " OpenSBI Switch mode arg1: 0x%x\n", (UINTN)&OpenSbiSwitchModeContext));
+ DEBUG ((DEBUG_INFO, " OpenSBI Switch mode handler address: 0x%x\n", (UINTN)RiscVDxeIplHandoffOpenSbiHandler));
+ DEBUG ((DEBUG_INFO, " OpenSBI Switch mode to privilege 0x%x\n", PRV_S));
+ sbi_init (ThisScratch);
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 20/39] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (18 preceding siblings ...)
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 19/39] RiscVPkg/Library: RISC-V platform level DxeIPL libraries Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 21/39] RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service Table Pointer library Abner Chang
` (18 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Dandan Bi, Liming Gao, Leif Lindholm, Gilbert Chen
Implementation of RISC-V platform level DxeIPL.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 13 +++-
RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h | 41 ++++++++++++
MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c | 76 ++++++++++++++++++++++
3 files changed, 129 insertions(+), 1 deletion(-)
create mode 100644 RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h
create mode 100644 MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
index 98bc17f..5532323 100644
--- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
@@ -7,6 +7,7 @@
#
# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -25,7 +26,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only) AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only) AARCH64 RISCV64
#
[Sources]
@@ -49,6 +50,9 @@
[Sources.ARM, Sources.AARCH64]
Arm/DxeLoadFunc.c
+[Sources.RISCV64]
+ RiscV64/DxeLoadFunc.c
+
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
@@ -56,6 +60,9 @@
[Packages.ARM, Packages.AARCH64]
ArmPkg/ArmPkg.dec
+[Packages.RISCV64]
+ RiscVPkg/RiscVPkg.dec
+
[LibraryClasses]
PcdLib
MemoryAllocationLib
@@ -75,6 +82,10 @@
[LibraryClasses.ARM, LibraryClasses.AARCH64]
ArmMmuLib
+[LibraryClasses.RISCV64]
+ RiscVPlatformDxeIplLib
+ RiscVOpensbiLib
+
[Ppis]
gEfiDxeIplPpiGuid ## PRODUCES
gEfiPeiDecompressPpiGuid ## PRODUCES
diff --git a/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h b/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h
new file mode 100644
index 0000000..30058f2
--- /dev/null
+++ b/RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h
@@ -0,0 +1,41 @@
+/** @file
+ Header file of RISC-V platform DXE IPL
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP.All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef RISC_V_PLATFORM_DXEIPL_H_
+#define RISC_V_PLATFORM_DXEIPL_H_
+
+typedef struct {
+ VOID *TopOfStack;
+ VOID *BaseOfStack;
+ EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint;
+ EFI_PEI_HOB_POINTERS HobList;
+} OPENSBI_SWITCH_MODE_CONTEXT;
+
+/**
+ RISC-V platform DXE IPL to DXE core handoff process.
+
+ This function performs a CPU architecture specific operations to execute
+ the entry point of DxeCore with the parameters of HobList.
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+
+ @param BaseOfStack Base address of stack
+ @param TopOfStack Top address of stack
+ @param DxeCoreEntryPoint The entry point of DxeCore.
+ @param HobList The start of HobList passed to DxeCore.
+
+**/
+
+VOID
+RiscVPlatformHandOffToDxeCore (
+ IN VOID *BaseOfStack,
+ IN VOID *TopOfStack,
+ IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
+ IN EFI_PEI_HOB_POINTERS HobList
+ );
+#endif
+
diff --git a/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
new file mode 100644
index 0000000..48efdd8
--- /dev/null
+++ b/MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c
@@ -0,0 +1,76 @@
+/** @file
+ RISC-V specific functionality for DxeLoad.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "DxeIpl.h"
+#include <Library/RiscVPlatformDxeIpl.h>
+
+typedef
+VOID*
+(EFIAPI *DXEENTRYPOINT) (
+ IN VOID *HobStart
+ );
+
+/**
+ Transfers control to DxeCore.
+
+ This function performs a CPU architecture specific operations to execute
+ the entry point of DxeCore with the parameters of HobList.
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+
+ @param DxeCoreEntryPoint The entry point of DxeCore.
+ @param HobList The start of HobList passed to DxeCore.
+
+**/
+VOID
+HandOffToDxeCore (
+ IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
+ IN EFI_PEI_HOB_POINTERS HobList
+ )
+{
+ VOID *BaseOfStack;
+ VOID *TopOfStack;
+ EFI_STATUS Status;
+ //
+ //
+ // Allocate 128KB for the Stack
+ //
+ BaseOfStack = AllocatePages (EFI_SIZE_TO_PAGES (STACK_SIZE));
+ if (BaseOfStack == NULL) {
+ DEBUG((DEBUG_ERROR, "%a: Can't allocate memory for stack.", __FUNCTION__));
+ ASSERT(FALSE);
+ }
+
+ //
+ // Compute the top of the stack we were allocated. Pre-allocate a UINTN
+ // for safety.
+ //
+ TopOfStack = (VOID *)((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT);
+ TopOfStack = ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);
+
+ //
+ // End of PEI phase signal
+ //
+ Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
+ if (EFI_ERROR (Status)) {
+ DEBUG((DEBUG_ERROR, "%a: Fail to signal End of PEI event.", __FUNCTION__));
+ ASSERT(FALSE);
+ }
+ //
+ // Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
+ //
+ UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN) BaseOfStack, STACK_SIZE);
+
+ DEBUG ((DEBUG_INFO, "DXE Core new stack at %x, stack pointer at %x\n", BaseOfStack, TopOfStack));
+
+ //
+ // Transfer the control to the entry point of DxeCore.
+ //
+ RiscVPlatformHandOffToDxeCore (BaseOfStack, TopOfStack, DxeCoreEntryPoint, HobList);
+}
+
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 21/39] RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service Table Pointer library
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (19 preceding siblings ...)
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 20/39] MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL Abner Chang
@ 2019-10-28 1:58 ` Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 22/39] RiscVPlatformPkg/RiscVPlatformTempMemoryInit: RISC-V Platform Temporary Memory library Abner Chang
` (17 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:58 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
Implementation of RISC-V PEI Service Table Pointer library using
RISC-V OpenSbi.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../PeiServicesTablePointerLibOpenSbi.inf | 38 +++++++
.../PeiServicesTablePointerOpenSbi.c | 121 +++++++++++++++++++++
.../PeiServicesTablePointerLibOpenSbi.uni | 23 ++++
3 files changed, 182 insertions(+)
create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
new file mode 100644
index 0000000..0b029ae
--- /dev/null
+++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
@@ -0,0 +1,38 @@
+## @file
+# Instance of PEI Services Table Pointer Library using RISC-V OpenSBI FirmwareContext.
+#
+# PEI Services Table Pointer Library implementation that retrieves a pointer to the
+# PEI Services Table from a RISC-V OpenSBI sbi_platform firmware context structure.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PeiServicesTablePointerLibOpenSbi
+ MODULE_UNI_FILE = PeiServicesTablePointerLibOpenSbi.uni
+ FILE_GUID = B4054E46-FE75-4290-B442-4836B1265D8F
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PeiServicesTablePointerLib|PEIM PEI_CORE
+
+ CONSTRUCTOR = PeiServicesTablePointerLibOpenSbiConstructor
+
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ PeiServicesTablePointerOpenSbi.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ RiscVCpuLib
+ RiscVOpensbiLib
diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
new file mode 100644
index 0000000..4f09e67
--- /dev/null
+++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerOpenSbi.c
@@ -0,0 +1,121 @@
+/** @file
+ PEI Services Table Pointer Library.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/SbiFirmwareContext.h>
+
+/**
+ Caches a pointer PEI Services Table.
+
+ Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer
+ in a CPU specific manner as specified in the CPU binding section of the Platform Initialization
+ Pre-EFI Initialization Core Interface Specification.
+
+ If PeiServicesTablePointer is NULL, then ASSERT().
+
+ @param PeiServicesTablePointer The address of PeiServices pointer.
+**/
+VOID
+EFIAPI
+SetPeiServicesTablePointer (
+ IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer
+ )
+{
+ struct sbi_platform *ThisSbiPlatform;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+
+ ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_thishart_ptr());
+ FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatform->firmware_context;
+ FirmwareContext->PeiServiceTable = (VOID *)(UINTN)PeiServicesTablePointer;
+
+ DEBUG ((DEBUG_INFO, "Set PEI Service 0x%x at OpenSBI Firmware Context at 0x%x\n",
+ PeiServicesTablePointer,
+ ThisSbiPlatform->firmware_context
+ ));
+}
+
+/**
+ Retrieves the cached value of the PEI Services Table pointer.
+
+ Returns the cached value of the PEI Services Table pointer in a CPU specific manner
+ as specified in the CPU binding section of the Platform Initialization Pre-EFI
+ Initialization Core Interface Specification.
+
+ If the cached PEI Services Table pointer is NULL, then ASSERT().
+
+ @return The pointer to PeiServices.
+
+**/
+CONST EFI_PEI_SERVICES **
+EFIAPI
+GetPeiServicesTablePointer (
+ VOID
+ )
+{
+ struct sbi_platform *ThisSbiPlatform;
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+
+ ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_thishart_ptr());
+ FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatform->firmware_context;
+ return (CONST EFI_PEI_SERVICES **)FirmwareContext->PeiServiceTable;
+}
+
+/**
+ The constructor function caches the pointer to PEI services.
+
+ The constructor function caches the pointer to PEI services.
+ It will always return EFI_SUCCESS.
+
+ @param FileHandle The handle of FFS header the loaded driver.
+ @param PeiServices The pointer to the PEI services.
+
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+PeiServicesTablePointerLibOpenSbiConstructor (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ SetPeiServicesTablePointer (PeiServices);
+ return EFI_SUCCESS;
+}
+
+/**
+ Perform CPU specific actions required to migrate the PEI Services Table
+ pointer from temporary RAM to permanent RAM.
+
+ For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
+ immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+ For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
+ immediately preceding the Interrupt Descriptor Table (IDT) in memory.
+ For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in
+ a dedicated CPU register. This means that there is no memory storage
+ associated with storing the PEI Services Table pointer, so no additional
+ migration actions are required for Itanium or ARM CPUs.
+
+**/
+VOID
+EFIAPI
+MigratePeiServicesTablePointer (
+ VOID
+ )
+{
+ //
+ // PEI Services Table pointer is cached in the global variable. No additional
+ // migration actions are required.
+ //
+ return;
+}
diff --git a/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
new file mode 100644
index 0000000..f6fad8b
--- /dev/null
+++ b/RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.uni
@@ -0,0 +1,23 @@
+// /** @file
+//
+// Instance of PEI Services Table Pointer Library using RISC-V OpenSBI FirmwareContext.
+//
+// PEI Services Table Pointer Library implementation that retrieves a pointer to the
+// PEI Services Table from a RISC-V OpenSBI sbi_platform firmware context structure.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php.
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Instance of PEI Services Table Pointer Library using global variable for the table pointer"
+
+#string STR_MODULE_DESCRIPTION #language en-US "The PEI Services Table Pointer Library implementation that retrieves a pointer to the PEI Services Table from a global variable. Not available to modules that execute from read-only memory."
+
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 22/39] RiscVPlatformPkg/RiscVPlatformTempMemoryInit: RISC-V Platform Temporary Memory library
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (20 preceding siblings ...)
2019-10-28 1:58 ` [edk2-staging/RISC-V-V2 PATCH v3 21/39] RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service Table Pointer library Abner Chang
@ 2019-10-28 1:59 ` Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 23/39] RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver Abner Chang
` (16 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:59 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
NULL instance of RISC-V Platform Temporary Memory library.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../RiscVPlatformTempMemoryInitLibNull.inf | 34 ++++++++++++++++++++++
.../Library/RiscVPlatformTempMemoryInitLib.h | 17 +++++++++++
.../Riscv64/TempMemInit.S | 26 +++++++++++++++++
3 files changed, 77 insertions(+)
create mode 100644 RiscVPlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
create mode 100644 RiscVPlatformPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
create mode 100644 RiscVPlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.S
diff --git a/RiscVPlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf b/RiscVPlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
new file mode 100644
index 0000000..12fa497
--- /dev/null
+++ b/RiscVPlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/RiscVPlatformTempMemoryInitLibNull.inf
@@ -0,0 +1,34 @@
+## @file
+# RISC-V platform temporary memory library.
+#
+# Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVPlatformTempMemoryInitLibNull
+ FILE_GUID = 67294857-C0F8-4ACB-8237-D91FE506B710
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVPlatformTempMemoryInitLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+
+[Sources.RISCV64]
+ Riscv64/TempMemInit.S
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+
diff --git a/RiscVPlatformPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h b/RiscVPlatformPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
new file mode 100644
index 0000000..4f9f795
--- /dev/null
+++ b/RiscVPlatformPkg/Include/Library/RiscVPlatformTempMemoryInitLib.h
@@ -0,0 +1,17 @@
+/** @file
+ RISC-V package definitions.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef RISCV_PLATFORM_TEMP_MEM_LIB_H_
+#define RISCV_PLATFORM_TEMP_MEM_LIB_H_
+
+#include "RiscVImpl.h"
+
+VOID EFIAPI RiscVPlatformTemporaryMemInit (VOID);
+UINT32 EFIAPI RiscVPlatformTemporaryMemSize (VOID);
+UINT32 EFIAPI RiscVPlatformTemporaryMemBase (VOID);
+#endif
diff --git a/RiscVPlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.S b/RiscVPlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.S
new file mode 100644
index 0000000..61a9923
--- /dev/null
+++ b/RiscVPlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.S
@@ -0,0 +1,26 @@
+//------------------------------------------------------------------------------
+//
+// RISC-V RiscVPlatformTemporaryMemInit.
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <Base.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(RiscVPlatformTemporaryMemInit)
+
+//
+// @retval a0 Temporary memory base.
+// a1 Temporary memory size.
+//
+ASM_PFX(RiscVPlatformTemporaryMemInit):
+ li a0, FixedPcdGet32 (PcdRiscVSecPeiTempRamBase)
+ li a1, FixedPcdGet32 (PcdRiscVSecPeiTempRamSize)
+ ret
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 23/39] RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver.
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (21 preceding siblings ...)
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 22/39] RiscVPlatformPkg/RiscVPlatformTempMemoryInit: RISC-V Platform Temporary Memory library Abner Chang
@ 2019-10-28 1:59 ` Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 24/39] BaseTools: BaseTools changes for RISC-V platform Abner Chang
` (15 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:59 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
The driver produces RISC-V EFI_CPU_ARCH_PROTOCOL and use RISC-V
platform level timer library.
Due to RISC-V timer Control Status Register (CSR) is platform
implementation specific, RISC-V CPU DXE driver invokes platform level
timer library to access to timer CSRs.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
RiscVPkg/Universal/CpuDxe/CpuDxe.inf | 48 +++++
RiscVPkg/Universal/CpuDxe/CpuDxe.h | 199 +++++++++++++++++++
RiscVPkg/Universal/CpuDxe/CpuDxe.c | 317 ++++++++++++++++++++++++++++++
RiscVPkg/Universal/CpuDxe/CpuDxe.uni | 13 ++
| 14 ++
5 files changed, 591 insertions(+)
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.inf
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.h
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.c
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.uni
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni
diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.inf b/RiscVPkg/Universal/CpuDxe/CpuDxe.inf
new file mode 100644
index 0000000..6db10f9
--- /dev/null
+++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.inf
@@ -0,0 +1,48 @@
+## @file
+# RISC-V CPU DXE module.
+#
+# Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = CpuDxe
+ MODULE_UNI_FILE = CpuDxe.uni
+ FILE_GUID = 1A1E4886-9517-440e-9FDE-3BE44CEE2136
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+
+ ENTRY_POINT = InitializeCpu
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ CpuLib
+ CpuExceptionHandlerLib
+ DebugLib
+ RiscVCpuLib
+ TimerLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Sources]
+ CpuDxe.c
+ CpuDxe.h
+
+[Protocols]
+ gEfiCpuArchProtocolGuid ## PRODUCES
+
+[Pcd]
+ gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz
+
+[Depex]
+ TRUE
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ CpuDxeExtra.uni
diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.h b/RiscVPkg/Universal/CpuDxe/CpuDxe.h
new file mode 100644
index 0000000..c2c2739
--- /dev/null
+++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.h
@@ -0,0 +1,199 @@
+/** @file
+ RISC-V CPU DXE module header file.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef CPU_DXE_H_
+#define CPU_DXE_H_
+
+#include <PiDxe.h>
+
+#include <Protocol/Cpu.h>
+#include <Library/BaseLib.h>
+#include <Library/CpuExceptionHandlerLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RiscVCpuLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+
+/**
+ Flush CPU data cache. If the instruction cache is fully coherent
+ with all DMA operations then function can just return EFI_SUCCESS.
+
+ @param This Protocol instance structure
+ @param Start Physical address to start flushing from.
+ @param Length Number of bytes to flush. Round up to chipset
+ granularity.
+ @param FlushType Specifies the type of flush operation to perform.
+
+ @retval EFI_SUCCESS If cache was flushed
+ @retval EFI_UNSUPPORTED If flush type is not supported.
+ @retval EFI_DEVICE_ERROR If requested range could not be flushed.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuFlushCpuDataCache (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS Start,
+ IN UINT64 Length,
+ IN EFI_CPU_FLUSH_TYPE FlushType
+ );
+
+/**
+ Enables CPU interrupts.
+
+ @param This Protocol instance structure
+
+ @retval EFI_SUCCESS If interrupts were enabled in the CPU
+ @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuEnableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ );
+
+/**
+ Disables CPU interrupts.
+
+ @param This Protocol instance structure
+
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.
+ @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuDisableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ );
+
+/**
+ Return the state of interrupts.
+
+ @param This Protocol instance structure
+ @param State Pointer to the CPU's current interrupt state
+
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.
+ @retval EFI_INVALID_PARAMETER State is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuGetInterruptState (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ OUT BOOLEAN *State
+ );
+
+/**
+ Generates an INIT to the CPU.
+
+ @param This Protocol instance structure
+ @param InitType Type of CPU INIT to perform
+
+ @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
+ seen.
+ @retval EFI_DEVICE_ERROR If CPU INIT failed.
+ @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuInit (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_CPU_INIT_TYPE InitType
+ );
+
+/**
+ Registers a function to be called from the CPU interrupt handler.
+
+ @param This Protocol instance structure
+ @param InterruptType Defines which interrupt to hook. IA-32
+ valid range is 0x00 through 0xFF
+ @param InterruptHandler A pointer to a function of type
+ EFI_CPU_INTERRUPT_HANDLER that is called
+ when a processor interrupt occurs. A null
+ pointer is an error condition.
+
+ @retval EFI_SUCCESS If handler installed or uninstalled.
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler
+ for InterruptType was previously installed.
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for
+ InterruptType was not previously installed.
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
+ is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuRegisterInterruptHandler (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ );
+
+/**
+ Returns a timer value from one of the CPU's internal timers. There is no
+ inherent time interval between ticks but is a function of the CPU frequency.
+
+ @param This - Protocol instance structure.
+ @param TimerIndex - Specifies which CPU timer is requested.
+ @param TimerValue - Pointer to the returned timer value.
+ @param TimerPeriod - A pointer to the amount of time that passes
+ in femtoseconds (10-15) for each increment
+ of TimerValue. If TimerValue does not
+ increment at a predictable rate, then 0 is
+ returned. The amount of time that has
+ passed between two calls to GetTimerValue()
+ can be calculated with the formula
+ (TimerValue2 - TimerValue1) * TimerPeriod.
+ This parameter is optional and may be NULL.
+
+ @retval EFI_SUCCESS - If the CPU timer count was returned.
+ @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.
+ @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.
+ @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuGetTimerValue (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN UINT32 TimerIndex,
+ OUT UINT64 *TimerValue,
+ OUT UINT64 *TimerPeriod OPTIONAL
+ );
+
+/**
+ Set memory cacheability attributes for given range of memeory.
+
+ @param This Protocol instance structure
+ @param BaseAddress Specifies the start address of the
+ memory range
+ @param Length Specifies the length of the memory range
+ @param Attributes The memory cacheability for the memory range
+
+ @retval EFI_SUCCESS If the cacheability of that memory range is
+ set successfully
+ @retval EFI_UNSUPPORTED If the desired operation cannot be done
+ @retval EFI_INVALID_PARAMETER The input parameter is not correct,
+ such as Length = 0
+
+**/
+EFI_STATUS
+EFIAPI
+CpuSetMemoryAttributes (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
+ );
+
+#endif
+
diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.c b/RiscVPkg/Universal/CpuDxe/CpuDxe.c
new file mode 100644
index 0000000..d9d2494
--- /dev/null
+++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.c
@@ -0,0 +1,317 @@
+/** @file
+ RISC-V CPU DXE driver.
+
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "CpuDxe.h"
+
+//
+// Global Variables
+//
+STATIC BOOLEAN mInterruptState = FALSE;
+STATIC EFI_HANDLE mCpuHandle = NULL;
+
+EFI_CPU_ARCH_PROTOCOL gCpu = {
+ CpuFlushCpuDataCache,
+ CpuEnableInterrupt,
+ CpuDisableInterrupt,
+ CpuGetInterruptState,
+ CpuInit,
+ CpuRegisterInterruptHandler,
+ CpuGetTimerValue,
+ CpuSetMemoryAttributes,
+ 1, // NumberOfTimers
+ 4 // DmaBufferAlignment
+};
+
+//
+// CPU Arch Protocol Functions
+//
+
+/**
+ Flush CPU data cache. If the instruction cache is fully coherent
+ with all DMA operations then function can just return EFI_SUCCESS.
+
+ @param This Protocol instance structure
+ @param Start Physical address to start flushing from.
+ @param Length Number of bytes to flush. Round up to chipset
+ granularity.
+ @param FlushType Specifies the type of flush operation to perform.
+
+ @retval EFI_SUCCESS If cache was flushed
+ @retval EFI_UNSUPPORTED If flush type is not supported.
+ @retval EFI_DEVICE_ERROR If requested range could not be flushed.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuFlushCpuDataCache (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS Start,
+ IN UINT64 Length,
+ IN EFI_CPU_FLUSH_TYPE FlushType
+ )
+{
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Enables CPU interrupts.
+
+ @param This Protocol instance structure
+
+ @retval EFI_SUCCESS If interrupts were enabled in the CPU
+ @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuEnableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ )
+{
+ EnableInterrupts ();
+ mInterruptState = TRUE;
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Disables CPU interrupts.
+
+ @param This Protocol instance structure
+
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.
+ @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuDisableInterrupt (
+ IN EFI_CPU_ARCH_PROTOCOL *This
+ )
+{
+ DisableInterrupts ();
+ mInterruptState = FALSE;
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Return the state of interrupts.
+
+ @param This Protocol instance structure
+ @param State Pointer to the CPU's current interrupt state
+
+ @retval EFI_SUCCESS If interrupts were disabled in the CPU.
+ @retval EFI_INVALID_PARAMETER State is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuGetInterruptState (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ OUT BOOLEAN *State
+ )
+{
+ if (State == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *State = mInterruptState;
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Generates an INIT to the CPU.
+
+ @param This Protocol instance structure
+ @param InitType Type of CPU INIT to perform
+
+ @retval EFI_SUCCESS If CPU INIT occurred. This value should never be
+ seen.
+ @retval EFI_DEVICE_ERROR If CPU INIT failed.
+ @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuInit (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_CPU_INIT_TYPE InitType
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+
+/**
+ Registers a function to be called from the CPU interrupt handler.
+
+ @param This Protocol instance structure
+ @param InterruptType Defines which interrupt to hook. IA-32
+ valid range is 0x00 through 0xFF
+ @param InterruptHandler A pointer to a function of type
+ EFI_CPU_INTERRUPT_HANDLER that is called
+ when a processor interrupt occurs. A null
+ pointer is an error condition.
+
+ @retval EFI_SUCCESS If handler installed or uninstalled.
+ @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler
+ for InterruptType was previously installed.
+ @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for
+ InterruptType was not previously installed.
+ @retval EFI_UNSUPPORTED The interrupt specified by InterruptType
+ is not supported.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuRegisterInterruptHandler (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ )
+{
+ return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
+}
+
+
+/**
+ Returns a timer value from one of the CPU's internal timers. There is no
+ inherent time interval between ticks but is a function of the CPU frequency.
+
+ @param This - Protocol instance structure.
+ @param TimerIndex - Specifies which CPU timer is requested.
+ @param TimerValue - Pointer to the returned timer value.
+ @param TimerPeriod - A pointer to the amount of time that passes
+ in femtoseconds (10-15) for each increment
+ of TimerValue. If TimerValue does not
+ increment at a predictable rate, then 0 is
+ returned. The amount of time that has
+ passed between two calls to GetTimerValue()
+ can be calculated with the formula
+ (TimerValue2 - TimerValue1) * TimerPeriod.
+ This parameter is optional and may be NULL.
+
+ @retval EFI_SUCCESS - If the CPU timer count was returned.
+ @retval EFI_UNSUPPORTED - If the CPU does not have any readable timers.
+ @retval EFI_DEVICE_ERROR - If an error occurred while reading the timer.
+ @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is NULL.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuGetTimerValue (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN UINT32 TimerIndex,
+ OUT UINT64 *TimerValue,
+ OUT UINT64 *TimerPeriod OPTIONAL
+ )
+{
+ if (TimerValue == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (TimerIndex != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *TimerValue = (UINT64)RiscVReadMachineTimer ();
+ if (TimerPeriod != NULL) {
+ *TimerPeriod = DivU64x32 (
+ 1000000000000000u,
+ PcdGet64 (PcdRiscVMachineTimerFrequencyInHerz)
+ );
+ }
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.
+
+ This function modifies the attributes for the memory region specified by BaseAddress and
+ Length from their current attributes to the attributes specified by Attributes.
+
+ @param This The EFI_CPU_ARCH_PROTOCOL instance.
+ @param BaseAddress The physical address that is the start address of a memory region.
+ @param Length The size in bytes of the memory region.
+ @param Attributes The bit mask of attributes to set for the memory region.
+
+ @retval EFI_SUCCESS The attributes were set for the memory region.
+ @retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by
+ BaseAddress and Length cannot be modified.
+ @retval EFI_INVALID_PARAMETER Length is zero.
+ Attributes specified an illegal combination of attributes that
+ cannot be set together.
+ @retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of
+ the memory resource range.
+ @retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory
+ resource range specified by BaseAddress and Length.
+ The bit mask of attributes is not support for the memory resource
+ range specified by BaseAddress and Length.
+
+**/
+EFI_STATUS
+EFIAPI
+CpuSetMemoryAttributes (
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
+ )
+{
+ DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __FUNCTION__));
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Initialize the state information for the CPU Architectural Protocol.
+
+ @param ImageHandle Image handle this driver.
+ @param SystemTable Pointer to the System Table.
+
+ @retval EFI_SUCCESS Thread can be successfully created
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Cannot create the thread
+
+**/
+EFI_STATUS
+EFIAPI
+InitializeCpu (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Machine mode handler is initiated in CpuExceptionHandlerLibConstructor in
+ // CpuExecptionHandlerLib.
+ //
+
+ //
+ // Make sure interrupts are disabled
+ //
+ DisableInterrupts ();
+
+ //
+ // Install CPU Architectural Protocol
+ //
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &mCpuHandle,
+ &gEfiCpuArchProtocolGuid, &gCpu,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
+
diff --git a/RiscVPkg/Universal/CpuDxe/CpuDxe.uni b/RiscVPkg/Universal/CpuDxe/CpuDxe.uni
new file mode 100644
index 0000000..460141a
--- /dev/null
+++ b/RiscVPkg/Universal/CpuDxe/CpuDxe.uni
@@ -0,0 +1,13 @@
+// /** @file
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Installs RISC-V CPU Architecture Protocol"
+
+#string STR_MODULE_DESCRIPTION #language en-US "RISC-V CPU driver installs CPU Architecture Protocol."
+
--git a/RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni b/RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni
new file mode 100644
index 0000000..6f819f0
--- /dev/null
+++ b/RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni
@@ -0,0 +1,14 @@
+// /** @file
+// CpuDxe Localized Strings and Content
+//
+// Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME
+#language en-US
+"RISC-V Architectural DXE Driver"
+
+
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 24/39] BaseTools: BaseTools changes for RISC-V platform.
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (22 preceding siblings ...)
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 23/39] RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver Abner Chang
@ 2019-10-28 1:59 ` Abner Chang
2019-11-21 16:55 ` Leif Lindholm
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 25/39] BaseTools/Scripts Abner Chang
` (14 subsequent siblings)
38 siblings, 1 reply; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:59 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Bob Feng, Liming Gao, Leif Lindholm, Gilbert Chen
BaseTools changes for building EDK2 RISC-V platform.
The changes made to build_rule.template is to avoid build errors
caused by GCC5 tool chain.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
BaseTools/Source/C/Common/PeCoffLib.h | 9 +
BaseTools/Source/C/GenFw/elf_common.h | 62 +++++
.../Source/C/Include/IndustryStandard/PeImage.h | 6 +
BaseTools/Source/C/Common/BasePeCoff.c | 15 +-
BaseTools/Source/C/Common/PeCoffLoaderEx.c | 86 +++++++
BaseTools/Source/C/GenFv/GenFvInternalLib.c | 128 +++++++++-
BaseTools/Source/C/GenFw/Elf32Convert.c | 5 +-
BaseTools/Source/C/GenFw/Elf64Convert.c | 282 ++++++++++++++++++++-
BaseTools/Conf/build_rule.template | 54 ++--
BaseTools/Conf/tools_def.template | 64 ++++-
BaseTools/Source/Python/Common/DataType.py | 7 +-
BaseTools/Source/Python/Common/buildoptions.py | 6 +-
12 files changed, 685 insertions(+), 39 deletions(-)
diff --git a/BaseTools/Source/C/Common/PeCoffLib.h b/BaseTools/Source/C/Common/PeCoffLib.h
index 2fb2265..8dd269e 100644
--- a/BaseTools/Source/C/Common/PeCoffLib.h
+++ b/BaseTools/Source/C/Common/PeCoffLib.h
@@ -2,6 +2,7 @@
Function prototypes and defines on Memory Only PE COFF loader
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+ Portion Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -25,6 +26,14 @@
#define IMAGE_ERROR_FAILED_RELOCATION 9
#define IMAGE_ERROR_FAILED_ICACHE_FLUSH 10
+//
+// Macro definitions for RISC-V architecture.
+//
+#define RV_X(x, s, n) (((x) >> (s)) & ((1<<(n))-1))
+#define RISCV_IMM_BITS 12
+#define RISCV_IMM_REACH (1LL<<RISCV_IMM_BITS)
+#define RISCV_CONST_HIGH_PART(VALUE) \
+ (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
//
// PE/COFF Loader Read Function passed in by caller
diff --git a/BaseTools/Source/C/GenFw/elf_common.h b/BaseTools/Source/C/GenFw/elf_common.h
index 15c9e33..1321f78 100644
--- a/BaseTools/Source/C/GenFw/elf_common.h
+++ b/BaseTools/Source/C/GenFw/elf_common.h
@@ -3,6 +3,7 @@ Ported ELF include files from FreeBSD
Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+Portion Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -178,6 +179,8 @@ typedef struct {
#define EM_X86_64 62 /* Advanced Micro Devices x86-64 */
#define EM_AMD64 EM_X86_64 /* Advanced Micro Devices x86-64 (compat) */
#define EM_AARCH64 183 /* ARM 64bit Architecture */
+#define EM_RISCV64 243 /* 64bit RISC-V Architecture */
+#define EM_RISCV 244 /* 32bit RISC-V Architecture */
/* Non-standard or deprecated. */
#define EM_486 6 /* Intel i486. */
@@ -979,5 +982,64 @@ typedef struct {
#define R_X86_64_GOTPCRELX 41 /* Load from 32 bit signed pc relative offset to GOT entry without REX prefix, relaxable. */
#define R_X86_64_REX_GOTPCRELX 42 /* Load from 32 bit signed pc relative offset to GOT entry with REX prefix, relaxable. */
+/*
+ * RISC-V relocation types
+ */
+
+/* Relocation types used by the dynamic linker */
+#define R_RISCV_NONE 0
+#define R_RISCV_32 1
+#define R_RISCV_64 2
+#define R_RISCV_RELATIVE 3
+#define R_RISCV_COPY 4
+#define R_RISCV_JUMP_SLOT 5
+#define R_RISCV_TLS_DTPMOD32 6
+#define R_RISCV_TLS_DTPMOD64 7
+#define R_RISCV_TLS_DTPREL32 8
+#define R_RISCV_TLS_DTPREL64 9
+#define R_RISCV_TLS_TPREL32 10
+#define R_RISCV_TLS_TPREL64 11
+/* Relocation types not used by the dynamic linker */
+#define R_RISCV_BRANCH 16
+#define R_RISCV_JAL 17
+#define R_RISCV_CALL 18
+#define R_RISCV_CALL_PLT 19
+#define R_RISCV_GOT_HI20 20
+#define R_RISCV_TLS_GOT_HI20 21
+#define R_RISCV_TLS_GD_HI20 22
+#define R_RISCV_PCREL_HI20 23
+#define R_RISCV_PCREL_LO12_I 24
+#define R_RISCV_PCREL_LO12_S 25
+#define R_RISCV_HI20 26
+#define R_RISCV_LO12_I 27
+#define R_RISCV_LO12_S 28
+#define R_RISCV_TPREL_HI20 29
+#define R_RISCV_TPREL_LO12_I 30
+#define R_RISCV_TPREL_LO12_S 31
+#define R_RISCV_TPREL_ADD 32
+#define R_RISCV_ADD8 33
+#define R_RISCV_ADD16 34
+#define R_RISCV_ADD32 35
+#define R_RISCV_ADD64 36
+#define R_RISCV_SUB8 37
+#define R_RISCV_SUB16 38
+#define R_RISCV_SUB32 39
+#define R_RISCV_SUB64 40
+#define R_RISCV_GNU_VTINHERIT 41
+#define R_RISCV_GNU_VTENTRY 42
+#define R_RISCV_ALIGN 43
+#define R_RISCV_RVC_BRANCH 44
+#define R_RISCV_RVC_JUMP 45
+#define R_RISCV_RVC_LUI 46
+#define R_RISCV_GPREL_I 47
+#define R_RISCV_GPREL_S 48
+#define R_RISCV_TPREL_I 49
+#define R_RISCV_TPREL_S 50
+#define R_RISCV_RELAX 51
+#define R_RISCV_SUB6 52
+#define R_RISCV_SET6 53
+#define R_RISCV_SET8 54
+#define R_RISCV_SET16 55
+#define R_RISCV_SET32 56
#endif /* !_SYS_ELF_COMMON_H_ */
diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
index 44037d1..2ed3008 100644
--- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
+++ b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
@@ -6,6 +6,7 @@
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -41,6 +42,7 @@
#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only
#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and Thumb/Thumb 2 Little Endian
#define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM Architecture, Little Endian
+#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA
//
// Support old names for backward compatible
@@ -50,6 +52,7 @@
#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64
#define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT
#define EFI_IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64
+#define EFI_IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64
#define EFI_IMAGE_DOS_SIGNATURE 0x5A4D // MZ
#define EFI_IMAGE_OS2_SIGNATURE 0x454E // NE
@@ -504,7 +507,10 @@ typedef struct {
#define EFI_IMAGE_REL_BASED_HIGHADJ 4
#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5
#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5
+#define EFI_IMAGE_REL_BASED_RISCV_HI20 5
#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
#define EFI_IMAGE_REL_BASED_IA64_IMM64 9
#define EFI_IMAGE_REL_BASED_DIR64 10
diff --git a/BaseTools/Source/C/Common/BasePeCoff.c b/BaseTools/Source/C/Common/BasePeCoff.c
index e7566b3..640f7a1 100644
--- a/BaseTools/Source/C/Common/BasePeCoff.c
+++ b/BaseTools/Source/C/Common/BasePeCoff.c
@@ -4,6 +4,7 @@
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -59,6 +60,14 @@ PeCoffLoaderRelocateArmImage (
IN UINT64 Adjust
);
+RETURN_STATUS
+PeCoffLoaderRelocateRiscVImage (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ );
+
STATIC
RETURN_STATUS
PeCoffLoaderGetPeHeader (
@@ -174,7 +183,8 @@ Returns:
ImageContext->Machine != EFI_IMAGE_MACHINE_X64 && \
ImageContext->Machine != EFI_IMAGE_MACHINE_ARMT && \
ImageContext->Machine != EFI_IMAGE_MACHINE_EBC && \
- ImageContext->Machine != EFI_IMAGE_MACHINE_AARCH64) {
+ ImageContext->Machine != EFI_IMAGE_MACHINE_AARCH64 && \
+ ImageContext->Machine != EFI_IMAGE_MACHINE_RISCV64) {
if (ImageContext->Machine == IMAGE_FILE_MACHINE_ARM) {
//
// There are two types of ARM images. Pure ARM and ARM/Thumb.
@@ -802,6 +812,9 @@ Returns:
case EFI_IMAGE_MACHINE_ARMT:
Status = PeCoffLoaderRelocateArmImage (&Reloc, Fixup, &FixupData, Adjust);
break;
+ case EFI_IMAGE_MACHINE_RISCV64:
+ Status = PeCoffLoaderRelocateRiscVImage (Reloc, Fixup, &FixupData, Adjust);
+ break;
default:
Status = RETURN_UNSUPPORTED;
break;
diff --git a/BaseTools/Source/C/Common/PeCoffLoaderEx.c b/BaseTools/Source/C/Common/PeCoffLoaderEx.c
index e367836..305906a 100644
--- a/BaseTools/Source/C/Common/PeCoffLoaderEx.c
+++ b/BaseTools/Source/C/Common/PeCoffLoaderEx.c
@@ -3,6 +3,7 @@ IA32 and X64 Specific relocation fixups
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
--*/
@@ -61,6 +62,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define IMM64_SIGN_INST_WORD_POS_X 27
#define IMM64_SIGN_VAL_POS_X 63
+UINT32 *RiscVHi20Fixup = NULL;
+
RETURN_STATUS
PeCoffLoaderRelocateIa32Image (
IN UINT16 *Reloc,
@@ -93,6 +96,89 @@ Returns:
return RETURN_UNSUPPORTED;
}
+/*++
+
+Routine Description:
+
+ Performs an RISC-V specific relocation fixup
+
+Arguments:
+
+ Reloc - Pointer to the relocation record
+
+ Fixup - Pointer to the address to fix up
+
+ FixupData - Pointer to a buffer to log the fixups
+
+ Adjust - The offset to adjust the fixup
+
+Returns:
+
+ Status code
+
+--*/
+RETURN_STATUS
+PeCoffLoaderRelocateRiscVImage (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ )
+{
+ UINT32 Value;
+ UINT32 Value2;
+ UINT32 OrgValue;
+
+ OrgValue = *(UINT32 *) Fixup;
+ OrgValue = OrgValue;
+ switch ((*Reloc) >> 12) {
+ case EFI_IMAGE_REL_BASED_RISCV_HI20:
+ RiscVHi20Fixup = (UINT32 *) Fixup;
+ break;
+
+ case EFI_IMAGE_REL_BASED_RISCV_LOW12I:
+ if (RiscVHi20Fixup != NULL) {
+ Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
+ Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 20, 12));
+ if (Value2 & (RISCV_IMM_REACH/2)) {
+ Value2 |= ~(RISCV_IMM_REACH-1);
+ }
+ Value += Value2;
+ Value += (UINT32)Adjust;
+ Value2 = RISCV_CONST_HIGH_PART (Value);
+ *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
+ (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
+ *(UINT32 *)Fixup = (RV_X (Value, 0, 12) << 20) | \
+ (RV_X (*(UINT32 *)Fixup, 0, 20));
+ }
+ RiscVHi20Fixup = NULL;
+ break;
+
+ case EFI_IMAGE_REL_BASED_RISCV_LOW12S:
+ if (RiscVHi20Fixup != NULL) {
+ Value = (UINT32)(RV_X(*RiscVHi20Fixup, 12, 20) << 12);
+ Value2 = (UINT32)(RV_X(*(UINT32 *)Fixup, 7, 5) | (RV_X(*(UINT32 *)Fixup, 25, 7) << 5));
+ if (Value2 & (RISCV_IMM_REACH/2)) {
+ Value2 |= ~(RISCV_IMM_REACH-1);
+ }
+ Value += Value2;
+ Value += (UINT32)Adjust;
+ Value2 = RISCV_CONST_HIGH_PART (Value);
+ *(UINT32 *)RiscVHi20Fixup = (RV_X (Value2, 12, 20) << 12) | \
+ (RV_X (*(UINT32 *)RiscVHi20Fixup, 0, 12));
+ Value2 = *(UINT32 *)Fixup & 0x01fff07f;
+ Value &= RISCV_IMM_REACH - 1;
+ *(UINT32 *)Fixup = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) | (RV_X(Value, 5, 7) << 25)));
+ }
+ RiscVHi20Fixup = NULL;
+ break;
+
+ default:
+ return EFI_UNSUPPORTED;
+
+ }
+ return RETURN_SUCCESS;
+}
/**
Pass in a pointer to an ARM MOVT or MOVW immediate instruction and
diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
index 908740d..fdbdd42 100644
--- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
+++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
@@ -4,6 +4,7 @@ This file contains the internal functions required to generate a Firmware Volume
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
Portions Copyright (c) 2016 HP Development Company, L.P.<BR>
+Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -37,6 +38,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define ARM64_UNCONDITIONAL_JUMP_INSTRUCTION 0x14000000
BOOLEAN mArm = FALSE;
+BOOLEAN mRiscV = FALSE;
STATIC UINT32 MaxFfsAlignment = 0;
BOOLEAN VtfFileFlag = FALSE;
@@ -2274,6 +2276,104 @@ Returns:
}
EFI_STATUS
+UpdateRiscvResetVectorIfNeeded (
+ MEMORY_FILE *FvImage,
+ FV_INFO *FvInfo
+ )
+/*++
+
+Routine Description:
+ This parses the FV looking for SEC and patches that address into the
+ beginning of the FV header.
+
+ For RISC-V ISA, the reset vector is at 0xfff~ff00h or 200h
+
+Arguments:
+ FvImage Memory file for the FV memory image/
+ FvInfo Information read from INF file.
+
+Returns:
+
+ EFI_SUCCESS Function Completed successfully.
+ EFI_ABORTED Error encountered.
+ EFI_INVALID_PARAMETER A required parameter was NULL.
+ EFI_NOT_FOUND PEI Core file not found.
+
+--*/
+{
+ EFI_STATUS Status;
+ UINT16 MachineType;
+ EFI_FILE_SECTION_POINTER SecPe32;
+ EFI_PHYSICAL_ADDRESS SecCoreEntryAddress;
+
+ UINT32 bSecCore;
+ UINT32 tmp;
+
+
+ //
+ // Verify input parameters
+ //
+ if (FvImage == NULL || FvInfo == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+ //
+ // Initialize FV library
+ //
+ InitializeFvLib (FvImage->FileImage, FvInfo->Size);
+
+ //
+ // Find the Sec Core
+ //
+ Status = FindCorePeSection(FvImage->FileImage, FvInfo->Size, EFI_FV_FILETYPE_SECURITY_CORE, &SecPe32);
+ if(EFI_ERROR(Status)) {
+ printf("skip because Secutiry Core not found\n");
+ return EFI_SUCCESS;
+ }
+
+ DebugMsg (NULL, 0, 9, "Update SEC core in FV Header", NULL);
+
+ Status = GetCoreMachineType(SecPe32, &MachineType);
+ if(EFI_ERROR(Status)) {
+ Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 machine type for SEC core.");
+ return EFI_ABORTED;
+ }
+
+ if (MachineType != EFI_IMAGE_MACHINE_RISCV64) {
+ Error(NULL, 0, 3000, "Invalid", "Could not update SEC core because Machine type is not RiscV.");
+ return EFI_ABORTED;
+ }
+
+ Status = GetCoreEntryPointAddress(FvImage->FileImage, FvInfo, SecPe32, &SecCoreEntryAddress);
+ if(EFI_ERROR(Status)) {
+ Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 entry point address for SEC Core.");
+ return EFI_ABORTED;
+ }
+
+ VerboseMsg("SecCore entry point Address = 0x%llX", (unsigned long long) SecCoreEntryAddress);
+ VerboseMsg("BaseAddress = 0x%llX", (unsigned long long) FvInfo->BaseAddress);
+ bSecCore = (SecCoreEntryAddress - FvInfo->BaseAddress);
+ VerboseMsg("offset = 0x%llX", bSecCore);
+
+ if(bSecCore > 0x0fffff) {
+ Error(NULL, 0, 3000, "Invalid", "SEC Entry point must be within 1MB of start of the FV");
+ return EFI_ABORTED;
+ }
+
+ tmp = bSecCore;
+ bSecCore = 0;
+ //J-type
+ bSecCore = (tmp&0x100000)<<11; //imm[20] at bit[31]
+ bSecCore |= (tmp&0x0007FE)<<20; //imm[10:1] at bit[30:21]
+ bSecCore |= (tmp&0x000800)<<9; //imm[11] at bit[20]
+ bSecCore |= (tmp&0x0FF000); //imm[19:12] at bit[19:12]
+ bSecCore |= 0x6F; //JAL opcode
+
+ memcpy(FvImage->FileImage, &bSecCore, sizeof(bSecCore));
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
GetPe32Info (
IN UINT8 *Pe32,
OUT UINT32 *EntryPoint,
@@ -2365,7 +2465,8 @@ Returns:
// Verify machine type is supported
//
if ((*MachineType != EFI_IMAGE_MACHINE_IA32) && (*MachineType != EFI_IMAGE_MACHINE_X64) && (*MachineType != EFI_IMAGE_MACHINE_EBC) &&
- (*MachineType != EFI_IMAGE_MACHINE_ARMT) && (*MachineType != EFI_IMAGE_MACHINE_AARCH64)) {
+ (*MachineType != EFI_IMAGE_MACHINE_ARMT) && (*MachineType != EFI_IMAGE_MACHINE_AARCH64) &&
+ (*MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
Error (NULL, 0, 3000, "Invalid", "Unrecognized machine type in the PE32 file.");
return EFI_UNSUPPORTED;
}
@@ -2808,7 +2909,8 @@ Returns:
Error (NULL, 0, 4002, "Resource", "FV space is full, cannot add pad file between the last file and the VTF file.");
goto Finish;
}
- if (!mArm) {
+
+ if (!mArm && !mRiscV) {
//
// Update reset vector (SALE_ENTRY for IPF)
// Now for IA32 and IA64 platform, the fv which has bsf file must have the
@@ -2843,6 +2945,22 @@ Returns:
FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
}
+ if (mRiscV) {
+ //
+ // Update RISCV reset vector.
+ //
+ Status = UpdateRiscvResetVectorIfNeeded (&FvImageMemoryFile, &mFvDataInfo);
+ if (EFI_ERROR (Status)) {
+ Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector for RISC-V.");
+ goto Finish;
+ }
+ //
+ // Update Checksum for FvHeader
+ //
+ FvHeader->Checksum = 0;
+ FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
+ }
+
//
// Update FV Alignment attribute to the largest alignment of all the FFS files in the FV
//
@@ -3430,6 +3548,10 @@ Returns:
mArm = TRUE;
}
+ if (ImageContext.Machine == EFI_IMAGE_MACHINE_RISCV64) {
+ mRiscV = TRUE;
+ }
+
//
// Keep Image Context for PE image in FV
//
@@ -3583,7 +3705,7 @@ Returns:
ImageContext.DestinationAddress = NewPe32BaseAddress;
Status = PeCoffLoaderRelocateImage (&ImageContext);
if (EFI_ERROR (Status)) {
- Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on rebase of %s", FileName);
+ Error (NULL, 0, 3000, "Invalid", "RelocateImage() call failed on rebase of %s Status=%d", FileName, Status);
free ((VOID *) MemoryImagePointer);
return Status;
}
diff --git a/BaseTools/Source/C/GenFw/Elf32Convert.c b/BaseTools/Source/C/GenFw/Elf32Convert.c
index 46089ff..4095b7c 100644
--- a/BaseTools/Source/C/GenFw/Elf32Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf32Convert.c
@@ -3,6 +3,7 @@ Elf32 Convert solution
Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2013, ARM Ltd. All rights reserved.<BR>
+Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -141,8 +142,8 @@ InitializeElf32 (
Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or ET_DYN");
return FALSE;
}
- if (!((mEhdr->e_machine == EM_386) || (mEhdr->e_machine == EM_ARM))) {
- Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not EM_386 or EM_ARM");
+ if (!((mEhdr->e_machine == EM_386) || (mEhdr->e_machine == EM_ARM) || (mEhdr->e_machine == EM_RISCV))) {
+ Error (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf32 machine.");
return FALSE;
}
if (mEhdr->e_version != EV_CURRENT) {
diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index 3d6319c..8c74669 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -3,6 +3,7 @@ Elf64 convert solution
Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>
+Portions Copyright (c) 2016 - 2019 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -123,6 +124,13 @@ STATIC UINT32 mRelocOffset;
STATIC UINT32 mDebugOffset;
//
+// Used for RISC-V relocations.
+//
+STATIC UINT8 *mRiscVPass1Targ = NULL;
+STATIC Elf_Shdr *mRiscVPass1Sym = NULL;
+STATIC Elf64_Half mRiscVPass1SymSecIndex = 0;
+
+//
// Initialization Function
//
BOOLEAN
@@ -153,8 +161,8 @@ InitializeElf64 (
Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or ET_DYN");
return FALSE;
}
- if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine == EM_AARCH64))) {
- Error (NULL, 0, 3000, "Unsupported", "ELF e_machine not EM_X86_64 or EM_AARCH64");
+ if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine == EM_AARCH64) || (mEhdr->e_machine == EM_RISCV64))) {
+ Error (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf64 machine.");
return FALSE;
}
if (mEhdr->e_version != EV_CURRENT) {
@@ -452,6 +460,147 @@ EmitGOTRelocations (
mGOTMaxCoffEntries = 0;
mGOTNumCoffEntries = 0;
}
+//
+// RISC-V 64 specific Elf WriteSection function.
+//
+STATIC
+VOID
+WriteSectionRiscV64 (
+ Elf_Rela *Rel,
+ UINT8 *Targ,
+ Elf_Shdr *SymShdr,
+ Elf_Sym *Sym
+ )
+{
+ UINT32 Value;
+ UINT32 Value2;
+
+ switch (ELF_R_TYPE(Rel->r_info)) {
+ case R_RISCV_NONE:
+ break;
+
+ case R_RISCV_32:
+ *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]);
+ break;
+
+ case R_RISCV_64:
+ *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
+ break;
+
+ case R_RISCV_HI20:
+ mRiscVPass1Targ = Targ;
+ mRiscVPass1Sym = SymShdr;
+ mRiscVPass1SymSecIndex = Sym->st_shndx;
+ break;
+
+ case R_RISCV_LO12_I:
+ if (mRiscVPass1Sym == SymShdr && mRiscVPass1Targ != NULL && mRiscVPass1SymSecIndex == Sym->st_shndx && mRiscVPass1SymSecIndex != 0) {
+ Value = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20) << 12);
+ Value2 = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
+ if (Value2 & (RISCV_IMM_REACH/2)) {
+ Value2 |= ~(RISCV_IMM_REACH-1);
+ }
+ Value += Value2;
+ Value = Value - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
+ Value2 = RISCV_CONST_HIGH_PART (Value);
+ *(UINT32 *)mRiscVPass1Targ = (RV_X (Value2, 12, 20) << 12) | \
+ (RV_X (*(UINT32 *)mRiscVPass1Targ, 0, 12));
+ *(UINT32 *)Targ = (RV_X (Value, 0, 12) << 20) | \
+ (RV_X (*(UINT32 *)Targ, 0, 20));
+ }
+ mRiscVPass1Sym = NULL;
+ mRiscVPass1Targ = NULL;
+ mRiscVPass1SymSecIndex = 0;
+ break;
+
+ case R_RISCV_LO12_S:
+ if (mRiscVPass1Sym == SymShdr && mRiscVPass1Targ != NULL && mRiscVPass1SymSecIndex == Sym->st_shndx && mRiscVPass1SymSecIndex != 0) {
+ Value = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20) << 12);
+ Value2 = (UINT32)(RV_X(*(UINT32 *)Targ, 7, 5) | (RV_X(*(UINT32 *)Targ, 25, 7) << 5));
+ if (Value2 & (RISCV_IMM_REACH/2)) {
+ Value2 |= ~(RISCV_IMM_REACH-1);
+ }
+ Value += Value2;
+ Value = Value - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
+ Value2 = RISCV_CONST_HIGH_PART (Value);
+ *(UINT32 *)mRiscVPass1Targ = (RV_X (Value2, 12, 20) << 12) | \
+ (RV_X (*(UINT32 *)mRiscVPass1Targ, 0, 12));
+ Value2 = *(UINT32 *)Targ & 0x01fff07f;
+ Value &= RISCV_IMM_REACH - 1;
+ *(UINT32 *)Targ = Value2 | (UINT32)(((RV_X(Value, 0, 5) << 7) | (RV_X(Value, 5, 7) << 25)));
+ }
+ mRiscVPass1Sym = NULL;
+ mRiscVPass1Targ = NULL;
+ mRiscVPass1SymSecIndex = 0;
+ break;
+
+ case R_RISCV_PCREL_HI20:
+ mRiscVPass1Targ = Targ;
+ mRiscVPass1Sym = SymShdr;
+ mRiscVPass1SymSecIndex = Sym->st_shndx;
+
+ Value = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));
+ break;
+
+ case R_RISCV_PCREL_LO12_I:
+ if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) {
+ int i;
+ Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));
+ Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
+ if(Value & (RISCV_IMM_REACH/2)) {
+ Value |= ~(RISCV_IMM_REACH-1);
+ }
+ Value = Value - mRiscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex];
+ if(-2048 > (INT32)Value) {
+ i = (-Value / 4096);
+ Value2 -= i;
+ Value += 4096 * i;
+ if(-2048 > (INT32)Value) {
+ Value2 -= 1;
+ Value += 4096;
+ }
+ }
+ else if( 2047 < (INT32)Value) {
+ i = (Value / 4096);
+ Value2 += i;
+ Value -= 4096 * i;
+ if(2047 < (INT32)Value) {
+ Value2 += 1;
+ Value -= 4096;
+ }
+ }
+
+ *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
+ *(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12));
+ }
+ mRiscVPass1Sym = NULL;
+ mRiscVPass1Targ = NULL;
+ mRiscVPass1SymSecIndex = 0;
+ break;
+
+ case R_RISCV_ADD64:
+ case R_RISCV_SUB64:
+ case R_RISCV_ADD32:
+ case R_RISCV_SUB32:
+ case R_RISCV_BRANCH:
+ case R_RISCV_JAL:
+ case R_RISCV_GPREL_I:
+ case R_RISCV_GPREL_S:
+ case R_RISCV_CALL:
+ case R_RISCV_RVC_BRANCH:
+ case R_RISCV_RVC_JUMP:
+ case R_RISCV_RELAX:
+ case R_RISCV_SUB6:
+ case R_RISCV_SET6:
+ case R_RISCV_SET8:
+ case R_RISCV_SET16:
+ case R_RISCV_SET32:
+ break;
+
+ default:
+ Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
+ }
+}
//
// Elf functions interface implementation
@@ -481,6 +630,7 @@ ScanSections64 (
switch (mEhdr->e_machine) {
case EM_X86_64:
case EM_AARCH64:
+ case EM_RISCV64:
mCoffOffset += sizeof (EFI_IMAGE_NT_HEADERS64);
break;
default:
@@ -690,6 +840,11 @@ ScanSections64 (
NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_AARCH64;
NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
break;
+ case EM_RISCV64:
+ NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_RISCV64;
+ NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
+ break;
+
default:
VerboseMsg ("%s unknown e_machine type. Assume X64", (UINTN)mEhdr->e_machine);
NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_X64;
@@ -894,12 +1049,18 @@ WriteSections64 (
SymName = (const UINT8 *)"<unknown>";
}
- Error (NULL, 0, 3000, "Invalid",
- "%s: Bad definition for symbol '%s'@%#llx or unsupported symbol type. "
- "For example, absolute and undefined symbols are not supported.",
- mInImageName, SymName, Sym->st_value);
+ //
+ // Skip error on EM_RISCV64 becasue no symble name is built
+ // from RISC-V toolchain.
+ //
+ if (mEhdr->e_machine != EM_RISCV64) {
+ Error (NULL, 0, 3000, "Invalid",
+ "%s: Bad definition for symbol '%s'@%#llx or unsupported symbol type. "
+ "For example, absolute and undefined symbols are not supported.",
+ mInImageName, SymName, Sym->st_value);
- exit(EXIT_FAILURE);
+ exit(EXIT_FAILURE);
+ }
}
SymShdr = GetShdrByIndex(Sym->st_shndx);
@@ -1114,6 +1275,11 @@ WriteSections64 (
default:
Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
}
+ } else if (mEhdr->e_machine == EM_RISCV64) {
+ //
+ // Write section for RISC-V 64 architecture.
+ //
+ WriteSectionRiscV64 (Rel, Targ, SymShdr, Sym);
} else {
Error (NULL, 0, 3000, "Invalid", "Not a supported machine type");
}
@@ -1133,6 +1299,7 @@ WriteRelocations64 (
UINT32 Index;
EFI_IMAGE_OPTIONAL_HEADER_UNION *NtHdr;
EFI_IMAGE_DATA_DIRECTORY *Dir;
+ UINT32 RiscVRelType;
for (Index = 0; Index < mEhdr->e_shnum; Index++) {
Elf_Shdr *RelShdr = GetShdrByIndex(Index);
@@ -1237,6 +1404,107 @@ WriteRelocations64 (
default:
Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_AARCH64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
}
+ } else if (mEhdr->e_machine == EM_RISCV64) {
+ RiscVRelType = ELF_R_TYPE(Rel->r_info);
+ switch (RiscVRelType) {
+ case R_RISCV_NONE:
+ break;
+
+ case R_RISCV_32:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_HIGHLOW);
+ break;
+
+ case R_RISCV_64:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_DIR64);
+ break;
+
+ case R_RISCV_HI20:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_RISCV_HI20);
+ break;
+
+ case R_RISCV_LO12_I:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_RISCV_LOW12I);
+ break;
+
+ case R_RISCV_LO12_S:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_RISCV_LOW12S);
+ break;
+
+ case R_RISCV_ADD64:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_ABSOLUTE);
+ break;
+
+ case R_RISCV_SUB64:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_ABSOLUTE);
+ break;
+
+ case R_RISCV_ADD32:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_ABSOLUTE);
+ break;
+
+ case R_RISCV_SUB32:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_ABSOLUTE);
+ break;
+
+ case R_RISCV_BRANCH:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_ABSOLUTE);
+ break;
+
+ case R_RISCV_JAL:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_ABSOLUTE);
+ break;
+
+ case R_RISCV_GPREL_I:
+ case R_RISCV_GPREL_S:
+ case R_RISCV_CALL:
+ case R_RISCV_RVC_BRANCH:
+ case R_RISCV_RVC_JUMP:
+ case R_RISCV_RELAX:
+ case R_RISCV_SUB6:
+ case R_RISCV_SET6:
+ case R_RISCV_SET8:
+ case R_RISCV_SET16:
+ case R_RISCV_SET32:
+ case R_RISCV_PCREL_HI20:
+ case R_RISCV_PCREL_LO12_I:
+ break;
+
+ default:
+ Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
+ }
} else {
Error (NULL, 0, 3000, "Not Supported", "This tool does not support relocations for ELF with e_machine %u (processor type).", (unsigned) mEhdr->e_machine);
}
diff --git a/BaseTools/Conf/build_rule.template b/BaseTools/Conf/build_rule.template
index db06d3a..57c3cf7 100755
--- a/BaseTools/Conf/build_rule.template
+++ b/BaseTools/Conf/build_rule.template
@@ -1,6 +1,7 @@
#
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
+# Portions Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -266,10 +267,10 @@
<Command.GCC>
$(RM) ${dst}
"$(SLINK)" cr ${dst} $(SLINK_FLAGS) @$(OBJECT_FILES_LIST)
-
+
<Command.RVCT>
"$(SLINK)" $(SLINK_FLAGS) ${dst} --via $(OBJECT_FILES_LIST)
-
+
<Command.RVCTCYGWIN>
# $(OBJECT_FILES_LIST) has wrong paths for cygwin
"$(SLINK)" $(SLINK_FLAGS) ${dst} $(OBJECT_FILES)
@@ -304,8 +305,8 @@
<Command.XCODE>
"$(DLINK)" $(DLINK_FLAGS) -o ${dst} $(DLINK_SPATH) -filelist $(STATIC_LIBRARY_FILES_LIST) $(DLINK2_FLAGS)
-
-
+
+
[Static-Library-File.SEC.AARCH64, Static-Library-File.PEI_CORE.AARCH64, Static-Library-File.PEIM.AARCH64,Static-Library-File.SEC.ARM, Static-Library-File.PEI_CORE.ARM, Static-Library-File.PEIM.ARM]
<InputFile>
*.lib
@@ -321,6 +322,21 @@
"$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst}
+[Static-Library-File.COMMON.RISCV64, Static-Library-File.COMMON.RISCV32]
+ <InputFile>
+ *.lib
+
+ <ExtraDependency>
+ $(MAKE_FILE)
+
+ <OutputFile>
+ $(DEBUG_DIR)(+)$(MODULE_NAME).dll
+
+ <Command.GCC>
+ "$(DLINK)" -o ${dst} $(DLINK_FLAGS) --start-group $(DLINK_SPATH) @$(STATIC_LIBRARY_FILES_LIST) --end-group $(DLINK2_FLAGS)
+ "$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst}
+
+
[Static-Library-File.USER_DEFINED, Static-Library-File.HOST_APPLICATION]
<InputFile>
*.lib
@@ -346,8 +362,8 @@
<Command.XCODE>
"$(DLINK)" -o ${dst} $(DLINK_FLAGS) $(DLINK_SPATH) -filelist $(STATIC_LIBRARY_FILES_LIST) $(DLINK2_FLAGS)
-
-
+
+
[Dynamic-Library-File]
<InputFile>
?.dll
@@ -360,7 +376,7 @@
$(CP) ${dst} $(DEBUG_DIR)
$(CP) ${dst} $(BIN_DIR)(+)$(MODULE_NAME_GUID).efi
-$(CP) $(DEBUG_DIR)(+)*.map $(OUTPUT_DIR)
- -$(CP) $(DEBUG_DIR)(+)*.pdb $(OUTPUT_DIR)
+ -$(CP) $(DEBUG_DIR)(+)*.pdb $(OUTPUT_DIR)
<Command.GCC>
$(CP) ${src} $(DEBUG_DIR)(+)$(MODULE_NAME).debug
$(OBJCOPY) --strip-unneeded -R .eh_frame ${src}
@@ -375,7 +391,7 @@
$(CP) ${dst} $(DEBUG_DIR)
$(CP) ${dst} $(BIN_DIR)(+)$(MODULE_NAME_GUID).efi
-$(CP) $(DEBUG_DIR)(+)*.map $(OUTPUT_DIR)
-
+
<Command.XCODE>
# tool to convert Mach-O to PE/COFF
"$(MTOC)" -subsystem $(MODULE_TYPE) $(MTOC_FLAGS) ${src} $(DEBUG_DIR)(+)$(MODULE_NAME).pecoff
@@ -414,13 +430,13 @@
<Command.MSFT, Command.INTEL>
Trim --asl-file -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i -i $(INC_LIST) ${src}
"$(ASLPP)" $(ASLPP_FLAGS) $(INC) /I${s_path} $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i > $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
- Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
+ Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
"$(ASL)" $(ASL_FLAGS) $(ASL_OUTFLAGS)${dst} $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii
<Command.GCC>
Trim --asl-file -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i -i $(INC_LIST) ${src}
"$(ASLPP)" $(ASLPP_FLAGS) $(INC) -I${s_path} $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i > $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
- Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
+ Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
"$(ASL)" $(ASL_FLAGS) $(ASL_OUTFLAGS)${dst} $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii
[C-Code-File.AcpiTable]
@@ -462,14 +478,14 @@
"$(ASLCC)" -c -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(CC_FLAGS) $(ASLCC_FLAGS) $(INC) ${src}
"$(ASLDLINK)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll $(ASLDLINK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj
"$(GENFW)" -o ${dst} -c $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll $(GENFW_FLAGS)
-
- <Command.XCODE>
+
+ <Command.XCODE>
"$(ASLCC)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(ASLCC_FLAGS) $(INC) ${src}
"$(ASLDLINK)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll $(ASLDLINK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj
"$(MTOC)" -subsystem $(MODULE_TYPE) $(MTOC_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.pecoff
"$(GENFW)" -o ${dst} -c $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.pecoff $(GENFW_FLAGS)
-
-
+
+
[Masm16-Code-File]
<InputFile>
?.asm16, ?.Asm16, ?.ASM16, ?.s16, ?.S16
@@ -492,14 +508,14 @@
Trim --source-code -o ${d_path}(+)${s_base}.iii ${d_path}(+)${s_base}.i
"$(ASM)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(ASM_FLAGS) $(INC) ${d_path}(+)${s_base}.iii
"$(DLINK)" -o ${dst} $(DLINK_FLAGS) --start-group $(DLINK_SPATH) $(LIBS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj --end-group
-
+
<Command.XCODE>
"$(PP)" $(PP_FLAGS) $(INC) ${src} > ${d_path}(+)${s_base}.i
Trim --source-code -o ${d_path}(+)${s_base}.iii ${d_path}(+)${s_base}.i
"$(ASM)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(ASM_FLAGS) $(INC) ${d_path}(+)${s_base}.iii
"$(SLINK)" $(SLINK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.slib $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj
otool -t $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.slib | hex2bin.py ${dst}
-
+
[Nasm-to-Binary-Code-File]
<InputFile>
@@ -635,8 +651,8 @@
<Command.GCC>
"$(GENFW)" -o $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc -g $(MODULE_GUID) --hiibinpackage $(HII_BINARY_PACKAGES) $(GENFW_FLAGS)
"$(RC)" $(RC_FLAGS) $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc ${dst}
-
+
<Command.XCODE, Command.RVCT>
GenFw -o $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc -g $(MODULE_GUID) --hiibinpackage $(HII_BINARY_PACKAGES)
-
-
+
+
diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template
index 8f0e6cb..8adfab0 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -3,7 +3,7 @@
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
# Copyright (c) 2015, Hewlett-Packard Development Company, L.P.<BR>
-# (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
+# (C) Copyright 2016-2019 Hewlett Packard Enterprise Development LP<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -231,11 +231,12 @@ DEFINE DTC_BIN = ENV(DTC_PREFIX)dtc
# Intel(r) ACPI Compiler from
# https://acpica.org/downloads
# GCC5 -Linux,Windows- Requires:
-# GCC 5 with LTO support, targeting x86_64-linux-gnu, aarch64-linux-gnu, or arm-linux-gnueabi
+# GCC 5 with LTO support, targeting x86_64-linux-gnu, aarch64-linux-gnu, arm-linux-gnueabi or riscv64-linux-gnu
# Optional:
# Required to build platforms or ACPI tables:
# Intel(r) ACPI Compiler from
# https://acpica.org/downloads
+#
# CLANG35 -Linux,Windows- Requires:
# Clang v3.5 or later, and GNU binutils targeting aarch64-linux-gnu or arm-linux-gnueabi
# Optional:
@@ -1735,6 +1736,7 @@ DEFINE GCC_IA32_RC_FLAGS = -I binary -O elf32-i386 -B i386
DEFINE GCC_X64_RC_FLAGS = -I binary -O elf64-x86-64 -B i386 --rename-section .data=.hii
DEFINE GCC_ARM_RC_FLAGS = -I binary -O elf32-littlearm -B arm --rename-section .data=.hii
DEFINE GCC_AARCH64_RC_FLAGS = -I binary -O elf64-littleaarch64 -B aarch64 --rename-section .data=.hii
+DEFINE GCC_RISCV64_RC_FLAGS = -I binary -O elf64-littleriscv -B riscv --rename-section .data=.hii
DEFINE GCC48_ALL_CC_FLAGS = -g -fshort-wchar -fno-builtin -fno-strict-aliasing -Wall -Werror -Wno-array-bounds -ffunction-sections -fdata-sections -include AutoGen.h -fno-common -DSTRING_ARRAY_NAME=$(BASE_NAME)Strings
DEFINE GCC48_IA32_X64_DLINK_COMMON = -nostdlib -Wl,-n,-q,--gc-sections -z common-page-size=0x20
@@ -1806,6 +1808,21 @@ DEFINE GCC5_ARM_ASLDLINK_FLAGS = DEF(GCC49_ARM_ASLDLINK_FLAGS)
DEFINE GCC5_AARCH64_ASLDLINK_FLAGS = DEF(GCC49_AARCH64_ASLDLINK_FLAGS)
DEFINE GCC5_ASLCC_FLAGS = DEF(GCC49_ASLCC_FLAGS) -fno-lto
+DEFINE GCC5_RISCV_ALL_CC_FLAGS = -g -fshort-wchar -fno-strict-aliasing -Wall -Werror -Wno-array-bounds -ffunction-sections -fdata-sections -c -include AutoGen.h -fno-common -DSTRING_ARRAY_NAME=$(BASE_NAME)Strings
+DEFINE GCC5_RISCV_ALL_DLINK_COMMON = -nostdlib -n -q --gc-sections -z common-page-size=0x40
+DEFINE GCC5_RISCV_ALL_DLINK_FLAGS = DEF(GCC5_RISCV_ALL_DLINK_COMMON) --entry $(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Map $(DEST_DIR_DEBUG)/$(BASE_NAME).map
+DEFINE GCC5_RISCV_ALL_DLINK2_FLAGS = --defsym=PECOFF_HEADER_SIZE=0x220 --script=$(EDK_TOOLS_PATH)/Scripts/GccBaseRiscV.lds
+DEFINE GCC5_RISCV_ALL_ASM_FLAGS = -c -x assembler -imacros $(DEST_DIR_DEBUG)/AutoGen.h
+DEFINE GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE = -Wno-tautological-compare -Wno-pointer-compare
+
+DEFINE GCC5_RISCV64_ARCH = rv64imafdc
+DEFINE GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS = DEF(GCC5_RISCV_ALL_DLINK_COMMON) --entry ReferenceAcpiTable -u ReferenceAcpiTable
+DEFINE GCC5_RISCV32_RISCV64_DLINK_FLAGS = DEF(GCC5_RISCV_ALL_DLINK_COMMON) --entry $(IMAGE_ENTRY_POINT) -u $(IMAGE_ENTRY_POINT) -Map $(DEST_DIR_DEBUG)/$(BASE_NAME).map
+DEFINE GCC5_RISCV64_CC_FLAGS = DEF(GCC5_RISCV_ALL_CC_FLAGS) DEF(GCC5_RISCV_ALL_CC_FLAGS_WARNING_DISABLE) -march=DEF(GCC5_RISCV64_ARCH) -fno-builtin -fno-builtin-memcpy -fno-stack-protector -Wno-address -fno-asynchronous-unwind-tables -Wno-unused-but-set-variable -fpack-struct=8 -mcmodel=medany -mabi=lp64
+DEFINE GCC5_RISCV64_DLINK_FLAGS = DEF(GCC5_RISCV_ALL_DLINK_FLAGS) -melf64lriscv --oformat=elf64-littleriscv --no-relax
+DEFINE GCC5_RISCV64_DLINK2_FLAGS = DEF(GCC5_RISCV_ALL_DLINK2_FLAGS)
+DEFINE GCC5_ASM_FLAGS = DEF(GCC5_RISCV_ALL_ASM_FLAGS) -march=DEF(GCC5_RISCV64_ARCH) -mcmodel=medany -mabi=lp64
+
####################################################################################
#
# GCC 4.8 - This configuration is used to compile under Linux to produce
@@ -2247,6 +2264,49 @@ RELEASE_GCC5_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
NOOPT_GCC5_AARCH64_DLINK_FLAGS = DEF(GCC5_AARCH64_DLINK_FLAGS) -O0
NOOPT_GCC5_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20 -O0
+###################################################################################
+####################################################################################
+#
+# GCC RISC-V This configuration is used to compile under Linux to produce
+# PE/COFF binaries using GCC RISC-V tool chain
+#
+####################################################################################
+
+#*_GCC5_*_*_FAMILY = GCC
+
+#*_GCC5_*_MAKE_PATH = DEF(GCC49_IA32_PREFIX)make
+#*_GCC5_*_PP_FLAGS = DEF(GCC_PP_FLAGS)
+#*_GCC5_*_ASLPP_FLAGS = DEF(GCC_ASLPP_FLAGS)
+#*_GCC5_*_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
+#*_GCC5_*_VFRPP_FLAGS = DEF(GCC_VFRPP_FLAGS)
+#*_GCC5_*_APP_FLAGS =
+#*_GCC5_*_ASL_FLAGS = DEF(IASL_FLAGS)
+#*_GCC5_*_ASL_OUTFLAGS = DEF(IASL_OUTFLAGS)
+
+##################
+# GCC5 RISCV64 definitions
+##################
+*_GCC5_RISCV64_OBJCOPY_PATH = ENV(GCC5_RISCV64_PREFIX)objcopy
+*_GCC5_RISCV64_CC_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
+*_GCC5_RISCV64_SLINK_PATH = ENV(GCC5_RISCV64_PREFIX)gcc-ar
+*_GCC5_RISCV64_DLINK_PATH = ENV(GCC5_RISCV64_PREFIX)ld
+*_GCC5_RISCV64_ASLDLINK_PATH = ENV(GCC5_RISCV64_PREFIX)ld
+*_GCC5_RISCV64_ASM_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
+*_GCC5_RISCV64_PP_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
+*_GCC5_RISCV64_VFRPP_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
+*_GCC5_RISCV64_ASLCC_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
+*_GCC5_RISCV64_ASLPP_PATH = ENV(GCC5_RISCV64_PREFIX)gcc
+*_GCC5_RISCV64_RC_PATH = ENV(GCC5_RISCV64_PREFIX)objcopy
+
+*_GCC5_RISCV64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
+*_GCC5_RISCV64_ASLDLINK_FLAGS = DEF(GCC5_RISCV32_RISCV64_ASLDLINK_FLAGS)
+*_GCC5_RISCV64_ASM_FLAGS = DEF(GCC5_ASM_FLAGS)
+*_GCC5_RISCV64_CC_FLAGS = DEF(GCC5_RISCV64_CC_FLAGS) -save-temps
+*_GCC5_RISCV64_DLINK_FLAGS = DEF(GCC5_RISCV64_DLINK_FLAGS)
+*_GCC5_RISCV64_DLINK2_FLAGS = DEF(GCC5_RISCV64_DLINK2_FLAGS)
+*_GCC5_RISCV64_RC_FLAGS = DEF(GCC_RISCV64_RC_FLAGS)
+*_GCC5_RISCV64_OBJCOPY_FLAGS =
+
####################################################################################
#
# CLANG35 - This configuration is used to compile under Linux to produce
diff --git a/BaseTools/Source/Python/Common/DataType.py b/BaseTools/Source/Python/Common/DataType.py
index 8ae1bd2..0bc5d47 100644
--- a/BaseTools/Source/Python/Common/DataType.py
+++ b/BaseTools/Source/Python/Common/DataType.py
@@ -3,6 +3,7 @@
#
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+# Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
@@ -52,7 +53,9 @@ TAB_ARCH_ARM = 'ARM'
TAB_ARCH_EBC = 'EBC'
TAB_ARCH_AARCH64 = 'AARCH64'
-ARCH_SET_FULL = {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC, TAB_ARCH_AARCH64, TAB_ARCH_COMMON}
+TAB_ARCH_RISCV64 = 'RISCV64'
+
+ARCH_SET_FULL = {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC, TAB_ARCH_AARCH64, TAB_ARCH_RISCV64, TAB_ARCH_COMMON}
SUP_MODULE_BASE = 'BASE'
SUP_MODULE_SEC = 'SEC'
@@ -532,4 +535,4 @@ PACK_CODE_BY_SIZE = {8:'=Q',
0:'=B',
16:""}
-TAB_COMPILER_MSFT = 'MSFT'
\ No newline at end of file
+TAB_COMPILER_MSFT = 'MSFT'
\ No newline at end of file
diff --git a/BaseTools/Source/Python/Common/buildoptions.py b/BaseTools/Source/Python/Common/buildoptions.py
index 7161aa6..b9357bc 100644
--- a/BaseTools/Source/Python/Common/buildoptions.py
+++ b/BaseTools/Source/Python/Common/buildoptions.py
@@ -3,7 +3,7 @@
#
# Copyright (c) 2014, Hewlett-Packard Development Company, L.P.<BR>
# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>
-# Copyright (c) 2018, Hewlett Packard Enterprise Development, L.P.<BR>
+# Copyright (c) 2018 - 2019, Hewlett Packard Enterprise Development, L.P.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -25,8 +25,8 @@ def SingleCheckCallback(option, opt_str, value, parser):
def MyOptionParser():
Parser = OptionParser(description=__copyright__, version=__version__, prog="build.exe", usage="%prog [options] [all|fds|genc|genmake|clean|cleanall|cleanlib|modules|libraries|run]")
- Parser.add_option("-a", "--arch", action="append", type="choice", choices=['IA32', 'X64', 'EBC', 'ARM', 'AARCH64'], dest="TargetArch",
- help="ARCHS is one of list: IA32, X64, ARM, AARCH64 or EBC, which overrides target.txt's TARGET_ARCH definition. To specify more archs, please repeat this option.")
+ Parser.add_option("-a", "--arch", action="append", type="choice", choices=['IA32', 'X64', 'EBC', 'ARM', 'AARCH64', 'RISCV64'], dest="TargetArch",
+ help="ARCHS is one of list: IA32, X64, ARM, AARCH64, RISCV64 or EBC, which overrides target.txt's TARGET_ARCH definition. To specify more archs, please repeat this option.")
Parser.add_option("-p", "--platform", action="callback", type="string", dest="PlatformFile", callback=SingleCheckCallback,
help="Build the platform specified by the DSC file name argument, overriding target.txt's ACTIVE_PLATFORM definition.")
Parser.add_option("-m", "--module", action="callback", type="string", dest="ModuleFile", callback=SingleCheckCallback,
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* Re: [edk2-staging/RISC-V-V2 PATCH v3 24/39] BaseTools: BaseTools changes for RISC-V platform.
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 24/39] BaseTools: BaseTools changes for RISC-V platform Abner Chang
@ 2019-11-21 16:55 ` Leif Lindholm
0 siblings, 0 replies; 77+ messages in thread
From: Leif Lindholm @ 2019-11-21 16:55 UTC (permalink / raw)
To: Abner Chang; +Cc: devel, Bob Feng, Liming Gao, Gilbert Chen
On Mon, Oct 28, 2019 at 09:59:02 +0800, Abner Chang wrote:
> BaseTools changes for building EDK2 RISC-V platform.
> The changes made to build_rule.template is to avoid build errors
> caused by GCC5 tool chain.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
>
> Cc: Bob Feng <bob.c.feng@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Gilbert Chen <gilbert.chen@hpe.com>
> ---
> BaseTools/Source/C/Common/PeCoffLib.h | 9 +
> BaseTools/Source/C/GenFw/elf_common.h | 62 +++++
> .../Source/C/Include/IndustryStandard/PeImage.h | 6 +
> BaseTools/Source/C/Common/BasePeCoff.c | 15 +-
> BaseTools/Source/C/Common/PeCoffLoaderEx.c | 86 +++++++
> BaseTools/Source/C/GenFv/GenFvInternalLib.c | 128 +++++++++-
> BaseTools/Source/C/GenFw/Elf32Convert.c | 5 +-
> BaseTools/Source/C/GenFw/Elf64Convert.c | 282 ++++++++++++++++++++-
> BaseTools/Conf/build_rule.template | 54 ++--
> BaseTools/Conf/tools_def.template | 64 ++++-
> BaseTools/Source/Python/Common/DataType.py | 7 +-
> BaseTools/Source/Python/Common/buildoptions.py | 6 +-
> 12 files changed, 685 insertions(+), 39 deletions(-)
>
> diff --git a/BaseTools/Conf/build_rule.template b/BaseTools/Conf/build_rule.template
> index db06d3a..57c3cf7 100755
> --- a/BaseTools/Conf/build_rule.template
> +++ b/BaseTools/Conf/build_rule.template
> @@ -1,6 +1,7 @@
> #
> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
> # Portions copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
> +# Portions Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
>
> @@ -266,10 +267,10 @@
> <Command.GCC>
> $(RM) ${dst}
> "$(SLINK)" cr ${dst} $(SLINK_FLAGS) @$(OBJECT_FILES_LIST)
> -
> +
There are a bunch of whitespace-only diffs in this file.
Please get rid of them.
(Or are you able to drop all of these changes after Mark's linker
script fix?)
/
Leif
> <Command.RVCT>
> "$(SLINK)" $(SLINK_FLAGS) ${dst} --via $(OBJECT_FILES_LIST)
> -
> +
> <Command.RVCTCYGWIN>
> # $(OBJECT_FILES_LIST) has wrong paths for cygwin
> "$(SLINK)" $(SLINK_FLAGS) ${dst} $(OBJECT_FILES)
> @@ -304,8 +305,8 @@
>
> <Command.XCODE>
> "$(DLINK)" $(DLINK_FLAGS) -o ${dst} $(DLINK_SPATH) -filelist $(STATIC_LIBRARY_FILES_LIST) $(DLINK2_FLAGS)
> -
> -
> +
> +
> [Static-Library-File.SEC.AARCH64, Static-Library-File.PEI_CORE.AARCH64, Static-Library-File.PEIM.AARCH64,Static-Library-File.SEC.ARM, Static-Library-File.PEI_CORE.ARM, Static-Library-File.PEIM.ARM]
> <InputFile>
> *.lib
> @@ -321,6 +322,21 @@
> "$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst}
>
>
> +[Static-Library-File.COMMON.RISCV64, Static-Library-File.COMMON.RISCV32]
> + <InputFile>
> + *.lib
> +
> + <ExtraDependency>
> + $(MAKE_FILE)
> +
> + <OutputFile>
> + $(DEBUG_DIR)(+)$(MODULE_NAME).dll
> +
> + <Command.GCC>
> + "$(DLINK)" -o ${dst} $(DLINK_FLAGS) --start-group $(DLINK_SPATH) @$(STATIC_LIBRARY_FILES_LIST) --end-group $(DLINK2_FLAGS)
> + "$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst}
> +
> +
> [Static-Library-File.USER_DEFINED, Static-Library-File.HOST_APPLICATION]
> <InputFile>
> *.lib
> @@ -346,8 +362,8 @@
>
> <Command.XCODE>
> "$(DLINK)" -o ${dst} $(DLINK_FLAGS) $(DLINK_SPATH) -filelist $(STATIC_LIBRARY_FILES_LIST) $(DLINK2_FLAGS)
> -
> -
> +
> +
> [Dynamic-Library-File]
> <InputFile>
> ?.dll
> @@ -360,7 +376,7 @@
> $(CP) ${dst} $(DEBUG_DIR)
> $(CP) ${dst} $(BIN_DIR)(+)$(MODULE_NAME_GUID).efi
> -$(CP) $(DEBUG_DIR)(+)*.map $(OUTPUT_DIR)
> - -$(CP) $(DEBUG_DIR)(+)*.pdb $(OUTPUT_DIR)
> + -$(CP) $(DEBUG_DIR)(+)*.pdb $(OUTPUT_DIR)
> <Command.GCC>
> $(CP) ${src} $(DEBUG_DIR)(+)$(MODULE_NAME).debug
> $(OBJCOPY) --strip-unneeded -R .eh_frame ${src}
> @@ -375,7 +391,7 @@
> $(CP) ${dst} $(DEBUG_DIR)
> $(CP) ${dst} $(BIN_DIR)(+)$(MODULE_NAME_GUID).efi
> -$(CP) $(DEBUG_DIR)(+)*.map $(OUTPUT_DIR)
> -
> +
> <Command.XCODE>
> # tool to convert Mach-O to PE/COFF
> "$(MTOC)" -subsystem $(MODULE_TYPE) $(MTOC_FLAGS) ${src} $(DEBUG_DIR)(+)$(MODULE_NAME).pecoff
> @@ -414,13 +430,13 @@
> <Command.MSFT, Command.INTEL>
> Trim --asl-file -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i -i $(INC_LIST) ${src}
> "$(ASLPP)" $(ASLPP_FLAGS) $(INC) /I${s_path} $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i > $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> - Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> + Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> "$(ASL)" $(ASL_FLAGS) $(ASL_OUTFLAGS)${dst} $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii
>
> <Command.GCC>
> Trim --asl-file -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i -i $(INC_LIST) ${src}
> "$(ASLPP)" $(ASLPP_FLAGS) $(INC) -I${s_path} $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.i > $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> - Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> + Trim --source-code -l -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iii
> "$(ASL)" $(ASL_FLAGS) $(ASL_OUTFLAGS)${dst} $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.iiii
>
> [C-Code-File.AcpiTable]
> @@ -462,14 +478,14 @@
> "$(ASLCC)" -c -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(CC_FLAGS) $(ASLCC_FLAGS) $(INC) ${src}
> "$(ASLDLINK)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll $(ASLDLINK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj
> "$(GENFW)" -o ${dst} -c $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll $(GENFW_FLAGS)
> -
> - <Command.XCODE>
> +
> + <Command.XCODE>
> "$(ASLCC)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(ASLCC_FLAGS) $(INC) ${src}
> "$(ASLDLINK)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll $(ASLDLINK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj
> "$(MTOC)" -subsystem $(MODULE_TYPE) $(MTOC_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.dll $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.pecoff
> "$(GENFW)" -o ${dst} -c $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.pecoff $(GENFW_FLAGS)
> -
> -
> +
> +
> [Masm16-Code-File]
> <InputFile>
> ?.asm16, ?.Asm16, ?.ASM16, ?.s16, ?.S16
> @@ -492,14 +508,14 @@
> Trim --source-code -o ${d_path}(+)${s_base}.iii ${d_path}(+)${s_base}.i
> "$(ASM)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(ASM_FLAGS) $(INC) ${d_path}(+)${s_base}.iii
> "$(DLINK)" -o ${dst} $(DLINK_FLAGS) --start-group $(DLINK_SPATH) $(LIBS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj --end-group
> -
> +
> <Command.XCODE>
> "$(PP)" $(PP_FLAGS) $(INC) ${src} > ${d_path}(+)${s_base}.i
> Trim --source-code -o ${d_path}(+)${s_base}.iii ${d_path}(+)${s_base}.i
> "$(ASM)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj $(ASM_FLAGS) $(INC) ${d_path}(+)${s_base}.iii
> "$(SLINK)" $(SLINK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.slib $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj
> otool -t $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.slib | hex2bin.py ${dst}
> -
> +
>
> [Nasm-to-Binary-Code-File]
> <InputFile>
> @@ -635,8 +651,8 @@
> <Command.GCC>
> "$(GENFW)" -o $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc -g $(MODULE_GUID) --hiibinpackage $(HII_BINARY_PACKAGES) $(GENFW_FLAGS)
> "$(RC)" $(RC_FLAGS) $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc ${dst}
> -
> +
> <Command.XCODE, Command.RVCT>
> GenFw -o $(OUTPUT_DIR)(+)$(MODULE_NAME)hii.rc -g $(MODULE_GUID) --hiibinpackage $(HII_BINARY_PACKAGES)
> -
> -
> +
> +
> diff --git a/BaseTools/Source/Python/Common/DataType.py b/BaseTools/Source/Python/Common/DataType.py
> index 8ae1bd2..0bc5d47 100644
> --- a/BaseTools/Source/Python/Common/DataType.py
> +++ b/BaseTools/Source/Python/Common/DataType.py
> @@ -3,6 +3,7 @@
> #
> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
> # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
> +# Portions Copyright (c) 2016 - 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
>
> ##
> @@ -52,7 +53,9 @@ TAB_ARCH_ARM = 'ARM'
> TAB_ARCH_EBC = 'EBC'
> TAB_ARCH_AARCH64 = 'AARCH64'
>
> -ARCH_SET_FULL = {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC, TAB_ARCH_AARCH64, TAB_ARCH_COMMON}
> +TAB_ARCH_RISCV64 = 'RISCV64'
> +
> +ARCH_SET_FULL = {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC, TAB_ARCH_AARCH64, TAB_ARCH_RISCV64, TAB_ARCH_COMMON}
>
> SUP_MODULE_BASE = 'BASE'
> SUP_MODULE_SEC = 'SEC'
> @@ -532,4 +535,4 @@ PACK_CODE_BY_SIZE = {8:'=Q',
> 0:'=B',
> 16:""}
>
> -TAB_COMPILER_MSFT = 'MSFT'
> \ No newline at end of file
> +TAB_COMPILER_MSFT = 'MSFT'
> \ No newline at end of file
The above hunk shouldn't be there.
/
Leif
^ permalink raw reply [flat|nested] 77+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v3 25/39] BaseTools/Scripts
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (23 preceding siblings ...)
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 24/39] BaseTools: BaseTools changes for RISC-V platform Abner Chang
@ 2019-10-28 1:59 ` Abner Chang
2019-11-19 18:17 ` [edk2-devel] " Mark Salter
2019-11-21 16:56 ` Leif Lindholm
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 26/39] RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms Abner Chang
` (13 subsequent siblings)
38 siblings, 2 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:59 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Bob Feng, Liming Gao, Leif Lindholm, Gilbert Chen
Add RISC-V specific LD scripts. ."rela(INFO)" in the latest GccBase.lds
causes PE32 relocation error.
This is the temporaty solution untill we find the root casue.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
BaseTools/Scripts/GccBaseRiscV.lds | 79 ++++++++++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
create mode 100644 BaseTools/Scripts/GccBaseRiscV.lds
diff --git a/BaseTools/Scripts/GccBaseRiscV.lds b/BaseTools/Scripts/GccBaseRiscV.lds
new file mode 100644
index 0000000..91937aa
--- /dev/null
+++ b/BaseTools/Scripts/GccBaseRiscV.lds
@@ -0,0 +1,79 @@
+/** @file
+
+ Unified linker script for GCC based builds
+
+ Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+SECTIONS {
+
+ /*
+ * The PE/COFF binary consists of DOS and PE/COFF headers, and a sequence of
+ * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs
+ * between 32-bit and 64-bit builds). The actual start of the .text section
+ * will be rounded up based on its actual alignment.
+ */
+ . = PECOFF_HEADER_SIZE;
+
+ .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {
+ *(.text .text.* .stub .gnu.linkonce.t.*)
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+ *(.got .got.*)
+
+ /*
+ * The contents of AutoGen.c files are mostly constant from the POV of the
+ * program, but most of it ends up in .data or .bss by default since few of
+ * the variable definitions that get emitted are declared as CONST.
+ * Unfortunately, we cannot pull it into the .text section entirely, since
+ * patchable PCDs are also emitted here, but we can at least move all of the
+ * emitted GUIDs here.
+ */
+ *:AutoGen.obj(.data.g*Guid)
+ }
+
+ /*
+ * The alignment of the .data section should be less than or equal to the
+ * alignment of the .text section. This ensures that the relative offset
+ * between these sections is the same in the ELF and the PE/COFF versions of
+ * this binary.
+ */
+ .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.bss .bss.*)
+ }
+
+ .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {
+ KEEP (*(.eh_frame))
+ }
+
+ .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {
+ *(.rela .rela.*)
+ }
+
+ .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {
+ KEEP (*(.hii))
+ }
+
+ /*
+ * Retain the GNU build id but in a non-allocatable section so GenFw
+ * does not copy it into the PE/COFF image.
+ */
+ .build-id (INFO) : { *(.note.gnu.build-id) }
+
+ /DISCARD/ : {
+ *(.note.GNU-stack)
+ *(.gnu_debuglink)
+ *(.interp)
+ *(.dynsym)
+ *(.dynstr)
+ *(.dynamic)
+ *(.hash .gnu.hash)
+ *(.comment)
+ *(COMMON)
+ }
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 25/39] BaseTools/Scripts
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 25/39] BaseTools/Scripts Abner Chang
@ 2019-11-19 18:17 ` Mark Salter
2019-11-20 8:23 ` Abner Chang
2019-11-21 16:56 ` Leif Lindholm
1 sibling, 1 reply; 77+ messages in thread
From: Mark Salter @ 2019-11-19 18:17 UTC (permalink / raw)
To: devel, abner.chang; +Cc: Bob Feng, Liming Gao, Leif Lindholm, Gilbert Chen
On Mon, 2019-10-28 at 09:59 +0800, Abner Chang wrote:
> Add RISC-V specific LD scripts. ."rela(INFO)" in the latest GccBase.lds
> causes PE32 relocation error.
> This is the temporaty solution untill we find the root casue.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
>
> Cc: Bob Feng <bob.c.feng@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Gilbert Chen <gilbert.chen@hpe.com>
> ---
> BaseTools/Scripts/GccBaseRiscV.lds | 79 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 79 insertions(+)
> create mode 100644 BaseTools/Scripts/GccBaseRiscV.lds
>
> diff --git a/BaseTools/Scripts/GccBaseRiscV.lds b/BaseTools/Scripts/GccBaseRiscV.lds
> new file mode 100644
> index 0000000..91937aa
> --- /dev/null
> +++ b/BaseTools/Scripts/GccBaseRiscV.lds
> @@ -0,0 +1,79 @@
> +/** @file
> +
> + Unified linker script for GCC based builds
> +
> + Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +SECTIONS {
> +
> + /*
> + * The PE/COFF binary consists of DOS and PE/COFF headers, and a sequence of
> + * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs
> + * between 32-bit and 64-bit builds). The actual start of the .text section
> + * will be rounded up based on its actual alignment.
> + */
> + . = PECOFF_HEADER_SIZE;
> +
> + .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> + *(.text .text.* .stub .gnu.linkonce.t.*)
> + *(.rodata .rodata.* .gnu.linkonce.r.*)
So, I tried running this risc-v port on a HiFive Unleashed board but
it crashed pretty early on. It turned out that the linker was placing
some const data at the start of .text before any actual code. That
didn't work out well. I got around that and was able to boot into the
efi shell by adding this to tell the linker explicitly where to put
that data:
*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
> + *(.got .got.*)
> +
> + /*
> + * The contents of AutoGen.c files are mostly constant from the POV of the
> + * program, but most of it ends up in .data or .bss by default since few of
> + * the variable definitions that get emitted are declared as CONST.
> + * Unfortunately, we cannot pull it into the .text section entirely, since
> + * patchable PCDs are also emitted here, but we can at least move all of the
> + * emitted GUIDs here.
> + */
> + *:AutoGen.obj(.data.g*Guid)
> + }
> +
> + /*
> + * The alignment of the .data section should be less than or equal to the
> + * alignment of the .text section. This ensures that the relative offset
> + * between these sections is the same in the ELF and the PE/COFF versions of
> + * this binary.
> + */
> + .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> + *(.data .data.* .gnu.linkonce.d.*)
> + *(.bss .bss.*)
> + }
> +
> + .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {
> + KEEP (*(.eh_frame))
> + }
> +
> + .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {
> + *(.rela .rela.*)
> + }
> +
> + .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> + KEEP (*(.hii))
> + }
> +
> + /*
> + * Retain the GNU build id but in a non-allocatable section so GenFw
> + * does not copy it into the PE/COFF image.
> + */
> + .build-id (INFO) : { *(.note.gnu.build-id) }
> +
> + /DISCARD/ : {
> + *(.note.GNU-stack)
> + *(.gnu_debuglink)
> + *(.interp)
> + *(.dynsym)
> + *(.dynstr)
> + *(.dynamic)
> + *(.hash .gnu.hash)
> + *(.comment)
> + *(COMMON)
> + }
> +}
^ permalink raw reply [flat|nested] 77+ messages in thread* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 25/39] BaseTools/Scripts
2019-11-19 18:17 ` [edk2-devel] " Mark Salter
@ 2019-11-20 8:23 ` Abner Chang
2019-11-21 7:40 ` Abner Chang
0 siblings, 1 reply; 77+ messages in thread
From: Abner Chang @ 2019-11-20 8:23 UTC (permalink / raw)
To: devel@edk2.groups.io, msalter@redhat.com
Cc: Bob Feng, Liming Gao, Leif Lindholm, Chen, Gilbert
Thanks Mark!
This is actually the problem of using latest RISC-V gnu toolchain which causes system hangs in the early POST. GNU toolchain at commit 64879b24 doesn't have this problem. Thanks for catching this and I am looking for the solution in edk2 build tool to fix this issue instead of changing lds file. We would like to use the common lds instead of creating specific one for RISC-V.
Or do you know is there any link options could avoid those special sections?
br
Abner
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Mark Salter
> Sent: Wednesday, November 20, 2019 2:18 AM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Cc: Bob Feng <bob.c.feng@intel.com>; Liming Gao <liming.gao@intel.com>;
> Leif Lindholm <leif.lindholm@linaro.org>; Chen, Gilbert
> <gilbert.chen@hpe.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 25/39]
> BaseTools/Scripts
>
> On Mon, 2019-10-28 at 09:59 +0800, Abner Chang wrote:
> > Add RISC-V specific LD scripts. ."rela(INFO)" in the latest
> > GccBase.lds causes PE32 relocation error.
> > This is the temporaty solution untill we find the root casue.
> >
> > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> >
> > Cc: Bob Feng <bob.c.feng@intel.com>
> > Cc: Liming Gao <liming.gao@intel.com>
> > Cc: Leif Lindholm <leif.lindholm@linaro.org>
> > Cc: Gilbert Chen <gilbert.chen@hpe.com>
> > ---
> > BaseTools/Scripts/GccBaseRiscV.lds | 79
> > ++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 79 insertions(+)
> > create mode 100644 BaseTools/Scripts/GccBaseRiscV.lds
> >
> > diff --git a/BaseTools/Scripts/GccBaseRiscV.lds
> > b/BaseTools/Scripts/GccBaseRiscV.lds
> > new file mode 100644
> > index 0000000..91937aa
> > --- /dev/null
> > +++ b/BaseTools/Scripts/GccBaseRiscV.lds
> > @@ -0,0 +1,79 @@
> > +/** @file
> > +
> > + Unified linker script for GCC based builds
> > +
> > + Copyright (c) 2010 - 2015, Intel Corporation. All rights
> > + reserved.<BR> Copyright (c) 2015, Linaro Ltd. All rights
> > + reserved.<BR> Copyright (c) 2019, Hewlett Packard Enterprise
> > + Development LP. All rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +SECTIONS {
> > +
> > + /*
> > + * The PE/COFF binary consists of DOS and PE/COFF headers, and a
> sequence of
> > + * section headers adding up to PECOFF_HEADER_SIZE bytes (which
> differs
> > + * between 32-bit and 64-bit builds). The actual start of the .text section
> > + * will be rounded up based on its actual alignment.
> > + */
> > + . = PECOFF_HEADER_SIZE;
> > +
> > + .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> > + *(.text .text.* .stub .gnu.linkonce.t.*)
> > + *(.rodata .rodata.* .gnu.linkonce.r.*)
>
> So, I tried running this risc-v port on a HiFive Unleashed board but it crashed
> pretty early on. It turned out that the linker was placing some const data at
> the start of .text before any actual code. That didn't work out well. I got
> around that and was able to boot into the efi shell by adding this to tell the
> linker explicitly where to put that data:
>
> *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
> *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
>
> > + *(.got .got.*)
> > +
> > + /*
> > + * The contents of AutoGen.c files are mostly constant from the POV of
> the
> > + * program, but most of it ends up in .data or .bss by default since few
> of
> > + * the variable definitions that get emitted are declared as CONST.
> > + * Unfortunately, we cannot pull it into the .text section entirely, since
> > + * patchable PCDs are also emitted here, but we can at least move all of
> the
> > + * emitted GUIDs here.
> > + */
> > + *:AutoGen.obj(.data.g*Guid)
> > + }
> > +
> > + /*
> > + * The alignment of the .data section should be less than or equal to the
> > + * alignment of the .text section. This ensures that the relative offset
> > + * between these sections is the same in the ELF and the PE/COFF
> versions of
> > + * this binary.
> > + */
> > + .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE))
> {
> > + *(.data .data.* .gnu.linkonce.d.*)
> > + *(.bss .bss.*)
> > + }
> > +
> > + .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {
> > + KEEP (*(.eh_frame))
> > + }
> > +
> > + .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {
> > + *(.rela .rela.*)
> > + }
> > +
> > + .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> > + KEEP (*(.hii))
> > + }
> > +
> > + /*
> > + * Retain the GNU build id but in a non-allocatable section so GenFw
> > + * does not copy it into the PE/COFF image.
> > + */
> > + .build-id (INFO) : { *(.note.gnu.build-id) }
> > +
> > + /DISCARD/ : {
> > + *(.note.GNU-stack)
> > + *(.gnu_debuglink)
> > + *(.interp)
> > + *(.dynsym)
> > + *(.dynstr)
> > + *(.dynamic)
> > + *(.hash .gnu.hash)
> > + *(.comment)
> > + *(COMMON)
> > + }
> > +}
>
>
>
>
^ permalink raw reply [flat|nested] 77+ messages in thread* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 25/39] BaseTools/Scripts
2019-11-20 8:23 ` Abner Chang
@ 2019-11-21 7:40 ` Abner Chang
0 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-11-21 7:40 UTC (permalink / raw)
To: devel@edk2.groups.io, msalter@redhat.com
Cc: Bob Feng, Liming Gao, Leif Lindholm, Chen, Gilbert
Mark, there is an option for RISC-V to limit the small data be placed in .sdata2 section. With the option -msmall-data-limit set to 0, the small data will be put into .text. Thus we can leverage Gccbase.lds without RISC-V specific one.
I sent the patches to devel for review. Thanks for finding the root cause.
Abner
> -----Original Message-----
> From: Chang, Abner (HPS SW/FW Technologist)
> Sent: Wednesday, November 20, 2019 4:23 PM
> To: devel@edk2.groups.io; msalter@redhat.com
> Cc: Bob Feng <bob.c.feng@intel.com>; Liming Gao <liming.gao@intel.com>;
> Leif Lindholm <leif.lindholm@linaro.org>; Chen, Gilbert
> <gilbert.chen@hpe.com>
> Subject: RE: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 25/39]
> BaseTools/Scripts
>
> Thanks Mark!
> This is actually the problem of using latest RISC-V gnu toolchain which causes
> system hangs in the early POST. GNU toolchain at commit 64879b24 doesn't
> have this problem. Thanks for catching this and I am looking for the solution
> in edk2 build tool to fix this issue instead of changing lds file. We would like to
> use the common lds instead of creating specific one for RISC-V.
>
> Or do you know is there any link options could avoid those special sections?
>
> br
> Abner
>
>
> > -----Original Message-----
> > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> > Mark Salter
> > Sent: Wednesday, November 20, 2019 2:18 AM
> > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> > <abner.chang@hpe.com>
> > Cc: Bob Feng <bob.c.feng@intel.com>; Liming Gao
> > <liming.gao@intel.com>; Leif Lindholm <leif.lindholm@linaro.org>;
> > Chen, Gilbert <gilbert.chen@hpe.com>
> > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 25/39]
> > BaseTools/Scripts
> >
> > On Mon, 2019-10-28 at 09:59 +0800, Abner Chang wrote:
> > > Add RISC-V specific LD scripts. ."rela(INFO)" in the latest
> > > GccBase.lds causes PE32 relocation error.
> > > This is the temporaty solution untill we find the root casue.
> > >
> > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > >
> > > Cc: Bob Feng <bob.c.feng@intel.com>
> > > Cc: Liming Gao <liming.gao@intel.com>
> > > Cc: Leif Lindholm <leif.lindholm@linaro.org>
> > > Cc: Gilbert Chen <gilbert.chen@hpe.com>
> > > ---
> > > BaseTools/Scripts/GccBaseRiscV.lds | 79
> > > ++++++++++++++++++++++++++++++++++++++
> > > 1 file changed, 79 insertions(+)
> > > create mode 100644 BaseTools/Scripts/GccBaseRiscV.lds
> > >
> > > diff --git a/BaseTools/Scripts/GccBaseRiscV.lds
> > > b/BaseTools/Scripts/GccBaseRiscV.lds
> > > new file mode 100644
> > > index 0000000..91937aa
> > > --- /dev/null
> > > +++ b/BaseTools/Scripts/GccBaseRiscV.lds
> > > @@ -0,0 +1,79 @@
> > > +/** @file
> > > +
> > > + Unified linker script for GCC based builds
> > > +
> > > + Copyright (c) 2010 - 2015, Intel Corporation. All rights
> > > + reserved.<BR> Copyright (c) 2015, Linaro Ltd. All rights
> > > + reserved.<BR> Copyright (c) 2019, Hewlett Packard Enterprise
> > > + Development LP. All rights reserved.<BR>
> > > +
> > > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > > +
> > > +**/
> > > +
> > > +SECTIONS {
> > > +
> > > + /*
> > > + * The PE/COFF binary consists of DOS and PE/COFF headers, and a
> > sequence of
> > > + * section headers adding up to PECOFF_HEADER_SIZE bytes (which
> > differs
> > > + * between 32-bit and 64-bit builds). The actual start of the .text
> section
> > > + * will be rounded up based on its actual alignment.
> > > + */
> > > + . = PECOFF_HEADER_SIZE;
> > > +
> > > + .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> > > + *(.text .text.* .stub .gnu.linkonce.t.*)
> > > + *(.rodata .rodata.* .gnu.linkonce.r.*)
> >
> > So, I tried running this risc-v port on a HiFive Unleashed board but
> > it crashed pretty early on. It turned out that the linker was placing
> > some const data at the start of .text before any actual code. That
> > didn't work out well. I got around that and was able to boot into the
> > efi shell by adding this to tell the linker explicitly where to put that data:
> >
> > *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
> > *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
> >
> > > + *(.got .got.*)
> > > +
> > > + /*
> > > + * The contents of AutoGen.c files are mostly constant from the
> > > + POV of
> > the
> > > + * program, but most of it ends up in .data or .bss by default
> > > + since few
> > of
> > > + * the variable definitions that get emitted are declared as CONST.
> > > + * Unfortunately, we cannot pull it into the .text section entirely, since
> > > + * patchable PCDs are also emitted here, but we can at least
> > > + move all of
> > the
> > > + * emitted GUIDs here.
> > > + */
> > > + *:AutoGen.obj(.data.g*Guid)
> > > + }
> > > +
> > > + /*
> > > + * The alignment of the .data section should be less than or equal to
> the
> > > + * alignment of the .text section. This ensures that the relative offset
> > > + * between these sections is the same in the ELF and the PE/COFF
> > versions of
> > > + * this binary.
> > > + */
> > > + .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE))
> > {
> > > + *(.data .data.* .gnu.linkonce.d.*)
> > > + *(.bss .bss.*)
> > > + }
> > > +
> > > + .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {
> > > + KEEP (*(.eh_frame))
> > > + }
> > > +
> > > + .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {
> > > + *(.rela .rela.*)
> > > + }
> > > +
> > > + .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> > > + KEEP (*(.hii))
> > > + }
> > > +
> > > + /*
> > > + * Retain the GNU build id but in a non-allocatable section so GenFw
> > > + * does not copy it into the PE/COFF image.
> > > + */
> > > + .build-id (INFO) : { *(.note.gnu.build-id) }
> > > +
> > > + /DISCARD/ : {
> > > + *(.note.GNU-stack)
> > > + *(.gnu_debuglink)
> > > + *(.interp)
> > > + *(.dynsym)
> > > + *(.dynstr)
> > > + *(.dynamic)
> > > + *(.hash .gnu.hash)
> > > + *(.comment)
> > > + *(COMMON)
> > > + }
> > > +}
> >
> >
> >
> >
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [edk2-staging/RISC-V-V2 PATCH v3 25/39] BaseTools/Scripts
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 25/39] BaseTools/Scripts Abner Chang
2019-11-19 18:17 ` [edk2-devel] " Mark Salter
@ 2019-11-21 16:56 ` Leif Lindholm
2019-11-22 3:49 ` Abner Chang
1 sibling, 1 reply; 77+ messages in thread
From: Leif Lindholm @ 2019-11-21 16:56 UTC (permalink / raw)
To: Abner Chang; +Cc: devel, Bob Feng, Liming Gao, Gilbert Chen
On Mon, Oct 28, 2019 at 09:59:03 +0800, Abner Chang wrote:
> Add RISC-V specific LD scripts. ."rela(INFO)" in the latest GccBase.lds
> causes PE32 relocation error.
> This is the temporaty solution untill we find the root casue.
And it can go now, right?
/
Leif
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
>
> Cc: Bob Feng <bob.c.feng@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Gilbert Chen <gilbert.chen@hpe.com>
> ---
> BaseTools/Scripts/GccBaseRiscV.lds | 79 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 79 insertions(+)
> create mode 100644 BaseTools/Scripts/GccBaseRiscV.lds
>
> diff --git a/BaseTools/Scripts/GccBaseRiscV.lds b/BaseTools/Scripts/GccBaseRiscV.lds
> new file mode 100644
> index 0000000..91937aa
> --- /dev/null
> +++ b/BaseTools/Scripts/GccBaseRiscV.lds
> @@ -0,0 +1,79 @@
> +/** @file
> +
> + Unified linker script for GCC based builds
> +
> + Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +SECTIONS {
> +
> + /*
> + * The PE/COFF binary consists of DOS and PE/COFF headers, and a sequence of
> + * section headers adding up to PECOFF_HEADER_SIZE bytes (which differs
> + * between 32-bit and 64-bit builds). The actual start of the .text section
> + * will be rounded up based on its actual alignment.
> + */
> + . = PECOFF_HEADER_SIZE;
> +
> + .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> + *(.text .text.* .stub .gnu.linkonce.t.*)
> + *(.rodata .rodata.* .gnu.linkonce.r.*)
> + *(.got .got.*)
> +
> + /*
> + * The contents of AutoGen.c files are mostly constant from the POV of the
> + * program, but most of it ends up in .data or .bss by default since few of
> + * the variable definitions that get emitted are declared as CONST.
> + * Unfortunately, we cannot pull it into the .text section entirely, since
> + * patchable PCDs are also emitted here, but we can at least move all of the
> + * emitted GUIDs here.
> + */
> + *:AutoGen.obj(.data.g*Guid)
> + }
> +
> + /*
> + * The alignment of the .data section should be less than or equal to the
> + * alignment of the .text section. This ensures that the relative offset
> + * between these sections is the same in the ELF and the PE/COFF versions of
> + * this binary.
> + */
> + .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> + *(.data .data.* .gnu.linkonce.d.*)
> + *(.bss .bss.*)
> + }
> +
> + .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {
> + KEEP (*(.eh_frame))
> + }
> +
> + .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {
> + *(.rela .rela.*)
> + }
> +
> + .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> + KEEP (*(.hii))
> + }
> +
> + /*
> + * Retain the GNU build id but in a non-allocatable section so GenFw
> + * does not copy it into the PE/COFF image.
> + */
> + .build-id (INFO) : { *(.note.gnu.build-id) }
> +
> + /DISCARD/ : {
> + *(.note.GNU-stack)
> + *(.gnu_debuglink)
> + *(.interp)
> + *(.dynsym)
> + *(.dynstr)
> + *(.dynamic)
> + *(.hash .gnu.hash)
> + *(.comment)
> + *(COMMON)
> + }
> +}
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 77+ messages in thread* Re: [edk2-staging/RISC-V-V2 PATCH v3 25/39] BaseTools/Scripts
2019-11-21 16:56 ` Leif Lindholm
@ 2019-11-22 3:49 ` Abner Chang
0 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-11-22 3:49 UTC (permalink / raw)
To: Leif Lindholm; +Cc: devel@edk2.groups.io, Bob Feng, Liming Gao, Chen, Gilbert
Yes. GccBaseRiscV has been killed. No more. ;)
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Friday, November 22, 2019 12:57 AM
> To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Cc: devel@edk2.groups.io; Bob Feng <bob.c.feng@intel.com>; Liming Gao
> <liming.gao@intel.com>; Chen, Gilbert <gilbert.chen@hpe.com>
> Subject: Re: [edk2-staging/RISC-V-V2 PATCH v3 25/39] BaseTools/Scripts
>
> On Mon, Oct 28, 2019 at 09:59:03 +0800, Abner Chang wrote:
> > Add RISC-V specific LD scripts. ."rela(INFO)" in the latest
> > GccBase.lds causes PE32 relocation error.
> > This is the temporaty solution untill we find the root casue.
>
> And it can go now, right?
>
> /
> Leif
>
> > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> >
> > Cc: Bob Feng <bob.c.feng@intel.com>
> > Cc: Liming Gao <liming.gao@intel.com>
> > Cc: Leif Lindholm <leif.lindholm@linaro.org>
> > Cc: Gilbert Chen <gilbert.chen@hpe.com>
> > ---
> > BaseTools/Scripts/GccBaseRiscV.lds | 79
> > ++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 79 insertions(+)
> > create mode 100644 BaseTools/Scripts/GccBaseRiscV.lds
> >
> > diff --git a/BaseTools/Scripts/GccBaseRiscV.lds
> > b/BaseTools/Scripts/GccBaseRiscV.lds
> > new file mode 100644
> > index 0000000..91937aa
> > --- /dev/null
> > +++ b/BaseTools/Scripts/GccBaseRiscV.lds
> > @@ -0,0 +1,79 @@
> > +/** @file
> > +
> > + Unified linker script for GCC based builds
> > +
> > + Copyright (c) 2010 - 2015, Intel Corporation. All rights
> > + reserved.<BR> Copyright (c) 2015, Linaro Ltd. All rights
> > + reserved.<BR> Copyright (c) 2019, Hewlett Packard Enterprise
> > + Development LP. All rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +SECTIONS {
> > +
> > + /*
> > + * The PE/COFF binary consists of DOS and PE/COFF headers, and a
> sequence of
> > + * section headers adding up to PECOFF_HEADER_SIZE bytes (which
> differs
> > + * between 32-bit and 64-bit builds). The actual start of the .text section
> > + * will be rounded up based on its actual alignment.
> > + */
> > + . = PECOFF_HEADER_SIZE;
> > +
> > + .text : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> > + *(.text .text.* .stub .gnu.linkonce.t.*)
> > + *(.rodata .rodata.* .gnu.linkonce.r.*)
> > + *(.got .got.*)
> > +
> > + /*
> > + * The contents of AutoGen.c files are mostly constant from the POV of
> the
> > + * program, but most of it ends up in .data or .bss by default since few
> of
> > + * the variable definitions that get emitted are declared as CONST.
> > + * Unfortunately, we cannot pull it into the .text section entirely, since
> > + * patchable PCDs are also emitted here, but we can at least move all of
> the
> > + * emitted GUIDs here.
> > + */
> > + *:AutoGen.obj(.data.g*Guid)
> > + }
> > +
> > + /*
> > + * The alignment of the .data section should be less than or equal to the
> > + * alignment of the .text section. This ensures that the relative offset
> > + * between these sections is the same in the ELF and the PE/COFF
> versions of
> > + * this binary.
> > + */
> > + .data ALIGN(ALIGNOF(.text)) : ALIGN(CONSTANT(COMMONPAGESIZE))
> {
> > + *(.data .data.* .gnu.linkonce.d.*)
> > + *(.bss .bss.*)
> > + }
> > +
> > + .eh_frame ALIGN(CONSTANT(COMMONPAGESIZE)) : {
> > + KEEP (*(.eh_frame))
> > + }
> > +
> > + .rela ALIGN(CONSTANT(COMMONPAGESIZE)) : {
> > + *(.rela .rela.*)
> > + }
> > +
> > + .hii : ALIGN(CONSTANT(COMMONPAGESIZE)) {
> > + KEEP (*(.hii))
> > + }
> > +
> > + /*
> > + * Retain the GNU build id but in a non-allocatable section so GenFw
> > + * does not copy it into the PE/COFF image.
> > + */
> > + .build-id (INFO) : { *(.note.gnu.build-id) }
> > +
> > + /DISCARD/ : {
> > + *(.note.GNU-stack)
> > + *(.gnu_debuglink)
> > + *(.interp)
> > + *(.dynsym)
> > + *(.dynstr)
> > + *(.dynamic)
> > + *(.hash .gnu.hash)
> > + *(.comment)
> > + *(COMMON)
> > + }
> > +}
> > --
> > 2.7.4
> >
^ permalink raw reply [flat|nested] 77+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v3 26/39] RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms.
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (24 preceding siblings ...)
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 25/39] BaseTools/Scripts Abner Chang
@ 2019-10-28 1:59 ` Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 27/39] RiscVPkg/RiscVOpensbLlib: Add submodule opensbi Abner Chang
` (12 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:59 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
RISC-V generic SMBIOS DXE driver for building up SMBIOS type 4, type 7
and type 44 records.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
RiscVPkg/RiscVPkg.dec | 6 +
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 55 ++++
RiscVPkg/Include/ProcessorSpecificHobData.h | 97 ++++++
RiscVPkg/Include/SmbiosProcessorSpecificData.h | 57 ++++
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h | 23 ++
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c | 339 +++++++++++++++++++++
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni | 12 +
| 13 +
8 files changed, 602 insertions(+)
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
create mode 100644 RiscVPkg/Include/ProcessorSpecificHobData.h
create mode 100644 RiscVPkg/Include/SmbiosProcessorSpecificData.h
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
diff --git a/RiscVPkg/RiscVPkg.dec b/RiscVPkg/RiscVPkg.dec
index 3542185..2314698 100644
--- a/RiscVPkg/RiscVPkg.dec
+++ b/RiscVPkg/RiscVPkg.dec
@@ -23,6 +23,12 @@
gUefiRiscVPkgTokenSpaceGuid = { 0x4261e9c8, 0x52c0, 0x4b34, { 0x85, 0x3d, 0x48, 0x46, 0xea, 0xd3, 0xb7, 0x2c}}
[PcdsFixedAtBuild]
+ # Processor Specific Data GUID HOB GUID
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid|{0x20, 0x72, 0xD5, 0x2F, 0xCF, 0x3C, 0x4C, 0xBC, 0xB1, 0x65, 0x94, 0x90, 0xDC, 0xF2, 0xFA, 0x93}|VOID*|0x00001000
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid|{0x0F, 0x34, 0x00, 0x92, 0x04, 0x12, 0x45, 0x4A, 0x9C, 0x11, 0xB8, 0x8B, 0xDF, 0xC6, 0xFA, 0x6F}|VOID*|0x00001001
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid|{0x5B, 0x36, 0xEA, 0x23, 0x79, 0x6D, 0x4F, 0xCF, 0x9C, 0x22, 0x25, 0xC0, 0x89, 0x8C, 0x25, 0xB9}|VOID*|0x00001002
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid|{0xBF, 0xB4, 0x6D, 0x1B, 0x7E, 0x10, 0x47, 0x44, 0xB8, 0xBD, 0xFF, 0x1E, 0xDD, 0xDF, 0x71, 0x65}|VOID*|0x00001003
+
#
# 1000000000
# PcdRiscVMachineTimerTickInNanoSecond = ---------------------------------------
diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
new file mode 100644
index 0000000..7a3c517
--- /dev/null
+++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
@@ -0,0 +1,55 @@
+## @file
+# RISC-V SMBIOS DXE module.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVSmbiosDxe
+ MODULE_UNI_FILE = RiscVSmbiosDxe.uni
+ FILE_GUID = 5FC01647-AADD-42E1-AD99-DF4CB89F5A92
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = RiscVSmbiosBuilderEntry
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ HobLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Sources]
+ RiscVSmbiosDxe.c
+ RiscVSmbiosDxe.h
+
+[Protocols]
+ gEfiSmbiosProtocolGuid # Consumed
+
+[Guids]
+
+
+[Pcd]
+
+[FixedPcd]
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid
+ gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid
+
+[Depex]
+ gEfiSmbiosProtocolGuid
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ RiscVSmbiosDxeExtra.uni
diff --git a/RiscVPkg/Include/ProcessorSpecificHobData.h b/RiscVPkg/Include/ProcessorSpecificHobData.h
new file mode 100644
index 0000000..c19f355
--- /dev/null
+++ b/RiscVPkg/Include/ProcessorSpecificHobData.h
@@ -0,0 +1,97 @@
+/** @file
+ Definition of Processor Specific Data HOB.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_
+#define RISC_V_PROCESSOR_SPECIFIC_HOB_DATA_H_
+
+#include <Uefi.h>
+#include <IndustryStandard/SmBios.h>
+#include <SmbiosProcessorSpecificData.h>
+
+#define TO_BE_FILLED 0
+#define TO_BE_FILLED_BY_VENDOR 0
+#define TO_BE_FILLED_BY_RISC_V_SMBIOS_DXE_DRIVER 0
+#define TO_BE_FILLED_BY_CODE 0
+
+#pragma pack(1)
+
+///
+/// RISC-V processor specific data HOB
+///
+typedef struct {
+ EFI_GUID ParentPrcessorGuid;
+ UINTN ParentProcessorUid;
+ EFI_GUID CoreGuid;
+ VOID *Context; // The additional information of this core which
+ // built in PEI phase and carried to DXE phase.
+ // The content is pocessor or platform specific.
+ SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;
+} RISC_V_PROCESSOR_SPECIFIC_HOB_DATA;
+
+///
+/// RISC-V SMBIOS type 4 (Processor) GUID data HOB
+///
+typedef struct {
+ EFI_GUID PrcessorGuid;
+ UINTN ProcessorUid;
+ SMBIOS_TABLE_TYPE4 SmbiosType4Processor;
+ UINT16 EndingZero;
+} RISC_V_PROCESSOR_TYPE4_HOB_DATA;
+
+#define RISC_V_CACHE_INFO_NOT_PROVIDED 0xFFFF
+
+#define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK 0x7
+ #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1 0x01
+ #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 0x02
+ #define RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3 0x03
+
+#define RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION 3
+#define RISC_V_CACHE_CONFIGURATION_SOCKET_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_SOCKET_SOCKETED (0x1 << RISC_V_CACHE_CONFIGURATION_SOCKET_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION 5
+#define RISC_V_CACHE_CONFIGURATION_LOCATION_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL (0x0 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL (0x1 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_LOCATION_RESERVED (0x2 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_LOCATION_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_LOCATION_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION 7
+#define RISC_V_CACHE_CONFIGURATION_ENABLE_MASK (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_ENABLED (0x1 << RISC_V_CACHE_CONFIGURATION_ENABLE_BIT_POSITION)
+
+#define RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION 8
+#define RISC_V_CACHE_CONFIGURATION_MODE_MASK (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_MODE_WT (0x0 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_MODE_WB (0x1 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_MODE_VARIES (0x2 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+ #define RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN (0x3 << RISC_V_CACHE_CONFIGURATION_MODE_BIT_POSITION)
+///
+/// RISC-V SMBIOS type 7 (Cache) GUID data HOB
+///
+typedef struct {
+ EFI_GUID PrcessorGuid;
+ UINTN ProcessorUid;
+ SMBIOS_TABLE_TYPE7 SmbiosType7Cache;
+ UINT16 EndingZero;
+} RISC_V_PROCESSOR_TYPE7_HOB_DATA;
+
+///
+/// RISC-V SMBIOS type 7 (Cache) GUID data HOB
+///
+typedef struct {
+ RISC_V_PROCESSOR_TYPE4_HOB_DATA *Processor;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1InstCache;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1DataCache;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2Cache;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *L3Cache;
+} RISC_V_PROCESSOR_SMBIOS_HOB_DATA;
+
+#pragma pack()
+
+#endif
diff --git a/RiscVPkg/Include/SmbiosProcessorSpecificData.h b/RiscVPkg/Include/SmbiosProcessorSpecificData.h
new file mode 100644
index 0000000..81e48cd
--- /dev/null
+++ b/RiscVPkg/Include/SmbiosProcessorSpecificData.h
@@ -0,0 +1,57 @@
+/** @file
+ Industry Standard Definitions of RISC-V Processor Specific data defined in
+ below link for complaiant with SMBIOS Table Specification v3.3.0.
+ https://github.com/riscv/riscv-smbios
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_
+#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_H_
+
+#include <IndustryStandard/SmBios.h>
+#include <RiscVImpl.h>
+
+#pragma pack(1)
+
+typedef enum{
+ RegisterUnsupported = 0x00,
+ RegisterLen32 = 0x01,
+ RegisterLen64 = 0x02,
+ RegisterLen128 = 0x03
+} RISC_V_REGISTER_LENGTH;
+
+#define SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION 0x100
+
+#define SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED (0x01 << 0)
+#define SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED (0x01 << 2)
+#define SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED (0x01 << 3)
+#define SMBIOS_RISC_V_PSD_DEBUG_MODE_SUPPORTED (0x01 << 7)
+
+///
+/// RISC-V processor specific data for SMBIOS type 44
+///
+typedef struct {
+ UINT16 Revision;
+ UINT8 Length;
+ RISCV_UINT128 HartId;
+ UINT8 BootHartId;
+ RISCV_UINT128 MachineVendorId;
+ RISCV_UINT128 MachineArchId;
+ RISCV_UINT128 MachineImplId;
+ UINT32 InstSetSupported;
+ UINT8 PrivilegeModeSupported;
+ RISCV_UINT128 MModeExcepDelegation;
+ RISCV_UINT128 MModeInterruptDelegation;
+ UINT8 HartXlen;
+ UINT8 MachineModeXlen;
+ UINT8 Reserved;
+ UINT8 SupervisorModeXlen;
+ UINT8 UserModeXlen;
+} SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA;
+
+#pragma pack()
+#endif
+
diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
new file mode 100644
index 0000000..1072877
--- /dev/null
+++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h
@@ -0,0 +1,23 @@
+/** @file
+ RISC-V SMBIOS Builder DXE module header file.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef RISC_V_SMBIOS_DXE_H_
+#define RISC_V_SMBIOS_DXE_H_
+
+#include <PiDxe.h>
+#include <Protocol/Smbios.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <ProcessorSpecificHobData.h>
+#include <SmbiosProcessorSpecificData.h>
+#endif
+
diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
new file mode 100644
index 0000000..90cbeea
--- /dev/null
+++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c
@@ -0,0 +1,339 @@
+/** @file
+ RISC-V generic SMBIOS DXE driver to build up SMBIOS type 4, type 7 and type 44 records.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "RiscVSmbiosDxe.h"
+
+#define RISCV_SMBIOS_DEBUG_INFO 1
+
+STATIC EFI_SMBIOS_PROTOCOL *mSmbios;
+
+/**
+ This function builds SMBIOS type 7 record according to
+ the given RISC_V_PROCESSOR_TYPE7_HOB_DATA.
+
+ @param Type4HobData Pointer to RISC_V_PROCESSOR_TYPE4_HOB_DATA
+ @param Type7DataHob Pointer to RISC_V_PROCESSOR_TYPE7_HOB_DATA
+ @param SmbiosHandle Pointer to SMBIOS_HANDLE
+
+ @retval EFI_STATUS
+
+**/
+STATIC
+EFI_STATUS
+BuildSmbiosType7 (
+ IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,
+ IN RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7DataHob,
+ OUT SMBIOS_HANDLE *SmbiosHandle
+)
+{
+ EFI_STATUS Status;
+ SMBIOS_HANDLE Handle;
+
+ if (!CompareGuid (&Type4HobData->PrcessorGuid, &Type7DataHob->PrcessorGuid) ||
+ Type4HobData->ProcessorUid != Type7DataHob->ProcessorUid) {
+ return EFI_INVALID_PARAMETER;
+ }
+ Handle = SMBIOS_HANDLE_PI_RESERVED;
+ Type7DataHob->SmbiosType7Cache.Hdr.Type = SMBIOS_TYPE_CACHE_INFORMATION;
+ Type7DataHob->SmbiosType7Cache.Hdr.Length = sizeof(SMBIOS_TABLE_TYPE7);
+ Type7DataHob->SmbiosType7Cache.Hdr.Handle = 0;
+ Type7DataHob->EndingZero = 0;
+ Status = mSmbios->Add (mSmbios, NULL, &Handle, &Type7DataHob->SmbiosType7Cache.Hdr);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Fail to add SMBIOS Type 7\n", __FUNCTION__));
+ return Status;
+ }
+ DEBUG ((DEBUG_INFO, "SMBIOS Type 7 was added. SMBIOS Handle: 0x%x\n", Handle));
+#if RISCV_SMBIOS_DEBUG_INFO
+ DEBUG ((DEBUG_INFO, " Cache belone to processor GUID: %g\n", &Type7DataHob->PrcessorGuid));
+ DEBUG ((DEBUG_INFO, " Cache belone processor UID: %d\n", Type7DataHob->ProcessorUid));
+ DEBUG ((DEBUG_INFO, " ==============================\n"));
+ DEBUG ((DEBUG_INFO, " Socket Designation: %d\n", Type7DataHob->SmbiosType7Cache.SocketDesignation));
+ DEBUG ((DEBUG_INFO, " Cache Configuration: 0x%x\n", Type7DataHob->SmbiosType7Cache.CacheConfiguration));
+ DEBUG ((DEBUG_INFO, " Maximum Cache Size: 0x%x\n", Type7DataHob->SmbiosType7Cache.MaximumCacheSize));
+ DEBUG ((DEBUG_INFO, " Installed Size: 0x%x\n", Type7DataHob->SmbiosType7Cache.InstalledSize));
+ DEBUG ((DEBUG_INFO, " Supported SRAM Type: 0x%x\n", Type7DataHob->SmbiosType7Cache.SupportedSRAMType));
+ DEBUG ((DEBUG_INFO, " Current SRAMT ype: 0x%x\n", Type7DataHob->SmbiosType7Cache.CurrentSRAMType));
+ DEBUG ((DEBUG_INFO, " Cache Speed: 0x%x\n", Type7DataHob->SmbiosType7Cache.CacheSpeed));
+ DEBUG ((DEBUG_INFO, " Error Correction Type: 0x%x\n", Type7DataHob->SmbiosType7Cache.ErrorCorrectionType));
+ DEBUG ((DEBUG_INFO, " System Cache Type: 0x%x\n", Type7DataHob->SmbiosType7Cache.SystemCacheType));
+ DEBUG ((DEBUG_INFO, " Associativity: 0x%x\n", Type7DataHob->SmbiosType7Cache.Associativity));
+#endif
+
+ *SmbiosHandle = Handle;
+ return EFI_SUCCESS;
+}
+
+/**
+ This function builds SMBIOS type 4 record according to
+ the given RISC_V_PROCESSOR_TYPE4_HOB_DATA.
+
+ @param Type4HobData Pointer to RISC_V_PROCESSOR_TYPE4_HOB_DATA
+ @param SmbiosHandle Pointer to SMBIOS_HANDLE
+
+ @retval EFI_STATUS
+
+**/
+STATIC
+EFI_STATUS
+BuildSmbiosType4 (
+ IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,
+ OUT SMBIOS_HANDLE *SmbiosHandle
+ )
+{
+ EFI_HOB_GUID_TYPE *GuidHob;
+ RISC_V_PROCESSOR_TYPE7_HOB_DATA *Type7HobData;
+ SMBIOS_HANDLE Cache;
+ SMBIOS_HANDLE Processor;
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "Building Type 4.\n"));
+ DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Type4HobData->PrcessorGuid));
+ DEBUG ((DEBUG_INFO, " Processor UUID: %d\n", Type4HobData->ProcessorUid));
+
+ Type4HobData->SmbiosType4Processor.L1CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
+ Type4HobData->SmbiosType4Processor.L2CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
+ Type4HobData->SmbiosType4Processor.L3CacheHandle = RISC_V_CACHE_INFO_NOT_PROVIDED;
+ GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType7GuidHobGuid));
+ if (GuidHob == NULL) {
+ DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS Type7 data HOB found.\n"));
+ return EFI_NOT_FOUND;
+ }
+ //
+ // Go through each RISC_V_PROCESSOR_TYPE4_HOB_DATA for multiple processors.
+ //
+ do {
+ Type7HobData = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)GET_GUID_HOB_DATA (GuidHob);
+ Status = BuildSmbiosType7 (Type4HobData, Type7HobData, &Cache);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
+ RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_1) {
+ Type4HobData->SmbiosType4Processor.L1CacheHandle = Cache;
+ } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
+ RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2) {
+ Type4HobData->SmbiosType4Processor.L2CacheHandle = Cache;
+ } else if ((Type7HobData->SmbiosType7Cache.SystemCacheType & RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_MASK) ==
+ RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_3) {
+ Type4HobData->SmbiosType4Processor.L3CacheHandle = Cache;
+ } else {
+ DEBUG ((DEBUG_ERROR, "Improper cache level of SMBIOS handle %d\n", Cache));
+ }
+ GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType7GuidHobGuid), GET_NEXT_HOB(GuidHob));
+ } while (GuidHob != NULL);
+
+ //
+ // Build SMBIOS Type 4 record
+ //
+ Processor = SMBIOS_HANDLE_PI_RESERVED;
+ Type4HobData->SmbiosType4Processor.Hdr.Type = SMBIOS_TYPE_PROCESSOR_INFORMATION;
+ Type4HobData->SmbiosType4Processor.Hdr.Length = sizeof(SMBIOS_TABLE_TYPE4);
+ Type4HobData->SmbiosType4Processor.Hdr.Handle = 0;
+ Type4HobData->EndingZero = 0;
+ Status = mSmbios->Add (mSmbios, NULL, &Processor, &Type4HobData->SmbiosType4Processor.Hdr);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "Fail to add SMBIOS Type 4\n"));
+ return Status;
+ }
+ DEBUG ((DEBUG_INFO, "SMBIOS Type 4 was added. SMBIOS Handle: 0x%x\n", Processor));
+#if RISCV_SMBIOS_DEBUG_INFO
+ DEBUG ((DEBUG_INFO, " Socket StringID: %d\n", Type4HobData->SmbiosType4Processor.Socket));
+ DEBUG ((DEBUG_INFO, " Processor Type: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorType));
+ DEBUG ((DEBUG_INFO, " Processor Family: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorFamily));
+ DEBUG ((DEBUG_INFO, " Processor Manufacture StringID: %d\n", Type4HobData->SmbiosType4Processor.ProcessorManufacture));
+ DEBUG ((DEBUG_INFO, " Processor Id: 0x%x:0x%x\n", \
+ Type4HobData->SmbiosType4Processor.ProcessorId.Signature, Type4HobData->SmbiosType4Processor.ProcessorId.FeatureFlags));
+ DEBUG ((DEBUG_INFO, " Processor Version StringID: %d\n", Type4HobData->SmbiosType4Processor.ProcessorVersion));
+ DEBUG ((DEBUG_INFO, " Voltage: 0x%x\n", Type4HobData->SmbiosType4Processor.Voltage));
+ DEBUG ((DEBUG_INFO, " External Clock: 0x%x\n", Type4HobData->SmbiosType4Processor.ExternalClock));
+ DEBUG ((DEBUG_INFO, " Max Speed: 0x%x\n", Type4HobData->SmbiosType4Processor.MaxSpeed));
+ DEBUG ((DEBUG_INFO, " Current Speed: 0x%x\n", Type4HobData->SmbiosType4Processor.CurrentSpeed));
+ DEBUG ((DEBUG_INFO, " Status: 0x%x\n", Type4HobData->SmbiosType4Processor.Status));
+ DEBUG ((DEBUG_INFO, " ProcessorUpgrade: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorUpgrade));
+ DEBUG ((DEBUG_INFO, " L1 Cache Handle: 0x%x\n", Type4HobData->SmbiosType4Processor.L1CacheHandle));
+ DEBUG ((DEBUG_INFO, " L2 Cache Handle: 0x%x\n",Type4HobData->SmbiosType4Processor.L2CacheHandle));
+ DEBUG ((DEBUG_INFO, " L3 Cache Handle: 0x%x\n", Type4HobData->SmbiosType4Processor.L3CacheHandle));
+ DEBUG ((DEBUG_INFO, " Serial Number StringID: %d\n", Type4HobData->SmbiosType4Processor.SerialNumber));
+ DEBUG ((DEBUG_INFO, " Asset Tag StringID: %d\n", Type4HobData->SmbiosType4Processor.AssetTag));
+ DEBUG ((DEBUG_INFO, " Part Number StringID: %d\n", Type4HobData->SmbiosType4Processor.PartNumber));
+ DEBUG ((DEBUG_INFO, " Core Count: %d\n", Type4HobData->SmbiosType4Processor.CoreCount));
+ DEBUG ((DEBUG_INFO, " Enabled CoreCount: %d\n", Type4HobData->SmbiosType4Processor.EnabledCoreCount));
+ DEBUG ((DEBUG_INFO, " Thread Count: %d\n", Type4HobData->SmbiosType4Processor.ThreadCount));
+ DEBUG ((DEBUG_INFO, " Processor Characteristics: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorCharacteristics));
+ DEBUG ((DEBUG_INFO, " Processor Family2: 0x%x\n", Type4HobData->SmbiosType4Processor.ProcessorFamily2));
+ DEBUG ((DEBUG_INFO, " Core Count 2: %d\n", Type4HobData->SmbiosType4Processor.CoreCount2));
+ DEBUG ((DEBUG_INFO, " Enabled CoreCount : %d\n", Type4HobData->SmbiosType4Processor.EnabledCoreCount2));
+ DEBUG ((DEBUG_INFO, " Thread Count 2: %d\n", Type4HobData->SmbiosType4Processor.ThreadCount2));
+#endif
+
+ *SmbiosHandle = Processor;
+ return EFI_SUCCESS;
+}
+
+/**
+ This function builds SMBIOS type 44 record according..
+
+ @param Type4HobData Pointer to RISC_V_PROCESSOR_TYPE4_HOB_DATA
+ @param Type4Handle SMBIOS handle of type 4
+
+ @retval EFI_STATUS
+
+**/
+EFI_STATUS
+BuildSmbiosType44 (
+ IN RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData,
+ IN SMBIOS_HANDLE Type4Handle
+ )
+{
+ EFI_HOB_GUID_TYPE *GuidHob;
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificData;
+ SMBIOS_HANDLE RiscVType44;
+ SMBIOS_TABLE_TYPE44 *Type44Ptr;
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "Building Type 44 for...\n"));
+#if RISCV_SMBIOS_DEBUG_INFO
+ DEBUG ((DEBUG_INFO, " Processor GUID: %g\n", &Type4HobData->PrcessorGuid));
+ DEBUG ((DEBUG_INFO, " Processor UUID: %d\n", Type4HobData->ProcessorUid));
+#endif
+
+ GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid));
+ if (GuidHob == NULL) {
+ DEBUG ((DEBUG_ERROR, "No RISC_V_PROCESSOR_SPECIFIC_HOB_DATA found.\n"));
+ return EFI_NOT_FOUND;
+ }
+ //
+ // Go through each RISC_V_PROCESSOR_SPECIFIC_HOB_DATA for multiple cores.
+ //
+ do {
+ ProcessorSpecificData = (RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *)GET_GUID_HOB_DATA (GuidHob);
+ if (!CompareGuid (&ProcessorSpecificData->ParentPrcessorGuid, &Type4HobData->PrcessorGuid) ||
+ ProcessorSpecificData->ParentProcessorUid != Type4HobData->ProcessorUid) {
+ GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB(GuidHob));
+ if (GuidHob == NULL) {
+ break;
+ }
+ continue;
+ }
+
+#if RISCV_SMBIOS_DEBUG_INFO
+ DEBUG ((DEBUG_INFO, "================================\n"));
+ DEBUG ((DEBUG_INFO, "Core GUID: %g\n", &ProcessorSpecificData->CoreGuid));
+#endif
+
+ Type44Ptr = AllocateZeroPool(sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA) + 2); // Two ending zero.
+ if (Type44Ptr == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ Type44Ptr->Hdr.Type = SMBIOS_TYPE_PROCESSOR_ADDITIONAL_INFORMATION;
+ Type44Ptr->Hdr.Handle = 0;
+ Type44Ptr->Hdr.Length = sizeof(SMBIOS_TABLE_TYPE44) + sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
+ Type44Ptr->RefHandle = Type4Handle;
+ Type44Ptr->ProcessorSpecificBlock.Length = sizeof(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
+ Type44Ptr->ProcessorSpecificBlock.ProcessorArchType = Type4HobData->SmbiosType4Processor.ProcessorFamily2 -
+ ProcessorFamilyRiscvRV32 + \
+ ProcessorSpecificBlockArchTypeRiscVRV32;
+ CopyMem ((VOID *)(Type44Ptr + 1), (VOID *)&ProcessorSpecificData->ProcessorSpecificData, sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA));
+
+#if RISCV_SMBIOS_DEBUG_INFO
+ DEBUG ((DEBUG_INFO, "Core type: %d\n", Type44Ptr->ProcessorSpecificBlock.ProcessorArchType));
+ DEBUG ((DEBUG_INFO, " HartId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->HartId.Value64_L));
+ DEBUG ((DEBUG_INFO, " Is Boot Hart? = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->BootHartId));
+ DEBUG ((DEBUG_INFO, " PrivilegeModeSupported = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->PrivilegeModeSupported));
+ DEBUG ((DEBUG_INFO, " MModeExcepDelegation = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MModeExcepDelegation.Value64_L));
+ DEBUG ((DEBUG_INFO, " MModeInterruptDelegation = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MModeInterruptDelegation.Value64_L));
+ DEBUG ((DEBUG_INFO, " HartXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->HartXlen));
+ DEBUG ((DEBUG_INFO, " MachineModeXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineModeXlen));
+ DEBUG ((DEBUG_INFO, " SupervisorModeXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->SupervisorModeXlen));
+ DEBUG ((DEBUG_INFO, " UserModeXlen = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->UserModeXlen));
+ DEBUG ((DEBUG_INFO, " InstSetSupported = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->InstSetSupported));
+ DEBUG ((DEBUG_INFO, " MachineVendorId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineVendorId.Value64_L));
+ DEBUG ((DEBUG_INFO, " MachineArchId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineArchId.Value64_L));
+ DEBUG ((DEBUG_INFO, " MachineImplId = 0x%x\n", ((SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA *)(Type44Ptr + 1))->MachineImplId.Value64_L));
+#endif
+
+ //
+ // Add to SMBIOS table.
+ //
+ RiscVType44 = SMBIOS_HANDLE_PI_RESERVED;
+ Status = mSmbios->Add (mSmbios, NULL, &RiscVType44, &Type44Ptr->Hdr);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((DEBUG_ERROR, "Fail to add SMBIOS Type 44\n"));
+ return Status;
+ }
+ DEBUG ((DEBUG_INFO, "SMBIOS Type 44 was added. SMBIOS Handle: 0x%x\n", RiscVType44));
+
+ GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSpecificDataGuidHobGuid), GET_NEXT_HOB(GuidHob));
+ } while (GuidHob != NULL);
+ return EFI_SUCCESS;
+}
+
+/**
+ Entry point of RISC-V SMBIOS builder.
+
+ @param ImageHandle Image handle this driver.
+ @param SystemTable Pointer to the System Table.
+
+ @retval EFI_SUCCESS Thread can be successfully created
+ @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure
+ @retval EFI_DEVICE_ERROR Cannot create the thread
+
+**/
+EFI_STATUS
+EFIAPI
+RiscVSmbiosBuilderEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ RISC_V_PROCESSOR_TYPE4_HOB_DATA *Type4HobData;
+ SMBIOS_HANDLE Processor;
+
+ DEBUG ((DEBUG_INFO, "%a: entry\n", __FUNCTION__));
+
+ Status = gBS->LocateProtocol (
+ &gEfiSmbiosProtocolGuid,
+ NULL,
+ (VOID **)&mSmbios
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Locate SMBIOS Protocol fail\n"));
+ return Status;
+ }
+ GuidHob = (EFI_HOB_GUID_TYPE *)GetFirstGuidHob ((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType4GuidHobGuid));
+ if (GuidHob == NULL) {
+ DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS information found.\n"));
+ return EFI_NOT_FOUND;
+ }
+ Type4HobData = (RISC_V_PROCESSOR_TYPE4_HOB_DATA *)GET_GUID_HOB_DATA (GuidHob);
+ Status = EFI_NOT_FOUND;
+ //
+ // Go through each RISC_V_PROCESSOR_TYPE4_HOB_DATA for multiple processors.
+ //
+ do {
+ Status = BuildSmbiosType4 (Type4HobData, &Processor);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS type 4 created.\n"));
+ ASSERT (FALSE);
+ }
+ Status = BuildSmbiosType44 (Type4HobData, Processor);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "No RISC-V SMBIOS type 44 found.\n"));
+ ASSERT (FALSE);
+ }
+
+ GuidHob = GetNextGuidHob((EFI_GUID *)PcdGetPtr(PcdProcessorSmbiosType4GuidHobGuid), GET_NEXT_HOB(GuidHob));
+ } while (GuidHob != NULL);
+ DEBUG ((DEBUG_INFO, "%a: exit\n", __FUNCTION__));
+ return Status;
+}
+
diff --git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
new file mode 100644
index 0000000..1bffe09
--- /dev/null
+++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
@@ -0,0 +1,12 @@
+// /** @file
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_MODULE_ABSTRACT #language en-US "RISC-V Processor SMBIOS Builder"
+
+#string STR_MODULE_DESCRIPTION #language en-US "Build RISC-V Processor SMBIOS Type 4, 7, 44 records."
+
--git a/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
new file mode 100644
index 0000000..4b37ca2
--- /dev/null
+++ b/RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
@@ -0,0 +1,13 @@
+// /** @file
+// RISC-V SMBIOS Builder Localized Strings and Content
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME
+#language en-US
+"RISC-V SMBIOS Record Builder DXE Driver"
+
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 27/39] RiscVPkg/RiscVOpensbLlib: Add submodule opensbi
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (25 preceding siblings ...)
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 26/39] RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V platforms Abner Chang
@ 2019-10-28 1:59 ` Abner Chang
2019-11-21 17:00 ` Leif Lindholm
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 28/39] RiscVPlatformPkg/FirmwareContextProcessorSpecificLib:Add FirmwareContextProcessorSpecificLib module Abner Chang
` (11 subsequent siblings)
38 siblings, 1 reply; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:59 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=y, Size: 1680 bytes --]
Add submodule opensbi under RiscVPkg/Library/RiscVOpensbLlib.
The current supported opensbi version for RISC-V edk2 port
is tags/v0.5.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.gitmodules | 15 +++++++++------
RiscVPkg/Library/RiscVOpensbiLib/opensbi | 1 +
2 files changed, 10 insertions(+), 6 deletions(-)
create mode 160000 RiscVPkg/Library/RiscVOpensbiLib/opensbi
diff --git a/.gitmodules b/.gitmodules
index 508f0c1..d2d823a 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,6 +1,9 @@
-[submodule "CryptoPkg/Library/OpensslLib/openssl"]
- path = CryptoPkg/Library/OpensslLib/openssl
- url = https://github.com/openssl/openssl
-[submodule "SoftFloat"]
- path = ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
- url = https://github.com/ucb-bar/berkeley-softfloat-3.git
+[submodule "CryptoPkg/Library/OpensslLib/openssl"]
+ path = CryptoPkg/Library/OpensslLib/openssl
+ url = https://github.com/openssl/openssl
+[submodule "SoftFloat"]
+ path = ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
+ url = https://github.com/ucb-bar/berkeley-softfloat-3.git
+[submodule "RiscVPkg/Library/RiscVOpensbiLib/opensbi"]
+ path = RiscVPkg/Library/RiscVOpensbiLib/opensbi
+ url = https://github.com/riscv/opensbi.git
diff --git a/RiscVPkg/Library/RiscVOpensbiLib/opensbi b/RiscVPkg/Library/RiscVOpensbiLib/opensbi
new file mode 160000
index 0000000..be92da2
--- /dev/null
+++ b/RiscVPkg/Library/RiscVOpensbiLib/opensbi
@@ -0,0 +1 @@
+Subproject commit be92da280d87c38a2e0adc5d3f43bab7b5468f09
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* Re: [edk2-staging/RISC-V-V2 PATCH v3 27/39] RiscVPkg/RiscVOpensbLlib: Add submodule opensbi
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 27/39] RiscVPkg/RiscVOpensbLlib: Add submodule opensbi Abner Chang
@ 2019-11-21 17:00 ` Leif Lindholm
0 siblings, 0 replies; 77+ messages in thread
From: Leif Lindholm @ 2019-11-21 17:00 UTC (permalink / raw)
To: Abner Chang; +Cc: devel, Gilbert Chen
On Mon, Oct 28, 2019 at 09:59:05 +0800, Abner Chang wrote:
> Add submodule opensbi under RiscVPkg/Library/RiscVOpensbLlib.
OpensbiLib (fix typo). Also in subject line.
> The current supported opensbi version for RISC-V edk2 port
> is tags/v0.5.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Gilbert Chen <gilbert.chen@hpe.com>
> ---
> .gitmodules | 15 +++++++++------
> RiscVPkg/Library/RiscVOpensbiLib/opensbi | 1 +
> 2 files changed, 10 insertions(+), 6 deletions(-)
> create mode 160000 RiscVPkg/Library/RiscVOpensbiLib/opensbi
>
> diff --git a/.gitmodules b/.gitmodules
> index 508f0c1..d2d823a 100644
> --- a/.gitmodules
> +++ b/.gitmodules
> @@ -1,6 +1,9 @@
> -[submodule "CryptoPkg/Library/OpensslLib/openssl"]
> - path = CryptoPkg/Library/OpensslLib/openssl
> - url = https://github.com/openssl/openssl
> -[submodule "SoftFloat"]
> - path = ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
> - url = https://github.com/ucb-bar/berkeley-softfloat-3.git
> +[submodule "CryptoPkg/Library/OpensslLib/openssl"]
Urgh.
> + path = CryptoPkg/Library/OpensslLib/openssl
> + url = https://github.com/openssl/openssl
> +[submodule "SoftFloat"]
> + path = ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
> + url = https://github.com/ucb-bar/berkeley-softfloat-3.git
Make sure this patch *only* adds Opensbi, without modifying the
existing entries.
And please move this patch to before the first one that contains a
.inf making use of the source in this submodule.
/
Leif
> +[submodule "RiscVPkg/Library/RiscVOpensbiLib/opensbi"]
> + path = RiscVPkg/Library/RiscVOpensbiLib/opensbi
> + url = https://github.com/riscv/opensbi.git
> diff --git a/RiscVPkg/Library/RiscVOpensbiLib/opensbi b/RiscVPkg/Library/RiscVOpensbiLib/opensbi
> new file mode 160000
> index 0000000..be92da2
> --- /dev/null
> +++ b/RiscVPkg/Library/RiscVOpensbiLib/opensbi
> @@ -0,0 +1 @@
> +Subproject commit be92da280d87c38a2e0adc5d3f43bab7b5468f09
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 77+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v3 28/39] RiscVPlatformPkg/FirmwareContextProcessorSpecificLib:Add FirmwareContextProcessorSpecificLib module
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (26 preceding siblings ...)
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 27/39] RiscVPkg/RiscVOpensbLlib: Add submodule opensbi Abner Chang
@ 2019-10-28 1:59 ` Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 29/39] RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib Abner Chang
` (10 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:59 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
Add OpenSBI firmware context processor specific library which
provides interface to create processor specific firmware
context hob data.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../FirmwareContextProcessorSpecificLib.inf | 31 +++++++
.../Library/FirmwareContextProcessorSpecificLib.h | 42 ++++++++++
.../FirmwareContextProcessorSpecificLib.c | 94 ++++++++++++++++++++++
3 files changed, 167 insertions(+)
create mode 100644 RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
create mode 100644 RiscVPlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
create mode 100644 RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
diff --git a/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf b/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
new file mode 100644
index 0000000..8ea37ae
--- /dev/null
+++ b/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
@@ -0,0 +1,31 @@
+#/** @file
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = FirmwareContextProcessorSpecificLib
+ FILE_GUID = 8BEC9FD7-C554-403A-94F1-0EBBFD81A242
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = FirmwareContextProcessorSpecificLib
+
+[Sources.common]
+ FirmwareContextProcessorSpecificLib.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ PcdLib
+ MemoryAllocationLib
+ PrintLib
+
+
diff --git a/RiscVPlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h b/RiscVPlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
new file mode 100644
index 0000000..5fe99a4
--- /dev/null
+++ b/RiscVPlatformPkg/Include/Library/FirmwareContextProcessorSpecificLib.h
@@ -0,0 +1,42 @@
+/** @file
+ Firmware Context Processor-specific common library
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H
+#define FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H
+
+#include <PiPei.h>
+#include <sbi/SbiFirmwareContext.h>
+#include <ProcessorSpecificHobData.h>
+
+/**
+ Build up common firmware context processor-specific information
+
+ @param FirmwareContextHartSpecific Pointer to EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
+ @param ParentProcessorGuid Pointer to GUID of Processor which contains this core
+ @param ParentProcessorUid Unique ID of pysical processor which owns this core.
+ @param CoreGuid Pointer to GUID of core
+ @param HartId Hart ID of this core.
+ @param IsBootHart This is boot hart or not
+ @param ProcessorSpecDataHob Pointer to RISC_V_PROCESSOR_SPECIFIC_DATA_HOB
+
+ @return EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+CommonFirmwareContextHartSpecificInfo (
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific,
+ EFI_GUID *ParentProcessorGuid,
+ UINTN ParentProcessorUid,
+ EFI_GUID *CoreGuid,
+ UINTN HartId,
+ BOOLEAN IsBootHart,
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecDataHob
+ );
+
+#endif
diff --git a/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c b/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
new file mode 100644
index 0000000..21b26be
--- /dev/null
+++ b/RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
@@ -0,0 +1,94 @@
+/**@file
+ Common library to build upfirmware context processor-specific information
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include <PiPei.h>
+
+//
+// The Library classes this module consumes
+//
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+#include <ProcessorSpecificHobData.h>
+#include <RiscVImpl.h>
+#include <sbi/sbi.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/SbiFirmwareContext.h>
+
+/**
+ Build up common firmware context processor-specific information
+
+ @param FirmwareContextHartSpecific Pointer to EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
+ @param ParentProcessorGuid Pointer to GUID of Processor which contains this core
+ @param ParentProcessorUid Unique ID of pysical processor which owns this core.
+ @param CoreGuid Pointer to GUID of core
+ @param HartId Hart ID of this core.
+ @param IsBootHart This is boot hart or not
+ @param ProcessorSpecificDataHob Pointer to RISC_V_PROCESSOR_SPECIFIC_DATA_HOB
+
+ @return EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+CommonFirmwareContextHartSpecificInfo (
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific,
+ EFI_GUID *ParentProcessorGuid,
+ UINTN ParentProcessorUid,
+ EFI_GUID *CoreGuid,
+ UINTN HartId,
+ BOOLEAN IsBootHart,
+ RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *ProcessorSpecificDataHob
+ )
+{
+ //
+ // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
+ //
+ CopyGuid (&ProcessorSpecificDataHob->ParentPrcessorGuid, ParentProcessorGuid);
+ ProcessorSpecificDataHob->ParentProcessorUid = ParentProcessorUid;
+ CopyGuid (&ProcessorSpecificDataHob->CoreGuid, CoreGuid);
+ ProcessorSpecificDataHob->Context = NULL;
+ ProcessorSpecificDataHob->ProcessorSpecificData.Revision =
+ SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION;
+ ProcessorSpecificDataHob->ProcessorSpecificData.Length =
+ sizeof (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
+ ProcessorSpecificDataHob->ProcessorSpecificData.HartId.Value64_L = (UINT64)HartId;
+ ProcessorSpecificDataHob->ProcessorSpecificData.HartId.Value64_H = 0;
+ ProcessorSpecificDataHob->ProcessorSpecificData.BootHartId = (UINT8)IsBootHart;
+ ProcessorSpecificDataHob->ProcessorSpecificData.InstSetSupported =
+ FirmwareContextHartSpecific->IsaExtensionSupported;
+ ProcessorSpecificDataHob->ProcessorSpecificData.PrivilegeModeSupported =
+ SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED;
+ if ((ProcessorSpecificDataHob->ProcessorSpecificData.InstSetSupported &
+ RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED) != 0) {
+ ProcessorSpecificDataHob->ProcessorSpecificData.PrivilegeModeSupported |=
+ SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED;
+ }
+ if ((ProcessorSpecificDataHob->ProcessorSpecificData.InstSetSupported &
+ RISC_V_ISA_USER_MODE_IMPLEMENTED) != 0) {
+ ProcessorSpecificDataHob->ProcessorSpecificData.PrivilegeModeSupported |=
+ SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED;
+ }
+ ProcessorSpecificDataHob->ProcessorSpecificData.MachineVendorId.Value64_L =
+ FirmwareContextHartSpecific->MachineVendorId.Value64_L;
+ ProcessorSpecificDataHob->ProcessorSpecificData.MachineVendorId.Value64_H =
+ FirmwareContextHartSpecific->MachineVendorId.Value64_H;
+ ProcessorSpecificDataHob->ProcessorSpecificData.MachineArchId.Value64_L =
+ FirmwareContextHartSpecific->MachineArchId.Value64_L;
+ ProcessorSpecificDataHob->ProcessorSpecificData.MachineArchId.Value64_H =
+ FirmwareContextHartSpecific->MachineArchId.Value64_H;
+ ProcessorSpecificDataHob->ProcessorSpecificData.MachineImplId.Value64_L =
+ FirmwareContextHartSpecific->MachineImplId.Value64_L;
+ ProcessorSpecificDataHob->ProcessorSpecificData.MachineImplId.Value64_H =
+ FirmwareContextHartSpecific->MachineImplId.Value64_H;
+ return EFI_SUCCESS;
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 29/39] RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib.
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (27 preceding siblings ...)
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 28/39] RiscVPlatformPkg/FirmwareContextProcessorSpecificLib:Add FirmwareContextProcessorSpecificLib module Abner Chang
@ 2019-10-28 1:59 ` Abner Chang
2019-11-21 17:02 ` Leif Lindholm
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 30/39] RiscVPlatformPkg/OpensbiPlatformLibNull: NULL instance of RiscVOpensbiPlatformLib Abner Chang
` (9 subsequent siblings)
38 siblings, 1 reply; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:59 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
Null instance of Real Time Clock lib for RISC-V platform.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../RealTimeClockLibNull/RealTimeClockLibNull.inf | 30 +++
.../RealTimeClockLibNull/RealTimeClockLibNull.c | 204 +++++++++++++++++++++
2 files changed, 234 insertions(+)
create mode 100644 RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.inf
create mode 100644 RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.c
diff --git a/RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.inf b/RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.inf
new file mode 100644
index 0000000..b9bffa1
--- /dev/null
+++ b/RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.inf
@@ -0,0 +1,30 @@
+#/** @file
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RealTimeClockLibNull
+ FILE_GUID = BFC3E25A-8AD0-4201-8A75-F00DE7964370
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RealTimeClockLib
+
+[Sources.common]
+ RealTimeClockLibNull.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ UefiLib
+ DebugLib
+# Use EFiAtRuntime to check stage
+ UefiRuntimeLib
+
+[Pcd]
+
diff --git a/RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.c b/RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.c
new file mode 100644
index 0000000..904e7e7
--- /dev/null
+++ b/RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.c
@@ -0,0 +1,204 @@
+/** @file
+ EFI RealTimeClock NULL library
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+// Use EfiAtRuntime to check stage
+#include <Library/UefiRuntimeLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Protocol/RealTimeClock.h>
+
+
+/**
+ Returns the current time and date information, and the time-keeping capabilities
+ of the hardware platform.
+
+ @param Time A pointer to storage to receive a snapshot of the current time.
+ @param Capabilities An optional pointer to a buffer to receive the real time clock
+ device's capabilities.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER Time is NULL.
+ @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
+ @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an authentication failure.
+**/
+EFI_STATUS
+EFIAPI
+LibGetTime (
+ OUT EFI_TIME *Time,
+ OUT EFI_TIME_CAPABILITIES *Capabilities
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+
+ return Status;
+
+}
+
+
+/**
+ Sets the current local time and date information.
+
+ @param Time A pointer to the current time.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetTime (
+ IN EFI_TIME *Time
+ )
+{
+
+ EFI_STATUS Status = EFI_SUCCESS;
+
+
+ return Status;
+}
+
+
+/**
+ Returns the current wakeup alarm clock setting.
+
+ @param Enabled Indicates if the alarm is currently enabled or disabled.
+ @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
+ @param Time The current alarm setting.
+
+ @retval EFI_SUCCESS The alarm settings were returned.
+ @retval EFI_INVALID_PARAMETER Any parameter is NULL.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
+
+**/
+EFI_STATUS
+EFIAPI
+LibGetWakeupTime (
+ OUT BOOLEAN *Enabled,
+ OUT BOOLEAN *Pending,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+
+/**
+ Sets the system wakeup alarm clock time.
+
+ @param Enabled Enable or disable the wakeup alarm.
+ @param Time If Enable is TRUE, the time to set the wakeup alarm for.
+
+ @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
+ Enable is FALSE, then the wakeup alarm was disabled.
+ @retval EFI_INVALID_PARAMETER A time field is out of range.
+ @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
+ @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
+
+**/
+EFI_STATUS
+EFIAPI
+LibSetWakeupTime (
+ IN BOOLEAN Enabled,
+ OUT EFI_TIME *Time
+ )
+{
+ // Not a required feature
+ return EFI_UNSUPPORTED;
+}
+
+
+
+/**
+ This is the declaration of an EFI image entry point. This can be the entry point to an application
+ written to this specification, an EFI boot service driver, or an EFI runtime driver.
+
+ @param ImageHandle Handle that identifies the loaded image.
+ @param SystemTable System Table for this image.
+
+ @retval EFI_SUCCESS The operation completed successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+LibRtcInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+
+ EFI_TIME EfiTime;
+
+ // Setup the setters and getters
+ gRT->GetTime = LibGetTime;
+ gRT->SetTime = LibSetTime;
+ gRT->GetWakeupTime = LibGetWakeupTime;
+ gRT->SetWakeupTime = LibSetWakeupTime;
+
+
+ (VOID)gRT->GetTime (&EfiTime, NULL);
+ if((EfiTime.Year < 2015) || (EfiTime.Year > 2099)){
+ EfiTime.Year = 2015;
+ EfiTime.Month = 1;
+ EfiTime.Day = 1;
+ EfiTime.Hour = 0;
+ EfiTime.Minute = 0;
+ EfiTime.Second = 0;
+ EfiTime.Nanosecond = 0;
+ Status = gRT->SetTime(&EfiTime);
+ if (EFI_ERROR(Status))
+ {
+ DEBUG((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n", __FUNCTION__, __LINE__, Status));
+ }
+ }
+
+ // Install the protocol
+ Handle = NULL;
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gEfiRealTimeClockArchProtocolGuid, NULL,
+ NULL
+ );
+
+ return Status;
+}
+
+
+/**
+ Fixup internal data so that EFI can be call in virtual mode.
+ Call the passed in Child Notify event and convert any pointers in
+ lib to virtual mode.
+
+ @param[in] Event The Event that is being processed
+ @param[in] Context Event Context
+**/
+VOID
+EFIAPI
+LibRtcVirtualNotifyEvent (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ //
+ // Only needed if you are going to support the OS calling RTC functions in virtual mode.
+ // You will need to call EfiConvertPointer (). To convert any stored physical addresses
+ // to virtual address. After the OS transitions to calling in virtual mode, all future
+ // runtime calls will be made in virtual mode.
+ //
+ return;
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* Re: [edk2-staging/RISC-V-V2 PATCH v3 29/39] RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib.
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 29/39] RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib Abner Chang
@ 2019-11-21 17:02 ` Leif Lindholm
2019-11-22 12:28 ` Abner Chang
0 siblings, 1 reply; 77+ messages in thread
From: Leif Lindholm @ 2019-11-21 17:02 UTC (permalink / raw)
To: Abner Chang; +Cc: devel, Gilbert Chen
On Mon, Oct 28, 2019 at 09:59:07 +0800, Abner Chang wrote:
> Null instance of Real Time Clock lib for RISC-V platform.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Gilbert Chen <gilbert.chen@hpe.com>
Can you drop this one in favour of
EmbeddedPkg/Library/VirtualRealTimeClockLib/
?
/
Leif
> ---
> .../RealTimeClockLibNull/RealTimeClockLibNull.inf | 30 +++
> .../RealTimeClockLibNull/RealTimeClockLibNull.c | 204 +++++++++++++++++++++
> 2 files changed, 234 insertions(+)
> create mode 100644 RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.inf
> create mode 100644 RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.c
>
> diff --git a/RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.inf b/RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.inf
> new file mode 100644
> index 0000000..b9bffa1
> --- /dev/null
> +++ b/RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.inf
> @@ -0,0 +1,30 @@
> +#/** @file
> +#
> +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 0x0001001b
> + BASE_NAME = RealTimeClockLibNull
> + FILE_GUID = BFC3E25A-8AD0-4201-8A75-F00DE7964370
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = RealTimeClockLib
> +
> +[Sources.common]
> + RealTimeClockLibNull.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> +
> +[LibraryClasses]
> + UefiLib
> + DebugLib
> +# Use EFiAtRuntime to check stage
> + UefiRuntimeLib
> +
> +[Pcd]
> +
> diff --git a/RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.c b/RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.c
> new file mode 100644
> index 0000000..904e7e7
> --- /dev/null
> +++ b/RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.c
> @@ -0,0 +1,204 @@
> +/** @file
> + EFI RealTimeClock NULL library
> +
> + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Uefi.h>
> +#include <PiDxe.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/UefiLib.h>
> +// Use EfiAtRuntime to check stage
> +#include <Library/UefiRuntimeLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiRuntimeServicesTableLib.h>
> +#include <Protocol/RealTimeClock.h>
> +
> +
> +/**
> + Returns the current time and date information, and the time-keeping capabilities
> + of the hardware platform.
> +
> + @param Time A pointer to storage to receive a snapshot of the current time.
> + @param Capabilities An optional pointer to a buffer to receive the real time clock
> + device's capabilities.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_INVALID_PARAMETER Time is NULL.
> + @retval EFI_DEVICE_ERROR The time could not be retrieved due to hardware error.
> + @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an authentication failure.
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibGetTime (
> + OUT EFI_TIME *Time,
> + OUT EFI_TIME_CAPABILITIES *Capabilities
> + )
> +{
> + EFI_STATUS Status = EFI_SUCCESS;
> +
> + return Status;
> +
> +}
> +
> +
> +/**
> + Sets the current local time and date information.
> +
> + @param Time A pointer to the current time.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> + @retval EFI_INVALID_PARAMETER A time field is out of range.
> + @retval EFI_DEVICE_ERROR The time could not be set due due to hardware error.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibSetTime (
> + IN EFI_TIME *Time
> + )
> +{
> +
> + EFI_STATUS Status = EFI_SUCCESS;
> +
> +
> + return Status;
> +}
> +
> +
> +/**
> + Returns the current wakeup alarm clock setting.
> +
> + @param Enabled Indicates if the alarm is currently enabled or disabled.
> + @param Pending Indicates if the alarm signal is pending and requires acknowledgement.
> + @param Time The current alarm setting.
> +
> + @retval EFI_SUCCESS The alarm settings were returned.
> + @retval EFI_INVALID_PARAMETER Any parameter is NULL.
> + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due to a hardware error.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibGetWakeupTime (
> + OUT BOOLEAN *Enabled,
> + OUT BOOLEAN *Pending,
> + OUT EFI_TIME *Time
> + )
> +{
> + // Not a required feature
> + return EFI_UNSUPPORTED;
> +}
> +
> +
> +/**
> + Sets the system wakeup alarm clock time.
> +
> + @param Enabled Enable or disable the wakeup alarm.
> + @param Time If Enable is TRUE, the time to set the wakeup alarm for.
> +
> + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was enabled. If
> + Enable is FALSE, then the wakeup alarm was disabled.
> + @retval EFI_INVALID_PARAMETER A time field is out of range.
> + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a hardware error.
> + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this platform.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibSetWakeupTime (
> + IN BOOLEAN Enabled,
> + OUT EFI_TIME *Time
> + )
> +{
> + // Not a required feature
> + return EFI_UNSUPPORTED;
> +}
> +
> +
> +
> +/**
> + This is the declaration of an EFI image entry point. This can be the entry point to an application
> + written to this specification, an EFI boot service driver, or an EFI runtime driver.
> +
> + @param ImageHandle Handle that identifies the loaded image.
> + @param SystemTable System Table for this image.
> +
> + @retval EFI_SUCCESS The operation completed successfully.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibRtcInitialize (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_HANDLE Handle;
> +
> +
> + EFI_TIME EfiTime;
> +
> + // Setup the setters and getters
> + gRT->GetTime = LibGetTime;
> + gRT->SetTime = LibSetTime;
> + gRT->GetWakeupTime = LibGetWakeupTime;
> + gRT->SetWakeupTime = LibSetWakeupTime;
> +
> +
> + (VOID)gRT->GetTime (&EfiTime, NULL);
> + if((EfiTime.Year < 2015) || (EfiTime.Year > 2099)){
> + EfiTime.Year = 2015;
> + EfiTime.Month = 1;
> + EfiTime.Day = 1;
> + EfiTime.Hour = 0;
> + EfiTime.Minute = 0;
> + EfiTime.Second = 0;
> + EfiTime.Nanosecond = 0;
> + Status = gRT->SetTime(&EfiTime);
> + if (EFI_ERROR(Status))
> + {
> + DEBUG((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n", __FUNCTION__, __LINE__, Status));
> + }
> + }
> +
> + // Install the protocol
> + Handle = NULL;
> + Status = gBS->InstallMultipleProtocolInterfaces (
> + &Handle,
> + &gEfiRealTimeClockArchProtocolGuid, NULL,
> + NULL
> + );
> +
> + return Status;
> +}
> +
> +
> +/**
> + Fixup internal data so that EFI can be call in virtual mode.
> + Call the passed in Child Notify event and convert any pointers in
> + lib to virtual mode.
> +
> + @param[in] Event The Event that is being processed
> + @param[in] Context Event Context
> +**/
> +VOID
> +EFIAPI
> +LibRtcVirtualNotifyEvent (
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + //
> + // Only needed if you are going to support the OS calling RTC functions in virtual mode.
> + // You will need to call EfiConvertPointer (). To convert any stored physical addresses
> + // to virtual address. After the OS transitions to calling in virtual mode, all future
> + // runtime calls will be made in virtual mode.
> + //
> + return;
> +}
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 77+ messages in thread* Re: [edk2-staging/RISC-V-V2 PATCH v3 29/39] RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib.
2019-11-21 17:02 ` Leif Lindholm
@ 2019-11-22 12:28 ` Abner Chang
2019-11-22 14:08 ` Leif Lindholm
0 siblings, 1 reply; 77+ messages in thread
From: Abner Chang @ 2019-11-22 12:28 UTC (permalink / raw)
To: Leif Lindholm; +Cc: devel@edk2.groups.io, Chen, Gilbert
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Friday, November 22, 2019 1:03 AM
> To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Cc: devel@edk2.groups.io; Chen, Gilbert <gilbert.chen@hpe.com>
> Subject: Re: [edk2-staging/RISC-V-V2 PATCH v3 29/39]
> RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib.
>
> On Mon, Oct 28, 2019 at 09:59:07 +0800, Abner Chang wrote:
> > Null instance of Real Time Clock lib for RISC-V platform.
> >
> > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> >
> > Cc: Leif Lindholm <leif.lindholm@linaro.org>
> > Cc: Gilbert Chen <gilbert.chen@hpe.com>
>
> Can you drop this one in favour of
> EmbeddedPkg/Library/VirtualRealTimeClockLib/
Both U500.dsc and U540.dsc use EmbeddedPkg/Library/VirtualRealTimeClockLib, you can see this in edk2-platform patches.
The NULL one is only used in RiscVplatformPkg for build. I don't think we have to use VirtualRealTimeClockLib in this RiscVplatformPkg package.
Abner
> ?
>
> /
> Leif
>
> > ---
> > .../RealTimeClockLibNull/RealTimeClockLibNull.inf | 30 +++
> > .../RealTimeClockLibNull/RealTimeClockLibNull.c | 204
> +++++++++++++++++++++
> > 2 files changed, 234 insertions(+)
> > create mode 100644
> > RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.inf
> > create mode 100644
> > RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.c
> >
> > diff --git
> > a/RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.i
> > nf
> > b/RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.i
> > nf
> > new file mode 100644
> > index 0000000..b9bffa1
> > --- /dev/null
> > +++ b/RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNu
> > +++ ll.inf
> > @@ -0,0 +1,30 @@
> > +#/** @file
> > +#
> > +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> > +rights reserved.<BR> # # SPDX-License-Identifier:
> > +BSD-2-Clause-Patent # #**/
> > +
> > +[Defines]
> > + INF_VERSION = 0x0001001b
> > + BASE_NAME = RealTimeClockLibNull
> > + FILE_GUID = BFC3E25A-8AD0-4201-8A75-F00DE7964370
> > + MODULE_TYPE = BASE
> > + VERSION_STRING = 1.0
> > + LIBRARY_CLASS = RealTimeClockLib
> > +
> > +[Sources.common]
> > + RealTimeClockLibNull.c
> > +
> > +[Packages]
> > + MdePkg/MdePkg.dec
> > +
> > +[LibraryClasses]
> > + UefiLib
> > + DebugLib
> > +# Use EFiAtRuntime to check stage
> > + UefiRuntimeLib
> > +
> > +[Pcd]
> > +
> > diff --git
> > a/RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.c
> > b/RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.c
> > new file mode 100644
> > index 0000000..904e7e7
> > --- /dev/null
> > +++ b/RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNu
> > +++ ll.c
> > @@ -0,0 +1,204 @@
> > +/** @file
> > + EFI RealTimeClock NULL library
> > +
> > + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All
> > + rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +#include <Uefi.h>
> > +#include <PiDxe.h>
> > +#include <Library/BaseLib.h>
> > +#include <Library/DebugLib.h>
> > +#include <Library/UefiLib.h>
> > +// Use EfiAtRuntime to check stage
> > +#include <Library/UefiRuntimeLib.h>
> > +#include <Library/UefiBootServicesTableLib.h>
> > +#include <Library/UefiRuntimeServicesTableLib.h>
> > +#include <Protocol/RealTimeClock.h>
> > +
> > +
> > +/**
> > + Returns the current time and date information, and the time-keeping
> > +capabilities
> > + of the hardware platform.
> > +
> > + @param Time A pointer to storage to receive a snapshot of the
> current time.
> > + @param Capabilities An optional pointer to a buffer to receive the
> real time clock
> > + device's capabilities.
> > +
> > + @retval EFI_SUCCESS The operation completed successfully.
> > + @retval EFI_INVALID_PARAMETER Time is NULL.
> > + @retval EFI_DEVICE_ERROR The time could not be retrieved due to
> hardware error.
> > + @retval EFI_SECURITY_VIOLATION The time could not be retrieved due
> to an authentication failure.
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +LibGetTime (
> > + OUT EFI_TIME *Time,
> > + OUT EFI_TIME_CAPABILITIES *Capabilities
> > + )
> > +{
> > + EFI_STATUS Status = EFI_SUCCESS;
> > +
> > + return Status;
> > +
> > +}
> > +
> > +
> > +/**
> > + Sets the current local time and date information.
> > +
> > + @param Time A pointer to the current time.
> > +
> > + @retval EFI_SUCCESS The operation completed successfully.
> > + @retval EFI_INVALID_PARAMETER A time field is out of range.
> > + @retval EFI_DEVICE_ERROR The time could not be set due due to
> hardware error.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +LibSetTime (
> > + IN EFI_TIME *Time
> > + )
> > +{
> > +
> > + EFI_STATUS Status = EFI_SUCCESS;
> > +
> > +
> > + return Status;
> > +}
> > +
> > +
> > +/**
> > + Returns the current wakeup alarm clock setting.
> > +
> > + @param Enabled Indicates if the alarm is currently enabled or
> disabled.
> > + @param Pending Indicates if the alarm signal is pending and
> requires acknowledgement.
> > + @param Time The current alarm setting.
> > +
> > + @retval EFI_SUCCESS The alarm settings were returned.
> > + @retval EFI_INVALID_PARAMETER Any parameter is NULL.
> > + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved
> due to a hardware error.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +LibGetWakeupTime (
> > + OUT BOOLEAN *Enabled,
> > + OUT BOOLEAN *Pending,
> > + OUT EFI_TIME *Time
> > + )
> > +{
> > + // Not a required feature
> > + return EFI_UNSUPPORTED;
> > +}
> > +
> > +
> > +/**
> > + Sets the system wakeup alarm clock time.
> > +
> > + @param Enabled Enable or disable the wakeup alarm.
> > + @param Time If Enable is TRUE, the time to set the wakeup
> alarm for.
> > +
> > + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm was
> enabled. If
> > + Enable is FALSE, then the wakeup alarm was disabled.
> > + @retval EFI_INVALID_PARAMETER A time field is out of range.
> > + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to
> a hardware error.
> > + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this
> platform.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +LibSetWakeupTime (
> > + IN BOOLEAN Enabled,
> > + OUT EFI_TIME *Time
> > + )
> > +{
> > + // Not a required feature
> > + return EFI_UNSUPPORTED;
> > +}
> > +
> > +
> > +
> > +/**
> > + This is the declaration of an EFI image entry point. This can be
> > +the entry point to an application
> > + written to this specification, an EFI boot service driver, or an EFI runtime
> driver.
> > +
> > + @param ImageHandle Handle that identifies the loaded image.
> > + @param SystemTable System Table for this image.
> > +
> > + @retval EFI_SUCCESS The operation completed successfully.
> > +
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +LibRtcInitialize (
> > + IN EFI_HANDLE ImageHandle,
> > + IN EFI_SYSTEM_TABLE *SystemTable
> > + )
> > +{
> > + EFI_STATUS Status;
> > + EFI_HANDLE Handle;
> > +
> > +
> > + EFI_TIME EfiTime;
> > +
> > + // Setup the setters and getters
> > + gRT->GetTime = LibGetTime;
> > + gRT->SetTime = LibSetTime;
> > + gRT->GetWakeupTime = LibGetWakeupTime; gRT->SetWakeupTime =
> > + LibSetWakeupTime;
> > +
> > +
> > + (VOID)gRT->GetTime (&EfiTime, NULL); if((EfiTime.Year < 2015) ||
> > + (EfiTime.Year > 2099)){
> > + EfiTime.Year = 2015;
> > + EfiTime.Month = 1;
> > + EfiTime.Day = 1;
> > + EfiTime.Hour = 0;
> > + EfiTime.Minute = 0;
> > + EfiTime.Second = 0;
> > + EfiTime.Nanosecond = 0;
> > + Status = gRT->SetTime(&EfiTime);
> > + if (EFI_ERROR(Status))
> > + {
> > + DEBUG((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n", __FUNCTION__,
> __LINE__, Status));
> > + }
> > + }
> > +
> > + // Install the protocol
> > + Handle = NULL;
> > + Status = gBS->InstallMultipleProtocolInterfaces (
> > + &Handle,
> > + &gEfiRealTimeClockArchProtocolGuid, NULL,
> > + NULL
> > + );
> > +
> > + return Status;
> > +}
> > +
> > +
> > +/**
> > + Fixup internal data so that EFI can be call in virtual mode.
> > + Call the passed in Child Notify event and convert any pointers in
> > + lib to virtual mode.
> > +
> > + @param[in] Event The Event that is being processed
> > + @param[in] Context Event Context
> > +**/
> > +VOID
> > +EFIAPI
> > +LibRtcVirtualNotifyEvent (
> > + IN EFI_EVENT Event,
> > + IN VOID *Context
> > + )
> > +{
> > + //
> > + // Only needed if you are going to support the OS calling RTC functions in
> virtual mode.
> > + // You will need to call EfiConvertPointer (). To convert any
> > +stored physical addresses
> > + // to virtual address. After the OS transitions to calling in
> > +virtual mode, all future
> > + // runtime calls will be made in virtual mode.
> > + //
> > + return;
> > +}
> > --
> > 2.7.4
> >
^ permalink raw reply [flat|nested] 77+ messages in thread* Re: [edk2-staging/RISC-V-V2 PATCH v3 29/39] RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib.
2019-11-22 12:28 ` Abner Chang
@ 2019-11-22 14:08 ` Leif Lindholm
2019-11-22 14:19 ` Abner Chang
0 siblings, 1 reply; 77+ messages in thread
From: Leif Lindholm @ 2019-11-22 14:08 UTC (permalink / raw)
To: Chang, Abner (HPS SW/FW Technologist); +Cc: devel@edk2.groups.io, Chen, Gilbert
On Fri, Nov 22, 2019 at 12:28:01 +0000, Chang, Abner (HPS SW/FW Technologist) wrote:
>
>
> > -----Original Message-----
> > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > Sent: Friday, November 22, 2019 1:03 AM
> > To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> > Cc: devel@edk2.groups.io; Chen, Gilbert <gilbert.chen@hpe.com>
> > Subject: Re: [edk2-staging/RISC-V-V2 PATCH v3 29/39]
> > RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib.
> >
> > On Mon, Oct 28, 2019 at 09:59:07 +0800, Abner Chang wrote:
> > > Null instance of Real Time Clock lib for RISC-V platform.
> > >
> > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > >
> > > Cc: Leif Lindholm <leif.lindholm@linaro.org>
> > > Cc: Gilbert Chen <gilbert.chen@hpe.com>
> >
> > Can you drop this one in favour of
> > EmbeddedPkg/Library/VirtualRealTimeClockLib/
>
> Both U500.dsc and U540.dsc use
> EmbeddedPkg/Library/VirtualRealTimeClockLib, you can see this in
> edk2-platform patches.
>
> The NULL one is only used in RiscVplatformPkg for build. I don't
> think we have to use VirtualRealTimeClockLib in this
> RiscVplatformPkg package.
Sure, but we also don't *need* to add a new implementation for this -
RiscVPkg can still use the EmbeddedPkg one.
(And if we did, it should probably be in MdeModulePkg.)
/
Leif
^ permalink raw reply [flat|nested] 77+ messages in thread* Re: [edk2-staging/RISC-V-V2 PATCH v3 29/39] RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib.
2019-11-22 14:08 ` Leif Lindholm
@ 2019-11-22 14:19 ` Abner Chang
2019-11-22 14:55 ` Leif Lindholm
0 siblings, 1 reply; 77+ messages in thread
From: Abner Chang @ 2019-11-22 14:19 UTC (permalink / raw)
To: Leif Lindholm; +Cc: devel@edk2.groups.io, Chen, Gilbert
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Friday, November 22, 2019 10:09 PM
> To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Cc: devel@edk2.groups.io; Chen, Gilbert <gilbert.chen@hpe.com>
> Subject: Re: [edk2-staging/RISC-V-V2 PATCH v3 29/39]
> RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib.
>
> On Fri, Nov 22, 2019 at 12:28:01 +0000, Chang, Abner (HPS SW/FW
> Technologist) wrote:
> >
> >
> > > -----Original Message-----
> > > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > > Sent: Friday, November 22, 2019 1:03 AM
> > > To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> > > Cc: devel@edk2.groups.io; Chen, Gilbert <gilbert.chen@hpe.com>
> > > Subject: Re: [edk2-staging/RISC-V-V2 PATCH v3 29/39]
> > > RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib.
> > >
> > > On Mon, Oct 28, 2019 at 09:59:07 +0800, Abner Chang wrote:
> > > > Null instance of Real Time Clock lib for RISC-V platform.
> > > >
> > > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > >
> > > > Cc: Leif Lindholm <leif.lindholm@linaro.org>
> > > > Cc: Gilbert Chen <gilbert.chen@hpe.com>
> > >
> > > Can you drop this one in favour of
> > > EmbeddedPkg/Library/VirtualRealTimeClockLib/
> >
> > Both U500.dsc and U540.dsc use
> > EmbeddedPkg/Library/VirtualRealTimeClockLib, you can see this in
> > edk2-platform patches.
> >
> > The NULL one is only used in RiscVplatformPkg for build. I don't think
> > we have to use VirtualRealTimeClockLib in this RiscVplatformPkg
> > package.
>
> Sure, but we also don't *need* to add a new implementation for this -
> RiscVPkg can still use the EmbeddedPkg one.
>
> (And if we did, it should probably be in MdeModulePkg.)
I think we had similar discussion about this before. My comment was RiscVPkg as a processor package should not have dependence with EmbeddedPkg.
But have NULL instance in MdeModulePkg is fine to me.
>
> /
> Leif
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [edk2-staging/RISC-V-V2 PATCH v3 29/39] RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib.
2019-11-22 14:19 ` Abner Chang
@ 2019-11-22 14:55 ` Leif Lindholm
2019-11-22 16:05 ` [edk2-devel] " Abner Chang
0 siblings, 1 reply; 77+ messages in thread
From: Leif Lindholm @ 2019-11-22 14:55 UTC (permalink / raw)
To: Chang, Abner (HPS SW/FW Technologist); +Cc: devel@edk2.groups.io, Chen, Gilbert
On Fri, Nov 22, 2019 at 14:19:55 +0000, Chang, Abner (HPS SW/FW Technologist) wrote:
> > > > On Mon, Oct 28, 2019 at 09:59:07 +0800, Abner Chang wrote:
> > > > > Null instance of Real Time Clock lib for RISC-V platform.
> > > > >
> > > > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > > >
> > > > > Cc: Leif Lindholm <leif.lindholm@linaro.org>
> > > > > Cc: Gilbert Chen <gilbert.chen@hpe.com>
> > > >
> > > > Can you drop this one in favour of
> > > > EmbeddedPkg/Library/VirtualRealTimeClockLib/
> > >
> > > Both U500.dsc and U540.dsc use
> > > EmbeddedPkg/Library/VirtualRealTimeClockLib, you can see this in
> > > edk2-platform patches.
> > >
> > > The NULL one is only used in RiscVplatformPkg for build. I don't think
> > > we have to use VirtualRealTimeClockLib in this RiscVplatformPkg
> > > package.
> >
> > Sure, but we also don't *need* to add a new implementation for this -
> > RiscVPkg can still use the EmbeddedPkg one.
> >
> > (And if we did, it should probably be in MdeModulePkg.)
>
> I think we had similar discussion about this before. My comment was
> RiscVPkg as a processor package should not have dependence with
> EmbeddedPkg.
This is not RiscVPkg though, this is RiscVPlatformPkg.
And also, it does not appear to be used there anyway?
Certainly I can still build RiscVPlatformPkg.dsc if I delete that
library mapping.
/
Leif
^ permalink raw reply [flat|nested] 77+ messages in thread* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 29/39] RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib.
2019-11-22 14:55 ` Leif Lindholm
@ 2019-11-22 16:05 ` Abner Chang
2019-11-22 16:32 ` Leif Lindholm
0 siblings, 1 reply; 77+ messages in thread
From: Abner Chang @ 2019-11-22 16:05 UTC (permalink / raw)
To: devel@edk2.groups.io, leif.lindholm@linaro.org; +Cc: Chen, Gilbert
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Friday, November 22, 2019 10:56 PM
> To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Cc: devel@edk2.groups.io; Chen, Gilbert <gilbert.chen@hpe.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 29/39]
> RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib.
>
> On Fri, Nov 22, 2019 at 14:19:55 +0000, Chang, Abner (HPS SW/FW
> Technologist) wrote:
> > > > > On Mon, Oct 28, 2019 at 09:59:07 +0800, Abner Chang wrote:
> > > > > > Null instance of Real Time Clock lib for RISC-V platform.
> > > > > >
> > > > > > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> > > > > >
> > > > > > Cc: Leif Lindholm <leif.lindholm@linaro.org>
> > > > > > Cc: Gilbert Chen <gilbert.chen@hpe.com>
> > > > >
> > > > > Can you drop this one in favour of
> > > > > EmbeddedPkg/Library/VirtualRealTimeClockLib/
> > > >
> > > > Both U500.dsc and U540.dsc use
> > > > EmbeddedPkg/Library/VirtualRealTimeClockLib, you can see this in
> > > > edk2-platform patches.
> > > >
> > > > The NULL one is only used in RiscVplatformPkg for build. I don't
> > > > think we have to use VirtualRealTimeClockLib in this
> > > > RiscVplatformPkg package.
> > >
> > > Sure, but we also don't *need* to add a new implementation for this
> > > - RiscVPkg can still use the EmbeddedPkg one.
> > >
> > > (And if we did, it should probably be in MdeModulePkg.)
> >
> > I think we had similar discussion about this before. My comment was
> > RiscVPkg as a processor package should not have dependence with
> > EmbeddedPkg.
>
> This is not RiscVPkg though, this is RiscVPlatformPkg.
> And also, it does not appear to be used there anyway?
Same comments from me for RiscVPlatformPkg. I don't see any reasons to have dependence with EmbeddedPkg in RiscVPlatformPkg as RiscVPlatformPkg is a generic RISC-V platform modules . Platform such as U540 could choice which RTC instance it needs.
>
> Certainly I can still build RiscVPlatformPkg.dsc if I delete that library mapping.
We can remove this one and create a null one in MdePkg which is akin to the null instance of TimerLib.
>
> /
> Leif
>
>
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 29/39] RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib.
2019-11-22 16:05 ` [edk2-devel] " Abner Chang
@ 2019-11-22 16:32 ` Leif Lindholm
2019-11-23 7:38 ` Abner Chang
0 siblings, 1 reply; 77+ messages in thread
From: Leif Lindholm @ 2019-11-22 16:32 UTC (permalink / raw)
To: devel, abner.chang; +Cc: Chen, Gilbert
On Fri, Nov 22, 2019 at 16:05:07 +0000, Abner Chang wrote:
> > > > Sure, but we also don't *need* to add a new implementation for this
> > > > - RiscVPkg can still use the EmbeddedPkg one.
> > > >
> > > > (And if we did, it should probably be in MdeModulePkg.)
> > >
> > > I think we had similar discussion about this before. My comment was
> > > RiscVPkg as a processor package should not have dependence with
> > > EmbeddedPkg.
> >
> > This is not RiscVPkg though, this is RiscVPlatformPkg.
> > And also, it does not appear to be used there anyway?
>
> Same comments from me for RiscVPlatformPkg. I don't see any reasons
> to have dependence with EmbeddedPkg in RiscVPlatformPkg as
> RiscVPlatformPkg is a generic RISC-V platform modules . Platform
> such as U540 could choice which RTC instance it needs.
I don't think there is any particular inherent aspect about
EmbeddedPkg being more evil or unreliable than MdeModulePkg. If
anything, it suffers from poor naming. (Basically, it was the staging
area for bringing a bunch of !x86 stuff into the tree, and the first
platform port was to an embedded board...)
But more importantly, RealTimeClockLib is only used by
EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf, so
it's a bit difficult to argue that EmbeddedPkg is an unsuitable source
for the library.
We will at some point do an overhaul of the directory tree, so getting
hung up on current package names isn't a worthwhile investment.
The only real exceptions to this are MdePkg and MdeModulePkg, which
should not depend on any other packages. And I tend to argue even
about that.
> > Certainly I can still build RiscVPlatformPkg.dsc if I delete that
> > library mapping.
>
> We can remove this one and create a null one in MdePkg which is akin
> to the null instance of TimerLib.
I have no issue with that as such.
I also don't see a value.
A RealTimeClockLibNull is only useful for enabling compilation of
incomplete platforms (and as such, if it was included in MdeModulePkg,
it should probably have unconditional ASSERTs added to all functions).
Whereas VirtualRealTimeClockLib can ameliorate the situation of not
having a persistent RTC in the system.
But for the purpose of this set, please just drop this patch and any
references to this module.
/
Leif
^ permalink raw reply [flat|nested] 77+ messages in thread* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 29/39] RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib.
2019-11-22 16:32 ` Leif Lindholm
@ 2019-11-23 7:38 ` Abner Chang
0 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-11-23 7:38 UTC (permalink / raw)
To: devel@edk2.groups.io, leif.lindholm@linaro.org; +Cc: Chen, Gilbert
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Saturday, November 23, 2019 12:32 AM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Cc: Chen, Gilbert <gilbert.chen@hpe.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 29/39]
> RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib.
>
> On Fri, Nov 22, 2019 at 16:05:07 +0000, Abner Chang wrote:
> > > > > Sure, but we also don't *need* to add a new implementation for
> > > > > this
> > > > > - RiscVPkg can still use the EmbeddedPkg one.
> > > > >
> > > > > (And if we did, it should probably be in MdeModulePkg.)
> > > >
> > > > I think we had similar discussion about this before. My comment
> > > > was RiscVPkg as a processor package should not have dependence
> > > > with EmbeddedPkg.
> > >
> > > This is not RiscVPkg though, this is RiscVPlatformPkg.
> > > And also, it does not appear to be used there anyway?
> >
> > Same comments from me for RiscVPlatformPkg. I don't see any reasons to
> > have dependence with EmbeddedPkg in RiscVPlatformPkg as
> > RiscVPlatformPkg is a generic RISC-V platform modules . Platform such
> > as U540 could choice which RTC instance it needs.
>
> I don't think there is any particular inherent aspect about EmbeddedPkg
> being more evil or unreliable than MdeModulePkg. If anything, it suffers
> from poor naming. (Basically, it was the staging area for bringing a bunch
> of !x86 stuff into the tree, and the first platform port was to an embedded
> board...)
>
> But more importantly, RealTimeClockLib is only used by
> EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf, so
> it's a bit difficult to argue that EmbeddedPkg is an unsuitable source for the
> library.
>
> We will at some point do an overhaul of the directory tree, so getting hung
> up on current package names isn't a worthwhile investment.
>
> The only real exceptions to this are MdePkg and MdeModulePkg, which
> should not depend on any other packages. And I tend to argue even about
> that.
>
> > > Certainly I can still build RiscVPlatformPkg.dsc if I delete that
> > > library mapping.
> >
> > We can remove this one and create a null one in MdePkg which is akin
> > to the null instance of TimerLib.
>
> I have no issue with that as such.
> I also don't see a value.
>
> A RealTimeClockLibNull is only useful for enabling compilation of incomplete
> platforms (and as such, if it was included in MdeModulePkg, it should
> probably have unconditional ASSERTs added to all functions).
>
> Whereas VirtualRealTimeClockLib can ameliorate the situation of not having a
> persistent RTC in the system.
>
> But for the purpose of this set, please just drop this patch and any
> references to this module.
no problem, I am fine with removing this lib. Thanks!
>
> /
> Leif
>
>
^ permalink raw reply [flat|nested] 77+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v3 30/39] RiscVPlatformPkg/OpensbiPlatformLibNull: NULL instance of RiscVOpensbiPlatformLib
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (28 preceding siblings ...)
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 29/39] RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib Abner Chang
@ 2019-10-28 1:59 ` Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 31/39] RiscVPlatformPkg/PlatformMemoryTestLibNull: NULL instance of PlatformMemoryTestLib Abner Chang
` (8 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:59 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
NULL instance of RiscVOpensbiPlatformLib.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../OpensbiPlatformLibNull.inf | 38 +++++++++++++++++++
.../Library/OpensbiPlatformLibNull/Platform.c | 44 ++++++++++++++++++++++
2 files changed, 82 insertions(+)
create mode 100644 RiscVPlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
create mode 100644 RiscVPlatformPkg/Library/OpensbiPlatformLibNull/Platform.c
diff --git a/RiscVPlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf b/RiscVPlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
new file mode 100644
index 0000000..cdc5f65
--- /dev/null
+++ b/RiscVPlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
@@ -0,0 +1,38 @@
+## @file
+# RISC-V OpenSbi Platform NULL Library
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVOpensbiPlatformLibNull
+ FILE_GUID = 9424ED54-EBDA-4FB5-8FF6-8291B07BB151
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVOpensbiPlatformLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ Platform.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ DebugAgentLib
+
+
diff --git a/RiscVPlatformPkg/Library/OpensbiPlatformLibNull/Platform.c b/RiscVPlatformPkg/Library/OpensbiPlatformLibNull/Platform.c
new file mode 100644
index 0000000..e78d811
--- /dev/null
+++ b/RiscVPlatformPkg/Library/OpensbiPlatformLibNull/Platform.c
@@ -0,0 +1,44 @@
+/*
+ *
+ * Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Atish Patra <atish.patra@wdc.com>
+ */
+
+#include <sbi/sbi_const.h>
+#include <sbi/sbi_platform.h>
+
+const struct sbi_platform_operations platform_ops = {
+ .pmp_region_count = NULL,
+ .pmp_region_info = NULL,
+ .final_init = NULL,
+ .console_putc = NULL,
+ .console_getc = NULL,
+ .console_init = NULL,
+ .irqchip_init = NULL,
+ .ipi_send = NULL,
+ .ipi_clear = NULL,
+ .ipi_init = NULL,
+ .timer_value = NULL,
+ .timer_event_stop = NULL,
+ .timer_event_start = NULL,
+ .timer_init = NULL,
+ .system_reboot = NULL,
+ .system_shutdown = NULL
+};
+
+const struct sbi_platform platform = {
+ .opensbi_version = OPENSBI_VERSION, // The OpenSBI version this platform table is built bassed on.
+ .platform_version = SBI_PLATFORM_VERSION(0x0000, 0x0000), // SBI Platform version 1.0
+ .name = "NULL platform",
+ .features = 0,
+ .hart_count = 0,
+ .hart_stack_size = 0,
+ .disabled_hart_mask = 0,
+ .platform_ops_addr = 0
+};
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 31/39] RiscVPlatformPkg/PlatformMemoryTestLibNull: NULL instance of PlatformMemoryTestLib
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (29 preceding siblings ...)
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 30/39] RiscVPlatformPkg/OpensbiPlatformLibNull: NULL instance of RiscVOpensbiPlatformLib Abner Chang
@ 2019-10-28 1:59 ` Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 32/39] RiscVPlatformPkg/PlatformUpdateProgressLibNull: NULL instance of PlatformUpdateProgressLib Abner Chang
` (7 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:59 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
NULL instance of PlatformMemoryTestLib.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../PlatformMemoryTestLibNull.inf | 29 ++++++++++++++++++++++
.../PlatformMemoryTestLibNull.c | 29 ++++++++++++++++++++++
2 files changed, 58 insertions(+)
create mode 100644 RiscVPlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
create mode 100644 RiscVPlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.c
diff --git a/RiscVPlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf b/RiscVPlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
new file mode 100644
index 0000000..a1b503e
--- /dev/null
+++ b/RiscVPlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
@@ -0,0 +1,29 @@
+#/** @file
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PlatformMemoryTestLibNull
+ FILE_GUID = 81EE52ED-3C6A-4A42-9564-5676766F5CE6
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformMemoryTestLib
+
+[Sources.common]
+ PlatformMemoryTestLibNull.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ UefiLib
+ DebugLib
+
+[Pcd]
+
diff --git a/RiscVPlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.c b/RiscVPlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.c
new file mode 100644
index 0000000..9246070
--- /dev/null
+++ b/RiscVPlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.c
@@ -0,0 +1,29 @@
+/** @file
+ Platform Memory Test NULL library
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Protocol/GenericMemoryTest.h>
+
+/**
+ Perform the memory test base on the memory test intensive level,
+ and update the memory resource.
+
+ @param Level The memory test intensive level.
+
+ @retval EFI_STATUS Success test all the system memory and update
+ the memory resource
+
+**/
+EFI_STATUS
+PlatformBootManagerMemoryTest (
+ IN EXTENDMEM_COVERAGE_LEVEL Level
+ )
+{
+ return EFI_SUCCESS;
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 32/39] RiscVPlatformPkg/PlatformUpdateProgressLibNull: NULL instance of PlatformUpdateProgressLib
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (30 preceding siblings ...)
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 31/39] RiscVPlatformPkg/PlatformMemoryTestLibNull: NULL instance of PlatformMemoryTestLib Abner Chang
@ 2019-10-28 1:59 ` Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 33/39] RiscVPlatformPkg/PlatformBootManagerLib: Platform Boot Manager library Abner Chang
` (6 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:59 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
NULL instance of PlatformUpdateProgressLib.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../PlatformUpdateProgressLibNull.inf | 29 ++++++++++++
.../PlatformUpdateProgressLibNull.c | 52 ++++++++++++++++++++++
2 files changed, 81 insertions(+)
create mode 100644 RiscVPlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
create mode 100644 RiscVPlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.c
diff --git a/RiscVPlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf b/RiscVPlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
new file mode 100644
index 0000000..fdba00c
--- /dev/null
+++ b/RiscVPlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
@@ -0,0 +1,29 @@
+#/** @file
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PlatformUpdateProgressLibNull
+ FILE_GUID = BFC3E25A-8AD0-4201-8A75-F00DE7964370
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformUpdateProgressLib
+
+[Sources.common]
+ PlatformUpdateProgressLibNull.c
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ UefiLib
+ DebugLib
+
+[Pcd]
+
diff --git a/RiscVPlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.c b/RiscVPlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.c
new file mode 100644
index 0000000..6b0bd05
--- /dev/null
+++ b/RiscVPlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.c
@@ -0,0 +1,52 @@
+/** @file
+ Platform Update Progress NULL library
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Protocol/GenericMemoryTest.h>
+#include <Protocol/GraphicsOutput.h>
+
+/**
+ This function is called each second during the boot manager waits the timeout.
+
+ @param TimeoutRemain The remaining timeout.
+**/
+VOID
+EFIAPI
+PlatformBootManagerWaitCallback (
+ UINT16 TimeoutRemain
+ )
+{
+ return;
+}
+/**
+
+ Show progress bar with title above it. It only works in Graphics mode.
+
+ @param TitleForeground Foreground color for Title.
+ @param TitleBackground Background color for Title.
+ @param Title Title above progress bar.
+ @param ProgressColor Progress bar color.
+ @param Progress Progress (0-100)
+ @param PreviousValue The previous value of the progress.
+
+ @retval EFI_STATUS Success update the progress bar
+
+**/
+EFI_STATUS
+PlatformBootManagerShowProgress (
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,
+ IN CHAR16 *Title,
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,
+ IN UINTN Progress,
+ IN UINTN PreviousValue
+ )
+{
+ return EFI_SUCCESS;
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 33/39] RiscVPlatformPkg/PlatformBootManagerLib: Platform Boot Manager library.
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (31 preceding siblings ...)
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 32/39] RiscVPlatformPkg/PlatformUpdateProgressLibNull: NULL instance of PlatformUpdateProgressLib Abner Chang
@ 2019-10-28 1:59 ` Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 34/39] RiscVPkg/RiscVPlatformTimerLibNull: NULL instance of RISC-V platform timer library Abner Chang
` (5 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:59 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=y, Size: 18639 bytes --]
Common Platform Boot Manager library for RISC-V platform.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../PlatformBootManagerLib.inf | 61 ++++++
.../PlatformBootManagerLib/PlatformBootManager.h | 117 ++++++++++
.../PlatformBootManagerLib/PlatformBootManager.c | 243 +++++++++++++++++++++
.../Library/PlatformBootManagerLib/PlatformData.c | 49 +++++
.../Library/PlatformBootManagerLib/Strings.uni | 28 +++
5 files changed, 498 insertions(+)
create mode 100644 RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
create mode 100644 RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
create mode 100644 RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
create mode 100644 RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c
create mode 100644 RiscVPlatformPkg/Library/PlatformBootManagerLib/Strings.uni
diff --git a/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
new file mode 100644
index 0000000..6086e54
--- /dev/null
+++ b/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -0,0 +1,61 @@
+## @file
+# Include all platform action which can be customized by IBV/OEM.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = PlatformBootManagerLib
+ FILE_GUID = 7DDA7916-6139-4D46-A415-30E854AF3BC7
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformBootManagerLib|DXE_DRIVER
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ PlatformData.c
+ PlatformBootManager.c
+ PlatformBootManager.h
+ Strings.uni
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ RiscVPlatformPkg/RiscVPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ UefiLib
+ UefiBootManagerLib
+ PcdLib
+ PlatformMemoryTestLib
+ PlatformUpdateProgressLib
+ DxeServicesLib
+ MemoryAllocationLib
+ DevicePathLib
+ HiiLib
+ PrintLib
+
+[Guids]
+
+[Protocols]
+ gEfiGenericMemTestProtocolGuid ## CONSUMES
+ gEfiGraphicsOutputProtocolGuid ## CONSUMES
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable
diff --git a/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h b/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
new file mode 100644
index 0000000..58c363a
--- /dev/null
+++ b/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.h
@@ -0,0 +1,117 @@
+/**@file
+ Head file for BDS Platform specific code
+
+Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PLATFORM_BOOT_MANAGER_H_
+#define PLATFORM_BOOT_MANAGER_H_
+
+#include <PiDxe.h>
+#include <IndustryStandard/Bmp.h>
+#include <Protocol/GenericMemoryTest.h>
+#include <Protocol/LoadedImage.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/BootLogo.h>
+#include <Protocol/DevicePath.h>
+
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootManagerLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/HiiLib.h>
+#include <Library/PrintLib.h>
+
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ UINTN ConnectType;
+} PLATFORM_CONSOLE_CONNECT_ENTRY;
+
+extern PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[];
+
+#define gEndEntire \
+ { \
+ END_DEVICE_PATH_TYPE,\
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,\
+ END_DEVICE_PATH_LENGTH,\
+ 0\
+ }
+
+#define CONSOLE_OUT BIT0
+#define CONSOLE_IN BIT1
+#define STD_ERROR BIT2
+
+//D3987D4B-971A-435F-8CAF-4967EB627241
+#define EFI_SERIAL_DXE_GUID \
+ { 0xD3987D4B, 0x971A, 0x435F, { 0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72, 0x41 } }
+
+typedef struct {
+ VENDOR_DEVICE_PATH Guid;
+ UART_DEVICE_PATH Uart;
+ VENDOR_DEVICE_PATH TerminalType;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} SERIAL_CONSOLE_DEVICE_PATH;
+
+/**
+ Use SystemTable Conout to turn on video based Simple Text Out consoles. The
+ Simple Text Out screens will now be synced up with all non video output devices
+
+ @retval EFI_SUCCESS UGA devices are back in text mode and synced up.
+
+**/
+EFI_STATUS
+PlatformBootManagerDisableQuietBoot (
+ VOID
+ );
+
+/**
+ Perform the memory test base on the memory test intensive level,
+ and update the memory resource.
+
+ @param Level The memory test intensive level.
+
+ @retval EFI_STATUS Success test all the system memory and update
+ the memory resource
+
+**/
+EFI_STATUS
+PlatformBootManagerMemoryTest (
+ IN EXTENDMEM_COVERAGE_LEVEL Level
+ );
+
+/**
+
+ Show progress bar with title above it. It only works in Graphics mode.
+
+
+ @param TitleForeground Foreground color for Title.
+ @param TitleBackground Background color for Title.
+ @param Title Title above progress bar.
+ @param ProgressColor Progress bar color.
+ @param Progress Progress (0-100)
+ @param PreviousValue The previous value of the progress.
+
+ @retval EFI_STATUS Success update the progress bar
+
+**/
+EFI_STATUS
+PlatformBootManagerShowProgress (
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,
+ IN CHAR16 *Title,
+ IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,
+ IN UINTN Progress,
+ IN UINTN PreviousValue
+ );
+
+#endif // _PLATFORM_BOOT_MANAGER_H
diff --git a/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c b/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
new file mode 100644
index 0000000..82cd311
--- /dev/null
+++ b/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManager.c
@@ -0,0 +1,243 @@
+/** @file
+ This file include all platform actions
+
+Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PlatformBootManager.h"
+
+
+EFI_GUID mUefiShellFileGuid = { 0x7C04A583, 0x9E3E, 0x4f1c, {0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1}};
+
+/**
+ Perform the platform diagnostic, such like test memory. OEM/IBV also
+ can customize this function to support specific platform diagnostic.
+
+ @param MemoryTestLevel The memory test intensive level
+ @param QuietBoot Indicate if need to enable the quiet boot
+
+**/
+VOID
+PlatformBootManagerDiagnostics (
+ IN EXTENDMEM_COVERAGE_LEVEL MemoryTestLevel,
+ IN BOOLEAN QuietBoot
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Here we can decide if we need to show
+ // the diagnostics screen
+ // Notes: this quiet boot code should be remove
+ // from the graphic lib
+ //
+ if (QuietBoot) {
+
+ //
+ // Perform system diagnostic
+ //
+ Status = PlatformBootManagerMemoryTest (MemoryTestLevel);
+ return;
+ }
+
+ //
+ // Perform system diagnostic
+ //
+ Status = PlatformBootManagerMemoryTest (MemoryTestLevel);
+}
+
+/**
+ Return the index of the load option in the load option array.
+
+ The function consider two load options are equal when the
+ OptionType, Attributes, Description, FilePath and OptionalData are equal.
+
+ @param Key Pointer to the load option to be found.
+ @param Array Pointer to the array of load options to be found.
+ @param Count Number of entries in the Array.
+
+ @retval -1 Key wasn't found in the Array.
+ @retval 0 ~ Count-1 The index of the Key in the Array.
+**/
+INTN
+PlatformFindLoadOption (
+ IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Key,
+ IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Array,
+ IN UINTN Count
+ )
+{
+ UINTN Index;
+
+ for (Index = 0; Index < Count; Index++) {
+ if ((Key->OptionType == Array[Index].OptionType) &&
+ (Key->Attributes == Array[Index].Attributes) &&
+ (StrCmp (Key->Description, Array[Index].Description) == 0) &&
+ (CompareMem (Key->FilePath, Array[Index].FilePath, GetDevicePathSize (Key->FilePath)) == 0) &&
+ (Key->OptionalDataSize == Array[Index].OptionalDataSize) &&
+ (CompareMem (Key->OptionalData, Array[Index].OptionalData, Key->OptionalDataSize) == 0)) {
+ return (INTN) Index;
+ }
+ }
+
+ return -1;
+}
+
+VOID
+PlatformRegisterFvBootOption (
+ EFI_GUID *FileGuid,
+ CHAR16 *Description,
+ UINT32 Attributes
+ )
+{
+ EFI_STATUS Status;
+ UINTN OptionIndex;
+ EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
+ EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
+ UINTN BootOptionCount;
+ MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
+ EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+
+ Status = gBS->HandleProtocol (gImageHandle, &gEfiLoadedImageProtocolGuid, (VOID **) &LoadedImage);
+ ASSERT_EFI_ERROR (Status);
+
+ EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid);
+ DevicePath = AppendDevicePathNode (
+ DevicePathFromHandle (LoadedImage->DeviceHandle),
+ (EFI_DEVICE_PATH_PROTOCOL *) &FileNode
+ );
+
+ Status = EfiBootManagerInitializeLoadOption (
+ &NewOption,
+ LoadOptionNumberUnassigned,
+ LoadOptionTypeBoot,
+ Attributes,
+ Description,
+ DevicePath,
+ NULL,
+ 0
+ );
+ if (!EFI_ERROR (Status)) {
+ BootOptions = EfiBootManagerGetLoadOptions (&BootOptionCount, LoadOptionTypeBoot);
+
+ OptionIndex = PlatformFindLoadOption (&NewOption, BootOptions, BootOptionCount);
+
+ if (OptionIndex == -1) {
+ Status = EfiBootManagerAddLoadOptionVariable (&NewOption, (UINTN) -1);
+ ASSERT_EFI_ERROR (Status);
+ }
+ EfiBootManagerFreeLoadOption (&NewOption);
+ EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);
+ }
+}
+
+/**
+ Do the platform specific action before the console is connected.
+
+ Such as:
+ Update console variable;
+ Register new Driver#### or Boot####;
+ Signal ReadyToLock event.
+**/
+VOID
+EFIAPI
+PlatformBootManagerBeforeConsole (
+ VOID
+ )
+{
+ UINTN Index;
+ EFI_STATUS Status;
+ EFI_INPUT_KEY Enter;
+ EFI_INPUT_KEY F2;
+ EFI_BOOT_MANAGER_LOAD_OPTION BootOption;
+
+ //
+ // Update the console variables.
+ //
+ for (Index = 0; gPlatformConsole[Index].DevicePath != NULL; Index++) {
+ DEBUG ((DEBUG_INFO, "Check gPlatformConsole %d\n", Index));
+ if ((gPlatformConsole[Index].ConnectType & CONSOLE_IN) == CONSOLE_IN) {
+ Status = EfiBootManagerUpdateConsoleVariable (ConIn, gPlatformConsole[Index].DevicePath, NULL);
+ DEBUG ((DEBUG_INFO, "CONSOLE_IN variable set %s : %r\n", ConvertDevicePathToText (gPlatformConsole[Index].DevicePath, FALSE, FALSE), Status));
+ }
+
+ if ((gPlatformConsole[Index].ConnectType & CONSOLE_OUT) == CONSOLE_OUT) {
+ Status = EfiBootManagerUpdateConsoleVariable (ConOut, gPlatformConsole[Index].DevicePath, NULL);
+ DEBUG ((DEBUG_INFO, "CONSOLE_OUT variable set %s : %r\n", ConvertDevicePathToText (gPlatformConsole[Index].DevicePath, FALSE, FALSE), Status));
+ }
+
+ if ((gPlatformConsole[Index].ConnectType & STD_ERROR) == STD_ERROR) {
+ Status = EfiBootManagerUpdateConsoleVariable (ErrOut, gPlatformConsole[Index].DevicePath, NULL);
+ DEBUG ((DEBUG_INFO, "STD_ERROR variable set %r", Status));
+ }
+ }
+
+ //
+ // Register ENTER as CONTINUE key
+ //
+ Enter.ScanCode = SCAN_NULL;
+ Enter.UnicodeChar = CHAR_CARRIAGE_RETURN;
+ EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL);
+ //
+ // Map F2 to Boot Manager Menu
+ //
+ F2.ScanCode = SCAN_F2;
+ F2.UnicodeChar = CHAR_NULL;
+ EfiBootManagerGetBootManagerMenu (&BootOption);
+ EfiBootManagerAddKeyOptionVariable (NULL, (UINT16) BootOption.OptionNumber, 0, &F2, NULL);
+ //
+ // Register UEFI Shell
+ //
+ PlatformRegisterFvBootOption (&mUefiShellFileGuid, L"UEFI Shell", LOAD_OPTION_ACTIVE);
+}
+
+/**
+ Do the platform specific action after the console is connected.
+
+ Such as:
+ Dynamically switch output mode;
+ Signal console ready platform customized event;
+ Run diagnostics like memory testing;
+ Connect certain devices;
+ Dispatch aditional option roms.
+**/
+VOID
+EFIAPI
+PlatformBootManagerAfterConsole (
+ VOID
+ )
+{
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL Black;
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL White;
+
+ Black.Blue = Black.Green = Black.Red = Black.Reserved = 0;
+ White.Blue = White.Green = White.Red = White.Reserved = 0xFF;
+
+ EfiBootManagerConnectAll ();
+ EfiBootManagerRefreshAllBootOption ();
+
+ PlatformBootManagerDiagnostics (QUICK, TRUE);
+
+ PrintXY (10, 10, &White, &Black, L"F2 to enter Boot Manager Menu. ");
+ PrintXY (10, 30, &White, &Black, L"Enter to boot directly.");
+}
+
+/**
+ The function is called when no boot option could be launched,
+ including platform recovery options and options pointing to applications
+ built into firmware volumes.
+
+ If this function returns, BDS attempts to enter an infinite loop.
+**/
+VOID
+EFIAPI
+PlatformBootManagerUnableToBoot (
+ VOID
+ )
+{
+ return;
+}
diff --git a/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c b/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c
new file mode 100644
index 0000000..3208051
--- /dev/null
+++ b/RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c
@@ -0,0 +1,49 @@
+/**@file
+ Defined the platform specific device path which will be filled to
+ ConIn/ConOut variables.
+
+Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PlatformBootManager.h"
+
+//
+// Platform specific serial device path
+//
+SERIAL_CONSOLE_DEVICE_PATH gSerialConsoleDevicePath0 = {
+ {
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0} },
+ EFI_SERIAL_DXE_GUID // Use the driver's GUID
+ },
+ {
+ { MESSAGING_DEVICE_PATH, MSG_UART_DP, { sizeof (UART_DEVICE_PATH), 0} },
+ 0, // Reserved
+ 115200, // BaudRate
+ 8, // DataBits
+ 1, // Parity
+ 1 // StopBits
+ },
+ {
+ { MESSAGING_DEVICE_PATH, MSG_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0} },
+ DEVICE_PATH_MESSAGING_PC_ANSI
+ },
+ { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } }
+};
+
+//
+// Predefined platform default console device path
+//
+PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[] = {
+ {
+ (EFI_DEVICE_PATH_PROTOCOL *) &gSerialConsoleDevicePath0,
+ CONSOLE_OUT | CONSOLE_IN
+ },
+ {
+ NULL,
+ 0
+ }
+};
diff --git a/RiscVPlatformPkg/Library/PlatformBootManagerLib/Strings.uni b/RiscVPlatformPkg/Library/PlatformBootManagerLib/Strings.uni
new file mode 100644
index 0000000..357cced
--- /dev/null
+++ b/RiscVPlatformPkg/Library/PlatformBootManagerLib/Strings.uni
@@ -0,0 +1,28 @@
+///** @file
+//
+// String definitions for PlatformBootManagerLib.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//**/
+
+/=#
+
+#langdef en-US "English"
+#langdef fr-FR "Français"
+
+#string STR_PERFORM_MEM_TEST #language en-US "Perform memory test (ESC to skip)"
+ #language fr-FR "Exécute l'examen de mémoire (ESC pour sauter)"
+#string STR_MEMORY_TEST_PERCENT #language en-US "% of the system memory tested OK"
+ #language fr-FR "% de la mémoire de système essayée D'ACCORD"
+#string STR_ESC_TO_SKIP_MEM_TEST #language en-US "Press ESC key to skip memory test"
+ #language fr-FR "Appuie sur ESC sauter examen de mémoire"
+#string STR_MEM_TEST_COMPLETED #language en-US " bytes of system memory tested OK\r\n"
+ #language fr-FR " octets dela mémoire de système essayée D'ACCORD\r\n"
+#string STR_SYSTEM_MEM_ERROR #language en-US "System encounters memory errors"
+ #language fr-FR "le Système rencontre les erreurs de mémoire"
+#string STR_START_BOOT_OPTION #language en-US "Start boot option"
+ #language fr-FR "l'option de botte de Début"
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 34/39] RiscVPkg/RiscVPlatformTimerLibNull: NULL instance of RISC-V platform timer library.
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (32 preceding siblings ...)
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 33/39] RiscVPlatformPkg/PlatformBootManagerLib: Platform Boot Manager library Abner Chang
@ 2019-10-28 1:59 ` Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 35/39] RiscVPlatformPkg/SecMain: RISC-V SecMain module Abner Chang
` (4 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:59 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
NULL instance of RISC-V platform timer library.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
.../RiscVPlatformTimerLib.inf | 35 +++++++++++++++++++
.../RiscVPlatformTimerLibNull.S | 40 ++++++++++++++++++++++
2 files changed, 75 insertions(+)
create mode 100644 RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
create mode 100644 RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S
diff --git a/RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf b/RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
new file mode 100644
index 0000000..6bf168c
--- /dev/null
+++ b/RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
@@ -0,0 +1,35 @@
+## @file
+# RISC-V CPU lib to override timer mechanism for U500 platform.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = RiscVPlatformTimerLibNull
+ FILE_GUID = 93FDB133-476E-4726-A65D-C10D5C9A68DE
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = RiscVPlatformTimerLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+
+[Sources.RISCV64]
+ RiscVPlatformTimerLibNull.S
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+
+
+
+
diff --git a/RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S b/RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S
new file mode 100644
index 0000000..815ab06
--- /dev/null
+++ b/RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S
@@ -0,0 +1,40 @@
+//------------------------------------------------------------------------------
+//
+// Null instance of Timer CSR functions.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <Base.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(RiscVReadMachineTimer)
+.global ASM_PFX(RiscVSetMachineTimerCmp)
+.global ASM_PFX(RiscVReadMachineTimerCmp)
+
+//
+// Read machine timer CSR.
+// @retval a0 : 64-bit machine timer.
+//
+ASM_PFX (RiscVReadMachineTimer):
+ ret
+
+//
+// Set machine timer compare CSR.
+// @param a0 : UINT64
+//
+ASM_PFX (RiscVSetMachineTimerCmp):
+ ret
+
+//
+// Read machine timer compare CSR.
+// @param a0 : UINT64
+//
+ASM_PFX (RiscVReadMachineTimerCmp):
+ ret
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 35/39] RiscVPlatformPkg/SecMain: RISC-V SecMain module.
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (33 preceding siblings ...)
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 34/39] RiscVPkg/RiscVPlatformTimerLibNull: NULL instance of RISC-V platform timer library Abner Chang
@ 2019-10-28 1:59 ` Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 36/39] RiscVPlatformPkg: Add RiscVPlatformPkg Abner Chang
` (3 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:59 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
From: Anup Patel <anup.patel@wdc.com>
SecMain module for RISC-V platform.
This was cloned from OpenSBI fw_base.S
(RiscVPkg/Library/RiscVOpensbiLib/opensbi/firmware/) and revised to
edk2 framework.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
RiscVPlatformPkg/Universal/Sec/SecMain.inf | 72 +++
RiscVPlatformPkg/Universal/Sec/SecMain.h | 57 +++
RiscVPlatformPkg/Universal/Sec/SecMain.c | 523 ++++++++++++++++++++++
RiscVPlatformPkg/Universal/Sec/Riscv64/SecEntry.S | 442 ++++++++++++++++++
4 files changed, 1094 insertions(+)
create mode 100644 RiscVPlatformPkg/Universal/Sec/SecMain.inf
create mode 100644 RiscVPlatformPkg/Universal/Sec/SecMain.h
create mode 100644 RiscVPlatformPkg/Universal/Sec/SecMain.c
create mode 100644 RiscVPlatformPkg/Universal/Sec/Riscv64/SecEntry.S
diff --git a/RiscVPlatformPkg/Universal/Sec/SecMain.inf b/RiscVPlatformPkg/Universal/Sec/SecMain.inf
new file mode 100644
index 0000000..7de269a
--- /dev/null
+++ b/RiscVPlatformPkg/Universal/Sec/SecMain.inf
@@ -0,0 +1,72 @@
+## @file
+# RISC-V SEC module.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001b
+ BASE_NAME = SecMain
+ FILE_GUID = df1ccef6-f301-4a63-9661-fc6030dcc880
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SecMain
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = RISCV64
+#
+
+[Sources]
+ SecMain.c
+
+[Sources.RISCV64]
+ Riscv64/SecEntry.S
+
+[Packages]
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ RiscVPkg/RiscVPkg.dec
+ RiscVPlatformPkg/RiscVPlatformPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugAgentLib
+ DebugLib
+ ExtractGuidedSectionLib
+ IoLib
+ PcdLib
+ PeCoffLib
+ PeCoffGetEntryPointLib
+ PeCoffExtraActionLib
+ PrintLib
+ RiscVCpuLib
+ RiscVOpensbiLib
+ RiscVOpensbiPlatformLib
+ SerialPortLib
+
+[Ppis]
+ gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED
+ gEfiTemporaryRamDonePpiGuid # PPI ALWAYS_PRODUCED
+
+[FixedPcd]
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize
+
+[Pcd]
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize
+
+
diff --git a/RiscVPlatformPkg/Universal/Sec/SecMain.h b/RiscVPlatformPkg/Universal/Sec/SecMain.h
new file mode 100644
index 0000000..94ea462
--- /dev/null
+++ b/RiscVPlatformPkg/Universal/Sec/SecMain.h
@@ -0,0 +1,57 @@
+/** @file
+ RISC-V SEC phase module definitions..
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef SECMAIN_H_
+#define SECMAIN_H_
+
+#include <PiPei.h>
+#include <Library/PeimEntryPoint.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugAgentLib.h>
+#include <Library/DebugLib.h>
+#include <Library/ExtractGuidedSectionLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeCoffExtraActionLib.h>
+#include <Library/PeCoffGetEntryPointLib.h>
+#include <Library/PeCoffLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/RiscVCpuLib.h>
+#include <Ppi/TemporaryRamDone.h>
+#include <Ppi/TemporaryRamSupport.h>
+
+VOID
+SecMachineModeTrapHandler (
+ IN VOID
+ );
+
+VOID
+EFIAPI
+SecStartupPhase2 (
+ IN VOID *Context
+ );
+
+EFI_STATUS
+EFIAPI
+TemporaryRamMigration (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
+ IN UINTN CopySize
+ );
+
+EFI_STATUS
+EFIAPI
+TemporaryRamDone (
+ VOID
+ );
+
+#endif // _SECMAIN_H_
diff --git a/RiscVPlatformPkg/Universal/Sec/SecMain.c b/RiscVPlatformPkg/Universal/Sec/SecMain.c
new file mode 100644
index 0000000..de33449
--- /dev/null
+++ b/RiscVPlatformPkg/Universal/Sec/SecMain.c
@@ -0,0 +1,523 @@
+/** @file
+ RISC-V SEC phase module.
+
+ Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "SecMain.h"
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/PrintLib.h>
+#include <sbi/sbi.h> // Reference to header file in Include/sbi
+#include <sbi/sbi_console.h> // Reference to header file in opensbi
+#include <sbi/sbi_hart.h> // Reference to header file in opensbi
+#include <sbi/sbi_scratch.h> // Reference to header file in opensbi
+#include <sbi/sbi_platform.h> // Reference to header file in opensbi
+#include <sbi/sbi_init.h> // Reference to header file in opensbi
+#include <sbi/SbiFirmwareContext.h> // Reference to header file in Include/sbi
+
+#define DEBUG_MSG_HART_INFO 0
+
+UINTN HartsIn = 0;
+
+STATIC EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = {
+ TemporaryRamMigration
+};
+
+STATIC EFI_PEI_TEMPORARY_RAM_DONE_PPI mTemporaryRamDonePpi = {
+ TemporaryRamDone
+};
+
+STATIC EFI_PEI_PPI_DESCRIPTOR mPrivateDispatchTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gEfiTemporaryRamSupportPpiGuid,
+ &mTemporaryRamSupportPpi
+ },
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiTemporaryRamDonePpiGuid,
+ &mTemporaryRamDonePpi
+ },
+};
+
+/**
+ Locates a section within a series of sections
+ with the specified section type.
+
+ The Instance parameter indicates which instance of the section
+ type to return. (0 is first instance, 1 is second...)
+
+ @param[in] Sections The sections to search
+ @param[in] SizeOfSections Total size of all sections
+ @param[in] SectionType The section type to locate
+ @param[in] Instance The section instance number
+ @param[out] FoundSection The FFS section if found
+
+ @retval EFI_SUCCESS The file and section was found
+ @retval EFI_NOT_FOUND The file and section was not found
+ @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
+
+**/
+EFI_STATUS
+FindFfsSectionInstance (
+ IN VOID *Sections,
+ IN UINTN SizeOfSections,
+ IN EFI_SECTION_TYPE SectionType,
+ IN UINTN Instance,
+ OUT EFI_COMMON_SECTION_HEADER **FoundSection
+ )
+{
+ EFI_PHYSICAL_ADDRESS CurrentAddress;
+ UINT32 Size;
+ EFI_PHYSICAL_ADDRESS EndOfSections;
+ EFI_COMMON_SECTION_HEADER *Section;
+ EFI_PHYSICAL_ADDRESS EndOfSection;
+
+ //
+ // Loop through the FFS file sections within the PEI Core FFS file
+ //
+ EndOfSection = (EFI_PHYSICAL_ADDRESS)(UINTN) Sections;
+ EndOfSections = EndOfSection + SizeOfSections;
+ for (;;) {
+ if (EndOfSection == EndOfSections) {
+ break;
+ }
+ CurrentAddress = (EndOfSection + 3) & ~(3ULL);
+ if (CurrentAddress >= EndOfSections) {
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ Section = (EFI_COMMON_SECTION_HEADER*)(UINTN) CurrentAddress;
+
+ Size = SECTION_SIZE (Section);
+ if (Size < sizeof (*Section)) {
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ EndOfSection = CurrentAddress + Size;
+ if (EndOfSection > EndOfSections) {
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ //
+ // Look for the requested section type
+ //
+ if (Section->Type == SectionType) {
+ if (Instance == 0) {
+ *FoundSection = Section;
+ return EFI_SUCCESS;
+ } else {
+ Instance--;
+ }
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/**
+ Locates a section within a series of sections
+ with the specified section type.
+
+ @param[in] Sections The sections to search
+ @param[in] SizeOfSections Total size of all sections
+ @param[in] SectionType The section type to locate
+ @param[out] FoundSection The FFS section if found
+
+ @retval EFI_SUCCESS The file and section was found
+ @retval EFI_NOT_FOUND The file and section was not found
+ @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
+
+**/
+EFI_STATUS
+FindFfsSectionInSections (
+ IN VOID *Sections,
+ IN UINTN SizeOfSections,
+ IN EFI_SECTION_TYPE SectionType,
+ OUT EFI_COMMON_SECTION_HEADER **FoundSection
+ )
+{
+ return FindFfsSectionInstance (
+ Sections,
+ SizeOfSections,
+ SectionType,
+ 0,
+ FoundSection
+ );
+}
+
+/**
+ Locates a FFS file with the specified file type and a section
+ within that file with the specified section type.
+
+ @param[in] Fv The firmware volume to search
+ @param[in] FileType The file type to locate
+ @param[in] SectionType The section type to locate
+ @param[out] FoundSection The FFS section if found
+
+ @retval EFI_SUCCESS The file and section was found
+ @retval EFI_NOT_FOUND The file and section was not found
+ @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
+
+**/
+EFI_STATUS
+FindFfsFileAndSection (
+ IN EFI_FIRMWARE_VOLUME_HEADER *Fv,
+ IN EFI_FV_FILETYPE FileType,
+ IN EFI_SECTION_TYPE SectionType,
+ OUT EFI_COMMON_SECTION_HEADER **FoundSection
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS CurrentAddress;
+ EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume;
+ EFI_FFS_FILE_HEADER *File;
+ UINT32 Size;
+ EFI_PHYSICAL_ADDRESS EndOfFile;
+
+ if (Fv->Signature != EFI_FVH_SIGNATURE) {
+ DEBUG ((DEBUG_ERROR, "%a: FV at %p does not have FV header signature\n", __FUNCTION__, Fv));
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ CurrentAddress = (EFI_PHYSICAL_ADDRESS)(UINTN) Fv;
+ EndOfFirmwareVolume = CurrentAddress + Fv->FvLength;
+
+ //
+ // Loop through the FFS files in the Boot Firmware Volume
+ //
+ for (EndOfFile = CurrentAddress + Fv->HeaderLength; ; ) {
+
+ CurrentAddress = (EndOfFile + 7) & ~(7ULL);
+ if (CurrentAddress > EndOfFirmwareVolume) {
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ File = (EFI_FFS_FILE_HEADER*)(UINTN) CurrentAddress;
+ Size = *(UINT32*) File->Size & 0xffffff;
+ if (Size < (sizeof (*File) + sizeof (EFI_COMMON_SECTION_HEADER))) {
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ EndOfFile = CurrentAddress + Size;
+ if (EndOfFile > EndOfFirmwareVolume) {
+ return EFI_VOLUME_CORRUPTED;
+ }
+
+ //
+ // Look for the request file type
+ //
+ if (File->Type != FileType) {
+ continue;
+ }
+
+ Status = FindFfsSectionInSections (
+ (VOID*) (File + 1),
+ (UINTN) EndOfFile - (UINTN) (File + 1),
+ SectionType,
+ FoundSection
+ );
+ if (!EFI_ERROR (Status) || (Status == EFI_VOLUME_CORRUPTED)) {
+ return Status;
+ }
+ }
+}
+
+/**
+ Locates the PEI Core entry point address
+
+ @param[in] Fv The firmware volume to search
+ @param[out] PeiCoreEntryPoint The entry point of the PEI Core image
+
+ @retval EFI_SUCCESS The file and section was found
+ @retval EFI_NOT_FOUND The file and section was not found
+ @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
+
+**/
+EFI_STATUS
+FindPeiCoreImageBaseInFv (
+ IN EFI_FIRMWARE_VOLUME_HEADER *Fv,
+ OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase
+ )
+{
+ EFI_STATUS Status;
+ EFI_COMMON_SECTION_HEADER *Section;
+
+ Status = FindFfsFileAndSection (
+ Fv,
+ EFI_FV_FILETYPE_PEI_CORE,
+ EFI_SECTION_PE32,
+ &Section
+ );
+ if (EFI_ERROR (Status)) {
+ Status = FindFfsFileAndSection (
+ Fv,
+ EFI_FV_FILETYPE_PEI_CORE,
+ EFI_SECTION_TE,
+ &Section
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "%a: Unable to find PEI Core image\n", __FUNCTION__));
+ return Status;
+ }
+ }
+ DEBUG ((DEBUG_INFO, "%a: PeiCoreImageBase found\n", __FUNCTION__));
+ *PeiCoreImageBase = (EFI_PHYSICAL_ADDRESS)(UINTN)(Section + 1);
+ return EFI_SUCCESS;
+}
+
+/**
+ Locates the PEI Core entry point address
+
+ @param[in,out] Fv The firmware volume to search
+ @param[out] PeiCoreEntryPoint The entry point of the PEI Core image
+
+ @retval EFI_SUCCESS The file and section was found
+ @retval EFI_NOT_FOUND The file and section was not found
+ @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted
+
+**/
+VOID
+FindPeiCoreImageBase (
+ IN OUT EFI_FIRMWARE_VOLUME_HEADER **BootFv,
+ OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase
+ )
+{
+ *PeiCoreImageBase = 0;
+
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+ FindPeiCoreImageBaseInFv (*BootFv, PeiCoreImageBase);
+}
+
+/*
+ Find and return Pei Core entry point.
+
+ It also find SEC and PEI Core file debug inforamtion. It will report them if
+ remote debug is enabled.
+
+**/
+VOID
+FindAndReportEntryPoints (
+ IN EFI_FIRMWARE_VOLUME_HEADER **BootFirmwareVolumePtr,
+ OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint
+ )
+{
+ EFI_STATUS Status;
+ EFI_PHYSICAL_ADDRESS PeiCoreImageBase;
+
+ DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
+
+ FindPeiCoreImageBase (BootFirmwareVolumePtr, &PeiCoreImageBase);
+ //
+ // Find PEI Core entry point
+ //
+ Status = PeCoffLoaderGetEntryPoint ((VOID *) (UINTN) PeiCoreImageBase, (VOID**) PeiCoreEntryPoint);
+ if (EFI_ERROR(Status)) {
+ *PeiCoreEntryPoint = 0;
+ }
+ DEBUG ((DEBUG_INFO, "%a: PeCoffLoaderGetEntryPoint success: %x\n", __FUNCTION__, *PeiCoreEntryPoint));
+
+ return;
+}
+/*
+ Print out the content of firmware context.
+
+**/
+VOID
+DebutPrintFirmwareContext (
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext
+ )
+{
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI Firmware Context at 0x%x\n", __FUNCTION__, FirmwareContext));
+ DEBUG ((DEBUG_INFO, "%a: PEI Service at 0x%x\n\n", __FUNCTION__, FirmwareContext->PeiServiceTable));
+}
+
+EFI_STATUS
+EFIAPI
+TemporaryRamMigration (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
+ IN UINTN CopySize
+ )
+{
+ VOID *OldHeap;
+ VOID *NewHeap;
+ VOID *OldStack;
+ VOID *NewStack;
+ struct sbi_platform *ThisSbiPlatform;
+
+ DEBUG ((DEBUG_INFO,
+ "%a: TemporaryRamMigration(0x%Lx, 0x%Lx, 0x%Lx)\n",
+ __FUNCTION__,
+ TemporaryMemoryBase,
+ PermanentMemoryBase,
+ (UINT64)CopySize
+ ));
+
+ OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;
+ NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize >> 1));
+
+ OldStack = (VOID*)((UINTN)TemporaryMemoryBase + (CopySize >> 1));
+ NewStack = (VOID*)(UINTN)PermanentMemoryBase;
+
+ CopyMem (NewHeap, OldHeap, CopySize >> 1); // Migrate Heap
+ CopyMem (NewStack, OldStack, CopySize >> 1); // Migrate Stack
+
+ //
+ // Reset firmware context pointer
+ //
+ ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_thishart_ptr());
+ ThisSbiPlatform->firmware_context += (unsigned long)((UINTN)NewStack - (UINTN)OldStack);
+ //
+ // Relocate PEI Service **
+ //
+ ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatform->firmware_context)->PeiServiceTable += (unsigned long)((UINTN)NewStack - (UINTN)OldStack);
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI Firmware Context is relocated to 0x%x\n", __FUNCTION__, ThisSbiPlatform->firmware_context));
+ DebutPrintFirmwareContext ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatform->firmware_context);
+
+ register uintptr_t a0 asm ("a0") = (uintptr_t)((UINTN)NewStack - (UINTN)OldStack);
+ asm volatile ("add sp, sp, a0"::"r"(a0):);
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS EFIAPI TemporaryRamDone (VOID)
+{
+ DEBUG ((DEBUG_INFO, "%a: 2nd time PEI core, temporary ram done.\n", __FUNCTION__));
+ return EFI_SUCCESS;
+}
+
+static VOID EFIAPI PeiCore(VOID)
+{
+ EFI_SEC_PEI_HAND_OFF SecCoreData;
+ EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint;
+ EFI_FIRMWARE_VOLUME_HEADER *BootFv = (EFI_FIRMWARE_VOLUME_HEADER *)FixedPcdGet32(PcdRiscVPeiFvBase);
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT FirmwareContext;
+ struct sbi_platform *ThisSbiPlatform;
+ UINT32 HartId;
+
+ FindAndReportEntryPoints (&BootFv, &PeiCoreEntryPoint);
+
+ SecCoreData.DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
+ SecCoreData.BootFirmwareVolumeBase = BootFv;
+ SecCoreData.BootFirmwareVolumeSize = (UINTN) BootFv->FvLength;
+ SecCoreData.TemporaryRamBase = (VOID*)(UINT64) FixedPcdGet32(PcdTemporaryRamBase);
+ SecCoreData.TemporaryRamSize = (UINTN) FixedPcdGet32(PcdTemporaryRamSize);
+ SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;
+ SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize >> 1;
+ SecCoreData.StackBase = (UINT8 *)SecCoreData.TemporaryRamBase + (SecCoreData.TemporaryRamSize >> 1);
+ SecCoreData.StackSize = SecCoreData.TemporaryRamSize >> 1;
+
+ //
+ // Print out scratch address of each hart
+ //
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI scratch address for each hart:\n", __FUNCTION__));
+ for (HartId = 0; HartId < FixedPcdGet32 (PcdHartCount); HartId ++) {
+ DEBUG ((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, sbi_hart_id_to_scratch(sbi_scratch_thishart_ptr(), HartId)));
+ }
+
+ //
+ // Set up OpepSBI firmware context poitner on boot hart OpenSbi scratch. Firmware context residents in stack and will be
+ // switched to memory when temporary ram migration.
+ //
+ ZeroMem ((VOID *)&FirmwareContext, sizeof (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT));
+ ThisSbiPlatform = (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_thishart_ptr());
+ if (ThisSbiPlatform->opensbi_version > OPENSBI_VERSION) {
+ DEBUG ((DEBUG_ERROR, "%a: OpenSBI platform table version 0x%x is newer than OpenSBI version 0x%x.\n"
+ "There maybe be some backward compatable issues.\n",
+ __FUNCTION__,
+ ThisSbiPlatform->opensbi_version,
+ OPENSBI_VERSION
+ ));
+ ASSERT(FALSE);
+ }
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI platform table at address: 0x%x\nFirmware Context is located at 0x%x\n",
+ __FUNCTION__,
+ ThisSbiPlatform,
+ &FirmwareContext
+ ));
+ ThisSbiPlatform->firmware_context = (unsigned long)&FirmwareContext;
+ //
+ // Set firmware context Hart-specific pointer
+ //
+ for (HartId = 0; HartId < FixedPcdGet32 (PcdHartCount); HartId ++) {
+ FirmwareContext.HartSpecific [HartId] = \
+ (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)sbi_hart_id_to_scratch(sbi_scratch_thishart_ptr(), HartId) - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE);
+ DEBUG ((DEBUG_INFO, "%a: OpenSBI Hart %d Firmware Context Hart-specific at address: 0x%x\n",
+ __FUNCTION__,
+ HartId,
+ FirmwareContext.HartSpecific [HartId]
+ ));
+ }
+
+ //
+ // Transfer the control to the PEI core
+ //
+ (*PeiCoreEntryPoint) (&SecCoreData, (EFI_PEI_PPI_DESCRIPTOR *)&mPrivateDispatchTable);
+}
+/**
+ This function initilizes hart specific information and SBI.
+ For the boot hart, it boots system through PEI core and initial SBI in the DXE IPL.
+ For others, it goes to initial SBI and halt.
+
+ the lay out of memory region for each hart is as below delineates,
+
+ _ ____
+ |----Scratch ends | |
+ | | sizeof (sbi_scratch) |
+ | _| |
+ |----Scratch buffer start s <----- *scratch |
+ |----Firmware Context Hart-specific ends _ |
+ | | |
+ | | FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE |
+ | | | PcdOpenSbiStackSize
+ | _| |
+ |----Firmware Context Hart-specific starts <----- **HartFirmwareContext |
+ |----Hart stack top _ |
+ | | |
+ | | |
+ | | Stack |
+ | | |
+ | _| ____|
+ |----Hart stack bottom
+
+**/
+VOID EFIAPI SecCoreStartUpWithStack(UINTN hartid, struct sbi_scratch *scratch)
+{
+ EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext;
+
+ //
+ // Setup EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC for each hart.
+ //
+ HartFirmwareContext = (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)scratch - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE);
+ HartFirmwareContext->IsaExtensionSupported = RiscVReadMisa ();
+ HartFirmwareContext->MachineVendorId.Value64_L = RiscVReadMVendorId ();
+ HartFirmwareContext->MachineVendorId.Value64_H = 0;
+ HartFirmwareContext->MachineArchId.Value64_L = RiscVReadMArchId ();
+ HartFirmwareContext->MachineArchId.Value64_H = 0;
+ HartFirmwareContext->MachineImplId.Value64_L = RiscVReadMImplId ();
+ HartFirmwareContext->MachineImplId.Value64_H = 0;
+
+#if DEBUG_MSG_HART_INFO
+ while (HartsIn != hartid);
+ DEBUG ((DEBUG_INFO, "Initial Firmware Context Hart-specific for HART ID:%d\n", hartid));
+ DEBUG ((DEBUG_INFO, " Scratch at address: 0x%x\n", scratch));
+ DEBUG ((DEBUG_INFO, " Firmware Context Hart-specific at address: 0x%x\n", HartFirmwareContext));
+ DEBUG ((DEBUG_INFO, " stack pointer at address: 0x%x\n", stack_point));
+ DEBUG ((DEBUG_INFO, " MISA: 0x%x\n", HartFirmwareContext->IsaExtensionSupported));
+ DEBUG ((DEBUG_INFO, " MVENDORID: 0x%x\n", HartFirmwareContext->MachineVendorId.Value64_L));
+ DEBUG ((DEBUG_INFO, " MARCHID: 0x%x\n", HartFirmwareContext->MachineArchId.Value64_L));
+ DEBUG ((DEBUG_INFO, " MIMPID: 0x%x\n\n", HartFirmwareContext->MachineImplId.Value64_L));
+ HartsIn ++;
+ for (;;);
+#endif
+ if (hartid == FixedPcdGet32(PcdBootHartId)) {
+ sbi_console_init(scratch); // Initial OpenSBI internal serial console on boot Hart.
+ PeiCore();
+ }
+ sbi_init(scratch);
+}
diff --git a/RiscVPlatformPkg/Universal/Sec/Riscv64/SecEntry.S b/RiscVPlatformPkg/Universal/Sec/Riscv64/SecEntry.S
new file mode 100644
index 0000000..83793ed
--- /dev/null
+++ b/RiscVPlatformPkg/Universal/Sec/Riscv64/SecEntry.S
@@ -0,0 +1,442 @@
+/*
+ * Copyright (c) 2019 , Hewlett Packard Enterprise Development LP. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ */
+
+#include <Base.h>
+#include <RiscVImpl.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/riscv_encoding.h>
+#include <sbi/sbi_platform.h>
+#include <sbi/sbi_scratch.h>
+#include <sbi/sbi_trap.h>
+
+#include <SecMain.h>
+#include <sbi/SbiFirmwareContext.h>
+
+.text
+.align 3
+.global ASM_PFX(_ModuleEntryPoint)
+ASM_PFX(_ModuleEntryPoint):
+ /*
+ * Jump to warm-boot if this is not the selected core booting,
+ */
+ csrr a6, CSR_MHARTID
+ li a5, FixedPcdGet32 (PcdBootHartId)
+ bne a6, a5, _wait_for_boot_hart
+
+ li ra, 0
+ call _reset_regs
+
+ /* Preload HART details
+ * s7 -> HART Count
+ * s8 -> HART Stack Size
+ */
+ li s7, FixedPcdGet32 (PcdHartCount)
+ li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
+
+ /* Setup scratch space for all the HARTs*/
+ li tp, FixedPcdGet32 (PcdScratchRamBase)
+ mul a5, s7, s8
+ add tp, tp, a5
+
+ /* Keep a copy of tp */
+ add t3, tp, zero
+
+ /* Counter */
+ li t2, 1
+
+ /* hartid 0 is mandated by ISA */
+ li t1, 0
+_scratch_init:
+ add tp, t3, zero
+ mul a5, s8, t1
+ sub tp, tp, a5
+ li a5, SBI_SCRATCH_SIZE
+ sub tp, tp, a5
+
+ /* Initialize scratch space */
+ li a4, FixedPcdGet32 (PcdFwStartAddress)
+ li a5, FixedPcdGet32 (PcdFwEndAddress)
+ sub a5, a5, a4
+ sd a4, SBI_SCRATCH_FW_START_OFFSET(tp)
+ sd a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp)
+
+ /* Note: fw_next_arg1() uses a0, a1, and ra */
+ call fw_next_arg1
+ sd a0, SBI_SCRATCH_NEXT_ARG1_OFFSET(tp)
+
+ /* Note: fw_next_addr() uses a0, a1, and ra */
+ call fw_next_addr
+ sd a0, SBI_SCRATCH_NEXT_ADDR_OFFSET(tp)
+
+ li a4, PRV_S
+ sd a4, SBI_SCRATCH_NEXT_MODE_OFFSET(tp)
+ la a4, _start_warm
+ sd a4, SBI_SCRATCH_WARMBOOT_ADDR_OFFSET(tp)
+ la a4, platform
+ sd a4, SBI_SCRATCH_PLATFORM_ADDR_OFFSET(tp)
+ la a4, _hartid_to_scratch
+ sd a4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp)
+ sd zero, SBI_SCRATCH_TMP0_OFFSET(tp)
+
+#ifdef FW_OPTIONS
+ li a4, FW_OPTIONS
+ sd a4, SBI_SCRATCH_OPTIONS_OFFSET(tp)
+#else
+ sd zero, SBI_SCRATCH_OPTIONS_OFFSET(tp)
+#endif
+
+ add t1, t1, t2
+ blt t1, s7, _scratch_init
+
+ /* Fill-out temporary memory with 55aa*/
+ li a4, FixedPcdGet32 (PcdTemporaryRamBase)
+ li a5, FixedPcdGet32 (PcdTemporaryRamSize)
+ add a5, a4, a5
+1:
+ li a3, 0x5AA55AA55AA55AA5
+ sd a3, (a4)
+ add a4, a4, __SIZEOF_POINTER__
+ blt a4, a5, 1b
+
+ /* Update boot hart flag */
+ la a4, _boot_hart_done
+ li a5, 1
+ sd a5, (a4)
+
+ /* Wait for boot hart */
+_wait_for_boot_hart:
+ la a4, _boot_hart_done
+ ld a5, (a4)
+
+ /* Reduce the bus traffic so that boot hart may proceed faster */
+ nop
+ nop
+ nop
+ beqz a5, _wait_for_boot_hart
+
+_start_warm:
+ li ra, 0
+ call _reset_regs
+
+ /* Disable and clear all interrupts */
+ csrw CSR_MIE, zero
+ csrw CSR_MIP, zero
+
+ li s7, FixedPcdGet32 (PcdHartCount)
+ li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
+
+ /* HART ID should be within expected limit */
+ csrr s6, CSR_MHARTID
+ bge s6, s7, _start_hang
+
+ /* find the scratch space for this hart */
+ li tp, FixedPcdGet32 (PcdScratchRamBase)
+ mul a5, s7, s8
+ add tp, tp, a5
+ mul a5, s8, s6
+ sub tp, tp, a5
+ li a5, SBI_SCRATCH_SIZE
+ sub tp, tp, a5
+
+ /* update the mscratch */
+ csrw CSR_MSCRATCH, tp
+
+ /*make room for Hart specific Firmware Context*/
+ li a5, FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE
+ sub tp, tp, a5
+
+ /* Setup stack */
+ add sp, tp, zero
+
+ /* Setup stack for the Hart executing EFI to top of temporary ram*/
+ csrr a6, CSR_MHARTID
+ li a5, FixedPcdGet32 (PcdBootHartId)
+ bne a6, a5, 1f
+
+ li a4, FixedPcdGet32(PcdTemporaryRamBase)
+ li a5, FixedPcdGet32(PcdTemporaryRamSize)
+ add sp, a4, a5
+ 1:
+
+ /* Setup trap handler */
+ la a4, _trap_handler
+ csrw CSR_MTVEC, a4
+
+ /* Make sure that mtvec is updated */
+ 1:
+ csrr a5, CSR_MTVEC
+ bne a4, a5, 1b
+
+ /* Call library constructors before jup to SEC core */
+ call ProcessLibraryConstructorList
+
+ /* jump to SEC Core C */
+ csrr a0, CSR_MHARTID
+ csrr a1, CSR_MSCRATCH
+ call SecCoreStartUpWithStack
+
+ /* We do not expect to reach here hence just hang */
+ j _start_hang
+
+ .align 3
+ .section .data, "aw"
+_boot_hart_done:
+ RISCV_PTR 0
+
+ .align 3
+ .section .entry, "ax", %progbits
+ .globl _hartid_to_scratch
+_hartid_to_scratch:
+ add sp, sp, -(3 * __SIZEOF_POINTER__)
+ sd s0, (sp)
+ sd s1, (__SIZEOF_POINTER__)(sp)
+ sd s2, (__SIZEOF_POINTER__ * 2)(sp)
+
+ /*
+ * a0 -> HART ID (passed by caller)
+ * s0 -> HART Stack Size
+ * s1 -> HART Stack End
+ * s2 -> Temporary
+ */
+ la s2, platform
+#if __riscv_xlen == 64
+ lwu s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2)
+ lwu s2, SBI_PLATFORM_HART_COUNT_OFFSET(s2)
+#else
+ lw s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2)
+ lw s2, SBI_PLATFORM_HART_COUNT_OFFSET(s2)
+#endif
+ mul s2, s2, s0
+ li s1, FixedPcdGet32 (PcdScratchRamBase)
+ add s1, s1, s2
+ mul s2, s0, a0
+ sub s1, s1, s2
+ li s2, SBI_SCRATCH_SIZE
+ sub a0, s1, s2
+ ld s0, (sp)
+ ld s1, (__SIZEOF_POINTER__)(sp)
+ ld s2, (__SIZEOF_POINTER__ * 2)(sp)
+ add sp, sp, (3 * __SIZEOF_POINTER__)
+ ret
+
+ .align 3
+ .section .entry, "ax", %progbits
+ .globl _start_hang
+_start_hang:
+ wfi
+ j _start_hang
+
+ .align 3
+ .section .entry, "ax", %progbits
+ .globl _trap_handler
+_trap_handler:
+
+ /* Swap TP and MSCRATCH */
+ csrrw tp, CSR_MSCRATCH, tp
+
+ /* Save T0 in scratch space */
+ sd t0, SBI_SCRATCH_TMP0_OFFSET(tp)
+
+ /* Check which mode we came from */
+ csrr t0, CSR_MSTATUS
+ srl t0, t0, MSTATUS_MPP_SHIFT
+ and t0, t0, PRV_M
+ xori t0, t0, PRV_M
+ beq t0, zero, _trap_handler_m_mode
+
+ /* We came from S-mode or U-mode */
+_trap_handler_s_mode:
+ /* Set T0 to original SP */
+ add t0, sp, zero
+
+ /* Setup exception stack */
+ add sp, tp, -(SBI_TRAP_REGS_SIZE)
+
+ /* Jump to code common for all modes */
+ j _trap_handler_all_mode
+
+ /* We came from M-mode */
+_trap_handler_m_mode:
+ /* Set T0 to original SP */
+ add t0, sp, zero
+
+ /* Re-use current SP as exception stack */
+ add sp, sp, -(SBI_TRAP_REGS_SIZE)
+
+_trap_handler_all_mode:
+ /* Save original SP (from T0) on stack */
+ sd t0, SBI_TRAP_REGS_OFFSET(sp)(sp)
+
+ /* Restore T0 from scratch space */
+ ld t0, SBI_SCRATCH_TMP0_OFFSET(tp)
+
+ /* Save T0 on stack */
+ sd t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
+
+ /* Swap TP and MSCRATCH */
+ csrrw tp, CSR_MSCRATCH, tp
+
+ /* Save MEPC and MSTATUS CSRs */
+ csrr t0, CSR_MEPC
+ sd t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
+ csrr t0, CSR_MSTATUS
+ sd t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
+
+ /* Save all general regisers except SP and T0 */
+ sd zero, SBI_TRAP_REGS_OFFSET(zero)(sp)
+ sd ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
+ sd gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
+ sd tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
+ sd t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
+ sd t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
+ sd s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
+ sd s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
+ sd a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
+ sd a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
+ sd a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
+ sd a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
+ sd a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
+ sd a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
+ sd a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
+ sd a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
+ sd s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
+ sd s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
+ sd s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
+ sd s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
+ sd s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
+ sd s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
+ sd s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
+ sd s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
+ sd s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
+ sd s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
+ sd t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
+ sd t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
+ sd t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
+ sd t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
+
+ /* Call C routine */
+ add a0, sp, zero
+ csrr a1, CSR_MSCRATCH
+ call sbi_trap_handler
+
+ /* Restore all general regisers except SP and T0 */
+ ld ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
+ ld gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
+ ld tp, SBI_TRAP_REGS_OFFSET(tp)(sp)
+ ld t1, SBI_TRAP_REGS_OFFSET(t1)(sp)
+ ld t2, SBI_TRAP_REGS_OFFSET(t2)(sp)
+ ld s0, SBI_TRAP_REGS_OFFSET(s0)(sp)
+ ld s1, SBI_TRAP_REGS_OFFSET(s1)(sp)
+ ld a0, SBI_TRAP_REGS_OFFSET(a0)(sp)
+ ld a1, SBI_TRAP_REGS_OFFSET(a1)(sp)
+ ld a2, SBI_TRAP_REGS_OFFSET(a2)(sp)
+ ld a3, SBI_TRAP_REGS_OFFSET(a3)(sp)
+ ld a4, SBI_TRAP_REGS_OFFSET(a4)(sp)
+ ld a5, SBI_TRAP_REGS_OFFSET(a5)(sp)
+ ld a6, SBI_TRAP_REGS_OFFSET(a6)(sp)
+ ld a7, SBI_TRAP_REGS_OFFSET(a7)(sp)
+ ld s2, SBI_TRAP_REGS_OFFSET(s2)(sp)
+ ld s3, SBI_TRAP_REGS_OFFSET(s3)(sp)
+ ld s4, SBI_TRAP_REGS_OFFSET(s4)(sp)
+ ld s5, SBI_TRAP_REGS_OFFSET(s5)(sp)
+ ld s6, SBI_TRAP_REGS_OFFSET(s6)(sp)
+ ld s7, SBI_TRAP_REGS_OFFSET(s7)(sp)
+ ld s8, SBI_TRAP_REGS_OFFSET(s8)(sp)
+ ld s9, SBI_TRAP_REGS_OFFSET(s9)(sp)
+ ld s10, SBI_TRAP_REGS_OFFSET(s10)(sp)
+ ld s11, SBI_TRAP_REGS_OFFSET(s11)(sp)
+ ld t3, SBI_TRAP_REGS_OFFSET(t3)(sp)
+ ld t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
+ ld t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
+ ld t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
+
+ /* Restore MEPC and MSTATUS CSRs */
+ ld t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
+ csrw CSR_MEPC, t0
+ ld t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
+ csrw CSR_MSTATUS, t0
+
+ /* Restore T0 */
+ ld t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
+
+ /* Restore SP */
+ ld sp, SBI_TRAP_REGS_OFFSET(sp)(sp)
+
+ mret
+
+ .align 3
+ .section .entry, "ax", %progbits
+ .globl _reset_regs
+_reset_regs:
+
+ /* flush the instruction cache */
+ fence.i
+
+ /* Reset all registers except ra, a0,a1 */
+ li sp, 0
+ li gp, 0
+ li tp, 0
+ li t0, 0
+ li t1, 0
+ li t2, 0
+ li s0, 0
+ li s1, 0
+ li a2, 0
+ li a3, 0
+ li a4, 0
+ li a5, 0
+ li a6, 0
+ li a7, 0
+ li s2, 0
+ li s3, 0
+ li s4, 0
+ li s5, 0
+ li s6, 0
+ li s7, 0
+ li s8, 0
+ li s9, 0
+ li s10, 0
+ li s11, 0
+ li t3, 0
+ li t4, 0
+ li t5, 0
+ li t6, 0
+ csrw CSR_MSCRATCH, 0
+ ret
+
+ .align 3
+ .section .entry, "ax", %progbits
+ .global fw_prev_arg1
+fw_prev_arg1:
+
+ /* We return previous arg1 in 'a0' */
+ add a0, zero, zero
+ ret
+
+ .align 3
+ .section .entry, "ax", %progbits
+ .global fw_next_arg1
+fw_next_arg1:
+ /* We return next arg1 in 'a0' */
+ li a0, FixedPcdGet32(PcdRiscVPeiFvBase)
+ ret
+
+ .align 3
+ .section .entry, "ax", %progbits
+ .global fw_next_addr
+fw_next_addr:
+ /* We return next address in 'a0' */
+ la a0, _jump_addr
+ ld a0, (a0)
+ ret
+
+ .align 3
+ .section .entry, "ax", %progbits
+_jump_addr:
+RISCV_PTR SecCoreStartUpWithStack
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 36/39] RiscVPlatformPkg: Add RiscVPlatformPkg
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (34 preceding siblings ...)
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 35/39] RiscVPlatformPkg/SecMain: RISC-V SecMain module Abner Chang
@ 2019-10-28 1:59 ` Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 37/39] edk2-staging:RISC-V-V2: Add RiscVEdk2Readme.md Abner Chang
` (2 subsequent siblings)
38 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:59 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
Add RISC-V platform package.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
RiscVPlatformPkg/RiscVPlatformPkg.dec | 72 +++++++++++++++++++++++++++
RiscVPlatformPkg/RiscVPlatformPkg.dsc | 73 ++++++++++++++++++++++++++++
RiscVPlatformPkg/Readme.md | 78 ++++++++++++++++++++++++++++++
RiscVPlatformPkg/RiscVPlatformPkg.uni | 15 ++++++
| 12 +++++
5 files changed, 250 insertions(+)
create mode 100644 RiscVPlatformPkg/RiscVPlatformPkg.dec
create mode 100644 RiscVPlatformPkg/RiscVPlatformPkg.dsc
create mode 100644 RiscVPlatformPkg/Readme.md
create mode 100644 RiscVPlatformPkg/RiscVPlatformPkg.uni
create mode 100644 RiscVPlatformPkg/RiscVPlatformPkgExtra.uni
diff --git a/RiscVPlatformPkg/RiscVPlatformPkg.dec b/RiscVPlatformPkg/RiscVPlatformPkg.dec
new file mode 100644
index 0000000..da7f846
--- /dev/null
+++ b/RiscVPlatformPkg/RiscVPlatformPkg.dec
@@ -0,0 +1,72 @@
+## @file RiscVPlatformPkg.dec
+# This Package provides UEFI RISC-V platform modules and libraries.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION = 0x0001001b
+ PACKAGE_NAME = RiscVPlatformPkg
+ PACKAGE_UNI_FILE = RiscVPlatformPkg.uni
+ PACKAGE_GUID = 6A67AF99-4592-40F8-B6BE-62BCA10DA1EC
+ PACKAGE_VERSION = 1.0
+
+[Includes]
+ Include
+
+[LibraryClasses]
+
+[LibraryClasses.RISCV32, LibraryClasses.RISCV64]
+
+[Guids]
+ gUefiRiscVPlatformPkgTokenSpaceGuid = {0x6A67AF99, 0x4592, 0x40F8, { 0xB6, 0xBE, 0x62, 0xBC, 0xA1, 0x0D, 0xA1, 0xEC}}
+
+[PcdsFixedAtBuild]
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvBase|0x0|UINT32|0x00001000
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvSize|0x0|UINT32|0x00001001
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase|0x0|UINT32|0x00001002
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize|0x0|UINT32|0x00001003
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|0x0|UINT32|0x00001004
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize|0x0|UINT32|0x00001005
+
+#
+# Definition of EFI Variable region
+#
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x00001010
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x00001011
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00001012
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|0|UINT32|0x00001013
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBase|0|UINT32|0x00001014
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|0|UINT32|0x00001015
+#
+# Firmware region which is protected by PMP.
+#
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwBlockSize|0|UINT32|0x00001020
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress|0|UINT32|0x00001021
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress|0|UINT32|0x00001022
+#
+# Definition of RISC-V Hart
+#
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001023
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001024
+#
+# Definitions for OpenSbi
+#
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase|0|UINT32|0x00001025
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize|0|UINT32|0x00001026
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize|0|UINT32|0x00001027
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase|0|UINT32|0x00001028
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize|0|UINT32|0x00001029
+
+[PcdsPatchableInModule]
+
+[PcdsFeatureFlag]
+ gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|0x00001006
+
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
+
+[UserExtensions.TianoCore."ExtraFiles"]
+ RiscVPlatformPkgExtra.uni
diff --git a/RiscVPlatformPkg/RiscVPlatformPkg.dsc b/RiscVPlatformPkg/RiscVPlatformPkg.dsc
new file mode 100644
index 0000000..7f4bdda
--- /dev/null
+++ b/RiscVPlatformPkg/RiscVPlatformPkg.dsc
@@ -0,0 +1,73 @@
+#/** @file
+# RISC-V platform package.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#**/
+
+################################################################################
+#
+# Defines Section
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = RiscVPlatform
+ PLATFORM_GUID = 840A9576-5869-491E-9210-89769DED4650
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x0001001c
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)
+ SUPPORTED_ARCHITECTURES = RISCV64
+ BUILD_TARGETS = DEBUG|RELEASE|NOOPT
+ SKUID_IDENTIFIER = DEFAULT
+
+[BuildOptions]
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+!ifdef $(SOURCE_DEBUG_ENABLE)
+ GCC:*_*_RISCV64_GENFW_FLAGS = --keepexceptiontable
+!endif
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this Platform.
+#
+################################################################################
+[SkuIds]
+ 0|DEFAULT
+
+[LibraryClasses.common]
+ RealTimeClockLib|RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.inf
+ RiscVOpensbiPlatformLib|RiscVPlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
+ RiscVCpuLib|RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
+ RiscVOpensbiLib|RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+ TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+
+[LibraryClasses.common.PEIM]
+ FirmwareContextProcessorSpecificLib|RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+
+[LibraryClasses.common.SEC]
+ ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ PlatformBootManagerLib|RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+
+[Components.common.SEC]
+ RiscVPlatformPkg/Universal/Sec/SecMain.inf
+
diff --git a/RiscVPlatformPkg/Readme.md b/RiscVPlatformPkg/Readme.md
new file mode 100644
index 0000000..ebf7bf5
--- /dev/null
+++ b/RiscVPlatformPkg/Readme.md
@@ -0,0 +1,78 @@
+# Introduction
+
+## EDK2 RISC-V Platform Package
+RISC-V platform package provides the generic and common modules for RISC-V
+platforms. RISC-V platform package could include RiscPlatformPkg.dec to
+use the common drivers, libraries, definitions, PCDs and etc. for the
+platform development.
+
+### Download the sources ###
+```
+git clone https://github.com/tianocore/edk2-staging.git
+# Checkout RISC-V-V2 branch
+git clone https://github.com/tianocore/edk2-platforms.git
+# Checkout devel-riscv-v2-PATCHv5 branch
+git clone https://github.com/tianocore/edk2-non-osi.git
+```
+### EDK2 project
+Currently, the EDK2 RISC-V platform can only build with edk2 project in
+**edk2-staging/RISC-V-V2** branch. The build architecture whcih is supported
+and verified so far is "RISCV64".
+The verified RISC-V toolchain is https://github.com/riscv/riscv-gnu-toolchain @64879b24,
+toolchain tag is "GCC5" declared in tools_def.txt
+
+## RISC-V Platform PCD settings
+### EDK2 Firmware Volume Settings
+EDK2 Firmware volume related PCDs which declared in platform FDF file.
+
+| **PCD name** |**Usage**|
+|----------------|----------|
+|PcdRiscVSecFvBase| The base address of SEC Firmware Volume|
+|PcdRiscVSecFvSize| The size of SEC Firmware Volume|
+|PcdRiscVPeiFvBase| The base address of PEI Firmware Volume|
+|PcdRiscVPeiFvSize| The size of SEC Firmware Volume|
+|PcdRiscVDxeFvBase| The base address of DXE Firmware Volume|
+|PcdRiscVDxeFvSize| The size of SEC Firmware Volume|
+
+### EDK2 EFI Variable Region Settings
+The PCD settings regard to EFI Variable
+
+| **PCD name** |**Usage**|
+|----------------|----------|
+|PcdVariableFdBaseAddress| The EFI variable firmware device base address|
+|PcdVariableFdSize| The EFI variable firmware device size|
+|PcdVariableFdBlockSize| The block size of EFI variable firmware device|
+|PcdPlatformFlashNvStorageVariableBase| EFI variable base address within firmware device|
+|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable fault tolerance worksapce (FTW) within firmware device|
+|PcdPlatformFlashNvStorageFtwSpareBase| The base address of EFI variable spare FTW within firmware device|
+
+### RISC-V Physical Memory Protection (PMP) Region Settings
+Below PCDs could be set in platform FDF file.
+
+| **PCD name** |**Usage**|
+|----------------|----------|
+|PcdFwStartAddress| The starting address of firmware region to protected by PMP|
+|PcdFwEndAddress| The ending address of firmware region to protected by PMP|
+
+### RISC-V Processor HART Settings
+
+| **PCD name** |**Usage**|
+|----------------|----------|
+|PcdHartCount| Number of RISC-V HARTs, the value is processor-implementation specific|
+|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and boot system to OS|
+
+### RISC-V OpenSBI Settings
+
+| **PCD name** |**Usage**|
+|----------------|----------|
+|PcdScratchRamBase| The base address of OpenSBI scratch buffer for all RISC-V HARTs|
+|PcdScratchRamSize| The total size of OpenSBI scratch buffer for all RISC-V HARTs|
+|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for booting system use OpenSBI|
+|PcdTemporaryRamBase| The base address of temporary memory for PEI phase|
+|PcdTemporaryRamSize| The temporary memory size for PEI phase|
+
+## Supported Operating Systems
+Only support to boot to EFI Shell so far.
+
+## Known Issues and Limitations
+Only RISC-V RV64 is verified.
diff --git a/RiscVPlatformPkg/RiscVPlatformPkg.uni b/RiscVPlatformPkg/RiscVPlatformPkg.uni
new file mode 100644
index 0000000..deb91fa
--- /dev/null
+++ b/RiscVPlatformPkg/RiscVPlatformPkg.uni
@@ -0,0 +1,15 @@
+// /** @file
+// RISC-V Package Localized Strings and Content.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_PACKAGE_ABSTRACT #language en-US "Provides UEFI compatible RISC-V platform modules and libraries"
+
+#string STR_PACKAGE_DESCRIPTION #language en-US "This Package provides UEFI compatible RISC-V platform modules and libraries."
+
+
--git a/RiscVPlatformPkg/RiscVPlatformPkgExtra.uni b/RiscVPlatformPkg/RiscVPlatformPkgExtra.uni
new file mode 100644
index 0000000..493f5f4
--- /dev/null
+++ b/RiscVPlatformPkg/RiscVPlatformPkgExtra.uni
@@ -0,0 +1,12 @@
+// /** @file
+// RISC-V Package Localized Strings and Content.
+//
+// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#string STR_PROPERTIES_PACKAGE_NAME
+#language en-US
+"RISC-V platform package"
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* [edk2-staging/RISC-V-V2 PATCH v3 37/39] edk2-staging:RISC-V-V2: Add RiscVEdk2Readme.md
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (35 preceding siblings ...)
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 36/39] RiscVPlatformPkg: Add RiscVPlatformPkg Abner Chang
@ 2019-10-28 1:59 ` Abner Chang
2019-11-21 17:09 ` Leif Lindholm
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 38/39] edk2-staging: Revise Maintainers.txt for RISC-V packages Abner Chang
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 39/39] edk2-staging: Revise Readme.md Abner Chang
38 siblings, 1 reply; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:59 UTC (permalink / raw)
To: devel; +Cc: abner.chang, Leif Lindholm, Gilbert Chen
Add readme of RISC-V edk2 port.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
RiscVEdk2Readme.md | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
create mode 100644 RiscVEdk2Readme.md
diff --git a/RiscVEdk2Readme.md b/RiscVEdk2Readme.md
new file mode 100644
index 0000000..ebd7495
--- /dev/null
+++ b/RiscVEdk2Readme.md
@@ -0,0 +1,64 @@
+This branch is used to contribute RISC-V architecture to EDK2
+
+The branch owner:
+Abner Chang < abner.chang@hpe.com >
+Gilbert Chen < gilbert.chen@hpe.com >
+
+## RISC-V EDK2 Port Introduction
+RISC-V is an open ISA which was designed to support research and education of
+computer architecture, but now it becomes a standard open Instruction Set
+Architecture for industry implementations. The RISC-V edk2 project is to create
+a new processor binding in UEFI spec and have the RISC-V edk2 implementation.
+The goal is to have RISC-V edk2 port as the firmware reference for RISC-V
+platforms.
+
+This branch (RISC-V-V2) on edk2-staging is RISC-V edk2 port with RISC-V
+OpenSbi (https://github.com/riscv/opensbi) library integrated.
+RiscVPkg provides the generic and common modules of RISC-V prcessor.
+Two edk2 RISC-V platforms are introduced in this branch,
+- SiFive Freedome U500 platform whcih is maintained in FreedomU500VC707Board
+under Platform/SiFive/U5SeriesPkg.
+- SiFive Freedome U540 HiFive Unleashed platform whcih is maintained in
+FreedomU540HiFiveUnleashedBoard under Platform/SiFive/U5SeriesPkg.
+
+Refer to Platform/SiFive/U5Series/Readme.md on edk2-platform repository.
+
+## RISC-V EDK2 Package
+```
+RiscVPkg - RISC-V processor package. This package provides RISC-V
+ processor related protocols/libraries accroding to UEFI
+ specification and edk2 implementations.
+RiscVPlatformPkg - RISC-V platform package. This package provides RISC-V
+ platform common modules, libraries, PCDs and definitoins.
+```
+## Toolchain of RISC-V EDK2 port
+Due to not yet tracked down bugs, only the following toolchain is known to
+produce bootoable binaries.
+https://github.com/riscv/riscv-gnu-toolchain at commit ID 64879b24.
+The commit ID 64879b24 of riscv-gnu-toolchain repository is verified to build
+RISC-V edk2 platform and boot to EFI SHELL successfully.
+You have to clone the toolchain from above link and check out commit:64879b24
+for building RISC-V edk2 port.
+The commit later than 64879b24 causes system hangs at the PEI phase to DXE phase
+transition. We are still figuring out the root cause.
+
+## EDK2 Build Target
+"RISCV64" ARCH is the RISC-V architecture which currently supported and verified.
+The verified RISC-V toolchain is https://github.com/riscv/riscv-gnu-toolchain
+@64879b24 as mentioned above, toolchain tag is "GCC5" which is declared in
+tools_def.txt.
+Below is the edk2 build options for building RISC-V RV64 platform,
+```
+build -a RISCV64 -p Platform/{Vendor}/{Platform}/{Platform}.dsc -t GCC5
+```
+For example,
+```
+build -a RISCV64 -p Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
+-t GCC5
+```
+
+Make sure RISC-V toolchain is built succesfully and the toolchain binaries are
+generated in somewhere you specified when building toolchain.
+'GCC5_RISCV64_PREFIX' is the cross compilation prefix to toolchain binraries.
+For example, set 'GCC5_RISCV64_PREFIX' to '~/RiscVToolchain/riscv64-unknown-elf-'
+before you build RISC-V edk2 port.
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* Re: [edk2-staging/RISC-V-V2 PATCH v3 37/39] edk2-staging:RISC-V-V2: Add RiscVEdk2Readme.md
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 37/39] edk2-staging:RISC-V-V2: Add RiscVEdk2Readme.md Abner Chang
@ 2019-11-21 17:09 ` Leif Lindholm
2019-11-22 3:57 ` [edk2-devel] " Abner Chang
0 siblings, 1 reply; 77+ messages in thread
From: Leif Lindholm @ 2019-11-21 17:09 UTC (permalink / raw)
To: Abner Chang; +Cc: devel, Gilbert Chen
On Mon, Oct 28, 2019 at 09:59:15 +0800, Abner Chang wrote:
> Add readme of RISC-V edk2 port.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Gilbert Chen <gilbert.chen@hpe.com>
> ---
> RiscVEdk2Readme.md | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 64 insertions(+)
> create mode 100644 RiscVEdk2Readme.md
>
> diff --git a/RiscVEdk2Readme.md b/RiscVEdk2Readme.md
> new file mode 100644
> index 0000000..ebd7495
> --- /dev/null
> +++ b/RiscVEdk2Readme.md
> @@ -0,0 +1,64 @@
> +This branch is used to contribute RISC-V architecture to EDK2
> +
> +The branch owner:
> +Abner Chang < abner.chang@hpe.com >
> +Gilbert Chen < gilbert.chen@hpe.com >
> +
> +## RISC-V EDK2 Port Introduction
> +RISC-V is an open ISA which was designed to support research and education of
> +computer architecture, but now it becomes a standard open Instruction Set
> +Architecture for industry implementations. The RISC-V edk2 project is to create
> +a new processor binding in UEFI spec and have the RISC-V edk2 implementation.
> +The goal is to have RISC-V edk2 port as the firmware reference for RISC-V
> +platforms.
> +
> +This branch (RISC-V-V2) on edk2-staging is RISC-V edk2 port with RISC-V
> +OpenSbi (https://github.com/riscv/opensbi) library integrated.
> +RiscVPkg provides the generic and common modules of RISC-V prcessor.
> +Two edk2 RISC-V platforms are introduced in this branch,
> +- SiFive Freedome U500 platform whcih is maintained in FreedomU500VC707Board
> +under Platform/SiFive/U5SeriesPkg.
> +- SiFive Freedome U540 HiFive Unleashed platform whcih is maintained in
> +FreedomU540HiFiveUnleashedBoard under Platform/SiFive/U5SeriesPkg.
> +
> +Refer to Platform/SiFive/U5Series/Readme.md on edk2-platform repository.
> +
> +## RISC-V EDK2 Package
> +```
> +RiscVPkg - RISC-V processor package. This package provides RISC-V
> + processor related protocols/libraries accroding to UEFI
> + specification and edk2 implementations.
> +RiscVPlatformPkg - RISC-V platform package. This package provides RISC-V
> + platform common modules, libraries, PCDs and definitoins.
> +```
> +## Toolchain of RISC-V EDK2 port
> +Due to not yet tracked down bugs, only the following toolchain is known to
> +produce bootoable binaries.
Was this issue also resolved by Mark's linker script patch?
> +https://github.com/riscv/riscv-gnu-toolchain at commit ID 64879b24.
> +The commit ID 64879b24 of riscv-gnu-toolchain repository is verified to build
> +RISC-V edk2 platform and boot to EFI SHELL successfully.
> +You have to clone the toolchain from above link and check out commit:64879b24
> +for building RISC-V edk2 port.
> +The commit later than 64879b24 causes system hangs at the PEI phase to DXE phase
> +transition. We are still figuring out the root cause.
> +
> +## EDK2 Build Target
> +"RISCV64" ARCH is the RISC-V architecture which currently supported and verified.
> +The verified RISC-V toolchain is https://github.com/riscv/riscv-gnu-toolchain
> +@64879b24 as mentioned above, toolchain tag is "GCC5" which is declared in
> +tools_def.txt.
If this text is still needed:
Which environment has this toolchain successfully been built in?
/
Leif
> +Below is the edk2 build options for building RISC-V RV64 platform,
> +```
> +build -a RISCV64 -p Platform/{Vendor}/{Platform}/{Platform}.dsc -t GCC5
> +```
> +For example,
> +```
> +build -a RISCV64 -p Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
> +-t GCC5
> +```
> +
> +Make sure RISC-V toolchain is built succesfully and the toolchain binaries are
> +generated in somewhere you specified when building toolchain.
> +'GCC5_RISCV64_PREFIX' is the cross compilation prefix to toolchain binraries.
> +For example, set 'GCC5_RISCV64_PREFIX' to '~/RiscVToolchain/riscv64-unknown-elf-'
> +before you build RISC-V edk2 port.
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 77+ messages in thread* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 37/39] edk2-staging:RISC-V-V2: Add RiscVEdk2Readme.md
2019-11-21 17:09 ` Leif Lindholm
@ 2019-11-22 3:57 ` Abner Chang
2019-11-22 9:34 ` Leif Lindholm
0 siblings, 1 reply; 77+ messages in thread
From: Abner Chang @ 2019-11-22 3:57 UTC (permalink / raw)
To: devel@edk2.groups.io, leif.lindholm@linaro.org; +Cc: Chen, Gilbert
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Leif Lindholm
> Sent: Friday, November 22, 2019 1:09 AM
> To: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
> Cc: devel@edk2.groups.io; Chen, Gilbert <gilbert.chen@hpe.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 37/39] edk2-
> staging:RISC-V-V2: Add RiscVEdk2Readme.md
>
> On Mon, Oct 28, 2019 at 09:59:15 +0800, Abner Chang wrote:
> > Add readme of RISC-V edk2 port.
> >
> > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> >
> > Cc: Leif Lindholm <leif.lindholm@linaro.org>
> > Cc: Gilbert Chen <gilbert.chen@hpe.com>
> > ---
> > RiscVEdk2Readme.md | 64
> > ++++++++++++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 64 insertions(+)
> > create mode 100644 RiscVEdk2Readme.md
> >
> > diff --git a/RiscVEdk2Readme.md b/RiscVEdk2Readme.md new file mode
> > 100644 index 0000000..ebd7495
> > --- /dev/null
> > +++ b/RiscVEdk2Readme.md
> > @@ -0,0 +1,64 @@
> > +This branch is used to contribute RISC-V architecture to EDK2
> > +
> > +The branch owner:
> > +Abner Chang < abner.chang@hpe.com >
> > +Gilbert Chen < gilbert.chen@hpe.com >
> > +
> > +## RISC-V EDK2 Port Introduction
> > +RISC-V is an open ISA which was designed to support research and
> > +education of computer architecture, but now it becomes a standard
> > +open Instruction Set Architecture for industry implementations. The
> > +RISC-V edk2 project is to create a new processor binding in UEFI spec and
> have the RISC-V edk2 implementation.
> > +The goal is to have RISC-V edk2 port as the firmware reference for
> > +RISC-V platforms.
> > +
> > +This branch (RISC-V-V2) on edk2-staging is RISC-V edk2 port with
> > +RISC-V OpenSbi (https://github.com/riscv/opensbi) library integrated.
> > +RiscVPkg provides the generic and common modules of RISC-V prcessor.
> > +Two edk2 RISC-V platforms are introduced in this branch,
> > +- SiFive Freedome U500 platform whcih is maintained in
> > +FreedomU500VC707Board under Platform/SiFive/U5SeriesPkg.
> > +- SiFive Freedome U540 HiFive Unleashed platform whcih is maintained
> > +in FreedomU540HiFiveUnleashedBoard under
> Platform/SiFive/U5SeriesPkg.
> > +
> > +Refer to Platform/SiFive/U5Series/Readme.md on edk2-platform
> repository.
> > +
> > +## RISC-V EDK2 Package
> > +```
> > +RiscVPkg - RISC-V processor package. This package provides RISC-V
> > + processor related protocols/libraries accroding to UEFI
> > + specification and edk2 implementations.
> > +RiscVPlatformPkg - RISC-V platform package. This package provides RISC-
> V
> > + platform common modules, libraries, PCDs and definitoins.
> > +```
> > +## Toolchain of RISC-V EDK2 port
> > +Due to not yet tracked down bugs, only the following toolchain is
> > +known to produce bootoable binaries.
>
> Was this issue also resolved by Mark's linker script patch?
The fix is not in lds, the fix is tool_def.template in which msmall-data-limit is added and set to 0 to avoid .sdata2 section. See below email on edk2-devel,
- [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3-2] BaseTools: Fix edk2 RISC-V binary hangs at POST with the latest toolchain
>
> > +https://github.com/riscv/riscv-gnu-toolchain at commit ID 64879b24.
> > +The commit ID 64879b24 of riscv-gnu-toolchain repository is verified
> > +to build RISC-V edk2 platform and boot to EFI SHELL successfully.
> > +You have to clone the toolchain from above link and check out
> > +commit:64879b24 for building RISC-V edk2 port.
> > +The commit later than 64879b24 causes system hangs at the PEI phase
> > +to DXE phase transition. We are still figuring out the root cause.
> > +
> > +## EDK2 Build Target
> > +"RISCV64" ARCH is the RISC-V architecture which currently supported and
> verified.
> > +The verified RISC-V toolchain is
> > +https://github.com/riscv/riscv-gnu-toolchain
> > +@64879b24 as mentioned above, toolchain tag is "GCC5" which is
> > +declared in tools_def.txt.
>
> If this text is still needed:
> Which environment has this toolchain successfully been built in?
Readme has been updated,
https://github.com/riscv/riscv-gnu-toolchain and "GCC5" till the toolchain used for building binary of RISC-V platform, just commit ID 64879b24 is not required.
- [edk2-devel] [Platform/devel-riscv-v2 PATCHv5-2] edk2-platforms: Update Readme.md for RISC-V platform.
- [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3-2] BaseTools: Fix edk2 RISC-V binary hangs at POST with the latest toolchain
>
> /
> Leif
>
> > +Below is the edk2 build options for building RISC-V RV64 platform,
> > +``` build -a RISCV64 -p Platform/{Vendor}/{Platform}/{Platform}.dsc
> > +-t GCC5 ``` For example, ``` build -a RISCV64 -p
> > +Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
> > +-t GCC5
> > +```
> > +
> > +Make sure RISC-V toolchain is built succesfully and the toolchain
> > +binaries are generated in somewhere you specified when building
> toolchain.
> > +'GCC5_RISCV64_PREFIX' is the cross compilation prefix to toolchain
> binraries.
> > +For example, set 'GCC5_RISCV64_PREFIX' to '~/RiscVToolchain/riscv64-
> unknown-elf-'
> > +before you build RISC-V edk2 port.
> > --
> > 2.7.4
> >
>
>
^ permalink raw reply [flat|nested] 77+ messages in thread* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 37/39] edk2-staging:RISC-V-V2: Add RiscVEdk2Readme.md
2019-11-22 3:57 ` [edk2-devel] " Abner Chang
@ 2019-11-22 9:34 ` Leif Lindholm
0 siblings, 0 replies; 77+ messages in thread
From: Leif Lindholm @ 2019-11-22 9:34 UTC (permalink / raw)
To: Chang, Abner (HPS SW/FW Technologist); +Cc: devel@edk2.groups.io, Chen, Gilbert
On Fri, Nov 22, 2019 at 03:57:22 +0000, Chang, Abner (HPS SW/FW Technologist) wrote:
> > > +## RISC-V EDK2 Package
> > > +```
> > > +RiscVPkg - RISC-V processor package. This package provides RISC-V
> > > + processor related protocols/libraries accroding to UEFI
> > > + specification and edk2 implementations.
> > > +RiscVPlatformPkg - RISC-V platform package. This package provides RISC-
> > V
> > > + platform common modules, libraries, PCDs and definitoins.
> > > +```
> > > +## Toolchain of RISC-V EDK2 port
> > > +Due to not yet tracked down bugs, only the following toolchain is
> > > +known to produce bootoable binaries.
> >
> > Was this issue also resolved by Mark's linker script patch?
>
> The fix is not in lds, the fix is tool_def.template in which
> msmall-data-limit is added and set to 0 to avoid .sdata2
> section. See below email on edk2-devel,
> - [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3-2] BaseTools: Fix
> edk2 RISC-V binary hangs at POST with the latest toolchain
Yes, I saw that. (I still think of it as a linker-script patch,
because that's what Mark sent, but that's just my brain for you.)
> > > +https://github.com/riscv/riscv-gnu-toolchain at commit ID 64879b24.
> > > +The commit ID 64879b24 of riscv-gnu-toolchain repository is verified
> > > +to build RISC-V edk2 platform and boot to EFI SHELL successfully.
> > > +You have to clone the toolchain from above link and check out
> > > +commit:64879b24 for building RISC-V edk2 port.
> > > +The commit later than 64879b24 causes system hangs at the PEI phase
> > > +to DXE phase transition. We are still figuring out the root cause.
> > > +
> > > +## EDK2 Build Target
> > > +"RISCV64" ARCH is the RISC-V architecture which currently supported and
> > verified.
> > > +The verified RISC-V toolchain is
> > > +https://github.com/riscv/riscv-gnu-toolchain
> > > +@64879b24 as mentioned above, toolchain tag is "GCC5" which is
> > > +declared in tools_def.txt.
> >
> > If this text is still needed:
> > Which environment has this toolchain successfully been built in?
>
> Readme has been updated,
> https://github.com/riscv/riscv-gnu-toolchain and "GCC5" till the
> toolchain used for building binary of RISC-V platform,
Ok - that is fine for the -staging branch, which will be useful for
getting help tracking remaining toolchain issues down.
> just commit
> ID 64879b24 is not required.
Yes.
But the fact remains that I still have not been told of in which
environment those toolchain sources might actually build. Certainly
they don't in any I have.
Please tell me the distribution of Linux, and version of said
distribution, that you have personally used to build said toolchain.
Please include this information in the readme.
It is very easy for me to set up a Fedora or Centos chroot under one
of my debian systems, but I do *not* have time to play around with all
possible ones to find one that finally works. None of the ones I
*have* tested will successfully build that toolchain, using those
sources, by following the steps provided.
So please state, explicitly, in the Readme, which distribution of
Linux you used, and what version of that distribution was installed at
the point you built it.
In the Readme.
Which distribution.
(and so on..., until you tell me (and the readme) which version of
which distribution *you* have successfully built said toolchain with)
/
Leif
> - [edk2-devel] [Platform/devel-riscv-v2 PATCHv5-2] edk2-platforms: Update Readme.md for RISC-V platform.
> - [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3-2] BaseTools: Fix edk2 RISC-V binary hangs at POST with the latest toolchain
>
>
> >
> > /
> > Leif
> >
> > > +Below is the edk2 build options for building RISC-V RV64 platform,
> > > +``` build -a RISCV64 -p Platform/{Vendor}/{Platform}/{Platform}.dsc
> > > +-t GCC5 ``` For example, ``` build -a RISCV64 -p
> > > +Platform/SiFive/U5SeriesPkg/FreedomU500VC707Board/U500.dsc
> > > +-t GCC5
> > > +```
> > > +
> > > +Make sure RISC-V toolchain is built succesfully and the toolchain
> > > +binaries are generated in somewhere you specified when building
> > toolchain.
> > > +'GCC5_RISCV64_PREFIX' is the cross compilation prefix to toolchain
> > binraries.
> > > +For example, set 'GCC5_RISCV64_PREFIX' to '~/RiscVToolchain/riscv64-
> > unknown-elf-'
> > > +before you build RISC-V edk2 port.
> > > --
> > > 2.7.4
> > >
> >
> >
>
^ permalink raw reply [flat|nested] 77+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v3 38/39] edk2-staging: Revise Maintainers.txt for RISC-V packages
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (36 preceding siblings ...)
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 37/39] edk2-staging:RISC-V-V2: Add RiscVEdk2Readme.md Abner Chang
@ 2019-10-28 1:59 ` Abner Chang
2019-10-29 1:05 ` [edk2-devel] " Laszlo Ersek
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 39/39] edk2-staging: Revise Readme.md Abner Chang
38 siblings, 1 reply; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:59 UTC (permalink / raw)
To: devel
Cc: abner.chang, Andrew Fish, Laszlo Ersek, Leif Lindholm,
Michael D Kinney, Gilbert Chen
Add maintainers of RiscVPkg and RiscVPlatformPkg.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
Maintainers.txt | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/Maintainers.txt b/Maintainers.txt
index 919bacc..68a3580 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -90,6 +90,11 @@ F: */Arm/
M: Leif Lindholm <leif.lindholm@linaro.org>
M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
+RISCV64
+F: */RiscV64/
+M: Abner Chang <abner.chang@hpe.com>
+R: Gilbert Chen <gilbert.chen@hpe.com>
+
EDK II Packages:
----------------
ArmPkg
@@ -408,6 +413,16 @@ F: PcAtChipsetPkg/
W: https://github.com/tianocore/tianocore.github.io/wiki/PcAtChipsetPkg
M: Ray Ni <ray.ni@intel.com>
+RiscVPkg: RISCV64 architecture modules
+F: RiscVPkg/
+M: Abner Chang <abner.chang@hpe.com>
+R: Gilbert Chen <gilbert.chen@hpe.com>
+
+RiscVPlatformPkg: RISC-V platform modules
+F: RiscVPlatformPkg/
+M: Abner Chang <abner.chang@hpe.com>
+R: Gilbert Chen <gilbert.chen@hpe.com>
+
SecurityPkg
F: SecurityPkg/
W: https://github.com/tianocore/tianocore.github.io/wiki/SecurityPkg
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 38/39] edk2-staging: Revise Maintainers.txt for RISC-V packages
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 38/39] edk2-staging: Revise Maintainers.txt for RISC-V packages Abner Chang
@ 2019-10-29 1:05 ` Laszlo Ersek
2019-10-29 1:31 ` Abner Chang
0 siblings, 1 reply; 77+ messages in thread
From: Laszlo Ersek @ 2019-10-29 1:05 UTC (permalink / raw)
To: devel, abner.chang
Cc: Andrew Fish, Leif Lindholm, Michael D Kinney, Gilbert Chen
On 10/28/19 02:59, Abner Chang wrote:
> Add maintainers of RiscVPkg and RiscVPlatformPkg.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
>
> Cc: Andrew Fish <afish@apple.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Gilbert Chen <gilbert.chen@hpe.com>
> ---
> Maintainers.txt | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/Maintainers.txt b/Maintainers.txt
> index 919bacc..68a3580 100644
> --- a/Maintainers.txt
> +++ b/Maintainers.txt
> @@ -90,6 +90,11 @@ F: */Arm/
> M: Leif Lindholm <leif.lindholm@linaro.org>
> M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>
> +RISCV64
> +F: */RiscV64/
> +M: Abner Chang <abner.chang@hpe.com>
> +R: Gilbert Chen <gilbert.chen@hpe.com>
> +
> EDK II Packages:
> ----------------
> ArmPkg
> @@ -408,6 +413,16 @@ F: PcAtChipsetPkg/
> W: https://github.com/tianocore/tianocore.github.io/wiki/PcAtChipsetPkg
> M: Ray Ni <ray.ni@intel.com>
>
> +RiscVPkg: RISCV64 architecture modules
> +F: RiscVPkg/
> +M: Abner Chang <abner.chang@hpe.com>
> +R: Gilbert Chen <gilbert.chen@hpe.com>
> +
> +RiscVPlatformPkg: RISC-V platform modules
> +F: RiscVPlatformPkg/
> +M: Abner Chang <abner.chang@hpe.com>
> +R: Gilbert Chen <gilbert.chen@hpe.com>
> +
> SecurityPkg
> F: SecurityPkg/
> W: https://github.com/tianocore/tianocore.github.io/wiki/SecurityPkg
>
The spelling of the "RISCV64" reference is not consistent with "RISC-V".
I'm not sure if both of those are the officially right rendering. If
they are fine, then:
Acked-by: Laszlo Ersek <lersek@redhat.com>
Thanks
Laszlo
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 38/39] edk2-staging: Revise Maintainers.txt for RISC-V packages
2019-10-29 1:05 ` [edk2-devel] " Laszlo Ersek
@ 2019-10-29 1:31 ` Abner Chang
0 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-29 1:31 UTC (permalink / raw)
To: Laszlo Ersek, devel@edk2.groups.io
Cc: Andrew Fish, Leif Lindholm, Michael D Kinney, Chen, Gilbert
> -----Original Message-----
> From: Laszlo Ersek [mailto:lersek@redhat.com]
> Sent: Tuesday, October 29, 2019 9:06 AM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Cc: Andrew Fish <afish@apple.com>; Leif Lindholm
> <leif.lindholm@linaro.org>; Michael D Kinney <michael.d.kinney@intel.com>;
> Chen, Gilbert <gilbert.chen@hpe.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 38/39] edk2-
> staging: Revise Maintainers.txt for RISC-V packages
>
> On 10/28/19 02:59, Abner Chang wrote:
> > Add maintainers of RiscVPkg and RiscVPlatformPkg.
> >
> > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> >
> > Cc: Andrew Fish <afish@apple.com>
> > Cc: Laszlo Ersek <lersek@redhat.com>
> > Cc: Leif Lindholm <leif.lindholm@linaro.org>
> > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > Cc: Gilbert Chen <gilbert.chen@hpe.com>
> > ---
> > Maintainers.txt | 15 +++++++++++++++
> > 1 file changed, 15 insertions(+)
> >
> > diff --git a/Maintainers.txt b/Maintainers.txt index 919bacc..68a3580
> > 100644
> > --- a/Maintainers.txt
> > +++ b/Maintainers.txt
> > @@ -90,6 +90,11 @@ F: */Arm/
> > M: Leif Lindholm <leif.lindholm@linaro.org>
> > M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> >
> > +RISCV64
> > +F: */RiscV64/
> > +M: Abner Chang <abner.chang@hpe.com>
> > +R: Gilbert Chen <gilbert.chen@hpe.com>
> > +
> > EDK II Packages:
> > ----------------
> > ArmPkg
> > @@ -408,6 +413,16 @@ F: PcAtChipsetPkg/
> > W:
> > https://github.com/tianocore/tianocore.github.io/wiki/PcAtChipsetPkg
> > M: Ray Ni <ray.ni@intel.com>
> >
> > +RiscVPkg: RISCV64 architecture modules
> > +F: RiscVPkg/
> > +M: Abner Chang <abner.chang@hpe.com>
> > +R: Gilbert Chen <gilbert.chen@hpe.com>
> > +
> > +RiscVPlatformPkg: RISC-V platform modules
> > +F: RiscVPlatformPkg/
> > +M: Abner Chang <abner.chang@hpe.com>
> > +R: Gilbert Chen <gilbert.chen@hpe.com>
> > +
> > SecurityPkg
> > F: SecurityPkg/
> > W: https://github.com/tianocore/tianocore.github.io/wiki/SecurityPkg
> >
>
> The spelling of the "RISCV64" reference is not consistent with "RISC-V".
> I'm not sure if both of those are the officially right rendering. If they are fine,
> then:
No. I will change it back to either RISC-V RV64 or RISC-V. I was thinking to use the build arch tag.
>
> Acked-by: Laszlo Ersek <lersek@redhat.com>
>
> Thanks
> Laszlo
^ permalink raw reply [flat|nested] 77+ messages in thread
* [edk2-staging/RISC-V-V2 PATCH v3 39/39] edk2-staging: Revise Readme.md
2019-10-28 1:58 [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on Abner Chang
` (37 preceding siblings ...)
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 38/39] edk2-staging: Revise Maintainers.txt for RISC-V packages Abner Chang
@ 2019-10-28 1:59 ` Abner Chang
2019-10-29 1:07 ` [edk2-devel] " Laszlo Ersek
2019-11-21 17:15 ` Leif Lindholm
38 siblings, 2 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-28 1:59 UTC (permalink / raw)
To: devel
Cc: abner.chang, Andrew Fish, Laszlo Ersek, Leif Lindholm,
Michael D Kinney, Gilbert Chen
Add opensbi submodule.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Gilbert Chen <gilbert.chen@hpe.com>
---
Readme.md | 1 +
1 file changed, 1 insertion(+)
diff --git a/Readme.md b/Readme.md
index 27e4ce0..4b3d2a5 100644
--- a/Readme.md
+++ b/Readme.md
@@ -148,6 +148,7 @@ as possible as we can. Currently EDK II contains two submodules
- CryptoPkg/Library/OpensslLib/openssl
- ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
+- RiscVPkg/Library/RiscVOpensbiLib/opensbi
The latter one is actually required by previous one. It's inevitable
in openssl-1.1.1 (since stable201905) for floating point parameter
--
2.7.4
^ permalink raw reply related [flat|nested] 77+ messages in thread* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 39/39] edk2-staging: Revise Readme.md
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 39/39] edk2-staging: Revise Readme.md Abner Chang
@ 2019-10-29 1:07 ` Laszlo Ersek
2019-10-29 1:35 ` Abner Chang
2019-10-29 2:01 ` Leif Lindholm
2019-11-21 17:15 ` Leif Lindholm
1 sibling, 2 replies; 77+ messages in thread
From: Laszlo Ersek @ 2019-10-29 1:07 UTC (permalink / raw)
To: devel, abner.chang
Cc: Andrew Fish, Leif Lindholm, Michael D Kinney, Gilbert Chen
On 10/28/19 02:59, Abner Chang wrote:
> Add opensbi submodule.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
>
> Cc: Andrew Fish <afish@apple.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Gilbert Chen <gilbert.chen@hpe.com>
> ---
> Readme.md | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Readme.md b/Readme.md
> index 27e4ce0..4b3d2a5 100644
> --- a/Readme.md
> +++ b/Readme.md
> @@ -148,6 +148,7 @@ as possible as we can. Currently EDK II contains two submodules
>
> - CryptoPkg/Library/OpensslLib/openssl
> - ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
> +- RiscVPkg/Library/RiscVOpensbiLib/opensbi
>
> The latter one is actually required by previous one. It's inevitable
> in openssl-1.1.1 (since stable201905) for floating point parameter
>
This will take an update that's a bit more extensive -- please see "two
submodules" just above the listing, and "latter one" right after the
listing. Adding opensbi in the proposed spot breaks both statements.
Thanks
Laszlo
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 39/39] edk2-staging: Revise Readme.md
2019-10-29 1:07 ` [edk2-devel] " Laszlo Ersek
@ 2019-10-29 1:35 ` Abner Chang
2019-10-29 2:01 ` Leif Lindholm
1 sibling, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-10-29 1:35 UTC (permalink / raw)
To: devel@edk2.groups.io, lersek@redhat.com
Cc: Andrew Fish, Leif Lindholm, Michael D Kinney, Chen, Gilbert
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Laszlo Ersek
> Sent: Tuesday, October 29, 2019 9:07 AM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Cc: Andrew Fish <afish@apple.com>; Leif Lindholm
> <leif.lindholm@linaro.org>; Michael D Kinney <michael.d.kinney@intel.com>;
> Chen, Gilbert <gilbert.chen@hpe.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 39/39] edk2-
> staging: Revise Readme.md
>
> On 10/28/19 02:59, Abner Chang wrote:
> > Add opensbi submodule.
> >
> > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> >
> > Cc: Andrew Fish <afish@apple.com>
> > Cc: Laszlo Ersek <lersek@redhat.com>
> > Cc: Leif Lindholm <leif.lindholm@linaro.org>
> > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > Cc: Gilbert Chen <gilbert.chen@hpe.com>
> > ---
> > Readme.md | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/Readme.md b/Readme.md
> > index 27e4ce0..4b3d2a5 100644
> > --- a/Readme.md
> > +++ b/Readme.md
> > @@ -148,6 +148,7 @@ as possible as we can. Currently EDK II contains
> > two submodules
> >
> > - CryptoPkg/Library/OpensslLib/openssl
> > - ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
> > +- RiscVPkg/Library/RiscVOpensbiLib/opensbi
> >
> > The latter one is actually required by previous one. It's inevitable
> > in openssl-1.1.1 (since stable201905) for floating point parameter
> >
>
> This will take an update that's a bit more extensive -- please see "two
> submodules" just above the listing, and "latter one" right after the listing.
> Adding opensbi in the proposed spot breaks both statements.
Sigh. Didn’t see it. will fix it. Thanks for catching this.
>
> Thanks
> Laszlo
>
>
>
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 39/39] edk2-staging: Revise Readme.md
2019-10-29 1:07 ` [edk2-devel] " Laszlo Ersek
2019-10-29 1:35 ` Abner Chang
@ 2019-10-29 2:01 ` Leif Lindholm
2019-10-31 8:20 ` Laszlo Ersek
1 sibling, 1 reply; 77+ messages in thread
From: Leif Lindholm @ 2019-10-29 2:01 UTC (permalink / raw)
To: Laszlo Ersek
Cc: devel, abner.chang, Andrew Fish, Michael D Kinney, Gilbert Chen
On Tue, Oct 29, 2019 at 02:07:20AM +0100, Laszlo Ersek wrote:
> > diff --git a/Readme.md b/Readme.md
> > index 27e4ce0..4b3d2a5 100644
> > --- a/Readme.md
> > +++ b/Readme.md
> > @@ -148,6 +148,7 @@ as possible as we can. Currently EDK II contains two submodules
> >
> > - CryptoPkg/Library/OpensslLib/openssl
> > - ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
> > +- RiscVPkg/Library/RiscVOpensbiLib/opensbi
> >
> > The latter one is actually required by previous one. It's inevitable
> > in openssl-1.1.1 (since stable201905) for floating point parameter
>
> This will take an update that's a bit more extensive -- please see "two
> submodules" just above the listing, and "latter one" right after the
> listing. Adding opensbi in the proposed spot breaks both statements.
This suggests the surrounding language should change.
Could we merge this to master?:
>From 39f08033c934b3e631c40e373aa6a351323ab4aa Mon Sep 17 00:00:00 2001
From: Leif Lindholm <leif.lindholm@linaro.org>
Date: Tue, 29 Oct 2019 09:54:36 +0800
Subject: [PATCH 1/1] Readme.md: remove positional references from submodule description
Remove references to the number of submodules in the tree, as well as
reword the referring to specific submodules as "former" and "previous".
This means we won't need to keep updating the surrounding text if we
add/remove submodules.
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
---
Readme.md | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Readme.md b/Readme.md
index 27e4ce07719b..9bf60bede8ec 100644
--- a/Readme.md
+++ b/Readme.md
@@ -144,12 +144,12 @@ Signed-off-by: Contributor Name <contributor@example.com>
# Submodules
Submodule in EDK II is allowed but submodule chain should be avoided
-as possible as we can. Currently EDK II contains two submodules
+as possible as we can. Currently EDK II contains the following submodules
- CryptoPkg/Library/OpensslLib/openssl
- ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
-The latter one is actually required by previous one. It's inevitable
+ArmSoftFloatLib is actually required by OpensslLib. It's inevitable
in openssl-1.1.1 (since stable201905) for floating point parameter
conversion, but should be dropped once there's no such need in future
release of openssl.
--
2.20.1
^ permalink raw reply related [flat|nested] 77+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 39/39] edk2-staging: Revise Readme.md
2019-10-29 2:01 ` Leif Lindholm
@ 2019-10-31 8:20 ` Laszlo Ersek
0 siblings, 0 replies; 77+ messages in thread
From: Laszlo Ersek @ 2019-10-31 8:20 UTC (permalink / raw)
To: Leif Lindholm
Cc: devel, abner.chang, Andrew Fish, Michael D Kinney, Gilbert Chen
On 10/29/19 03:01, Leif Lindholm wrote:
> On Tue, Oct 29, 2019 at 02:07:20AM +0100, Laszlo Ersek wrote:
>>> diff --git a/Readme.md b/Readme.md
>>> index 27e4ce0..4b3d2a5 100644
>>> --- a/Readme.md
>>> +++ b/Readme.md
>>> @@ -148,6 +148,7 @@ as possible as we can. Currently EDK II contains two submodules
>>>
>>> - CryptoPkg/Library/OpensslLib/openssl
>>> - ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
>>> +- RiscVPkg/Library/RiscVOpensbiLib/opensbi
>>>
>>> The latter one is actually required by previous one. It's inevitable
>>> in openssl-1.1.1 (since stable201905) for floating point parameter
>>
>> This will take an update that's a bit more extensive -- please see "two
>> submodules" just above the listing, and "latter one" right after the
>> listing. Adding opensbi in the proposed spot breaks both statements.
>
> This suggests the surrounding language should change.
>
> Could we merge this to master?:
>
> From 39f08033c934b3e631c40e373aa6a351323ab4aa Mon Sep 17 00:00:00 2001
> From: Leif Lindholm <leif.lindholm@linaro.org>
> Date: Tue, 29 Oct 2019 09:54:36 +0800
> Subject: [PATCH 1/1] Readme.md: remove positional references from submodule description
>
> Remove references to the number of submodules in the tree, as well as
> reword the referring to specific submodules as "former" and "previous".
> This means we won't need to keep updating the surrounding text if we
> add/remove submodules.
>
> Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> Readme.md | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Readme.md b/Readme.md
> index 27e4ce07719b..9bf60bede8ec 100644
> --- a/Readme.md
> +++ b/Readme.md
> @@ -144,12 +144,12 @@ Signed-off-by: Contributor Name <contributor@example.com>
> # Submodules
>
> Submodule in EDK II is allowed but submodule chain should be avoided
> -as possible as we can. Currently EDK II contains two submodules
> +as possible as we can. Currently EDK II contains the following submodules
>
> - CryptoPkg/Library/OpensslLib/openssl
> - ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
>
> -The latter one is actually required by previous one. It's inevitable
> +ArmSoftFloatLib is actually required by OpensslLib. It's inevitable
> in openssl-1.1.1 (since stable201905) for floating point parameter
> conversion, but should be dropped once there's no such need in future
> release of openssl.
>
Good idea. When you post this in isolation for edk2, please add:
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Thanks
Laszlo
^ permalink raw reply [flat|nested] 77+ messages in thread
* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 39/39] edk2-staging: Revise Readme.md
2019-10-28 1:59 ` [edk2-staging/RISC-V-V2 PATCH v3 39/39] edk2-staging: Revise Readme.md Abner Chang
2019-10-29 1:07 ` [edk2-devel] " Laszlo Ersek
@ 2019-11-21 17:15 ` Leif Lindholm
2019-11-22 2:05 ` Abner Chang
1 sibling, 1 reply; 77+ messages in thread
From: Leif Lindholm @ 2019-11-21 17:15 UTC (permalink / raw)
To: devel, abner.chang
Cc: Andrew Fish, Laszlo Ersek, Michael D Kinney, Gilbert Chen,
Palmer Dabbelt
Well, there's no 0/39 for me to give a generic comment on (please use
a cover-letter).
Anything in this set I have not commented on I would consider good to
go into -staging (and pretty close to be able to go into edk2 master).
I have given a few comments that should be trivial to respin.
I have given one comment that will not be, but it needs to happen -
the include wrappers. Clearly that will have impact on other patches
as well, but as long as include statements are all that changes, that
does not need further review.
*But*, it will mean we have compartmentalised the opensbi
import, and can improve its importability upstream without having to
do this work at the same time.
/
Leif
On Mon, Oct 28, 2019 at 09:59:17 +0800, Abner Chang wrote:
> Add opensbi submodule.
>
> Signed-off-by: Abner Chang <abner.chang@hpe.com>
>
> Cc: Andrew Fish <afish@apple.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Leif Lindholm <leif.lindholm@linaro.org>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Gilbert Chen <gilbert.chen@hpe.com>
> ---
> Readme.md | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Readme.md b/Readme.md
> index 27e4ce0..4b3d2a5 100644
> --- a/Readme.md
> +++ b/Readme.md
> @@ -148,6 +148,7 @@ as possible as we can. Currently EDK II contains two submodules
>
> - CryptoPkg/Library/OpensslLib/openssl
> - ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
> +- RiscVPkg/Library/RiscVOpensbiLib/opensbi
>
> The latter one is actually required by previous one. It's inevitable
> in openssl-1.1.1 (since stable201905) for floating point parameter
> --
> 2.7.4
>
>
>
>
^ permalink raw reply [flat|nested] 77+ messages in thread* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 39/39] edk2-staging: Revise Readme.md
2019-11-21 17:15 ` Leif Lindholm
@ 2019-11-22 2:05 ` Abner Chang
2019-11-22 9:42 ` Leif Lindholm
0 siblings, 1 reply; 77+ messages in thread
From: Abner Chang @ 2019-11-22 2:05 UTC (permalink / raw)
To: Leif Lindholm, devel@edk2.groups.io
Cc: Andrew Fish, Laszlo Ersek, Michael D Kinney, Chen, Gilbert
[-- Attachment #1: Type: text/plain, Size: 2573 bytes --]
Palmer removed.
> -----Original Message-----
> From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> Sent: Friday, November 22, 2019 1:15 AM
> To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> <abner.chang@hpe.com>
> Cc: Andrew Fish <afish@apple.com>; Laszlo Ersek <lersek@redhat.com>;
> Michael D Kinney <michael.d.kinney@intel.com>; Chen, Gilbert
> <gilbert.chen@hpe.com>; Palmer Dabbelt <palmer@sifive.com>
> Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 39/39] edk2-
> staging: Revise Readme.md
>
> Well, there's no 0/39 for me to give a generic comment on (please use a
> cover-letter).
There is a cover letter sent with this set of patches, you probably missed it. attached here in case you would like to give comments there.
>
> Anything in this set I have not commented on I would consider good to go
> into -staging (and pretty close to be able to go into edk2 master).
Got it.
>
> I have given a few comments that should be trivial to respin.
>
> I have given one comment that will not be, but it needs to happen - the
> include wrappers. Clearly that will have impact on other patches as well, but
> as long as include statements are all that changes, that does not need further
> review.
>
> *But*, it will mean we have compartmentalised the opensbi import, and can
> improve its importability upstream without having to do this work at the
> same time.
I didn't look into this in detail yet. Let me see if any better solutions out there.
>
> /
> Leif
>
> On Mon, Oct 28, 2019 at 09:59:17 +0800, Abner Chang wrote:
> > Add opensbi submodule.
> >
> > Signed-off-by: Abner Chang <abner.chang@hpe.com>
> >
> > Cc: Andrew Fish <afish@apple.com>
> > Cc: Laszlo Ersek <lersek@redhat.com>
> > Cc: Leif Lindholm <leif.lindholm@linaro.org>
> > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > Cc: Gilbert Chen <gilbert.chen@hpe.com>
> > ---
> > Readme.md | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/Readme.md b/Readme.md
> > index 27e4ce0..4b3d2a5 100644
> > --- a/Readme.md
> > +++ b/Readme.md
> > @@ -148,6 +148,7 @@ as possible as we can. Currently EDK II contains
> > two submodules
> >
> > - CryptoPkg/Library/OpensslLib/openssl
> > - ArmPkg/Library/ArmSoftFloatLib/berkeley-softfloat-3
> > +- RiscVPkg/Library/RiscVOpensbiLib/opensbi
> >
> > The latter one is actually required by previous one. It's inevitable
> > in openssl-1.1.1 (since stable201905) for floating point parameter
> > --
> > 2.7.4
> >
> >
> >
> >
[-- Attachment #2: Type: message/rfc822, Size: 26434 bytes --]
From: "Chang, Abner (HPS SW/FW Technologist)" <abner.chang@hpe.com>
To: "devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Chang, Abner (HPS SW/FW Technologist)" <abner.chang@hpe.com>
Subject: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 00/39] RISC-V EDK2 Port on
Date: Mon, 28 Oct 2019 01:58:38 +0000
Message-ID: <15D1AEC59F048373.15779@groups.io>
The order of first 27 pacthes in "RISC-V-V2 PATCH v3" is identical to
"RISC-V-V2 PATCH v2", this is easier for reviewers to compare this set with v2.
This branch "RISC-V-V2" is used to contribute RISC-V architecture on EDK2.
The main changes of these series of patches are,
- Add RiscVPkg which conform with RISC-V Privilege Spec v1.10.
- Add RiscVPlatformPkg which provides common RISC-V library and driver modules
for RISC-V platform.
- Incorporate and leverage RISC-V OpenSBI to provide EDK2 port OpenSBI library.
- Provide RISC-V platform implementation specific drivers to EDK2 RISC-V platform
package.
- Provide generic RISC-V SMBIOS DXE drive to create SMBIOS type 4, 7 and 44 records,
in which the SMBIOS type 44 record is introduced in SMBIOS spec 3.3.0.
Besides of patches, you can also get code from belwo git repositories.
- edk2-platforms/devel-riscv-v2-PATCHv5 for RISC-V platform,
https://github.com/gilbert225/edk2-platforms/tree/devel-riscv-v2-PATCHv5
- edk2-staging-riscv/RISC-V-V2-v3 for RISC-V,
https://github.com/changab/edk2-staging-riscv/tree/RISC-V-V2-v3
KNOWN ISSUES of this set of patches.
1. 0024-BaseTools-BaseTools-changes-for-RISC-V-platform
* Line ending ('\n') is not CRLF
File: BaseTools/Source/Python/Common/DataType.py
Lines: TAB_COMPILER_MSFT = 'MSFT'
Not caused by chages of RISC-V edk2 port, will need a sperate patch to fix
this issue.
2. 0027-RiscVPkg-RiscVOpensbLlib-Add-submodule-opensbi
* Tab character used
Not caused by chages of RISC-V edk2 port. Shall we fix this in .gitmodule?
* Line ending ('\n') is not CRLF
File: RiscVPkg/Library/RiscVOpensbiLib/opensbi
Line: Subproject commit be92da280d87c38a2e0adc5d3f43bab7b5468f09
Caused by submodle itself.
3. Some patches have subject is too long issue.
Abner Chang (38):
RiscVPkg: RISC-V processor package.
RiscVPkg/Include: Add header files of RISC-V CPU package
RiscVPkg/opensbi: EDK2 RISC-V OpenSBI support
MdePkg: RISC-V RV64 binding in MdePkg
MdePkg/Include: RISC-V definitions.
MdeModulePkg/CapsuleRuntimeDxe: Add RISCV64 arch.
MdePkg/BaseLib: BaseLib for RISC-V RV64 Processor.
MdePkg/BaseCacheMaintenanceLib: RISC-V cache maintenance
implementation.
MdePkg/BaseIoLibIntrinsic: RISC-V I/O intrinsic functions.
MdePkg/BasePeCoff: Add RISC-V PE/Coff related code.
MdePkg/BaseCpuLib: RISC-V Base CPU library implementation.
MdePkg/BaseSynchronizationLib: RISC-V cache related code.
MdeModulePkg/Logo
NetworkPkg
RiscVPkg/Library: RISC-V CPU library
RiscVPkg/Library: Add RISC-V exception library
RiscVPkg/Library: Add RISC-V timer library
RiscVPkg/Library: Add EDK2 RISC-V OpenSBI library.
RiscVPkg/Library: RISC-V platform level DxeIPL libraries.
MdeModulePkg/DxeIplPeim : RISC-V platform level DxeIPL
RiscVPkg/PeiServicesTablePointerLibOpenSbi: RISC-V PEI Service
Table Pointer library
RiscVPlatformPkg/RiscVPlatformTempMemoryInit: RISC-V Platform
Temporary Memory library
RiscVPkg/CpuDxe: Add RISC-V CPU DXE driver.
BaseTools: BaseTools changes for RISC-V platform.
BaseTools/Scripts
RiscVPkg/SmbiosDxe: Generic SMBIOS DXE driver for RISC-V
platforms.
RiscVPkg/RiscVOpensbLlib: Add submodule opensbi
RiscVPlatformPkg/FirmwareContextProcessorSpecificLib:Add
FirmwareContextProcessorSpecificLib module
RiscVPlatformPkg/RealTimeClockLibNull: Null instance of RTC lib.
RiscVPlatformPkg/OpensbiPlatformLibNull: NULL instance of
RiscVOpensbiPlatformLib
RiscVPlatformPkg/PlatformMemoryTestLibNull: NULL instance of
PlatformMemoryTestLib
RiscVPlatformPkg/PlatformUpdateProgressLibNull: NULL instance of
PlatformUpdateProgressLib
RiscVPlatformPkg/PlatformBootManagerLib: Platform Boot Manager
library.
RiscVPkg/RiscVPlatformTimerLibNull: NULL instance of RISC-V platform
timer library.
RiscVPlatformPkg: Add RiscVPlatformPkg
edk2-staging:RISC-V-V2: Add RiscVEdk2Readme.md
edk2-staging: Revise Maintainers.txt for RISC-V packages
edk2-staging: Revise Readme.md
Anup Patel (1):
RiscVPlatformPkg/SecMain: RISC-V SecMain module.
MdePkg/MdePkg.dec | 5 +-
RiscVPkg/RiscVPkg.dec | 41 ++
RiscVPlatformPkg/RiscVPlatformPkg.dec | 72 +++
NetworkPkg/Network.dsc.inc | 2 +-
RiscVPkg/RiscVPkg.dsc | 92 ++++
RiscVPlatformPkg/RiscVPlatformPkg.dsc | 73 +++
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 13 +-
MdeModulePkg/Logo/Logo.inf | 2 +-
.../CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf | 9 +-
.../BaseCacheMaintenanceLib.inf | 4 +
MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 6 +-
.../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 12 +-
MdePkg/Library/BaseLib/BaseLib.inf | 18 +-
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
.../BaseSynchronizationLib.inf | 5 +
.../PeiServicesTablePointerLibOpenSbi.inf | 38 ++
RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf | 34 ++
.../RiscVDxeIplHandoffLib.inf | 32 ++
.../RiscVDxeIplHandoffOpenSbiLib.inf | 33 ++
.../CpuExceptionHandlerDxeLib.inf | 43 ++
.../Library/RiscVOpensbiLib/RiscVOpensbiLib.inf | 53 ++
.../RiscVPlatformTimerLib.inf | 35 ++
.../Library/RiscVTimerLib/BaseRiscVTimerLib.inf | 34 ++
RiscVPkg/Universal/CpuDxe/CpuDxe.inf | 48 ++
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf | 55 ++
.../FirmwareContextProcessorSpecificLib.inf | 31 ++
.../OpensbiPlatformLibNull.inf | 38 ++
.../PlatformBootManagerLib.inf | 61 +++
.../PlatformMemoryTestLibNull.inf | 29 +
.../PlatformUpdateProgressLibNull.inf | 29 +
.../RealTimeClockLibNull/RealTimeClockLibNull.inf | 30 ++
.../RiscVPlatformTempMemoryInitLibNull.inf | 34 ++
RiscVPlatformPkg/Universal/Sec/SecMain.inf | 72 +++
BaseTools/Source/C/Common/PeCoffLib.h | 9 +
BaseTools/Source/C/GenFw/elf_common.h | 62 +++
.../Source/C/Include/IndustryStandard/PeImage.h | 6 +
MdePkg/Include/IndustryStandard/PeImage.h | 12 +
MdePkg/Include/Library/BaseLib.h | 26 +
MdePkg/Include/Protocol/DebugSupport.h | 55 ++
MdePkg/Include/Protocol/PxeBaseCode.h | 4 +
MdePkg/Include/RiscV64/ProcessorBind.h | 173 ++++++
MdePkg/Include/Uefi/UefiBaseType.h | 13 +
MdePkg/Include/Uefi/UefiSpec.h | 5 +
.../Library/BasePeCoffLib/BasePeCoffLibInternals.h | 9 +
RiscVPkg/Include/IndustryStandard/RiscV.h | 118 ++++
RiscVPkg/Include/Library/RiscVCpuLib.h | 68 +++
RiscVPkg/Include/Library/RiscVPlatformDxeIpl.h | 41 ++
RiscVPkg/Include/ProcessorSpecificHobData.h | 97 ++++
RiscVPkg/Include/RiscVImpl.h | 72 +++
RiscVPkg/Include/SmbiosProcessorSpecificData.h | 57 ++
RiscVPkg/Include/sbi/SbiFirmwareContext.h | 33 ++
RiscVPkg/Include/sbi/sbi.h | 52 ++
RiscVPkg/Include/sbi/sbi_bits.h | 17 +
RiscVPkg/Include/sbi/sbi_types.h | 45 ++
.../RiscVExceptionLib/CpuExceptionHandlerLib.h | 16 +
RiscVPkg/Universal/CpuDxe/CpuDxe.h | 199 +++++++
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.h | 23 +
.../Library/FirmwareContextProcessorSpecificLib.h | 42 ++
.../Library/RiscVPlatformTempMemoryInitLib.h | 17 +
.../PlatformBootManagerLib/PlatformBootManager.h | 117 ++++
RiscVPlatformPkg/Universal/Sec/SecMain.h | 57 ++
BaseTools/Source/C/Common/BasePeCoff.c | 15 +-
BaseTools/Source/C/Common/PeCoffLoaderEx.c | 86 +++
BaseTools/Source/C/GenFv/GenFvInternalLib.c | 128 ++++-
BaseTools/Source/C/GenFw/Elf32Convert.c | 5 +-
BaseTools/Source/C/GenFw/Elf64Convert.c | 282 +++++++++-
MdeModulePkg/Core/DxeIplPeim/RiscV64/DxeLoadFunc.c | 76 +++
.../Library/BaseCacheMaintenanceLib/RiscVCache.c | 250 +++++++++
MdePkg/Library/BaseIoLibIntrinsic/IoLibArm.c | 593 ---------------------
MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c | 593 +++++++++++++++++++++
MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c | 27 +
MdePkg/Library/BaseLib/RiscV64/CpuPause.c | 29 +
MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c | 24 +
MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c | 25 +
MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c | 35 ++
.../Library/BaseLib/RiscV64/InternalSwitchStack.c | 55 ++
MdePkg/Library/BaseLib/RiscV64/LongJump.c | 32 ++
MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
.../Library/BasePeCoffLib/RiscV/PeCoffLoaderEx.c | 133 +++++
.../PeiServicesTablePointerOpenSbi.c | 121 +++++
.../RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.c | 41 ++
.../RiscVDxeIplHandoffOpenSbiLib.c | 101 ++++
.../RiscVExceptionLib/CpuExceptionHandlerLib.c | 191 +++++++
RiscVPkg/Library/RiscVTimerLib/RiscVTimerLib.c | 199 +++++++
RiscVPkg/Universal/CpuDxe/CpuDxe.c | 317 +++++++++++
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.c | 339 ++++++++++++
.../FirmwareContextProcessorSpecificLib.c | 94 ++++
.../Library/OpensbiPlatformLibNull/Platform.c | 44 ++
.../PlatformBootManagerLib/PlatformBootManager.c | 243 +++++++++
.../Library/PlatformBootManagerLib/PlatformData.c | 49 ++
.../PlatformMemoryTestLibNull.c | 29 +
.../PlatformUpdateProgressLibNull.c | 52 ++
.../RealTimeClockLibNull/RealTimeClockLibNull.c | 204 +++++++
RiscVPlatformPkg/Universal/Sec/SecMain.c | 523 ++++++++++++++++++
Readme.md | 1 +
RiscVEdk2Readme.md | 64 +++
RiscVPlatformPkg/Readme.md | 78 +++
.gitmodules | 15 +-
BaseTools/Conf/build_rule.template | 54 +-
BaseTools/Conf/tools_def.template | 64 ++-
BaseTools/Scripts/GccBaseRiscV.lds | 79 +++
BaseTools/Source/Python/Common/DataType.py | 7 +-
BaseTools/Source/Python/Common/buildoptions.py | 6 +-
Maintainers.txt | 15 +
MdePkg/Library/BaseCpuLib/BaseCpuLib.uni | 5 +-
MdePkg/Library/BaseCpuLib/RiscV/Cpu.S | 19 +
MdePkg/Library/BaseLib/RiscV64/FlushCache.S | 21 +
.../Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S | 14 +
MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S | 14 +
MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 32 ++
.../Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S | 55 ++
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +
.../RiscV64/SynchronizationAsm.S | 78 +++
.../PeiServicesTablePointerLibOpenSbi.uni | 23 +
RiscVPkg/Library/RiscVCpuLib/Cpu.S | 115 ++++
.../RiscVExceptionLib/CpuExceptionHandlerLib.uni | 13 +
.../RiscVExceptionLib/SupervisorTrapHandler.S | 88 +++
RiscVPkg/Library/RiscVOpensbiLib/opensbi | 1 +
.../RiscVPlatformTimerLibNull.S | 40 ++
RiscVPkg/RiscVPkg.uni | 13 +
RiscVPkg/RiscVPkgExtra.uni | 13 +
RiscVPkg/Universal/CpuDxe/CpuDxe.uni | 13 +
RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni | 14 +
RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni | 12 +
.../Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni | 13 +
.../Library/PlatformBootManagerLib/Strings.uni | 28 +
.../Riscv64/TempMemInit.S | 26 +
RiscVPlatformPkg/RiscVPlatformPkg.uni | 15 +
RiscVPlatformPkg/RiscVPlatformPkgExtra.uni | 12 +
RiscVPlatformPkg/Universal/Sec/Riscv64/SecEntry.S | 442 +++++++++++++++
130 files changed, 8320 insertions(+), 655 deletions(-)
create mode 100644 RiscVPkg/RiscVPkg.dec
create mode 100644 RiscVPlatformPkg/RiscVPlatformPkg.dec
create mode 100644 RiscVPkg/RiscVPkg.dsc
create mode 100644 RiscVPlatformPkg/RiscVPlatformPkg.dsc
create mode 100644 RiscVPkg/Library/PeiServicesTablePointerLibOpenSbi/PeiServicesTablePointerLibOpenSbi.inf
create mode 100644 RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffLib/RiscVDxeIplHandoffLib.inf
create mode 100644 RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/RiscVDxeIplHandoffOpenSbiLib.inf
create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerDxeLib.inf
create mode 100644 RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf
create mode 100644 RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLib.inf
create mode 100644 RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.inf
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf
create mode 100644 RiscVPlatformPkg/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
create mode 100644 RiscVPlatformPkg/Library/OpensbiPlatformLibNull/OpensbiPlatformLibNull.inf
create mode 100644 RiscVPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
create mode 100644 RiscVPlatformPkg/Library/PlatformMemoryTestLibNull/PlatformMemoryTestLibNull.inf
create mode 100644 RiscVPlatformPkg/Library/PlatformUpdateProgressLibNull/PlatformUpdateProgressLibNull.inf
create mode 100644 RiscVPlatformPkg/Library/RealTimeClockLibNull/RealTimeClockLibNull.inf
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create mode 100644 RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHandlerLib.uni
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create mode 100644 RiscVPkg/Library/RiscVPlatformTimerLibNull/RiscVPlatformTimerLibNull.S
create mode 100644 RiscVPkg/RiscVPkg.uni
create mode 100644 RiscVPkg/RiscVPkgExtra.uni
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxe.uni
create mode 100644 RiscVPkg/Universal/CpuDxe/CpuDxeExtra.uni
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.uni
create mode 100644 RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxeExtra.uni
create mode 100644 RiscVPlatformPkg/Library/PlatformBootManagerLib/Strings.uni
create mode 100644 RiscVPlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/Riscv64/TempMemInit.S
create mode 100644 RiscVPlatformPkg/RiscVPlatformPkg.uni
create mode 100644 RiscVPlatformPkg/RiscVPlatformPkgExtra.uni
create mode 100644 RiscVPlatformPkg/Universal/Sec/Riscv64/SecEntry.S
--
2.7.4
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^ permalink raw reply [flat|nested] 77+ messages in thread* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 39/39] edk2-staging: Revise Readme.md
2019-11-22 2:05 ` Abner Chang
@ 2019-11-22 9:42 ` Leif Lindholm
2019-11-22 11:46 ` Abner Chang
0 siblings, 1 reply; 77+ messages in thread
From: Leif Lindholm @ 2019-11-22 9:42 UTC (permalink / raw)
To: devel, abner.chang
Cc: Andrew Fish, Laszlo Ersek, Michael D Kinney, Chen, Gilbert
On Fri, Nov 22, 2019 at 02:05:30 +0000, Abner Chang wrote:
> Palmer removed.
>
> > -----Original Message-----
> > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > Sent: Friday, November 22, 2019 1:15 AM
> > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> > <abner.chang@hpe.com>
> > Cc: Andrew Fish <afish@apple.com>; Laszlo Ersek <lersek@redhat.com>;
> > Michael D Kinney <michael.d.kinney@intel.com>; Chen, Gilbert
> > <gilbert.chen@hpe.com>; Palmer Dabbelt <palmer@sifive.com>
> > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 39/39] edk2-
> > staging: Revise Readme.md
> >
> > Well, there's no 0/39 for me to give a generic comment on (please use a
> > cover-letter).
>
> There is a cover letter sent with this set of patches, you probably
> missed it. attached here in case you would like to give comments
> there.
Ah, having the original made it possible for me to find it in gmail.
I think you forgot to cc me on the cover letter(s - the same for the
edk2-platforms one), while I was Cc:d on each of the individual
patches.
(I can find the edk2-platforms one as well now.)
/
Leif
^ permalink raw reply [flat|nested] 77+ messages in thread* Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 39/39] edk2-staging: Revise Readme.md
2019-11-22 9:42 ` Leif Lindholm
@ 2019-11-22 11:46 ` Abner Chang
0 siblings, 0 replies; 77+ messages in thread
From: Abner Chang @ 2019-11-22 11:46 UTC (permalink / raw)
To: Leif Lindholm, devel@edk2.groups.io
Cc: Andrew Fish, Laszlo Ersek, Michael D Kinney, Chen, Gilbert
Oops. You are right. Just forward that email to all in CCed.
-----Original Message-----
From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
Sent: Friday, November 22, 2019 5:43 PM
To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>
Cc: Andrew Fish <afish@apple.com>; Laszlo Ersek <lersek@redhat.com>; Michael D Kinney <michael.d.kinney@intel.com>; Chen, Gilbert <gilbert.chen@hpe.com>
Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 39/39] edk2-staging: Revise Readme.md
On Fri, Nov 22, 2019 at 02:05:30 +0000, Abner Chang wrote:
> Palmer removed.
>
> > -----Original Message-----
> > From: Leif Lindholm [mailto:leif.lindholm@linaro.org]
> > Sent: Friday, November 22, 2019 1:15 AM
> > To: devel@edk2.groups.io; Chang, Abner (HPS SW/FW Technologist)
> > <abner.chang@hpe.com>
> > Cc: Andrew Fish <afish@apple.com>; Laszlo Ersek <lersek@redhat.com>;
> > Michael D Kinney <michael.d.kinney@intel.com>; Chen, Gilbert
> > <gilbert.chen@hpe.com>; Palmer Dabbelt <palmer@sifive.com>
> > Subject: Re: [edk2-devel] [edk2-staging/RISC-V-V2 PATCH v3 39/39]
> > edk2-
> > staging: Revise Readme.md
> >
> > Well, there's no 0/39 for me to give a generic comment on (please
> > use a cover-letter).
>
> There is a cover letter sent with this set of patches, you probably
> missed it. attached here in case you would like to give comments
> there.
Ah, having the original made it possible for me to find it in gmail.
I think you forgot to cc me on the cover letter(s - the same for the edk2-platforms one), while I was Cc:d on each of the individual patches.
(I can find the edk2-platforms one as well now.)
/
Leif
^ permalink raw reply [flat|nested] 77+ messages in thread