From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: redhat.com, ip: 209.132.183.28, mailfrom: pbonzini@redhat.com) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Wed, 21 Aug 2019 10:39:56 -0700 Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 093F84E4E6 for ; Wed, 21 Aug 2019 17:39:56 +0000 (UTC) Received: by mail-wm1-f71.google.com with SMTP id x13so1467756wmj.9 for ; Wed, 21 Aug 2019 10:39:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:openpgp:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=3fIbpvs6SbC2YcldVU0fUEsoUNj38bm721AqOi/WasY=; b=ZKfmm1YCr3Q1gt1kY2uv3aRBEYGQogBW95jwEGdBtW3UUqgfU3EU3frIZIWp8Tt6m/ LZUbK+dbDZGBnaRX+X5jhJRgAm5dkOapAX5CFA5LF6CMLwYkgir8tkUdIjbl4LakSh+M aNzYhJkFM1PegqYtHvAFvgTxx2Kza/eIm4+fN40s1elsa7weEQ1UAL9Ds2BvLtk2rvMq OU2ByGE1yBPoaqQfy6uV+Azpk/FjDGwr06t3NiDDs4Umvy4vbAAKLG+T515Ho3uIyOyG YW8qFR3cDrp5D1BEWEEv6k3B1YJgVhXOHtlyff27pyQRAM3CfMFaPfJ3FqL1EhvclNij QZVw== X-Gm-Message-State: APjAAAWToOVoPIekjyRTtObKjFeuSNY0+8Ve2lSdjuFH99GrAsRaAg9o cTRZiXLVWWi2PFWS9cqAgP/ez0+AHQFjocC9BgynSgCdahCHEzX9ZhbBlju+hRLOWRuyEiqPK4A 5hzLRw11RDoCTwQ== X-Received: by 2002:a1c:cb01:: with SMTP id b1mr1356240wmg.69.1566409194575; Wed, 21 Aug 2019 10:39:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqwOlsiuoI8bDDbDdjGjhf3ZCdr2vxHB6S5LHFmsN/e4KHtKJvvUqplimeFuI/HyjgvFW2dbLg== X-Received: by 2002:a1c:cb01:: with SMTP id b1mr1356216wmg.69.1566409194282; Wed, 21 Aug 2019 10:39:54 -0700 (PDT) Received: from ?IPv6:2001:b07:6468:f312:21b9:ff1f:a96c:9fb3? ([2001:b07:6468:f312:21b9:ff1f:a96c:9fb3]) by smtp.gmail.com with ESMTPSA id l5sm390331wmj.4.2019.08.21.10.39.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Aug 2019 10:39:53 -0700 (PDT) Subject: Re: [edk2-rfc] [edk2-devel] CPU hotplug using SMM with QEMU+OVMF To: "Kinney, Michael D" , "rfc@edk2.groups.io" , "Yao, Jiewen" Cc: Alex Williamson , Laszlo Ersek , "devel@edk2.groups.io" , qemu devel list , Igor Mammedov , "Chen, Yingwen" , "Nakajima, Jun" , Boris Ostrovsky , Joao Marcal Lemos Martins , Phillip Goerl References: <8091f6e8-b1ec-f017-1430-00b0255729f4@redhat.com> <74D8A39837DF1E4DA445A8C0B3885C503F75B680@shsmsx102.ccr.corp.intel.com> <047801f8-624a-2300-3cf7-1daa1395ce59@redhat.com> <99219f81-33a3-f447-95f8-f10341d70084@redhat.com> <6f8b9507-58d0-5fbd-b827-c7194b3b2948@redhat.com> <74D8A39837DF1E4DA445A8C0B3885C503F75FAD3@shsmsx102.ccr.corp.intel.com> <7cb458ea-956e-c1df-33f7-025e4f0f22df@redhat.com> <74D8A39837DF1E4DA445A8C0B3885C503F7600B9@shsmsx102.ccr.corp.intel.com> <20190816161933.7d30a881@x1.home> <74D8A39837DF1E4DA445A8C0B3885C503F761B96@shsmsx102.ccr.corp.intel.com> <35396800-32d2-c25f-b0d0-2d7cd8438687@redhat.com> From: Paolo Bonzini Openpgp: preference=signencrypt Message-ID: Date: Wed, 21 Aug 2019 19:39:52 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=iso-2022-jp Content-Language: en-US Content-Transfer-Encoding: 7bit On 21/08/19 19:25, Kinney, Michael D wrote: > Could we have an initial SMBASE that is within TSEG. > > If we bring in hot plug CPUs one at a time, then initial > SMBASE in TSEG can reprogram the SMBASE to the correct > value for that CPU. > > Can we add a register to the hot plug controller that > allows the BSP to set the initial SMBASE value for > a hot added CPU? The default can be 3000:8000 for > compatibility. > > Another idea is when the SMI handler runs for a hot add > CPU event, the SMM monarch programs the hot plug controller > register with the SMBASE to use for the CPU that is being > added. As each CPU is added, a different SMBASE value can > be programmed by the SMM Monarch. Yes, all of these would work. Again, I'm interested in having something that has a hope of being implemented in real hardware. Another, far easier to implement possibility could be a lockable MSR (could be the existing MSR_SMM_FEATURE_CONTROL) that allows programming the SMBASE outside SMM. It would be nice if such a bit could be defined by Intel. Paolo