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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by DS1PEPF0000E642.mail.protection.outlook.com (10.167.17.198) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6178.13 via Frontend Transport; Fri, 17 Mar 2023 06:29:00 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Fri, 17 Mar 2023 01:28:59 -0500 Received: from BLR-LAB-SFW01.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Fri, 17 Mar 2023 01:28:58 -0500 From: "Abdul Lateef Attar" To: CC: Abdul Lateef Attar , Ard Biesheuvel , Leif Lindholm , Michael D Kinney Subject: [PATCH v2 3/4] Platform/AMD/BoarkPkg: Adds SetCacheMtrrLib library Date: Fri, 17 Mar 2023 11:58:47 +0530 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Return-Path: AbdulLateef.Attar@amd.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E642:EE_|SA1PR12MB6871:EE_ X-MS-Office365-Filtering-Correlation-Id: 4e539316-985a-4ba0-9399-08db26b0e529 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2023 06:29:00.3082 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4e539316-985a-4ba0-9399-08db26b0e529 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E642.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6871 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain Adds SetCacheMtrrLib library for AMD processor based boards. This library sets MTRR value or various memory ranges. Signed-off-by: Abdul Lateef Attar Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Abner Chang --- Platform/AMD/BoardPkg/BoardPkg.dsc | 10 ++ .../SetCacheMtrrLib/SetCacheMtrrLib.inf | 37 +++++ .../Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 132 ++++++++++++++++++ 3 files changed, 179 insertions(+) create mode 100644 Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheM= trrLib.inf create mode 100644 Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheM= trrLib.c diff --git a/Platform/AMD/BoardPkg/BoardPkg.dsc b/Platform/AMD/BoardPkg/Boa= rdPkg.dsc index cb4065b86c60..aa0ee8287cd8 100644 --- a/Platform/AMD/BoardPkg/BoardPkg.dsc +++ b/Platform/AMD/BoardPkg/BoardPkg.dsc @@ -18,3 +18,13 @@ [Defines] =20 [Packages] BoardPkg/BoardPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses.common.PEIM] + SetCacheMtrrLib|BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf + +[Components.IA32] + BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf + diff --git a/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.= inf b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf new file mode 100644 index 000000000000..c66661d3f8dc --- /dev/null +++ b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf @@ -0,0 +1,37 @@ +## @file +# Component information file for Platform SetCacheMtrr Library. +# This library implementation is for AMD processor based platforms. +# +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 1.29 + BASE_NAME =3D PeiSetCacheMtrrLib + FILE_GUID =3D 1E8468E0-5EB4-4088-9B52-BFDC6E4DAE87 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SetCacheMtrrLib + +[LibraryClasses] + BaseLib + DebugLib + MtrrLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[Sources] + SetCacheMtrrLib.c + +[Guids] + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize + diff --git a/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.= c b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c new file mode 100644 index 000000000000..18404405d9fa --- /dev/null +++ b/Platform/AMD/BoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c @@ -0,0 +1,132 @@ +/** @file + +SetCacheMtrr library functions. +This library implementation is for AMD processor based platforms. + +Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +/** + This function sets the cache MTRR values for PEI phase. +**/ +VOID +EFIAPI +SetCacheMtrr ( + VOID + ) +{ + EFI_STATUS Status; + + Status =3D MtrrSetMemoryAttribute ( + 0, + 0xA0000, + CacheWriteBack + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteBack for 0-0x9FFFF\n", + Status + )); + } + + Status =3D MtrrSetMemoryAttribute ( + 0xA0000, + 0x20000, + CacheUncacheable + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheUncacheable for 0xA0000-0xBFFFF\n", + Status + )); + } + + Status =3D MtrrSetMemoryAttribute ( + 0xC0000, + 0x40000, + CacheWriteProtected + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteProtected for 0xC0000-0xFFFFF\n", + Status + )); + } + + Status =3D MtrrSetMemoryAttribute ( + 0x100000, + 0xAFF00000, + CacheWriteBack + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteBack for 0x100000-0xAFFFFFFF\n", + Status + )); + } + + Status =3D MtrrSetMemoryAttribute ( + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaSize), + CacheWriteProtected + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteProtected for 0x%X-0x%X\n", + Status, + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaBaseAddress) + PcdGet32 (PcdFlashAreaSize) + )); + } + + MtrrDebugPrintAllMtrrs (); + return; +} + +/** + Update MTRR setting in EndOfPei phase. + This function will set the MTRR value as CacheUncacheable + for Flash address. + + @retval EFI_SUCCESS The function completes successfully. + @retval Others Some error occurs. +**/ +EFI_STATUS +EFIAPI +SetCacheMtrrAfterEndOfPei ( + VOID + ) +{ + EFI_STATUS Status; + + Status =3D MtrrSetMemoryAttribute ( + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaSize), + CacheUncacheable + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheUncacheable for 0x%X-0x%X\n", + Status, + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaBaseAddress) + PcdGet32 (PcdFlashAreaSize) + )); + } + + MtrrDebugPrintAllMtrrs (); + return EFI_SUCCESS; +} --=20 2.25.1