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Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB3915.namprd12.prod.outlook.com (2603:10b6:5:1c4::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2835.22; Tue, 24 Mar 2020 17:42:12 +0000 Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2835.023; Tue, 24 Mar 2020 17:42:12 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [PATCH v6 37/42] UefiCpuPkg: Add a 16-bit protected mode code segment descriptor Date: Tue, 24 Mar 2020 12:40:51 -0500 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-ClientProxiedBy: DM5PR06CA0025.namprd06.prod.outlook.com (2603:10b6:3:5d::11) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) Return-Path: thomas.lendacky@amd.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR06CA0025.namprd06.prod.outlook.com (2603:10b6:3:5d::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2835.19 via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: NtZsP12Ab+1DCUlERCNLiOr3g9ulpwdMo6UB1ABAObxmgah7L1z5LTxN0vGVXcuqFPofMmU8PIAY/jtaoizaZ6hzeexG2KqF/ZA/bI+OFLncZVpb4/gEuZRJ4jaWhmff7w2DoOqt3Coxd4eY4N27yGj3wZyW8tjJ9MQa8vErAyUKp2DseN6YY8DoTX7trNPsVOcl8rgFzV0TbzMkQWjETpilHhlbt8UpYqiHOA92CSavhwqiBB/4IWSBbLVisl7/ZJiGQny978qUa5uXi4g8ruxfYlGN2/Y4bnmJMRC5tylOWbCluVu2YB+lUbGy3pUI9L1s+kt3jGEUOvk/dRR11dIZYRhp/PbYacDHzuHSb4uBnM8neHGU0+s1BtTvJYk/H2ZdCYC/U9j8sMx7E5ywqZFA7nqjxnJDJayXMVogvYkUnurN9PAulrWmoGgsU5t+Xf6CC/GYaz0KNjFokHg7pcGK6sc6M+RYqLsztMdcuV2TUb/3q4/3SxhgEvzLYXWTDx2en5K06Ft+pmwbHI+Nz2nssHYC3jlh4RiUegHcLHu/yU+eGHbjfk+VW6CmdqUpa/vtt5/ygSWzJSAFeL/Rjw== X-MS-Exchange-AntiSpam-MessageData: JifYmdv2dcIsmRXwMXUsmLJ/DCViXLtcLAlzHD9+LMNrzwKaaTA6BQXyqNqnN1Kg27DHG+5Acyg1J8H0Owtw46xI7WVqNvwZ7h44NxvYTLbN7fz7CNEvZ1/6HpeMwlTm4vz6ZInNmFHQnmrwVxHDqQ== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 60e57b3d-94fe-48a1-59bc-08d7d01a9eca X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Mar 2020 17:41:45.0001 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: F7K3CJedp6w+QRuc0K9Ej85wioMn6ZkwrNy2z/UQ1Fu0Y24n1FbX8sww/ReEqwZmEYzYNFf8j4qLsqsp+aeFXQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3915 Content-Type: text/plain BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 A hypervisor is not allowed to update an SEV-ES guests register state, so when booting an SEV-ES guest AP, the hypervisor is not allowed to set the RIP to the guest requested value. Instead, an SEV-ES AP must be transition from 64-bit long mode to 16-bit real mode in response to an INIT-SIPI-SIPI sequence. This requires a 16-bit code segment descriptor. For PEI, create this descriptor in the reset vector GDT table. For DXE, create this descriptor from the newly reserved entry at location 0x28. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- UefiCpuPkg/CpuDxe/CpuGdt.h | 4 ++-- UefiCpuPkg/CpuDxe/CpuGdt.c | 8 ++++---- UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 9 +++++++++ 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.h b/UefiCpuPkg/CpuDxe/CpuGdt.h index 3a0210b2f172..1c94487cbee8 100644 --- a/UefiCpuPkg/CpuDxe/CpuGdt.h +++ b/UefiCpuPkg/CpuDxe/CpuGdt.h @@ -36,7 +36,7 @@ struct _GDT_ENTRIES { GDT_ENTRY LinearCode; GDT_ENTRY SysData; GDT_ENTRY SysCode; - GDT_ENTRY Spare4; + GDT_ENTRY SysCode16; GDT_ENTRY LinearData64; GDT_ENTRY LinearCode64; GDT_ENTRY Spare5; @@ -49,7 +49,7 @@ struct _GDT_ENTRIES { #define LINEAR_CODE_SEL OFFSET_OF (GDT_ENTRIES, LinearCode) #define SYS_DATA_SEL OFFSET_OF (GDT_ENTRIES, SysData) #define SYS_CODE_SEL OFFSET_OF (GDT_ENTRIES, SysCode) -#define SPARE4_SEL OFFSET_OF (GDT_ENTRIES, Spare4) +#define SYS_CODE16_SEL OFFSET_OF (GDT_ENTRIES, SysCode16) #define LINEAR_DATA64_SEL OFFSET_OF (GDT_ENTRIES, LinearData64) #define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64) #define SPARE5_SEL OFFSET_OF (GDT_ENTRIES, Spare5) diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.c b/UefiCpuPkg/CpuDxe/CpuGdt.c index 64efadeba601..a1ab543f2da5 100644 --- a/UefiCpuPkg/CpuDxe/CpuGdt.c +++ b/UefiCpuPkg/CpuDxe/CpuGdt.c @@ -70,14 +70,14 @@ STATIC GDT_ENTRIES GdtTemplate = { 0x0, }, // - // SPARE4_SEL + // SYS_CODE16_SEL // { - 0x0, // limit 15:0 + 0x0FFFF, // limit 15:0 0x0, // base 15:0 0x0, // base 23:16 - 0x0, // type - 0x0, // limit 19:16, flags + 0x09A, // present, ring 0, code, execute/read + 0x08F, // page-granular, 16-bit 0x0, // base 31:24 }, // diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm index ce4ebfffb688..0e79a3984b16 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm @@ -129,5 +129,14 @@ LINEAR_CODE64_SEL equ $-GDT_BASE DB 0 ; base 31:24 %endif +; linear code segment descriptor +LINEAR_CODE16_SEL equ $-GDT_BASE + DW 0xffff ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE32_TYPE) + DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(0)|CODE64_FLAG(0)|UPPER_LIMIT(0xf) + DB 0 ; base 31:24 + GDT_END: -- 2.17.1