[PATCH 0/3] OvmfPkg/QemuVideoDxe/VbeShim: handle PAM1 register on Q35 correctly

[PATCH 0/3] OvmfPkg/QemuVideoDxe/VbeShim: handle PAM1 register on Q35 correctly

[Laszlo Ersek]

Repo:   https://github.com/lersek/edk2.git
Branch: vbe_shim_q35_pam

Fix the long-standing OVMF/Q35 bug recently exposed by a QEMU change,
and reported under <https://bugs.launchpad.net/qemu/+bug/1715700>.

Aleksei, can you please fetch the branch, build it, and report back with
your Tested-by if it works for you?

I performed my own tests as well; I'll include those in a separate
email.

Cc: Aleksei Kovura <alex3kov@zoho.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>

Thank you,
Laszlo

Laszlo Ersek (3):
  OvmfPkg/CsmSupportLib: move PAM register addresses to IndustryStandard
  OvmfPkg/QemuVideoDxe/VbeShim: rename Status to
    Segment0AllocationStatus
  OvmfPkg/QemuVideoDxe/VbeShim: handle PAM1 register on Q35 correctly

 OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c       | 62 ++++++++++----------
 OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h       | 22 +------
 OvmfPkg/Include/IndustryStandard/I440FxPiix4.h | 13 ++++
 OvmfPkg/Include/IndustryStandard/Q35MchIch9.h  |  8 +++
 OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf          |  3 +-
 OvmfPkg/QemuVideoDxe/VbeShim.c                 | 47 ++++++++++++---
 6 files changed, 95 insertions(+), 60 deletions(-)

-- 
2.14.1.3.gb7cf6e02401b

[PATCH 1/3] OvmfPkg/CsmSupportLib: move PAM register addresses to IndustryStandard

[Laszlo Ersek]

* Introduce the PIIX4_PAM* and MCH_PAM* macros under
  "OvmfPkg/Include/IndustryStandard". These macros capture the PAM
  register offsets (in PCI config space) on the respective Memory
  Controller B/D/F, from the respective data sheets.

* Under IndustryStandard, introduce the PMC_REGISTER_PIIX4() macro for
  PIIX4. (For Q35, we already have DRAMC_REGISTER_Q35().) In both cases,
  the B/D/F is 0/0/0.

* Under CsmSupportLib, replace the "PAMRegOffset" field (UINT8) in the
  PAM_REGISTER_VALUE structure with "PAMRegPciLibAddress" (UINTN). The new
  field contains the return value of the PCI_LIB_ADDRESS() macro.

* Under CsmSupportLib, replace the "mRegisterValues440" elements as
  follows:

    REG_PAMx_OFFSET_440, ReadEnableData, WriteEnableData
    -->
    PMC_REGISTER_PIIX4 (PIIX4_PAMx), ReadEnableData, WriteEnableData

* Under CsmSupportLib, replace the "mRegisterValuesQ35" elements as
  follows:

    REG_PAMx_OFFSET_Q35, ReadEnableData, WriteEnableData
    -->
    DRAMC_REGISTER_Q35 (MCH_PAMx), ReadEnableData, WriteEnableData

* Under CsmSupportLib, update the register address calculations as follows
  (for all of PciOr8(), PciAnd8() and PciRead8()):

    PCI_LIB_ADDRESS (
      PAM_PCI_BUS,
      PAM_PCI_DEV,
      PAM_PCI_FUNC,
      mRegisterValues[Index].PAMRegOffset
      )
    -->
    mRegisterValues[Index].PAMRegPciLibAddress

* Under CsmSupportLib, remove the PAM_PCI_* and REG_PAM*_OFFSET_* macros.

Technically speaking, these changes could be split into three patches
(IndustryStandard macro additions, CsmSupportLib code updates,
CsmSupportLib macro removals). However, the patch is not big, and in this
case it is actually helpful to present the code movement / refactoring in
one step, for easier verification.

Cc: Aleksei Kovura <alex3kov@zoho.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Ref: https://bugs.launchpad.net/qemu/+bug/1715700
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
---
 OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h       | 22 +------
 OvmfPkg/Include/IndustryStandard/I440FxPiix4.h | 13 ++++
 OvmfPkg/Include/IndustryStandard/Q35MchIch9.h  |  8 +++
 OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c       | 62 ++++++++++----------
 4 files changed, 53 insertions(+), 52 deletions(-)

diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h
index f755a2a359e5..01d3109a7d7d 100644
--- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h
+++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h
@@ -30,26 +30,6 @@
 #include <Library/MemoryAllocationLib.h>
 #include <Library/UefiBootServicesTableLib.h>
 
-#define PAM_PCI_BUS        0
-#define PAM_PCI_DEV        0
-#define PAM_PCI_FUNC       0
-
-#define REG_PAM0_OFFSET_440    0x59    // Programmable Attribute Map 0
-#define REG_PAM1_OFFSET_440    0x5a    // Programmable Attribute Map 1
-#define REG_PAM2_OFFSET_440    0x5b    // Programmable Attribute Map 2
-#define REG_PAM3_OFFSET_440    0x5c    // Programmable Attribute Map 3
-#define REG_PAM4_OFFSET_440    0x5d    // Programmable Attribute Map 4
-#define REG_PAM5_OFFSET_440    0x5e    // Programmable Attribute Map 5
-#define REG_PAM6_OFFSET_440    0x5f    // Programmable Attribute Map 6
-
-#define REG_PAM0_OFFSET_Q35    0x90    // Programmable Attribute Map 0
-#define REG_PAM1_OFFSET_Q35    0x91    // Programmable Attribute Map 1
-#define REG_PAM2_OFFSET_Q35    0x92    // Programmable Attribute Map 2
-#define REG_PAM3_OFFSET_Q35    0x93    // Programmable Attribute Map 3
-#define REG_PAM4_OFFSET_Q35    0x94    // Programmable Attribute Map 4
-#define REG_PAM5_OFFSET_Q35    0x95    // Programmable Attribute Map 5
-#define REG_PAM6_OFFSET_Q35    0x96    // Programmable Attribute Map 6
-
 #define PAM_BASE_ADDRESS   0xc0000
 #define PAM_LIMIT_ADDRESS  BASE_1MB
 
@@ -67,7 +47,7 @@ typedef struct {
 // Provides a map of the PAM registers and bits used to set Read/Write access.
 //
 typedef struct {
-  UINT8   PAMRegOffset;
+  UINTN   PAMRegPciLibAddress;
   UINT8   ReadEnableData;
   UINT8   WriteEnableData;
 } PAM_REGISTER_VALUE;
diff --git a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
index baa4c063f16a..efe6e5c27834 100644
--- a/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
+++ b/OvmfPkg/Include/IndustryStandard/I440FxPiix4.h
@@ -27,6 +27,19 @@
 //
 #define INTEL_82441_DEVICE_ID 0x1237
 
+//
+// B/D/F/Type: 0/0/0/PCI
+//
+#define PMC_REGISTER_PIIX4(Offset) PCI_LIB_ADDRESS (0, 0, 0, (Offset))
+
+#define PIIX4_PAM0              0x59
+#define PIIX4_PAM1              0x5A
+#define PIIX4_PAM2              0x5B
+#define PIIX4_PAM3              0x5C
+#define PIIX4_PAM4              0x5D
+#define PIIX4_PAM5              0x5E
+#define PIIX4_PAM6              0x5F
+
 //
 // B/D/F/Type: 0/1/3/PCI
 //
diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
index 68485bec71f7..193a262e5b54 100644
--- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
+++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h
@@ -47,6 +47,14 @@
 #define MCH_PCIEXBAR_HIGH     0x64
 #define MCH_PCIEXBAR_HIGHMASK   0xFFFFFFF0
 
+#define MCH_PAM0              0x90
+#define MCH_PAM1              0x91
+#define MCH_PAM2              0x92
+#define MCH_PAM3              0x93
+#define MCH_PAM4              0x94
+#define MCH_PAM5              0x95
+#define MCH_PAM6              0x96
+
 #define MCH_SMRAM             0x9D
 #define MCH_SMRAM_D_LCK         BIT4
 #define MCH_SMRAM_G_SMRAME      BIT3
diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c
index 8d5d2e58a994..c13d4bb88f47 100644
--- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c
+++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c
@@ -52,35 +52,35 @@ STATIC LEGACY_MEMORY_SECTION_INFO   mSectionArray[] = {
 };
 
 STATIC PAM_REGISTER_VALUE  mRegisterValues440[] = {
-  {REG_PAM1_OFFSET_440, 0x01, 0x02},
-  {REG_PAM1_OFFSET_440, 0x10, 0x20},
-  {REG_PAM2_OFFSET_440, 0x01, 0x02},
-  {REG_PAM2_OFFSET_440, 0x10, 0x20},
-  {REG_PAM3_OFFSET_440, 0x01, 0x02},
-  {REG_PAM3_OFFSET_440, 0x10, 0x20},
-  {REG_PAM4_OFFSET_440, 0x01, 0x02},
-  {REG_PAM4_OFFSET_440, 0x10, 0x20},
-  {REG_PAM5_OFFSET_440, 0x01, 0x02},
-  {REG_PAM5_OFFSET_440, 0x10, 0x20},
-  {REG_PAM6_OFFSET_440, 0x01, 0x02},
-  {REG_PAM6_OFFSET_440, 0x10, 0x20},
-  {REG_PAM0_OFFSET_440, 0x10, 0x20}
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM1), 0x01, 0x02},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM1), 0x10, 0x20},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM2), 0x01, 0x02},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM2), 0x10, 0x20},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM3), 0x01, 0x02},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM3), 0x10, 0x20},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM4), 0x01, 0x02},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM4), 0x10, 0x20},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM5), 0x01, 0x02},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM5), 0x10, 0x20},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM6), 0x01, 0x02},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM6), 0x10, 0x20},
+  {PMC_REGISTER_PIIX4 (PIIX4_PAM0), 0x10, 0x20}
 };
 
 STATIC PAM_REGISTER_VALUE  mRegisterValuesQ35[] = {
-  {REG_PAM1_OFFSET_Q35, 0x01, 0x02},
-  {REG_PAM1_OFFSET_Q35, 0x10, 0x20},
-  {REG_PAM2_OFFSET_Q35, 0x01, 0x02},
-  {REG_PAM2_OFFSET_Q35, 0x10, 0x20},
-  {REG_PAM3_OFFSET_Q35, 0x01, 0x02},
-  {REG_PAM3_OFFSET_Q35, 0x10, 0x20},
-  {REG_PAM4_OFFSET_Q35, 0x01, 0x02},
-  {REG_PAM4_OFFSET_Q35, 0x10, 0x20},
-  {REG_PAM5_OFFSET_Q35, 0x01, 0x02},
-  {REG_PAM5_OFFSET_Q35, 0x10, 0x20},
-  {REG_PAM6_OFFSET_Q35, 0x01, 0x02},
-  {REG_PAM6_OFFSET_Q35, 0x10, 0x20},
-  {REG_PAM0_OFFSET_Q35, 0x10, 0x20}
+  {DRAMC_REGISTER_Q35 (MCH_PAM1), 0x01, 0x02},
+  {DRAMC_REGISTER_Q35 (MCH_PAM1), 0x10, 0x20},
+  {DRAMC_REGISTER_Q35 (MCH_PAM2), 0x01, 0x02},
+  {DRAMC_REGISTER_Q35 (MCH_PAM2), 0x10, 0x20},
+  {DRAMC_REGISTER_Q35 (MCH_PAM3), 0x01, 0x02},
+  {DRAMC_REGISTER_Q35 (MCH_PAM3), 0x10, 0x20},
+  {DRAMC_REGISTER_Q35 (MCH_PAM4), 0x01, 0x02},
+  {DRAMC_REGISTER_Q35 (MCH_PAM4), 0x10, 0x20},
+  {DRAMC_REGISTER_Q35 (MCH_PAM5), 0x01, 0x02},
+  {DRAMC_REGISTER_Q35 (MCH_PAM5), 0x10, 0x20},
+  {DRAMC_REGISTER_Q35 (MCH_PAM6), 0x01, 0x02},
+  {DRAMC_REGISTER_Q35 (MCH_PAM6), 0x10, 0x20},
+  {DRAMC_REGISTER_Q35 (MCH_PAM0), 0x10, 0x20}
 };
 
 STATIC PAM_REGISTER_VALUE *mRegisterValues;
@@ -145,12 +145,12 @@ LegacyRegionManipulationInternal (
     if (ReadEnable != NULL) {
       if (*ReadEnable) {
         PciOr8 (
-          PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),
+          mRegisterValues[Index].PAMRegPciLibAddress,
           mRegisterValues[Index].ReadEnableData
           );
       } else {
         PciAnd8 (
-          PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),
+          mRegisterValues[Index].PAMRegPciLibAddress,
           (UINT8) (~mRegisterValues[Index].ReadEnableData)
           );
       }
@@ -158,12 +158,12 @@ LegacyRegionManipulationInternal (
     if (WriteEnable != NULL) {
       if (*WriteEnable) {
         PciOr8 (
-          PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),
+          mRegisterValues[Index].PAMRegPciLibAddress,
           mRegisterValues[Index].WriteEnableData
           );
       } else {
         PciAnd8 (
-          PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),
+          mRegisterValues[Index].PAMRegPciLibAddress,
           (UINT8) (~mRegisterValues[Index].WriteEnableData)
           );
       }
@@ -204,7 +204,7 @@ LegacyRegionGetInfoInternal (
   //
   *DescriptorCount = sizeof(mSectionArray) / sizeof (mSectionArray[0]);
   for (Index = 0; Index < *DescriptorCount; Index++) {
-    PamValue = PciRead8 (PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset));
+    PamValue = PciRead8 (mRegisterValues[Index].PAMRegPciLibAddress);
     mSectionArray[Index].ReadEnabled = FALSE;
     if ((PamValue & mRegisterValues[Index].ReadEnableData) != 0) {
       mSectionArray[Index].ReadEnabled = TRUE;
-- 
2.14.1.3.gb7cf6e02401b

[PATCH 2/3] OvmfPkg/QemuVideoDxe/VbeShim: rename Status to Segment0AllocationStatus

[Laszlo Ersek]

This clarifies the purpose of the local variable in InstallVbeShim().

Cc: Aleksei Kovura <alex3kov@zoho.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Ref: https://bugs.launchpad.net/qemu/+bug/1715700
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
---
 OvmfPkg/QemuVideoDxe/VbeShim.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/OvmfPkg/QemuVideoDxe/VbeShim.c b/OvmfPkg/QemuVideoDxe/VbeShim.c
index 4c4517e9da27..bc90e067266d 100644
--- a/OvmfPkg/QemuVideoDxe/VbeShim.c
+++ b/OvmfPkg/QemuVideoDxe/VbeShim.c
@@ -63,7 +63,7 @@ InstallVbeShim (
   EFI_PHYSICAL_ADDRESS Segment0, SegmentC, SegmentF;
   UINTN                Segment0Pages;
   IVT_ENTRY            *Int0x10;
-  EFI_STATUS           Status;
+  EFI_STATUS           Segment0AllocationStatus;
   UINTN                Pam1Address;
   UINT8                Pam1;
   UINTN                SegmentCPages;
@@ -87,10 +87,14 @@ InstallVbeShim (
   //
   Segment0Pages = 1;
   Int0x10       = (IVT_ENTRY *)(UINTN)Segment0 + 0x10;
-  Status = gBS->AllocatePages (AllocateAddress, EfiBootServicesCode,
-                  Segment0Pages, &Segment0);
+  Segment0AllocationStatus = gBS->AllocatePages (
+                                    AllocateAddress,
+                                    EfiBootServicesCode,
+                                    Segment0Pages,
+                                    &Segment0
+                                    );
 
-  if (EFI_ERROR (Status)) {
+  if (EFI_ERROR (Segment0AllocationStatus)) {
     EFI_PHYSICAL_ADDRESS Handler;
 
     //
@@ -109,8 +113,12 @@ InstallVbeShim (
     // Otherwise we'll overwrite the Int10h vector, even though we may not own
     // the page at zero.
     //
-    DEBUG ((EFI_D_INFO, "%a: failed to allocate page at zero: %r\n",
-      __FUNCTION__, Status));
+    DEBUG ((
+      DEBUG_INFO,
+      "%a: failed to allocate page at zero: %r\n",
+      __FUNCTION__,
+      Segment0AllocationStatus
+      ));
   } else {
     //
     // We managed to allocate the page at zero. SVN r14218 guarantees that it
-- 
2.14.1.3.gb7cf6e02401b

[PATCH 3/3] OvmfPkg/QemuVideoDxe/VbeShim: handle PAM1 register on Q35 correctly

[Laszlo Ersek]

In commit db27e9f3d8f0 ("OvmfPkg/LegacyRegion: Support legacy region
manipulation of Q35", 2016-03-15), Ray extended the
OvmfPkg/Csm/CsmSupportLib PAM register manipulation to Q35. However, we
missed that the same should be done to the QemuVideoDxe VBE Shim as well.

The omission has caused no problems in practice on Q35, because QEMU has
let us write to the ROM area, regardless of the PAM1 setting, all this
time. This has now changed with recent QEMU commit 208fa0e43645 ("pc: make
'pc.rom' readonly when machine has PCI enabled", 2017-07-28). The QEMU
commit exposes the OVMF bug when Windows 7 is started on Q35, using QEMU
2.10 -- the VBE Shim is no longer put in place and Windows 7 cannot find
it.

To remedy this, assign the "Pam1Address" local variable a PciLib address
that matches the board type (i440fx vs. q35).

Regarding the PcdLib dependency: QemuVideoDxe already uses PcdLib, both
directly (see "PcdDriverSupportedEfiVersion") and indirectly (e.g. via the
DxePciLibI440FxQ35 PciLib instance). Add PcdLib to [LibraryClasses] for
completeness.

Cc: Aleksei Kovura <alex3kov@zoho.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Ref: https://bugs.launchpad.net/qemu/+bug/1715700
Reported-by: Aleksei Kovura <alex3kov@zoho.com>
Special-thanks-to: Gerd Hoffmann <kraxel@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
---
 OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf |  3 ++-
 OvmfPkg/QemuVideoDxe/VbeShim.c        | 27 +++++++++++++++++++-
 2 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf b/OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf
index 7c7d429bca27..577e07b0a8bf 100644
--- a/OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf
+++ b/OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf
@@ -60,6 +60,7 @@ [LibraryClasses]
   DebugLib
   DevicePathLib
   MemoryAllocationLib
+  PcdLib
   PciLib
   PrintLib
   TimerLib
@@ -75,4 +76,4 @@ [Protocols]
 
 [Pcd]
   gOptionRomPkgTokenSpaceGuid.PcdDriverSupportedEfiVersion
-
+  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId
diff --git a/OvmfPkg/QemuVideoDxe/VbeShim.c b/OvmfPkg/QemuVideoDxe/VbeShim.c
index bc90e067266d..e45a08e8873f 100644
--- a/OvmfPkg/QemuVideoDxe/VbeShim.c
+++ b/OvmfPkg/QemuVideoDxe/VbeShim.c
@@ -25,6 +25,7 @@
 #include <Library/DebugLib.h>
 #include <Library/PciLib.h>
 #include <Library/PrintLib.h>
+#include <OvmfPlatforms.h>
 
 #include "Qemu.h"
 #include "VbeShim.h"
@@ -64,6 +65,7 @@ InstallVbeShim (
   UINTN                Segment0Pages;
   IVT_ENTRY            *Int0x10;
   EFI_STATUS           Segment0AllocationStatus;
+  UINT16               HostBridgeDevId;
   UINTN                Pam1Address;
   UINT8                Pam1;
   UINTN                SegmentCPages;
@@ -131,7 +133,30 @@ InstallVbeShim (
   //
   // Put the shim in place first.
   //
-  Pam1Address = PCI_LIB_ADDRESS (0, 0, 0, 0x5A);
+  // Start by determining the address of the PAM1 register.
+  //
+  HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);
+  switch (HostBridgeDevId) {
+  case INTEL_82441_DEVICE_ID:
+    Pam1Address = PMC_REGISTER_PIIX4 (PIIX4_PAM1);
+    break;
+  case INTEL_Q35_MCH_DEVICE_ID:
+    Pam1Address = DRAMC_REGISTER_Q35 (MCH_PAM1);
+    break;
+  default:
+    DEBUG ((
+      DEBUG_ERROR,
+      "%a: unknown host bridge device ID: 0x%04x\n",
+      __FUNCTION__,
+      HostBridgeDevId
+      ));
+    ASSERT (FALSE);
+
+    if (!EFI_ERROR (Segment0AllocationStatus)) {
+      gBS->FreePages (Segment0, Segment0Pages);
+    }
+    return;
+  }
   //
   // low nibble covers 0xC0000 to 0xC3FFF
   // high nibble covers 0xC4000 to 0xC7FFF
-- 
2.14.1.3.gb7cf6e02401b

Re: [PATCH 0/3] OvmfPkg/QemuVideoDxe/VbeShim: handle PAM1 register on Q35 correctly

[Laszlo Ersek]

On 09/19/17 21:18, Laszlo Ersek wrote:
> Repo:   https://github.com/lersek/edk2.git
> Branch: vbe_shim_q35_pam
>
> Fix the long-standing OVMF/Q35 bug recently exposed by a QEMU change,
> and reported under <https://bugs.launchpad.net/qemu/+bug/1715700>.
>
> Aleksei, can you please fetch the branch, build it, and report back
> with your Tested-by if it works for you?
>
> I performed my own tests as well; I'll include those in a separate
> email.

Testing:

- QEMU version: v2.10.0-611-g11e06ce1ed28.

- Edk2 basis: a3a473705101.

- ISO image used for testing:
  en_windows_server_2008_r2_with_sp1_x64_dvd_617601.iso

Test  CSM included  Machine type (2.10)  Boot Mode  Patch applied  Result
----  ------------  -------------------  ---------  -------------  ------
  01  no            i440fx               UEFI       no             pass
  03  no            i440fx               UEFI       yes            pass

  02  no            q35                  UEFI       no             fail
  04  no            q35                  UEFI       yes            pass

  05  yes           i440fx               UEFI       no             pass
  09  yes           i440fx               UEFI       yes            pass

  06  yes           i440fx               legacy     no             fail
  10  yes           i440fx               legacy     yes            n/a

  07  yes           q35                  UEFI       no             pass
  11  yes           q35                  UEFI       yes            pass

  08  yes           q35                  legacy     no             n/a
  12  yes           q35                  legacy     yes            n/a

(Please excuse the strange ordering of the test numbers; the reason is
that testing all the cases is much faster in a different order, while
presenting the results is best in this order. The test case numbering
reflects the order in which I performed the tests.)

Test cases 01 and 03 explain that there is no regression due to the
patches, on i440fx and in UEFI boot mode.

Test cases 02 and 04 show that the patches fix the bug reported by
Aleksei.

The remaining cases cover a build when the SeaBIOS CSM is included in
OVMF. For this I used current SeaBIOS master (at commit ec6cb17f8949),
plus a minimal patch that removes the runningOnQEMU() requirement from
qemu_debug_putc() -- because this check used to fail when running
SeaBIOS as an OVMF CSM, preventing SeaBIOS debug messages from reaching
the QEMU debug port. Furthermore, I built the SeaBIOS QXL option ROM
from the same SeaBIOS tree.

Test cases 05 and 09 explain that there is no regression due to the
patches, on i440fx and in UEFI boot mode.

Test case 06 shows that legacy boot stopped working at an unspecified
point in the past. I emphasize that this boot failure was *without* the
present patch set. I'm going to attach the OVMF debug logs for all
cases, which include the SeaBIOS and VGABIOS output as well. If someone
is interested in getting the CSM build to work again (for legacy OS
boot), please feel free to go ahead. (Personally I'd suggest to stick
with pure SeaBIOS if you have a legacy guest OS.)

Due to the failure of test case 06, I didn't check the behavior with the
current series applied on top (that is, in case 10).

Test cases 07 and 11 demonstrate that there is no regression due to the
patches, on q35 and in UEFI boot mode.

As a side note, test case 07 also demonstrates that the bug reported by
Aleksei is specific to the VBE Shim; it does not hit when the VBE Shim
is unused due to CSM presence. This is consistent with Gerd's result in
<https://bugs.launchpad.net/qemu/+bug/1715700/comments/24>.

Test cases 08 and 12 are not possible to test (i.e., the current series
makes no difference). This is because Q35 has an AHCI/SATA controller
(with six ports), not a traditional IDE controller (with
primary/secondary and master/slave), therefore edk2's UefiBootManagerLib
and/or BdsDxe do not generate BBS (= legacy BIOS) boot options for the
CD-ROM. (I used an "ide-cd" device in all cases.)

Given my earlier experience that the edk2-devel list software does not
reflect attachments, and does not include them in the mailing list
archive, I'm manually including a base-64 encoded tarball below, with
the debug logs. The SHA256 sum is
ad196c202cf300e2028ac67256c6966b1ce7a13042e47351d19d8408bb0b32ab.

Thanks,
Laszlo

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====

Re: [PATCH 0/3] OvmfPkg/QemuVideoDxe/VbeShim: handle PAM1 register on Q35 correctly

[Aleksei]

Hi Laszlo,

I've built it (despite edk2/ovmf build process being as convoluted as 
ever) and am trying to run it with qemu 2.10.0 - it's not booting at 
all, stuck at "Guest has not initialized the display (yet)."

Maybe the problem is gcc version? I have 7.2.0 while edk2 instructions 
mention gcc5.

On 19/09/17 22:18, Laszlo Ersek wrote:
> Repo:   https://github.com/lersek/edk2.git
> Branch: vbe_shim_q35_pam
>
> Fix the long-standing OVMF/Q35 bug recently exposed by a QEMU change,
> and reported under <https://bugs.launchpad.net/qemu/+bug/1715700>.
>
> Aleksei, can you please fetch the branch, build it, and report back with
> your Tested-by if it works for you?
>
> I performed my own tests as well; I'll include those in a separate
> email.
>
> Cc: Aleksei Kovura <alex3kov@zoho.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Igor Mammedov <imammedo@redhat.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
>
> Thank you,
> Laszlo
>
> Laszlo Ersek (3):
>    OvmfPkg/CsmSupportLib: move PAM register addresses to IndustryStandard
>    OvmfPkg/QemuVideoDxe/VbeShim: rename Status to
>      Segment0AllocationStatus
>    OvmfPkg/QemuVideoDxe/VbeShim: handle PAM1 register on Q35 correctly
>
>   OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c       | 62 ++++++++++----------
>   OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h       | 22 +------
>   OvmfPkg/Include/IndustryStandard/I440FxPiix4.h | 13 ++++
>   OvmfPkg/Include/IndustryStandard/Q35MchIch9.h  |  8 +++
>   OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf          |  3 +-
>   OvmfPkg/QemuVideoDxe/VbeShim.c                 | 47 ++++++++++++---
>   6 files changed, 95 insertions(+), 60 deletions(-)
>

-- 
/--Regards, Aleksei/

Re: [PATCH 0/3] OvmfPkg/QemuVideoDxe/VbeShim: handle PAM1 register on Q35 correctly

[Laszlo Ersek]

On 09/20/17 09:05, Aleksei wrote:
> Hi Laszlo,
> 
> I've built it (despite edk2/ovmf build process being as convoluted as
> ever)

Criticism well deserved :) , but at least we have excuses
(multi-platform, multi-compiler build system, and freestanding (i.e.,
not hosted) codebase).

> and am trying to run it with qemu 2.10.0 - it's not booting at
> all, stuck at "Guest has not initialized the display (yet)."
> 
> Maybe the problem is gcc version? I have 7.2.0 while edk2 instructions
> mention gcc5.

Hm, my prime suspect isn't gcc-7.2 (it should work with the GCC5
toolchain, but just to be sure you can try the GCC49 toolchain as well
with it).

My prime suspect is that you've been using a 2MB firmware image
(speaking in unified image terms) from Gerd's firmware repo, but the
upstream default is now 4MB.

You can't mix and match (a) firmware binary and (b) variable store
between different unified sizes; that is, if your previous firmware was
2MB in size (unified), you have to pass the following switch to your new
build too:

  -D FD_SIZE_2MB

Are you on IRC? I'll hop on #edk2 on OFTC for a while now (nick is
"lersek").

Thanks,
Laszlo

> 
> On 19/09/17 22:18, Laszlo Ersek wrote:
>> Repo:   https://github.com/lersek/edk2.git
>> Branch: vbe_shim_q35_pam
>>
>> Fix the long-standing OVMF/Q35 bug recently exposed by a QEMU change,
>> and reported under <https://bugs.launchpad.net/qemu/+bug/1715700>.
>>
>> Aleksei, can you please fetch the branch, build it, and report back with
>> your Tested-by if it works for you?
>>
>> I performed my own tests as well; I'll include those in a separate
>> email.
>>
>> Cc: Aleksei Kovura <alex3kov@zoho.com>
>> Cc: Gerd Hoffmann <kraxel@redhat.com>
>> Cc: Igor Mammedov <imammedo@redhat.com>
>> Cc: Jordan Justen <jordan.l.justen@intel.com>
>> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
>>
>> Thank you,
>> Laszlo
>>
>> Laszlo Ersek (3):
>>    OvmfPkg/CsmSupportLib: move PAM register addresses to IndustryStandard
>>    OvmfPkg/QemuVideoDxe/VbeShim: rename Status to
>>      Segment0AllocationStatus
>>    OvmfPkg/QemuVideoDxe/VbeShim: handle PAM1 register on Q35 correctly
>>
>>   OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c       | 62
>> ++++++++++----------
>>   OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h       | 22 +------
>>   OvmfPkg/Include/IndustryStandard/I440FxPiix4.h | 13 ++++
>>   OvmfPkg/Include/IndustryStandard/Q35MchIch9.h  |  8 +++
>>   OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf          |  3 +-
>>   OvmfPkg/QemuVideoDxe/VbeShim.c                 | 47 ++++++++++++---
>>   6 files changed, 95 insertions(+), 60 deletions(-)
>>
> 

Re: [PATCH 0/3] OvmfPkg/QemuVideoDxe/VbeShim: handle PAM1 register on Q35 correctly

[Aleksei]

Tested-by: Aleksei Kovura

Works for me with Qemu 2.10.0.


On 19/09/17 22:18, Laszlo Ersek wrote:
> Repo:   https://github.com/lersek/edk2.git
> Branch: vbe_shim_q35_pam
>
> Fix the long-standing OVMF/Q35 bug recently exposed by a QEMU change,
> and reported under <https://bugs.launchpad.net/qemu/+bug/1715700>.
>
> Aleksei, can you please fetch the branch, build it, and report back with
> your Tested-by if it works for you?
>
> I performed my own tests as well; I'll include those in a separate
> email.
>
> Cc: Aleksei Kovura <alex3kov@zoho.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Igor Mammedov <imammedo@redhat.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
>
> Thank you,
> Laszlo
>
> Laszlo Ersek (3):
>    OvmfPkg/CsmSupportLib: move PAM register addresses to IndustryStandard
>    OvmfPkg/QemuVideoDxe/VbeShim: rename Status to
>      Segment0AllocationStatus
>    OvmfPkg/QemuVideoDxe/VbeShim: handle PAM1 register on Q35 correctly
>
>   OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c       | 62 ++++++++++----------
>   OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h       | 22 +------
>   OvmfPkg/Include/IndustryStandard/I440FxPiix4.h | 13 ++++
>   OvmfPkg/Include/IndustryStandard/Q35MchIch9.h  |  8 +++
>   OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf          |  3 +-
>   OvmfPkg/QemuVideoDxe/VbeShim.c                 | 47 ++++++++++++---
>   6 files changed, 95 insertions(+), 60 deletions(-)
>

-- 
/--Regards, Aleksei/

Re: [PATCH 0/3] OvmfPkg/QemuVideoDxe/VbeShim: handle PAM1 register on Q35 correctly

[Jordan Justen]

Series Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

On 2017-09-19 12:18:12, Laszlo Ersek wrote:
> Repo:   https://github.com/lersek/edk2.git
> Branch: vbe_shim_q35_pam
> 
> Fix the long-standing OVMF/Q35 bug recently exposed by a QEMU change,
> and reported under <https://bugs.launchpad.net/qemu/+bug/1715700>.
> 
> Aleksei, can you please fetch the branch, build it, and report back with
> your Tested-by if it works for you?
> 
> I performed my own tests as well; I'll include those in a separate
> email.
> 
> Cc: Aleksei Kovura <alex3kov@zoho.com>
> Cc: Gerd Hoffmann <kraxel@redhat.com>
> Cc: Igor Mammedov <imammedo@redhat.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
> 
> Thank you,
> Laszlo
> 
> Laszlo Ersek (3):
>   OvmfPkg/CsmSupportLib: move PAM register addresses to IndustryStandard
>   OvmfPkg/QemuVideoDxe/VbeShim: rename Status to
>     Segment0AllocationStatus
>   OvmfPkg/QemuVideoDxe/VbeShim: handle PAM1 register on Q35 correctly
> 
>  OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c       | 62 ++++++++++----------
>  OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h       | 22 +------
>  OvmfPkg/Include/IndustryStandard/I440FxPiix4.h | 13 ++++
>  OvmfPkg/Include/IndustryStandard/Q35MchIch9.h  |  8 +++
>  OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf          |  3 +-
>  OvmfPkg/QemuVideoDxe/VbeShim.c                 | 47 ++++++++++++---
>  6 files changed, 95 insertions(+), 60 deletions(-)
> 
> -- 
> 2.14.1.3.gb7cf6e02401b
> 

Re: [PATCH 0/3] OvmfPkg/QemuVideoDxe/VbeShim: handle PAM1 register on Q35 correctly

[Laszlo Ersek]

On 09/20/17 20:11, Jordan Justen wrote:
> Series Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

Much appreciated! :)


Aleksei, thank you for the LaunchPad bug report (complete with
bisection) and the testing.

Pushed: b68c793144e8..947f3737abf6.

Cheers,
Laszlo

> On 2017-09-19 12:18:12, Laszlo Ersek wrote:
>> Repo:   https://github.com/lersek/edk2.git
>> Branch: vbe_shim_q35_pam
>>
>> Fix the long-standing OVMF/Q35 bug recently exposed by a QEMU change,
>> and reported under <https://bugs.launchpad.net/qemu/+bug/1715700>.
>>
>> Aleksei, can you please fetch the branch, build it, and report back with
>> your Tested-by if it works for you?
>>
>> I performed my own tests as well; I'll include those in a separate
>> email.
>>
>> Cc: Aleksei Kovura <alex3kov@zoho.com>
>> Cc: Gerd Hoffmann <kraxel@redhat.com>
>> Cc: Igor Mammedov <imammedo@redhat.com>
>> Cc: Jordan Justen <jordan.l.justen@intel.com>
>> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
>>
>> Thank you,
>> Laszlo
>>
>> Laszlo Ersek (3):
>>   OvmfPkg/CsmSupportLib: move PAM register addresses to IndustryStandard
>>   OvmfPkg/QemuVideoDxe/VbeShim: rename Status to
>>     Segment0AllocationStatus
>>   OvmfPkg/QemuVideoDxe/VbeShim: handle PAM1 register on Q35 correctly
>>
>>  OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c       | 62 ++++++++++----------
>>  OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h       | 22 +------
>>  OvmfPkg/Include/IndustryStandard/I440FxPiix4.h | 13 ++++
>>  OvmfPkg/Include/IndustryStandard/Q35MchIch9.h  |  8 +++
>>  OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf          |  3 +-
>>  OvmfPkg/QemuVideoDxe/VbeShim.c                 | 47 ++++++++++++---
>>  6 files changed, 95 insertions(+), 60 deletions(-)
>>
>> -- 
>> 2.14.1.3.gb7cf6e02401b
>>