From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A0D5E21A16EF7 for ; Thu, 18 May 2017 12:10:46 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id F1ABA3D942; Thu, 18 May 2017 19:10:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com F1ABA3D942 Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx06.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com F1ABA3D942 Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-86.phx2.redhat.com [10.3.116.86]) by smtp.corp.redhat.com (Postfix) with ESMTP id CFBDF18203; Thu, 18 May 2017 19:10:44 +0000 (UTC) To: Michael Kinney , edk2-devel@lists.01.org Cc: Jeff Fan , Andrew Fish References: <1495131268-25444-1-git-send-email-michael.d.kinney@intel.com> From: Laszlo Ersek Message-ID: Date: Thu, 18 May 2017 21:10:43 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: <1495131268-25444-1-git-send-email-michael.d.kinney@intel.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Thu, 18 May 2017 19:10:46 +0000 (UTC) Subject: Re: [Patch] UefiCpuPkg/PiSmmCpuDxeSmm: Add missing JMP instruction X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 18 May 2017 19:10:46 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 05/18/17 20:14, Michael Kinney wrote: > https://bugzilla.tianocore.org/show_bug.cgi?id=555 > > Add JMP instruction in SmiEntry.S file that is missing. This > updates SmiEntry.S to match the logic in SmiEntry.asm and > SmiEntry.nasm. > > The default BUILDRULEORDER has .nasm higher priority than > .asm or .S, so this issue was not seen with MSFT or GCC > tool chain families. The XCODE5 tool chain overrides the > BUILDRULEORDER with .S higher than .nasm, so this issue > was only seen when using XCODE5 tool chain when IA32 SMM > is enabled. > > Cc: Jeff Fan > Cc: Andrew Fish > Cc: Laszlo Ersek > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Michael Kinney > --- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S > index 62f1697..3243a91 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S > @@ -1,6 +1,6 @@ > #------------------------------------------------------------------------------ > # > -# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
> +# Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
> # This program and the accompanying materials > # are licensed and made available under the terms and conditions of the BSD License > # which accompanies this distribution. The full text of the license may be found at > @@ -159,6 +159,7 @@ L13: > rdmsr > orw $MSR_EFER_XD,%ax # enable NXE > wrmsr > + jmp NxeDone > SkipNxe: > subl $4, %esp > NxeDone: > Reviewed-by: Laszlo Ersek