From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: redhat.com, ip: 209.85.128.67, mailfrom: philmd@redhat.com) Received: from mail-wm1-f67.google.com (mail-wm1-f67.google.com [209.85.128.67]) by groups.io with SMTP; Wed, 29 May 2019 08:24:56 -0700 Received: by mail-wm1-f67.google.com with SMTP id y3so1968753wmm.2 for ; Wed, 29 May 2019 08:24:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:openpgp:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=UdqrToT969rmsoj1XcKxqKsy2L5yLZjD+0Hi24ORMW0=; b=dJgVtF6Kll3mCKCK1ODKwfqYlGQ6S67FgbN+sq5ovWlsufaFz84aUA5iCdV+wEJyXd YJaiAJY7JxNCM1uB5mCzG7Tuiv4YGXPrYzT0+Ap7+QUS7jwUXDlvgsfJcOyhfZBfPv31 92yuEEDY/AwBW1AE6+rvlRHYUeDMEekWU7cvni9eU1Djcjd2v3vthi0GZwqAAtfhH/mO QuuLxQSR9fA+BDZSAAl4Gj81V2kzG8zzgfw7WjhTw10keLDbSqH1/OazbcwkMMz1kUMZ H42nZw8Jmee0jacDc0qOzZBh4b4Rg6oX/Yfbrjsth+qRPKuWS5osxHg1iPkMdf4ZUsXF sGow== X-Gm-Message-State: APjAAAVqpmdyjOGJdD3pVC7Ljn2TW4oeY0pdir4/Ohiybf/KIF/svelh mJ7NgX5rZa1OikfhZxlhVr3DeA== X-Google-Smtp-Source: APXvYqy/4fLDkrReWve2h6xoHWVc2cb9JC8kgh1Hj5IsF7jsuBi5s6iFOW57PZR8EpCf25fvrHarjg== X-Received: by 2002:a1c:2d83:: with SMTP id t125mr7045878wmt.83.1559143494906; Wed, 29 May 2019 08:24:54 -0700 (PDT) Return-Path: Received: from [10.201.33.53] ([195.166.127.210]) by smtp.gmail.com with ESMTPSA id l13sm2367503wme.37.2019.05.29.08.24.53 (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Wed, 29 May 2019 08:24:54 -0700 (PDT) Subject: Re: [edk2-devel] [PATCH for-edk2-stable201905 2/6] Revert "OvmfPkg/PlatformPei: reorder the 32-bit PCI window vs. the PCIEXBAR on q35" To: devel@edk2.groups.io, lersek@redhat.com Cc: Ard Biesheuvel , Gerd Hoffmann , Jordan Justen References: <20190529151209.17503-1-lersek@redhat.com> <20190529151209.17503-3-lersek@redhat.com> From: =?UTF-8?B?UGhpbGlwcGUgTWF0aGlldS1EYXVkw6k=?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: Date: Wed, 29 May 2019 17:24:53 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190529151209.17503-3-lersek@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 5/29/19 5:12 PM, Laszlo Ersek wrote: > This reverts commit 75136b29541b0e093a51d2e2c2af8d19855c2b60. > > The original fix for > triggered a bug / incorrect assumption in QEMU. > > QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above > it. When the firmware doesn't satisfy this assumption, QEMU generates an > \_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the > firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign > 32-bit MMIO BARs. > > Working around the problem in the firmware looks less problematic than > fixing QEMU. Revert the original changes first, before implementing an > alternative fix. > > Cc: Ard Biesheuvel > Cc: Gerd Hoffmann > Cc: Jordan Justen > Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859 > Signed-off-by: Laszlo Ersek Reviewed-by: Philippe Mathieu-Daude > --- > OvmfPkg/OvmfPkgIa32.dsc | 5 ++++- > OvmfPkg/OvmfPkgIa32X64.dsc | 5 ++++- > OvmfPkg/OvmfPkgX64.dsc | 5 ++++- > OvmfPkg/PlatformPei/Platform.c | 9 +++++---- > 4 files changed, 17 insertions(+), 7 deletions(-) > > diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc > index b3446ece311a..578fc6c98ec8 100644 > --- a/OvmfPkg/OvmfPkgIa32.dsc > +++ b/OvmfPkg/OvmfPkgIa32.dsc > @@ -490,7 +490,10 @@ [PcdsFixedAtBuild] > # This PCD is used to set the base address of the PCI express hierarchy. It > # is only consulted when OVMF runs on Q35. In that case it is programmed into > # the PCIEXBAR register. > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 > + # > + # On Q35 machine types that QEMU intends to support in the long term, QEMU > + # never lets the RAM below 4 GB exceed 2 GB. > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 > > !ifdef $(SOURCE_DEBUG_ENABLE) > gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 > diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc > index 679d4eb8dd36..eade8f62d3de 100644 > --- a/OvmfPkg/OvmfPkgIa32X64.dsc > +++ b/OvmfPkg/OvmfPkgIa32X64.dsc > @@ -495,7 +495,10 @@ [PcdsFixedAtBuild] > # This PCD is used to set the base address of the PCI express hierarchy. It > # is only consulted when OVMF runs on Q35. In that case it is programmed into > # the PCIEXBAR register. > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 > + # > + # On Q35 machine types that QEMU intends to support in the long term, QEMU > + # never lets the RAM below 4 GB exceed 2 GB. > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 > > !ifdef $(SOURCE_DEBUG_ENABLE) > gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 > diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc > index 56a9560262aa..733a4c9d8a43 100644 > --- a/OvmfPkg/OvmfPkgX64.dsc > +++ b/OvmfPkg/OvmfPkgX64.dsc > @@ -495,7 +495,10 @@ [PcdsFixedAtBuild] > # This PCD is used to set the base address of the PCI express hierarchy. It > # is only consulted when OVMF runs on Q35. In that case it is programmed into > # the PCIEXBAR register. > - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 > + # > + # On Q35 machine types that QEMU intends to support in the long term, QEMU > + # never lets the RAM below 4 GB exceed 2 GB. > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 > > !ifdef $(SOURCE_DEBUG_ENABLE) > gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 > diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c > index fd8eccaf3e50..9c013613a1a0 100644 > --- a/OvmfPkg/PlatformPei/Platform.c > +++ b/OvmfPkg/PlatformPei/Platform.c > @@ -184,13 +184,14 @@ MemMapInitialization ( > PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; > if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { > // > - // The 32-bit PCI host aperture is expected to fall between the top of > - // low RAM and the base of the MMCONFIG area. > + // The MMCONFIG area is expected to fall between the top of low RAM and > + // the base of the 32-bit PCI host aperture. > // > PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress); > - ASSERT (PciBase < PciExBarBase); > + ASSERT (TopOfLowRam <= PciExBarBase); > ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB); > - PciSize = (UINT32)(PciExBarBase - PciBase); > + PciBase = (UINT32)(PciExBarBase + SIZE_256MB); > + PciSize = 0xFC000000 - PciBase; > } else { > PciSize = 0xFC000000 - PciBase; > } >